ssdfb_i2c.c revision 1.9.4.1
1 /* $NetBSD: ssdfb_i2c.c,v 1.9.4.1 2021/08/01 22:42:23 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ssdfb_i2c.c,v 1.9.4.1 2021/08/01 22:42:23 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <dev/wscons/wsdisplayvar.h> 38 #include <dev/rasops/rasops.h> 39 #include <dev/i2c/i2cvar.h> 40 #include <dev/ic/ssdfbvar.h> 41 42 struct ssdfb_i2c_softc { 43 struct ssdfb_softc sc; 44 i2c_tag_t sc_i2c_tag; 45 i2c_addr_t sc_i2c_addr; 46 size_t sc_transfer_size; 47 }; 48 49 static int ssdfb_i2c_match(device_t, cfdata_t, void *); 50 static void ssdfb_i2c_attach(device_t, device_t, void *); 51 static int ssdfb_i2c_detach(device_t, int); 52 53 static int ssdfb_i2c_probe_transfer_size(struct ssdfb_i2c_softc *, bool); 54 static int ssdfb_i2c_transfer(struct ssdfb_i2c_softc *, uint8_t, uint8_t *, 55 size_t, int); 56 static int ssdfb_i2c_cmd(void *, uint8_t *, size_t, bool); 57 static int ssdfb_i2c_transfer_rect(void *, uint8_t, uint8_t, uint8_t, 58 uint8_t, uint8_t *, size_t, bool); 59 static int ssdfb_i2c_transfer_rect_ssd1306(void *, uint8_t, uint8_t, 60 uint8_t, uint8_t, uint8_t *, size_t, bool); 61 static int ssdfb_i2c_transfer_rect_sh1106(void *, uint8_t, uint8_t, 62 uint8_t, uint8_t, uint8_t *, size_t, bool); 63 static int ssdfb_smbus_transfer_rect(void *, uint8_t, uint8_t, uint8_t, 64 uint8_t, uint8_t *, size_t, bool); 65 66 CFATTACH_DECL_NEW(ssdfb_iic, sizeof(struct ssdfb_i2c_softc), 67 ssdfb_i2c_match, ssdfb_i2c_attach, ssdfb_i2c_detach, NULL); 68 69 static const struct device_compatible_entry compat_data[] = { 70 { .compat = "solomon,ssd1306fb-i2c", 71 .value = SSDFB_PRODUCT_SSD1306_GENERIC }, 72 73 { .compat = "sino,sh1106fb-i2c", 74 .value = SSDFB_PRODUCT_SH1106_GENERIC }, 75 76 DEVICE_COMPAT_EOL 77 }; 78 79 static int 80 ssdfb_i2c_match(device_t parent, cfdata_t match, void *aux) 81 { 82 struct i2c_attach_args *ia = aux; 83 int match_result; 84 85 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 86 return match_result; 87 88 switch (ia->ia_addr) { 89 case SSDFB_I2C_DEFAULT_ADDR: 90 case SSDFB_I2C_ALTERNATIVE_ADDR: 91 return I2C_MATCH_ADDRESS_ONLY; 92 } 93 94 return 0; 95 } 96 97 static void 98 ssdfb_i2c_attach(device_t parent, device_t self, void *aux) 99 { 100 struct ssdfb_i2c_softc *sc = device_private(self); 101 struct cfdata *cf = device_cfdata(self); 102 struct i2c_attach_args *ia = aux; 103 int flags = cf->cf_flags; 104 105 if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN) { 106 const struct device_compatible_entry *dce = 107 iic_compatible_lookup(ia, compat_data); 108 if (dce != NULL) { 109 flags |= (int)dce->value; 110 } 111 } 112 if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN) 113 flags |= SSDFB_PRODUCT_SSD1306_GENERIC; 114 115 sc->sc.sc_dev = self; 116 sc->sc_i2c_tag = ia->ia_tag; 117 sc->sc_i2c_addr = ia->ia_addr; 118 sc->sc.sc_cookie = (void *)sc; 119 sc->sc.sc_cmd = ssdfb_i2c_cmd; 120 sc->sc.sc_transfer_rect = ssdfb_i2c_transfer_rect; 121 122 ssdfb_attach(&sc->sc, flags); 123 } 124 125 static int 126 ssdfb_i2c_detach(device_t self, int flags) 127 { 128 struct ssdfb_i2c_softc *sc = device_private(self); 129 130 return ssdfb_detach(&sc->sc); 131 } 132 133 static int 134 ssdfb_i2c_probe_transfer_size(struct ssdfb_i2c_softc *sc, bool usepoll) 135 { 136 int flags = usepoll ? I2C_F_POLL : 0; 137 uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK; 138 int error; 139 uint8_t buf[128]; 140 size_t len; 141 142 error = iic_acquire_bus(sc->sc_i2c_tag, flags); 143 if (error) 144 return error; 145 len = sizeof(buf); 146 memset(buf, 0, len); 147 while (len > 0) { 148 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 149 sc->sc_i2c_addr, &cb, sizeof(cb), buf, len, flags); 150 if (!error) { 151 break; 152 } 153 len >>= 1; 154 } 155 if (!error && len < 2) { 156 error = E2BIG; 157 } else { 158 sc->sc_transfer_size = len; 159 } 160 (void) iic_release_bus(sc->sc_i2c_tag, flags); 161 162 return error; 163 } 164 165 static int 166 ssdfb_i2c_transfer(struct ssdfb_i2c_softc *sc, uint8_t cb, uint8_t *data, 167 size_t len, int flags) 168 { 169 int error; 170 size_t xfer_size = sc->sc_transfer_size; 171 172 while (len >= xfer_size) { 173 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 174 sc->sc_i2c_addr, &cb, sizeof(cb), data, xfer_size, flags); 175 if (error) 176 return error; 177 len -= xfer_size; 178 data += xfer_size; 179 } 180 if (len > 0) { 181 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 182 sc->sc_i2c_addr, &cb, sizeof(cb), data, len, flags); 183 } 184 185 return error; 186 } 187 188 static int 189 ssdfb_i2c_cmd(void *cookie, uint8_t *cmd, size_t len, bool usepoll) 190 { 191 struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie; 192 int flags = usepoll ? I2C_F_POLL : 0; 193 uint8_t cb = 0; 194 int error; 195 196 error = iic_acquire_bus(sc->sc_i2c_tag, flags); 197 if (error) 198 return error; 199 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 200 sc->sc_i2c_addr, &cb, sizeof(cb), cmd, len, flags); 201 (void) iic_release_bus(sc->sc_i2c_tag, flags); 202 203 return error; 204 } 205 206 static int 207 ssdfb_i2c_transfer_rect(void *cookie, uint8_t fromcol, uint8_t tocol, 208 uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll) 209 { 210 struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie; 211 uint8_t cmd[2]; 212 int error; 213 214 /* 215 * Test if large transfers are supported by the parent i2c bus and 216 * pick the fastest transfer routine for subsequent invocations. 217 */ 218 switch (sc->sc.sc_p->p_controller_id) { 219 case SSDFB_CONTROLLER_SSD1306: 220 sc->sc.sc_transfer_rect = ssdfb_i2c_transfer_rect_ssd1306; 221 break; 222 case SSDFB_CONTROLLER_SH1106: 223 sc->sc.sc_transfer_rect = ssdfb_i2c_transfer_rect_sh1106; 224 break; 225 default: 226 sc->sc.sc_transfer_rect = ssdfb_smbus_transfer_rect; 227 break; 228 } 229 230 if (sc->sc.sc_transfer_rect != ssdfb_smbus_transfer_rect) { 231 error = ssdfb_i2c_probe_transfer_size(sc, usepoll); 232 if (error) 233 return error; 234 aprint_verbose_dev(sc->sc.sc_dev, "%zd-byte transfers\n", 235 sc->sc_transfer_size); 236 if (sc->sc_transfer_size == 2) { 237 sc->sc.sc_transfer_rect = ssdfb_smbus_transfer_rect; 238 } 239 } 240 241 /* 242 * Set addressing mode for SSD1306. 243 */ 244 if (sc->sc.sc_p->p_controller_id == SSDFB_CONTROLLER_SSD1306) { 245 cmd[0] = SSD1306_CMD_SET_MEMORY_ADDRESSING_MODE; 246 cmd[1] = sc->sc.sc_transfer_rect 247 == ssdfb_i2c_transfer_rect_ssd1306 248 ? SSD1306_MEMORY_ADDRESSING_MODE_HORIZONTAL 249 : SSD1306_MEMORY_ADDRESSING_MODE_PAGE; 250 error = ssdfb_i2c_cmd(cookie, cmd, sizeof(cmd), usepoll); 251 if (error) 252 return error; 253 } 254 255 return sc->sc.sc_transfer_rect(cookie, fromcol, tocol, frompage, topage, 256 p, stride, usepoll); 257 } 258 259 260 static int 261 ssdfb_i2c_transfer_rect_ssd1306(void *cookie, uint8_t fromcol, uint8_t tocol, 262 uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll) 263 { 264 struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie; 265 int flags = usepoll ? I2C_F_POLL : 0; 266 uint8_t cc = 0; 267 uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK; 268 size_t len = tocol + 1 - fromcol; 269 int error; 270 /* 271 * SSD1306 does not implement the Continuation bit correctly. 272 * The SH1106 protocol defines that a control byte WITH Co 273 * set must be inserted between each command. But SSD1306 274 * fails to parse the commands if we do that. 275 */ 276 uint8_t cmds[] = { 277 SSD1306_CMD_SET_COLUMN_ADDRESS, 278 fromcol, tocol, 279 SSD1306_CMD_SET_PAGE_ADDRESS, 280 frompage, topage 281 }; 282 283 error = iic_acquire_bus(sc->sc_i2c_tag, flags); 284 if (error) 285 return error; 286 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 287 sc->sc_i2c_addr, &cc, sizeof(cc), cmds, sizeof(cmds), flags); 288 if (error) 289 goto out; 290 while (frompage <= topage) { 291 error = ssdfb_i2c_transfer(sc, cb, p, len, flags); 292 if (error) 293 goto out; 294 frompage++; 295 p += stride; 296 } 297 out: 298 (void) iic_release_bus(sc->sc_i2c_tag, flags); 299 300 return error; 301 } 302 303 static int 304 ssdfb_i2c_transfer_rect_sh1106(void *cookie, uint8_t fromcol, uint8_t tocol, 305 uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll) 306 { 307 struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie; 308 int flags = usepoll ? I2C_F_POLL : 0; 309 uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK; 310 uint8_t cc = SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK; 311 size_t len = tocol + 1 - fromcol; 312 int error; 313 uint8_t cmds[] = { 314 SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE + frompage, 315 SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK, 316 SSDFB_CMD_SET_HIGHER_COLUMN_START_ADDRESS_BASE + (fromcol >> 4), 317 SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK, 318 SSDFB_CMD_SET_LOWER_COLUMN_START_ADDRESS_BASE + (fromcol & 0xf) 319 }; 320 321 error = iic_acquire_bus(sc->sc_i2c_tag, flags); 322 if (error) 323 return error; 324 while (frompage <= topage) { 325 cmds[0] = SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE + frompage; 326 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 327 sc->sc_i2c_addr, &cc, sizeof(cc), cmds, sizeof(cmds), flags); 328 if (error) 329 goto out; 330 error = ssdfb_i2c_transfer(sc, cb, p, len, flags); 331 if (error) 332 goto out; 333 frompage++; 334 p += stride; 335 } 336 out: 337 (void) iic_release_bus(sc->sc_i2c_tag, flags); 338 339 return error; 340 } 341 342 /* 343 * If the parent is an SMBus, then we can only send 2 bytes 344 * of payload per txn. The SSD1306 triple byte commands are 345 * not available so we have to use PAGE addressing mode 346 * and split data into multiple txns. 347 * This is ugly and slow but it's the best we can do. 348 */ 349 static int 350 ssdfb_smbus_transfer_rect(void *cookie, uint8_t fromcol, uint8_t tocol, 351 uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll) 352 { 353 struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie; 354 int flags = usepoll ? I2C_F_POLL : 0; 355 uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK; 356 uint8_t cc = 0; 357 size_t len = tocol + 1 - fromcol; 358 uint8_t cmd_higher_col = 359 SSDFB_CMD_SET_HIGHER_COLUMN_START_ADDRESS_BASE + (fromcol >> 4); 360 uint8_t cmd_lower_col = 361 SSDFB_CMD_SET_LOWER_COLUMN_START_ADDRESS_BASE + (fromcol & 0xf); 362 uint8_t cmd_page; 363 uint8_t data[2]; 364 uint8_t *colp; 365 uint8_t *endp; 366 int error; 367 368 error = iic_acquire_bus(sc->sc_i2c_tag, flags); 369 if (error) 370 return error; 371 while (frompage <= topage) { 372 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 373 sc->sc_i2c_addr, &cc, sizeof(cc), 374 &cmd_higher_col, sizeof(cmd_higher_col), flags); 375 if (error) 376 goto out; 377 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 378 sc->sc_i2c_addr, &cc, sizeof(cc), 379 &cmd_lower_col, sizeof(cmd_lower_col), flags); 380 if (error) 381 goto out; 382 cmd_page = SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE + frompage; 383 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 384 sc->sc_i2c_addr, &cc, sizeof(cc), 385 &cmd_page, sizeof(cmd_page), flags); 386 if (error) 387 goto out; 388 colp = p; 389 endp = colp + len; 390 if (len & 1) { 391 data[0] = *colp++; 392 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 393 sc->sc_i2c_addr, &cb, sizeof(cb), data, 1, flags); 394 if (error) 395 goto out; 396 } 397 while (colp < endp) { 398 /* 399 * Send two bytes at a time. We can't use colp directly 400 * because i2c controllers sometimes have data alignment 401 * requirements. 402 */ 403 data[0] = *colp++; 404 data[1] = *colp++; 405 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP, 406 sc->sc_i2c_addr, &cb, sizeof(cb), data, 2, flags); 407 if (error) 408 goto out; 409 } 410 frompage++; 411 p += stride; 412 } 413 out: 414 (void) iic_release_bus(sc->sc_i2c_tag, flags); 415 416 return error; 417 } 418
Indexes created Mon Sep 29 21:09:56 GMT 2025