tda19988.c revision 1.3
1 /* $NetBSD: tda19988.c,v 1.3 2019/11/04 10:02:39 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo (at) freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tda19988.c,v 1.3 2019/11/04 10:02:39 jmcneill Exp $"); 31 32 /* 33 * NXP TDA19988 HDMI encoder 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/time.h> 39 #include <sys/bus.h> 40 #include <sys/types.h> 41 42 #include <dev/i2c/i2cvar.h> 43 #include <dev/i2c/ddcvar.h> 44 #include <dev/i2c/ddcreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 #include <dev/fdt/fdt_port.h> 48 49 #include <dev/videomode/videomode.h> 50 #include <dev/videomode/edidvar.h> 51 52 #include <drm/drmP.h> 53 #include <drm/drm_crtc.h> 54 #include <drm/drm_crtc_helper.h> 55 #include <drm/drm_edid.h> 56 57 enum { 58 TDA19988_PORT_INPUT = 0 59 }; 60 61 #define MKREG(page, addr) (((page) << 8) | (addr)) 62 63 #define REGPAGE(reg) (((reg) >> 8) & 0xff) 64 #define REGADDR(reg) ((reg) & 0xff) 65 66 #define TDA_VERSION MKREG(0x00, 0x00) 67 #define TDA_MAIN_CNTRL0 MKREG(0x00, 0x01) 68 #define MAIN_CNTRL0_SR (1 << 0) 69 #define TDA_VERSION_MSB MKREG(0x00, 0x02) 70 #define TDA_SOFTRESET MKREG(0x00, 0x0a) 71 #define SOFTRESET_I2C (1 << 1) 72 #define SOFTRESET_AUDIO (1 << 0) 73 #define TDA_DDC_CTRL MKREG(0x00, 0x0b) 74 #define DDC_ENABLE 0 75 #define TDA_CCLK MKREG(0x00, 0x0c) 76 #define CCLK_ENABLE 1 77 #define TDA_INT_FLAGS_2 MKREG(0x00, 0x11) 78 #define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 79 80 #define TDA_VIP_CNTRL_0 MKREG(0x00, 0x20) 81 #define TDA_VIP_CNTRL_1 MKREG(0x00, 0x21) 82 #define TDA_VIP_CNTRL_2 MKREG(0x00, 0x22) 83 #define TDA_VIP_CNTRL_3 MKREG(0x00, 0x23) 84 #define VIP_CNTRL_3_SYNC_HS (2 << 4) 85 #define VIP_CNTRL_3_V_TGL (1 << 2) 86 #define VIP_CNTRL_3_H_TGL (1 << 1) 87 88 #define TDA_VIP_CNTRL_4 MKREG(0x00, 0x24) 89 #define VIP_CNTRL_4_BLANKIT_NDE (0 << 2) 90 #define VIP_CNTRL_4_BLANKIT_HS_VS (1 << 2) 91 #define VIP_CNTRL_4_BLANKIT_NHS_VS (2 << 2) 92 #define VIP_CNTRL_4_BLANKIT_HE_VE (3 << 2) 93 #define VIP_CNTRL_4_BLC_NONE (0 << 0) 94 #define VIP_CNTRL_4_BLC_RGB444 (1 << 0) 95 #define VIP_CNTRL_4_BLC_YUV444 (2 << 0) 96 #define VIP_CNTRL_4_BLC_YUV422 (3 << 0) 97 #define TDA_VIP_CNTRL_5 MKREG(0x00, 0x25) 98 #define VIP_CNTRL_5_SP_CNT(n) (((n) & 3) << 1) 99 #define TDA_MUX_VP_VIP_OUT MKREG(0x00, 0x27) 100 #define TDA_MAT_CONTRL MKREG(0x00, 0x80) 101 #define MAT_CONTRL_MAT_BP (1 << 2) 102 #define TDA_VIDFORMAT MKREG(0x00, 0xa0) 103 #define TDA_REFPIX_MSB MKREG(0x00, 0xa1) 104 #define TDA_REFPIX_LSB MKREG(0x00, 0xa2) 105 #define TDA_REFLINE_MSB MKREG(0x00, 0xa3) 106 #define TDA_REFLINE_LSB MKREG(0x00, 0xa4) 107 #define TDA_NPIX_MSB MKREG(0x00, 0xa5) 108 #define TDA_NPIX_LSB MKREG(0x00, 0xa6) 109 #define TDA_NLINE_MSB MKREG(0x00, 0xa7) 110 #define TDA_NLINE_LSB MKREG(0x00, 0xa8) 111 #define TDA_VS_LINE_STRT_1_MSB MKREG(0x00, 0xa9) 112 #define TDA_VS_LINE_STRT_1_LSB MKREG(0x00, 0xaa) 113 #define TDA_VS_PIX_STRT_1_MSB MKREG(0x00, 0xab) 114 #define TDA_VS_PIX_STRT_1_LSB MKREG(0x00, 0xac) 115 #define TDA_VS_LINE_END_1_MSB MKREG(0x00, 0xad) 116 #define TDA_VS_LINE_END_1_LSB MKREG(0x00, 0xae) 117 #define TDA_VS_PIX_END_1_MSB MKREG(0x00, 0xaf) 118 #define TDA_VS_PIX_END_1_LSB MKREG(0x00, 0xb0) 119 #define TDA_VS_LINE_STRT_2_MSB MKREG(0x00, 0xb1) 120 #define TDA_VS_LINE_STRT_2_LSB MKREG(0x00, 0xb2) 121 #define TDA_VS_PIX_STRT_2_MSB MKREG(0x00, 0xb3) 122 #define TDA_VS_PIX_STRT_2_LSB MKREG(0x00, 0xb4) 123 #define TDA_VS_LINE_END_2_MSB MKREG(0x00, 0xb5) 124 #define TDA_VS_LINE_END_2_LSB MKREG(0x00, 0xb6) 125 #define TDA_VS_PIX_END_2_MSB MKREG(0x00, 0xb7) 126 #define TDA_VS_PIX_END_2_LSB MKREG(0x00, 0xb8) 127 #define TDA_HS_PIX_START_MSB MKREG(0x00, 0xb9) 128 #define TDA_HS_PIX_START_LSB MKREG(0x00, 0xba) 129 #define TDA_HS_PIX_STOP_MSB MKREG(0x00, 0xbb) 130 #define TDA_HS_PIX_STOP_LSB MKREG(0x00, 0xbc) 131 #define TDA_VWIN_START_1_MSB MKREG(0x00, 0xbd) 132 #define TDA_VWIN_START_1_LSB MKREG(0x00, 0xbe) 133 #define TDA_VWIN_END_1_MSB MKREG(0x00, 0xbf) 134 #define TDA_VWIN_END_1_LSB MKREG(0x00, 0xc0) 135 #define TDA_VWIN_START_2_MSB MKREG(0x00, 0xc1) 136 #define TDA_VWIN_START_2_LSB MKREG(0x00, 0xc2) 137 #define TDA_VWIN_END_2_MSB MKREG(0x00, 0xc3) 138 #define TDA_VWIN_END_2_LSB MKREG(0x00, 0xc4) 139 #define TDA_DE_START_MSB MKREG(0x00, 0xc5) 140 #define TDA_DE_START_LSB MKREG(0x00, 0xc6) 141 #define TDA_DE_STOP_MSB MKREG(0x00, 0xc7) 142 #define TDA_DE_STOP_LSB MKREG(0x00, 0xc8) 143 144 #define TDA_TBG_CNTRL_0 MKREG(0x00, 0xca) 145 #define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 146 #define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 147 148 #define TDA_TBG_CNTRL_1 MKREG(0x00, 0xcb) 149 #define TBG_CNTRL_1_DWIN_DIS (1 << 6) 150 #define TBG_CNTRL_1_TGL_EN (1 << 2) 151 #define TBG_CNTRL_1_V_TGL (1 << 1) 152 #define TBG_CNTRL_1_H_TGL (1 << 0) 153 154 #define TDA_HVF_CNTRL_0 MKREG(0x00, 0xe4) 155 #define HVF_CNTRL_0_PREFIL_NONE (0 << 2) 156 #define HVF_CNTRL_0_INTPOL_BYPASS (0 << 0) 157 #define TDA_HVF_CNTRL_1 MKREG(0x00, 0xe5) 158 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 159 #define HVF_CNTRL_1_VQR_FULL HVF_CNTRL_1_VQR(0) 160 #define TDA_ENABLE_SPACE MKREG(0x00, 0xd6) 161 #define TDA_RPT_CNTRL MKREG(0x00, 0xf0) 162 163 #define TDA_PLL_SERIAL_1 MKREG(0x02, 0x00) 164 #define PLL_SERIAL_1_SRL_MAN_IP (1 << 6) 165 #define TDA_PLL_SERIAL_2 MKREG(0x02, 0x01) 166 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 167 #define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0) 168 #define TDA_PLL_SERIAL_3 MKREG(0x02, 0x02) 169 #define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 170 #define PLL_SERIAL_3_SRL_DE (1 << 2) 171 #define PLL_SERIAL_3_SRL_CCIR (1 << 0) 172 #define TDA_SERIALIZER MKREG(0x02, 0x03) 173 #define TDA_BUFFER_OUT MKREG(0x02, 0x04) 174 #define TDA_PLL_SCG1 MKREG(0x02, 0x05) 175 #define TDA_PLL_SCG2 MKREG(0x02, 0x06) 176 #define TDA_PLL_SCGN1 MKREG(0x02, 0x07) 177 #define TDA_PLL_SCGN2 MKREG(0x02, 0x08) 178 #define TDA_PLL_SCGR1 MKREG(0x02, 0x09) 179 #define TDA_PLL_SCGR2 MKREG(0x02, 0x0a) 180 181 #define TDA_SEL_CLK MKREG(0x02, 0x11) 182 #define SEL_CLK_ENA_SC_CLK (1 << 3) 183 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 184 #define SEL_CLK_SEL_CLK1 (1 << 0) 185 #define TDA_ANA_GENERAL MKREG(0x02, 0x12) 186 187 #define TDA_EDID_DATA0 MKREG(0x09, 0x00) 188 #define TDA_EDID_CTRL MKREG(0x09, 0xfa) 189 #define TDA_DDC_ADDR MKREG(0x09, 0xfb) 190 #define TDA_DDC_OFFS MKREG(0x09, 0xfc) 191 #define TDA_DDC_SEGM_ADDR MKREG(0x09, 0xfd) 192 #define TDA_DDC_SEGM MKREG(0x09, 0xfe) 193 194 #define TDA_IF_VSP MKREG(0x10, 0x20) 195 #define TDA_IF_AVI MKREG(0x10, 0x40) 196 #define TDA_IF_SPD MKREG(0x10, 0x60) 197 #define TDA_IF_AUD MKREG(0x10, 0x80) 198 #define TDA_IF_MPS MKREG(0x10, 0xa0) 199 200 #define TDA_ENC_CNTRL MKREG(0x11, 0x0d) 201 #define ENC_CNTRL_DVI_MODE (0 << 2) 202 #define ENC_CNTRL_HDMI_MODE (1 << 2) 203 #define TDA_DIP_IF_FLAGS MKREG(0x11, 0x0f) 204 #define DIP_IF_FLAGS_IF5 (1 << 5) 205 #define DIP_IF_FLAGS_IF4 (1 << 4) 206 #define DIP_IF_FLAGS_IF3 (1 << 3) 207 #define DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */ 208 #define DIP_IF_FLAGS_IF1 (1 << 1) 209 210 #define TDA_TX3 MKREG(0x12, 0x9a) 211 #define TDA_TX4 MKREG(0x12, 0x9b) 212 #define TX4_PD_RAM (1 << 1) 213 #define TDA_HDCP_TX33 MKREG(0x12, 0xb8) 214 #define HDCP_TX33_HDMI (1 << 1) 215 216 #define TDA_CURPAGE_ADDR 0xff 217 218 #define TDA_CEC_RXSHPDLEV 0xfe 219 #define RXSHPDLEV_HPD __BIT(1) 220 221 #define TDA_CEC_ENAMODS 0xff 222 #define ENAMODS_RXSENS (1 << 2) 223 #define ENAMODS_HDMI (1 << 1) 224 #define TDA_CEC_FRO_IM_CLK_CTRL 0xfb 225 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 226 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 227 228 /* EDID reading */ 229 #define MAX_READ_ATTEMPTS 100 230 231 /* EDID fields */ 232 #define EDID_MODES0 35 233 #define EDID_MODES1 36 234 #define EDID_TIMING_START 38 235 #define EDID_TIMING_END 54 236 #define EDID_TIMING_X(v) (((v) + 31) * 8) 237 #define EDID_FREQ(v) (((v) & 0x3f) + 60) 238 #define EDID_RATIO(v) (((v) >> 6) & 0x3) 239 #define EDID_RATIO_10x16 0 240 #define EDID_RATIO_3x4 1 241 #define EDID_RATIO_4x5 2 242 #define EDID_RATIO_9x16 3 243 244 #define TDA19988 0x0301 245 246 static const struct device_compatible_entry compat_data[] = { 247 { "nxp,tda998x", 1 }, 248 { NULL } 249 }; 250 251 struct tda19988_softc; 252 253 struct tda19988_connector { 254 struct drm_connector base; 255 struct tda19988_softc *sc; 256 }; 257 258 struct tda19988_softc { 259 device_t sc_dev; 260 int sc_phandle; 261 i2c_tag_t sc_i2c; 262 i2c_addr_t sc_addr; 263 uint32_t sc_cec_addr; 264 uint16_t sc_version; 265 int sc_current_page; 266 uint8_t *sc_edid; 267 uint32_t sc_edid_len; 268 bool sc_edid_valid; 269 270 struct drm_bridge sc_bridge; 271 struct tda19988_connector sc_connector; 272 273 struct fdt_device_ports sc_ports; 274 275 enum drm_connector_status sc_last_status; 276 }; 277 278 #define to_tda_connector(x) container_of(x, struct tda19988_connector, base) 279 280 static int 281 tda19988_set_page(struct tda19988_softc *sc, uint8_t page) 282 { 283 uint8_t buf[2] = { TDA_CURPAGE_ADDR, page }; 284 int result; 285 286 result = iic_exec(sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, buf, 2, NULL, 0, 287 cold ? I2C_F_POLL : 0); 288 if (result == 0) 289 sc->sc_current_page = page; 290 291 return result; 292 } 293 294 static int 295 tda19988_cec_read(struct tda19988_softc *sc, uint8_t addr, uint8_t *data) 296 { 297 return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP, sc->sc_cec_addr, &addr, 1, data, 1, 298 cold ? I2C_F_POLL : 0); 299 } 300 301 static int 302 tda19988_cec_write(struct tda19988_softc *sc, uint8_t addr, uint8_t data) 303 { 304 uint8_t buf[2] = { addr, data }; 305 306 return iic_exec(sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, sc->sc_cec_addr, buf, 2, NULL, 0, 307 cold ? I2C_F_POLL : 0); 308 } 309 310 static int 311 tda19988_block_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data, int len) 312 { 313 uint8_t reg; 314 315 reg = REGADDR(addr); 316 317 if (sc->sc_current_page != REGPAGE(addr)) 318 tda19988_set_page(sc, REGPAGE(addr)); 319 320 return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP, sc->sc_addr, ®, 1, data, len, 321 cold ? I2C_F_POLL : 0); 322 } 323 324 static int 325 tda19988_reg_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data) 326 { 327 uint8_t reg; 328 329 reg = REGADDR(addr); 330 331 if (sc->sc_current_page != REGPAGE(addr)) 332 tda19988_set_page(sc, REGPAGE(addr)); 333 334 return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP, sc->sc_addr, ®, 1, data, 1, 335 cold ? I2C_F_POLL : 0); 336 } 337 338 static int 339 tda19988_reg_write(struct tda19988_softc *sc, uint16_t addr, uint8_t data) 340 { 341 uint8_t buf[2] = { REGADDR(addr), data }; 342 343 if (sc->sc_current_page != REGPAGE(addr)) 344 tda19988_set_page(sc, REGPAGE(addr)); 345 346 return iic_exec(sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, buf, 2, NULL, 0, 347 cold ? I2C_F_POLL : 0); 348 } 349 350 static int 351 tda19988_reg_write2(struct tda19988_softc *sc, uint16_t address, uint16_t data) 352 { 353 uint8_t buf[3]; 354 355 buf[0] = REGADDR(address); 356 buf[1] = (data >> 8); 357 buf[2] = (data & 0xff); 358 359 if (sc->sc_current_page != REGPAGE(address)) 360 tda19988_set_page(sc, REGPAGE(address)); 361 362 return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP, sc->sc_addr, buf, 3, NULL, 0, 363 cold ? I2C_F_POLL : 0); 364 } 365 366 static void 367 tda19988_reg_set(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) 368 { 369 uint8_t data; 370 371 tda19988_reg_read(sc, addr, &data); 372 data |= flags; 373 tda19988_reg_write(sc, addr, data); 374 } 375 376 static void 377 tda19988_reg_clear(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) 378 { 379 uint8_t data; 380 381 tda19988_reg_read(sc, addr, &data); 382 data &= ~flags; 383 tda19988_reg_write(sc, addr, data); 384 } 385 386 static int 387 tda19988_match(device_t parent, cfdata_t match, void *aux) 388 { 389 struct i2c_attach_args * const ia = aux; 390 int match_result; 391 392 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 393 return match_result; 394 395 return 0; 396 } 397 398 static void 399 tda19988_init_encoder(struct tda19988_softc *sc, const struct drm_display_mode *mode) 400 { 401 uint16_t ref_pix, ref_line, n_pix, n_line; 402 uint16_t hs_pix_start, hs_pix_stop; 403 uint16_t vs1_pix_start, vs1_pix_stop; 404 uint16_t vs1_line_start, vs1_line_end; 405 uint16_t vs2_pix_start, vs2_pix_stop; 406 uint16_t vs2_line_start, vs2_line_end; 407 uint16_t vwin1_line_start, vwin1_line_end; 408 uint16_t vwin2_line_start, vwin2_line_end; 409 uint16_t de_start, de_stop; 410 uint8_t reg, div; 411 412 n_pix = mode->crtc_htotal; 413 n_line = mode->crtc_vtotal; 414 415 hs_pix_stop = mode->crtc_hsync_end - mode->crtc_hdisplay; 416 hs_pix_start = mode->crtc_hsync_start - mode->crtc_hdisplay; 417 418 de_stop = mode->crtc_htotal; 419 de_start = mode->crtc_htotal - mode->crtc_hdisplay; 420 ref_pix = hs_pix_start + 3; 421 422 if (mode->flags & DRM_MODE_FLAG_HSKEW) 423 ref_pix += mode->crtc_hskew; 424 425 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 426 ref_line = 1 + mode->crtc_vsync_start - mode->crtc_vdisplay; 427 vwin1_line_start = mode->crtc_vtotal - mode->crtc_vdisplay - 1; 428 vwin1_line_end = vwin1_line_start + mode->crtc_vdisplay; 429 430 vs1_pix_start = vs1_pix_stop = hs_pix_start; 431 vs1_line_start = mode->crtc_vsync_start - mode->crtc_vdisplay; 432 vs1_line_end = vs1_line_start + mode->crtc_vsync_end - mode->crtc_vsync_start; 433 434 vwin2_line_start = vwin2_line_end = 0; 435 vs2_pix_start = vs2_pix_stop = 0; 436 vs2_line_start = vs2_line_end = 0; 437 } else { 438 ref_line = 1 + (mode->crtc_vsync_start - mode->crtc_vdisplay)/2; 439 vwin1_line_start = (mode->crtc_vtotal - mode->crtc_vdisplay)/2; 440 vwin1_line_end = vwin1_line_start + mode->crtc_vdisplay/2; 441 442 vs1_pix_start = vs1_pix_stop = hs_pix_start; 443 vs1_line_start = (mode->crtc_vsync_start - mode->crtc_vdisplay)/2; 444 vs1_line_end = vs1_line_start + (mode->crtc_vsync_end - mode->crtc_vsync_start)/2; 445 446 vwin2_line_start = vwin1_line_start + mode->crtc_vtotal/2; 447 vwin2_line_end = vwin2_line_start + mode->crtc_vdisplay/2; 448 449 vs2_pix_start = vs2_pix_stop = hs_pix_start + mode->crtc_htotal/2; 450 vs2_line_start = vs1_line_start + mode->crtc_vtotal/2 ; 451 vs2_line_end = vs2_line_start + (mode->crtc_vsync_end - mode->crtc_vsync_start)/2; 452 } 453 454 div = 148500 / mode->crtc_clock; 455 if (div != 0) { 456 div--; 457 if (div > 3) 458 div = 3; 459 } 460 461 /* set HDMI HDCP mode off */ 462 tda19988_reg_set(sc, TDA_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 463 tda19988_reg_clear(sc, TDA_HDCP_TX33, HDCP_TX33_HDMI); 464 tda19988_reg_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE); 465 466 /* no pre-filter or interpolator */ 467 tda19988_reg_write(sc, TDA_HVF_CNTRL_0, 468 HVF_CNTRL_0_INTPOL_BYPASS | HVF_CNTRL_0_PREFIL_NONE); 469 tda19988_reg_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 470 tda19988_reg_write(sc, TDA_VIP_CNTRL_4, 471 VIP_CNTRL_4_BLANKIT_NDE | VIP_CNTRL_4_BLC_NONE); 472 473 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 474 tda19988_reg_clear(sc, TDA_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IP); 475 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 476 tda19988_reg_write(sc, TDA_SERIALIZER, 0); 477 tda19988_reg_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL); 478 479 tda19988_reg_write(sc, TDA_RPT_CNTRL, 0); 480 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 481 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 482 483 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 484 PLL_SERIAL_2_SRL_PR(0)); 485 486 tda19988_reg_set(sc, TDA_MAT_CONTRL, MAT_CONTRL_MAT_BP); 487 488 tda19988_reg_write(sc, TDA_ANA_GENERAL, 0x09); 489 490 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 491 492 /* 493 * Sync on rising HSYNC/VSYNC 494 */ 495 reg = VIP_CNTRL_3_SYNC_HS; 496 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 497 reg |= VIP_CNTRL_3_H_TGL; 498 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 499 reg |= VIP_CNTRL_3_V_TGL; 500 tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg); 501 502 reg = TBG_CNTRL_1_TGL_EN; 503 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 504 reg |= TBG_CNTRL_1_H_TGL; 505 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 506 reg |= TBG_CNTRL_1_V_TGL; 507 tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg); 508 509 /* Program timing */ 510 tda19988_reg_write(sc, TDA_VIDFORMAT, 0x00); 511 512 tda19988_reg_write2(sc, TDA_REFPIX_MSB, ref_pix); 513 tda19988_reg_write2(sc, TDA_REFLINE_MSB, ref_line); 514 tda19988_reg_write2(sc, TDA_NPIX_MSB, n_pix); 515 tda19988_reg_write2(sc, TDA_NLINE_MSB, n_line); 516 517 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_1_MSB, vs1_line_start); 518 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_1_MSB, vs1_pix_start); 519 tda19988_reg_write2(sc, TDA_VS_LINE_END_1_MSB, vs1_line_end); 520 tda19988_reg_write2(sc, TDA_VS_PIX_END_1_MSB, vs1_pix_stop); 521 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_2_MSB, vs2_line_start); 522 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_2_MSB, vs2_pix_start); 523 tda19988_reg_write2(sc, TDA_VS_LINE_END_2_MSB, vs2_line_end); 524 tda19988_reg_write2(sc, TDA_VS_PIX_END_2_MSB, vs2_pix_stop); 525 tda19988_reg_write2(sc, TDA_HS_PIX_START_MSB, hs_pix_start); 526 tda19988_reg_write2(sc, TDA_HS_PIX_STOP_MSB, hs_pix_stop); 527 tda19988_reg_write2(sc, TDA_VWIN_START_1_MSB, vwin1_line_start); 528 tda19988_reg_write2(sc, TDA_VWIN_END_1_MSB, vwin1_line_end); 529 tda19988_reg_write2(sc, TDA_VWIN_START_2_MSB, vwin2_line_start); 530 tda19988_reg_write2(sc, TDA_VWIN_END_2_MSB, vwin2_line_end); 531 tda19988_reg_write2(sc, TDA_DE_START_MSB, de_start); 532 tda19988_reg_write2(sc, TDA_DE_STOP_MSB, de_stop); 533 534 if (sc->sc_version == TDA19988) 535 tda19988_reg_write(sc, TDA_ENABLE_SPACE, 0x00); 536 537 /* must be last register set */ 538 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 539 } 540 541 static int 542 tda19988_read_edid_block(struct tda19988_softc *sc, uint8_t *buf, int block) 543 { 544 int attempt, err; 545 uint8_t data; 546 547 err = 0; 548 549 tda19988_reg_set(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 550 551 /* Block 0 */ 552 tda19988_reg_write(sc, TDA_DDC_ADDR, 0xa0); 553 tda19988_reg_write(sc, TDA_DDC_OFFS, (block % 2) ? 128 : 0); 554 tda19988_reg_write(sc, TDA_DDC_SEGM_ADDR, 0x60); 555 tda19988_reg_write(sc, TDA_DDC_SEGM, block / 2); 556 557 tda19988_reg_write(sc, TDA_EDID_CTRL, 1); 558 tda19988_reg_write(sc, TDA_EDID_CTRL, 0); 559 560 data = 0; 561 for (attempt = 0; attempt < MAX_READ_ATTEMPTS; attempt++) { 562 tda19988_reg_read(sc, TDA_INT_FLAGS_2, &data); 563 if (data & INT_FLAGS_2_EDID_BLK_RD) 564 break; 565 delay(1000); 566 } 567 568 if (attempt == MAX_READ_ATTEMPTS) { 569 err = -1; 570 goto done; 571 } 572 573 if (tda19988_block_read(sc, TDA_EDID_DATA0, buf, EDID_LENGTH) != 0) { 574 err = -1; 575 goto done; 576 } 577 578 done: 579 tda19988_reg_clear(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 580 581 return (err); 582 } 583 584 static int 585 tda19988_read_edid(struct tda19988_softc *sc) 586 { 587 int err; 588 int blocks, i; 589 uint8_t *buf, *edid; 590 591 err = 0; 592 if (sc->sc_version == TDA19988) 593 tda19988_reg_clear(sc, TDA_TX4, TX4_PD_RAM); 594 595 err = tda19988_read_edid_block(sc, sc->sc_edid, 0); 596 if (err) 597 goto done; 598 599 blocks = sc->sc_edid[0x7e]; 600 if (blocks > 0) { 601 if (sc->sc_edid_len != EDID_LENGTH*(blocks+1)) { 602 edid = kmem_zalloc(EDID_LENGTH*(blocks+1), KM_SLEEP); 603 memcpy(edid, sc->sc_edid, EDID_LENGTH); 604 kmem_free(sc->sc_edid, sc->sc_edid_len); 605 sc->sc_edid = edid; 606 sc->sc_edid_len = EDID_LENGTH*(blocks+1); 607 } 608 for (i = 0; i < blocks; i++) { 609 /* TODO: check validity */ 610 buf = sc->sc_edid + EDID_LENGTH*(i+1); 611 err = tda19988_read_edid_block(sc, buf, i); 612 if (err) 613 goto done; 614 } 615 } 616 617 done: 618 if (sc->sc_version == TDA19988) 619 tda19988_reg_set(sc, TDA_TX4, TX4_PD_RAM); 620 621 return (err); 622 } 623 624 static void 625 tda19988_start(struct tda19988_softc *sc) 626 { 627 device_t dev; 628 uint8_t data; 629 uint16_t ver; 630 631 dev = sc->sc_dev; 632 633 tda19988_cec_write(sc, TDA_CEC_ENAMODS, ENAMODS_RXSENS | ENAMODS_HDMI); 634 DELAY(1000); 635 tda19988_cec_read(sc, TDA_CEC_RXSHPDLEV, &data); 636 637 /* Reset core */ 638 tda19988_reg_set(sc, TDA_SOFTRESET, 3); 639 DELAY(100); 640 tda19988_reg_clear(sc, TDA_SOFTRESET, 3); 641 DELAY(100); 642 643 /* reset transmitter: */ 644 tda19988_reg_set(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); 645 tda19988_reg_clear(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); 646 647 /* PLL registers common configuration */ 648 tda19988_reg_write(sc, TDA_PLL_SERIAL_1, 0x00); 649 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 650 tda19988_reg_write(sc, TDA_PLL_SERIAL_3, 0x00); 651 tda19988_reg_write(sc, TDA_SERIALIZER, 0x00); 652 tda19988_reg_write(sc, TDA_BUFFER_OUT, 0x00); 653 tda19988_reg_write(sc, TDA_PLL_SCG1, 0x00); 654 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 655 tda19988_reg_write(sc, TDA_PLL_SCGN1, 0xfa); 656 tda19988_reg_write(sc, TDA_PLL_SCGN2, 0x00); 657 tda19988_reg_write(sc, TDA_PLL_SCGR1, 0x5b); 658 tda19988_reg_write(sc, TDA_PLL_SCGR2, 0x00); 659 tda19988_reg_write(sc, TDA_PLL_SCG2, 0x10); 660 661 /* Write the default value MUX register */ 662 tda19988_reg_write(sc, TDA_MUX_VP_VIP_OUT, 0x24); 663 664 ver = 0; 665 tda19988_reg_read(sc, TDA_VERSION, &data); 666 ver |= data; 667 tda19988_reg_read(sc, TDA_VERSION_MSB, &data); 668 ver |= (data << 8); 669 670 /* Clear feature bits */ 671 sc->sc_version = ver & ~0x30; 672 switch (sc->sc_version) { 673 case TDA19988: 674 device_printf(dev, "TDA19988\n"); 675 break; 676 default: 677 device_printf(dev, "Unknown device: %04x\n", sc->sc_version); 678 return; 679 } 680 681 tda19988_reg_write(sc, TDA_DDC_CTRL, DDC_ENABLE); 682 tda19988_reg_write(sc, TDA_TX3, 39); 683 684 tda19988_cec_write(sc, TDA_CEC_FRO_IM_CLK_CTRL, 685 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 686 687 /* Default values for RGB 4:4:4 mapping */ 688 tda19988_reg_write(sc, TDA_VIP_CNTRL_0, 0x23); 689 tda19988_reg_write(sc, TDA_VIP_CNTRL_1, 0x01); 690 tda19988_reg_write(sc, TDA_VIP_CNTRL_2, 0x45); 691 } 692 693 static enum drm_connector_status 694 tda19988_connector_detect(struct drm_connector *connector, bool force) 695 { 696 struct tda19988_connector *tda_connector = to_tda_connector(connector); 697 struct tda19988_softc * const sc = tda_connector->sc; 698 enum drm_connector_status status; 699 uint8_t data = 0; 700 701 iic_acquire_bus(sc->sc_i2c, cold ? I2C_F_POLL : 0); 702 tda19988_cec_read(sc, TDA_CEC_RXSHPDLEV, &data); 703 iic_release_bus(sc->sc_i2c, cold ? I2C_F_POLL : 0); 704 705 status = (data & RXSHPDLEV_HPD) ? 706 connector_status_connected : 707 connector_status_disconnected; 708 709 /* On connect, invalidate the last EDID */ 710 if (status == connector_status_connected && 711 sc->sc_last_status != connector_status_connected) 712 sc->sc_edid_valid = false; 713 714 sc->sc_last_status = status; 715 716 return status; 717 } 718 719 static void 720 tda19988_connector_destroy(struct drm_connector *connector) 721 { 722 drm_connector_unregister(connector); 723 drm_connector_cleanup(connector); 724 } 725 726 static const struct drm_connector_funcs tda19988_connector_funcs = { 727 .dpms = drm_helper_connector_dpms, 728 .detect = tda19988_connector_detect, 729 .fill_modes = drm_helper_probe_single_connector_modes, 730 .destroy = tda19988_connector_destroy, 731 }; 732 733 static int 734 tda19988_connector_get_modes(struct drm_connector *connector) 735 { 736 struct tda19988_connector *tda_connector = to_tda_connector(connector); 737 struct tda19988_softc * const sc = tda_connector->sc; 738 struct edid *pedid = NULL; 739 int error; 740 741 if (sc->sc_edid_valid) { 742 pedid = (struct edid *)sc->sc_edid; 743 } else { 744 iic_acquire_bus(sc->sc_i2c, cold ? I2C_F_POLL : 0); 745 if (tda19988_read_edid(sc) == 0) 746 pedid = (struct edid *)sc->sc_edid; 747 iic_release_bus(sc->sc_i2c, cold ? I2C_F_POLL : 0); 748 sc->sc_edid_valid = true; 749 } 750 751 drm_mode_connector_update_edid_property(connector, pedid); 752 if (pedid == NULL) 753 return 0; 754 755 error = drm_add_edid_modes(connector, pedid); 756 drm_edid_to_eld(connector, pedid); 757 758 return error; 759 } 760 761 static struct drm_encoder * 762 tda19988_connector_best_encoder(struct drm_connector *connector) 763 { 764 int enc_id = connector->encoder_ids[0]; 765 struct drm_mode_object *obj; 766 struct drm_encoder *encoder = NULL; 767 768 if (enc_id) { 769 obj = drm_mode_object_find(connector->dev, enc_id, 770 DRM_MODE_OBJECT_ENCODER); 771 if (obj == NULL) 772 return NULL; 773 encoder = obj_to_encoder(obj); 774 } 775 776 return encoder; 777 } 778 779 static const struct drm_connector_helper_funcs tda19988_connector_helper_funcs = { 780 .get_modes = tda19988_connector_get_modes, 781 .best_encoder = tda19988_connector_best_encoder, 782 }; 783 784 static int 785 tda19988_bridge_attach(struct drm_bridge *bridge) 786 { 787 struct tda19988_softc *sc = bridge->driver_private; 788 struct tda19988_connector *tda_connector = &sc->sc_connector; 789 struct drm_connector *connector = &tda_connector->base; 790 int error; 791 792 tda_connector->sc = sc; 793 794 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 795 connector->interlace_allowed = 1; 796 connector->doublescan_allowed = 0; 797 798 drm_connector_init(bridge->dev, connector, &tda19988_connector_funcs, 799 DRM_MODE_CONNECTOR_HDMIA); 800 drm_connector_helper_add(connector, &tda19988_connector_helper_funcs); 801 802 error = drm_mode_connector_attach_encoder(connector, bridge->encoder); 803 if (error != 0) 804 return error; 805 806 return drm_connector_register(connector); 807 } 808 809 static void 810 tda19988_bridge_enable(struct drm_bridge *bridge) 811 { 812 struct tda19988_softc * const sc = bridge->driver_private; 813 814 fdtbus_pinctrl_set_config(sc->sc_phandle, "default"); 815 } 816 817 static void 818 tda19988_bridge_pre_enable(struct drm_bridge *bridge) 819 { 820 } 821 822 static void 823 tda19988_bridge_disable(struct drm_bridge *bridge) 824 { 825 struct tda19988_softc * const sc = bridge->driver_private; 826 827 fdtbus_pinctrl_set_config(sc->sc_phandle, "off"); 828 } 829 830 static void 831 tda19988_bridge_post_disable(struct drm_bridge *bridge) 832 { 833 } 834 835 static void 836 tda19988_bridge_mode_set(struct drm_bridge *bridge, 837 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 838 { 839 struct tda19988_softc * const sc = bridge->driver_private; 840 841 iic_acquire_bus(sc->sc_i2c, cold ? I2C_F_POLL : 0); 842 tda19988_init_encoder(sc, adjusted_mode); 843 iic_release_bus(sc->sc_i2c, cold ? I2C_F_POLL : 0); 844 } 845 846 static bool 847 tda19988_bridge_mode_fixup(struct drm_bridge *bridge, 848 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 849 { 850 return true; 851 } 852 853 static const struct drm_bridge_funcs tda19988_bridge_funcs = { 854 .attach = tda19988_bridge_attach, 855 .enable = tda19988_bridge_enable, 856 .pre_enable = tda19988_bridge_pre_enable, 857 .disable = tda19988_bridge_disable, 858 .post_disable = tda19988_bridge_post_disable, 859 .mode_set = tda19988_bridge_mode_set, 860 .mode_fixup = tda19988_bridge_mode_fixup, 861 }; 862 863 static int 864 tda19988_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 865 { 866 struct tda19988_softc *sc = device_private(dev); 867 struct fdt_endpoint *in_ep = fdt_endpoint_remote(ep); 868 struct drm_encoder *encoder; 869 int error; 870 871 if (!activate) 872 return EINVAL; 873 874 if (fdt_endpoint_port_index(ep) != TDA19988_PORT_INPUT) 875 return EINVAL; 876 877 switch (fdt_endpoint_type(in_ep)) { 878 case EP_DRM_ENCODER: 879 encoder = fdt_endpoint_get_data(in_ep); 880 break; 881 default: 882 encoder = NULL; 883 break; 884 } 885 886 if (encoder == NULL) 887 return EINVAL; 888 889 sc->sc_bridge.driver_private = sc; 890 sc->sc_bridge.funcs = &tda19988_bridge_funcs; 891 sc->sc_bridge.encoder = encoder; 892 error = drm_bridge_attach(encoder->dev, &sc->sc_bridge); 893 if (error != 0) 894 return EIO; 895 896 encoder->bridge = &sc->sc_bridge; 897 898 return 0; 899 } 900 901 static void * 902 tda19988_ep_get_data(device_t dev, struct fdt_endpoint *ep) 903 { 904 struct tda19988_softc *sc = device_private(dev); 905 906 return &sc->sc_bridge; 907 } 908 909 static void 910 tda19988_attach(device_t parent, device_t self, void *aux) 911 { 912 struct tda19988_softc *sc = device_private(self); 913 struct i2c_attach_args * const ia = aux; 914 const int phandle = ia->ia_cookie; 915 916 sc->sc_dev = self; 917 sc->sc_phandle = phandle; 918 sc->sc_i2c = ia->ia_tag; 919 sc->sc_addr = ia->ia_addr; 920 sc->sc_cec_addr = 0x34; /* hardcoded */ 921 sc->sc_current_page = 0xff; 922 sc->sc_edid = kmem_zalloc(EDID_LENGTH, KM_SLEEP); 923 sc->sc_edid_len = EDID_LENGTH; 924 sc->sc_edid_valid = false; 925 sc->sc_last_status = connector_status_unknown; 926 927 aprint_naive("\n"); 928 aprint_normal(": NXP TDA19988 HDMI transmitter\n"); 929 930 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 931 tda19988_start(sc); 932 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 933 934 sc->sc_ports.dp_ep_activate = tda19988_ep_activate; 935 sc->sc_ports.dp_ep_get_data = tda19988_ep_get_data; 936 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_ENCODER); 937 } 938 939 CFATTACH_DECL_NEW(tdahdmi, sizeof(struct tda19988_softc), 940 tda19988_match, tda19988_attach, NULL, NULL); 941
Indexes created Thu Oct 02 01:09:59 GMT 2025