iop.c revision 1.10.2.15 1 1.10.2.14 nathanw /* $NetBSD: iop.c,v 1.10.2.15 2002/10/18 02:41:42 nathanw Exp $ */
2 1.1 ad
3 1.1 ad /*-
4 1.10.2.2 nathanw * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 1.1 ad * All rights reserved.
6 1.1 ad *
7 1.1 ad * This code is derived from software contributed to The NetBSD Foundation
8 1.1 ad * by Andrew Doran.
9 1.1 ad *
10 1.1 ad * Redistribution and use in source and binary forms, with or without
11 1.1 ad * modification, are permitted provided that the following conditions
12 1.1 ad * are met:
13 1.1 ad * 1. Redistributions of source code must retain the above copyright
14 1.1 ad * notice, this list of conditions and the following disclaimer.
15 1.1 ad * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 ad * notice, this list of conditions and the following disclaimer in the
17 1.1 ad * documentation and/or other materials provided with the distribution.
18 1.1 ad * 3. All advertising materials mentioning features or use of this software
19 1.1 ad * must display the following acknowledgement:
20 1.1 ad * This product includes software developed by the NetBSD
21 1.1 ad * Foundation, Inc. and its contributors.
22 1.1 ad * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 ad * contributors may be used to endorse or promote products derived
24 1.1 ad * from this software without specific prior written permission.
25 1.1 ad *
26 1.1 ad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 ad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 ad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 ad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 ad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 ad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 ad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 ad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 ad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 ad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 ad * POSSIBILITY OF SUCH DAMAGE.
37 1.1 ad */
38 1.1 ad
39 1.1 ad /*
40 1.1 ad * Support for I2O IOPs (intelligent I/O processors).
41 1.1 ad */
42 1.10.2.8 nathanw
43 1.10.2.8 nathanw #include <sys/cdefs.h>
44 1.10.2.14 nathanw __KERNEL_RCSID(0, "$NetBSD: iop.c,v 1.10.2.15 2002/10/18 02:41:42 nathanw Exp $");
45 1.1 ad
46 1.1 ad #include "opt_i2o.h"
47 1.5 ad #include "iop.h"
48 1.1 ad
49 1.1 ad #include <sys/param.h>
50 1.1 ad #include <sys/systm.h>
51 1.1 ad #include <sys/kernel.h>
52 1.1 ad #include <sys/device.h>
53 1.1 ad #include <sys/queue.h>
54 1.1 ad #include <sys/proc.h>
55 1.1 ad #include <sys/malloc.h>
56 1.1 ad #include <sys/ioctl.h>
57 1.1 ad #include <sys/endian.h>
58 1.5 ad #include <sys/conf.h>
59 1.5 ad #include <sys/kthread.h>
60 1.1 ad
61 1.4 thorpej #include <uvm/uvm_extern.h>
62 1.4 thorpej
63 1.1 ad #include <machine/bus.h>
64 1.1 ad
65 1.1 ad #include <dev/i2o/i2o.h>
66 1.10.2.2 nathanw #include <dev/i2o/iopio.h>
67 1.1 ad #include <dev/i2o/iopreg.h>
68 1.1 ad #include <dev/i2o/iopvar.h>
69 1.1 ad
70 1.1 ad #define POLL(ms, cond) \
71 1.1 ad do { \
72 1.1 ad int i; \
73 1.1 ad for (i = (ms) * 10; i; i--) { \
74 1.1 ad if (cond) \
75 1.1 ad break; \
76 1.1 ad DELAY(100); \
77 1.1 ad } \
78 1.1 ad } while (/* CONSTCOND */0);
79 1.1 ad
80 1.1 ad #ifdef I2ODEBUG
81 1.1 ad #define DPRINTF(x) printf x
82 1.1 ad #else
83 1.1 ad #define DPRINTF(x)
84 1.1 ad #endif
85 1.1 ad
86 1.1 ad #ifdef I2OVERBOSE
87 1.5 ad #define IFVERBOSE(x) x
88 1.10.2.2 nathanw #define COMMENT(x) NULL
89 1.1 ad #else
90 1.1 ad #define IFVERBOSE(x)
91 1.10.2.2 nathanw #define COMMENT(x)
92 1.1 ad #endif
93 1.1 ad
94 1.5 ad #define IOP_ICTXHASH_NBUCKETS 16
95 1.5 ad #define IOP_ICTXHASH(ictx) (&iop_ictxhashtbl[(ictx) & iop_ictxhash])
96 1.10.2.2 nathanw
97 1.10.2.2 nathanw #define IOP_MAX_SEGS (((IOP_MAX_XFER + PAGE_SIZE - 1) / PAGE_SIZE) + 1)
98 1.10.2.2 nathanw
99 1.10.2.2 nathanw #define IOP_TCTX_SHIFT 12
100 1.10.2.2 nathanw #define IOP_TCTX_MASK ((1 << IOP_TCTX_SHIFT) - 1)
101 1.5 ad
102 1.5 ad static LIST_HEAD(, iop_initiator) *iop_ictxhashtbl;
103 1.5 ad static u_long iop_ictxhash;
104 1.1 ad static void *iop_sdh;
105 1.5 ad static struct i2o_systab *iop_systab;
106 1.5 ad static int iop_systab_size;
107 1.1 ad
108 1.1 ad extern struct cfdriver iop_cd;
109 1.1 ad
110 1.10.2.14 nathanw dev_type_open(iopopen);
111 1.10.2.14 nathanw dev_type_close(iopclose);
112 1.10.2.14 nathanw dev_type_ioctl(iopioctl);
113 1.10.2.14 nathanw
114 1.10.2.14 nathanw const struct cdevsw iop_cdevsw = {
115 1.10.2.14 nathanw iopopen, iopclose, noread, nowrite, iopioctl,
116 1.10.2.14 nathanw nostop, notty, nopoll, nommap,
117 1.10.2.14 nathanw };
118 1.10.2.14 nathanw
119 1.5 ad #define IC_CONFIGURE 0x01
120 1.10.2.2 nathanw #define IC_PRIORITY 0x02
121 1.1 ad
122 1.1 ad struct iop_class {
123 1.5 ad u_short ic_class;
124 1.5 ad u_short ic_flags;
125 1.10.2.2 nathanw #ifdef I2OVERBOSE
126 1.1 ad const char *ic_caption;
127 1.10.2.2 nathanw #endif
128 1.1 ad } static const iop_class[] = {
129 1.1 ad {
130 1.1 ad I2O_CLASS_EXECUTIVE,
131 1.1 ad 0,
132 1.5 ad COMMENT("executive")
133 1.1 ad },
134 1.1 ad {
135 1.1 ad I2O_CLASS_DDM,
136 1.1 ad 0,
137 1.5 ad COMMENT("device driver module")
138 1.1 ad },
139 1.1 ad {
140 1.1 ad I2O_CLASS_RANDOM_BLOCK_STORAGE,
141 1.10.2.2 nathanw IC_CONFIGURE | IC_PRIORITY,
142 1.1 ad IFVERBOSE("random block storage")
143 1.1 ad },
144 1.1 ad {
145 1.1 ad I2O_CLASS_SEQUENTIAL_STORAGE,
146 1.10.2.2 nathanw IC_CONFIGURE | IC_PRIORITY,
147 1.1 ad IFVERBOSE("sequential storage")
148 1.1 ad },
149 1.1 ad {
150 1.1 ad I2O_CLASS_LAN,
151 1.10.2.2 nathanw IC_CONFIGURE | IC_PRIORITY,
152 1.1 ad IFVERBOSE("LAN port")
153 1.1 ad },
154 1.1 ad {
155 1.1 ad I2O_CLASS_WAN,
156 1.10.2.2 nathanw IC_CONFIGURE | IC_PRIORITY,
157 1.1 ad IFVERBOSE("WAN port")
158 1.1 ad },
159 1.1 ad {
160 1.1 ad I2O_CLASS_FIBRE_CHANNEL_PORT,
161 1.1 ad IC_CONFIGURE,
162 1.1 ad IFVERBOSE("fibrechannel port")
163 1.1 ad },
164 1.1 ad {
165 1.1 ad I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL,
166 1.1 ad 0,
167 1.5 ad COMMENT("fibrechannel peripheral")
168 1.1 ad },
169 1.1 ad {
170 1.1 ad I2O_CLASS_SCSI_PERIPHERAL,
171 1.1 ad 0,
172 1.5 ad COMMENT("SCSI peripheral")
173 1.1 ad },
174 1.1 ad {
175 1.1 ad I2O_CLASS_ATE_PORT,
176 1.1 ad IC_CONFIGURE,
177 1.1 ad IFVERBOSE("ATE port")
178 1.1 ad },
179 1.1 ad {
180 1.1 ad I2O_CLASS_ATE_PERIPHERAL,
181 1.1 ad 0,
182 1.5 ad COMMENT("ATE peripheral")
183 1.1 ad },
184 1.1 ad {
185 1.1 ad I2O_CLASS_FLOPPY_CONTROLLER,
186 1.1 ad IC_CONFIGURE,
187 1.1 ad IFVERBOSE("floppy controller")
188 1.1 ad },
189 1.1 ad {
190 1.1 ad I2O_CLASS_FLOPPY_DEVICE,
191 1.1 ad 0,
192 1.5 ad COMMENT("floppy device")
193 1.1 ad },
194 1.1 ad {
195 1.1 ad I2O_CLASS_BUS_ADAPTER_PORT,
196 1.1 ad IC_CONFIGURE,
197 1.1 ad IFVERBOSE("bus adapter port" )
198 1.1 ad },
199 1.1 ad };
200 1.1 ad
201 1.1 ad #if defined(I2ODEBUG) && defined(I2OVERBOSE)
202 1.10.2.2 nathanw static const char * const iop_status[] = {
203 1.1 ad "success",
204 1.1 ad "abort (dirty)",
205 1.1 ad "abort (no data transfer)",
206 1.1 ad "abort (partial transfer)",
207 1.1 ad "error (dirty)",
208 1.1 ad "error (no data transfer)",
209 1.1 ad "error (partial transfer)",
210 1.1 ad "undefined error code",
211 1.1 ad "process abort (dirty)",
212 1.1 ad "process abort (no data transfer)",
213 1.1 ad "process abort (partial transfer)",
214 1.1 ad "transaction error",
215 1.1 ad };
216 1.1 ad #endif
217 1.1 ad
218 1.5 ad static inline u_int32_t iop_inl(struct iop_softc *, int);
219 1.5 ad static inline void iop_outl(struct iop_softc *, int, u_int32_t);
220 1.5 ad
221 1.1 ad static void iop_config_interrupts(struct device *);
222 1.10.2.2 nathanw static void iop_configure_devices(struct iop_softc *, int, int);
223 1.1 ad static void iop_devinfo(int, char *);
224 1.1 ad static int iop_print(void *, const char *);
225 1.1 ad static void iop_shutdown(void *);
226 1.1 ad static int iop_submatch(struct device *, struct cfdata *, void *);
227 1.1 ad static int iop_vendor_print(void *, const char *);
228 1.1 ad
229 1.10.2.2 nathanw static void iop_adjqparam(struct iop_softc *, int);
230 1.9 ad static void iop_create_reconf_thread(void *);
231 1.10.2.2 nathanw static int iop_handle_reply(struct iop_softc *, u_int32_t);
232 1.1 ad static int iop_hrt_get(struct iop_softc *);
233 1.1 ad static int iop_hrt_get0(struct iop_softc *, struct i2o_hrt *, int);
234 1.10.2.2 nathanw static void iop_intr_event(struct device *, struct iop_msg *, void *);
235 1.5 ad static int iop_lct_get0(struct iop_softc *, struct i2o_lct *, int,
236 1.5 ad u_int32_t);
237 1.10.2.2 nathanw static void iop_msg_poll(struct iop_softc *, struct iop_msg *, int);
238 1.10.2.2 nathanw static void iop_msg_wait(struct iop_softc *, struct iop_msg *, int);
239 1.1 ad static int iop_ofifo_init(struct iop_softc *);
240 1.10.2.4 nathanw static int iop_passthrough(struct iop_softc *, struct ioppt *,
241 1.10.2.4 nathanw struct proc *);
242 1.9 ad static void iop_reconf_thread(void *);
243 1.1 ad static void iop_release_mfa(struct iop_softc *, u_int32_t);
244 1.1 ad static int iop_reset(struct iop_softc *);
245 1.1 ad static int iop_systab_set(struct iop_softc *);
246 1.10.2.2 nathanw static void iop_tfn_print(struct iop_softc *, struct i2o_fault_notify *);
247 1.1 ad
248 1.1 ad #ifdef I2ODEBUG
249 1.10.2.2 nathanw static void iop_reply_print(struct iop_softc *, struct i2o_reply *);
250 1.1 ad #endif
251 1.5 ad
252 1.5 ad static inline u_int32_t
253 1.5 ad iop_inl(struct iop_softc *sc, int off)
254 1.5 ad {
255 1.5 ad
256 1.5 ad bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4,
257 1.5 ad BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ);
258 1.5 ad return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off));
259 1.5 ad }
260 1.5 ad
261 1.5 ad static inline void
262 1.5 ad iop_outl(struct iop_softc *sc, int off, u_int32_t val)
263 1.5 ad {
264 1.5 ad
265 1.5 ad bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
266 1.5 ad bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4,
267 1.5 ad BUS_SPACE_BARRIER_WRITE);
268 1.5 ad }
269 1.5 ad
270 1.1 ad /*
271 1.10.2.2 nathanw * Initialise the IOP and our interface.
272 1.1 ad */
273 1.5 ad void
274 1.1 ad iop_init(struct iop_softc *sc, const char *intrstr)
275 1.1 ad {
276 1.10.2.2 nathanw struct iop_msg *im;
277 1.10.2.4 nathanw int rv, i, j, state, nsegs;
278 1.1 ad u_int32_t mask;
279 1.1 ad char ident[64];
280 1.1 ad
281 1.10.2.4 nathanw state = 0;
282 1.10.2.4 nathanw
283 1.10.2.4 nathanw printf("I2O adapter");
284 1.10.2.4 nathanw
285 1.10.2.2 nathanw if (iop_ictxhashtbl == NULL)
286 1.5 ad iop_ictxhashtbl = hashinit(IOP_ICTXHASH_NBUCKETS, HASH_LIST,
287 1.5 ad M_DEVBUF, M_NOWAIT, &iop_ictxhash);
288 1.1 ad
289 1.10.2.4 nathanw /* Disable interrupts at the IOP. */
290 1.10.2.4 nathanw mask = iop_inl(sc, IOP_REG_INTR_MASK);
291 1.10.2.4 nathanw iop_outl(sc, IOP_REG_INTR_MASK, mask | IOP_INTR_OFIFO);
292 1.5 ad
293 1.10.2.4 nathanw /* Allocate a scratch DMA map for small miscellaneous shared data. */
294 1.10.2.4 nathanw if (bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0,
295 1.10.2.4 nathanw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_scr_dmamap) != 0) {
296 1.10.2.4 nathanw printf("%s: cannot create scratch dmamap\n",
297 1.10.2.4 nathanw sc->sc_dv.dv_xname);
298 1.5 ad return;
299 1.1 ad }
300 1.10.2.4 nathanw
301 1.10.2.4 nathanw if (bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 0,
302 1.10.2.4 nathanw sc->sc_scr_seg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) {
303 1.10.2.4 nathanw printf("%s: cannot alloc scratch dmamem\n",
304 1.10.2.4 nathanw sc->sc_dv.dv_xname);
305 1.10.2.4 nathanw goto bail_out;
306 1.10.2.4 nathanw }
307 1.10.2.4 nathanw state++;
308 1.10.2.4 nathanw
309 1.10.2.4 nathanw if (bus_dmamem_map(sc->sc_dmat, sc->sc_scr_seg, nsegs, PAGE_SIZE,
310 1.10.2.4 nathanw &sc->sc_scr, 0)) {
311 1.10.2.4 nathanw printf("%s: cannot map scratch dmamem\n", sc->sc_dv.dv_xname);
312 1.10.2.4 nathanw goto bail_out;
313 1.10.2.4 nathanw }
314 1.10.2.4 nathanw state++;
315 1.10.2.4 nathanw
316 1.10.2.4 nathanw if (bus_dmamap_load(sc->sc_dmat, sc->sc_scr_dmamap, sc->sc_scr,
317 1.10.2.4 nathanw PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) {
318 1.10.2.4 nathanw printf("%s: cannot load scratch dmamap\n", sc->sc_dv.dv_xname);
319 1.10.2.4 nathanw goto bail_out;
320 1.10.2.4 nathanw }
321 1.10.2.4 nathanw state++;
322 1.10.2.4 nathanw
323 1.10.2.9 nathanw #ifdef I2ODEBUG
324 1.10.2.9 nathanw /* So that our debug checks don't choke. */
325 1.10.2.9 nathanw sc->sc_framesize = 128;
326 1.10.2.9 nathanw #endif
327 1.10.2.9 nathanw
328 1.10.2.4 nathanw /* Reset the adapter and request status. */
329 1.10.2.4 nathanw if ((rv = iop_reset(sc)) != 0) {
330 1.10.2.4 nathanw printf("%s: not responding (reset)\n", sc->sc_dv.dv_xname);
331 1.10.2.4 nathanw goto bail_out;
332 1.10.2.4 nathanw }
333 1.10.2.4 nathanw
334 1.10.2.4 nathanw if ((rv = iop_status_get(sc, 1)) != 0) {
335 1.10.2.4 nathanw printf("%s: not responding (get status)\n",
336 1.10.2.4 nathanw sc->sc_dv.dv_xname);
337 1.10.2.4 nathanw goto bail_out;
338 1.10.2.4 nathanw }
339 1.10.2.4 nathanw
340 1.5 ad sc->sc_flags |= IOP_HAVESTATUS;
341 1.5 ad iop_strvis(sc, sc->sc_status.productid, sizeof(sc->sc_status.productid),
342 1.1 ad ident, sizeof(ident));
343 1.5 ad printf(" <%s>\n", ident);
344 1.5 ad
345 1.5 ad #ifdef I2ODEBUG
346 1.5 ad printf("%s: orgid=0x%04x version=%d\n", sc->sc_dv.dv_xname,
347 1.5 ad le16toh(sc->sc_status.orgid),
348 1.5 ad (le32toh(sc->sc_status.segnumber) >> 12) & 15);
349 1.5 ad printf("%s: type want have cbase\n", sc->sc_dv.dv_xname);
350 1.5 ad printf("%s: mem %04x %04x %08x\n", sc->sc_dv.dv_xname,
351 1.5 ad le32toh(sc->sc_status.desiredprivmemsize),
352 1.5 ad le32toh(sc->sc_status.currentprivmemsize),
353 1.5 ad le32toh(sc->sc_status.currentprivmembase));
354 1.5 ad printf("%s: i/o %04x %04x %08x\n", sc->sc_dv.dv_xname,
355 1.5 ad le32toh(sc->sc_status.desiredpriviosize),
356 1.5 ad le32toh(sc->sc_status.currentpriviosize),
357 1.5 ad le32toh(sc->sc_status.currentpriviobase));
358 1.5 ad #endif
359 1.1 ad
360 1.10.2.2 nathanw sc->sc_maxob = le32toh(sc->sc_status.maxoutboundmframes);
361 1.10.2.2 nathanw if (sc->sc_maxob > IOP_MAX_OUTBOUND)
362 1.10.2.2 nathanw sc->sc_maxob = IOP_MAX_OUTBOUND;
363 1.10.2.2 nathanw sc->sc_maxib = le32toh(sc->sc_status.maxinboundmframes);
364 1.10.2.2 nathanw if (sc->sc_maxib > IOP_MAX_INBOUND)
365 1.10.2.2 nathanw sc->sc_maxib = IOP_MAX_INBOUND;
366 1.10.2.7 nathanw sc->sc_framesize = le16toh(sc->sc_status.inboundmframesize) << 2;
367 1.10.2.7 nathanw if (sc->sc_framesize > IOP_MAX_MSG_SIZE)
368 1.10.2.7 nathanw sc->sc_framesize = IOP_MAX_MSG_SIZE;
369 1.10.2.7 nathanw
370 1.10.2.7 nathanw #if defined(I2ODEBUG) || defined(DIAGNOSTIC)
371 1.10.2.7 nathanw if (sc->sc_framesize < IOP_MIN_MSG_SIZE) {
372 1.10.2.7 nathanw printf("%s: frame size too small (%d)\n",
373 1.10.2.7 nathanw sc->sc_dv.dv_xname, sc->sc_framesize);
374 1.10.2.11 nathanw goto bail_out;
375 1.10.2.7 nathanw }
376 1.10.2.7 nathanw #endif
377 1.10.2.2 nathanw
378 1.10.2.2 nathanw /* Allocate message wrappers. */
379 1.10.2.10 nathanw im = malloc(sizeof(*im) * sc->sc_maxib, M_DEVBUF, M_NOWAIT|M_ZERO);
380 1.10.2.11 nathanw if (im == NULL) {
381 1.10.2.11 nathanw printf("%s: memory allocation failure\n", sc->sc_dv.dv_xname);
382 1.10.2.11 nathanw goto bail_out;
383 1.10.2.11 nathanw }
384 1.10.2.11 nathanw state++;
385 1.10.2.2 nathanw sc->sc_ims = im;
386 1.10.2.2 nathanw SLIST_INIT(&sc->sc_im_freelist);
387 1.10.2.2 nathanw
388 1.10.2.4 nathanw for (i = 0, state++; i < sc->sc_maxib; i++, im++) {
389 1.10.2.2 nathanw rv = bus_dmamap_create(sc->sc_dmat, IOP_MAX_XFER,
390 1.10.2.2 nathanw IOP_MAX_SEGS, IOP_MAX_XFER, 0,
391 1.10.2.2 nathanw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
392 1.10.2.2 nathanw &im->im_xfer[0].ix_map);
393 1.10.2.2 nathanw if (rv != 0) {
394 1.10.2.2 nathanw printf("%s: couldn't create dmamap (%d)",
395 1.10.2.2 nathanw sc->sc_dv.dv_xname, rv);
396 1.10.2.4 nathanw goto bail_out;
397 1.10.2.2 nathanw }
398 1.10.2.2 nathanw
399 1.10.2.2 nathanw im->im_tctx = i;
400 1.10.2.2 nathanw SLIST_INSERT_HEAD(&sc->sc_im_freelist, im, im_chain);
401 1.10.2.2 nathanw }
402 1.1 ad
403 1.10.2.5 nathanw /* Initialise the IOP's outbound FIFO. */
404 1.5 ad if (iop_ofifo_init(sc) != 0) {
405 1.10.2.4 nathanw printf("%s: unable to init oubound FIFO\n",
406 1.10.2.4 nathanw sc->sc_dv.dv_xname);
407 1.10.2.4 nathanw goto bail_out;
408 1.5 ad }
409 1.1 ad
410 1.5 ad /*
411 1.5 ad * Defer further configuration until (a) interrupts are working and
412 1.5 ad * (b) we have enough information to build the system table.
413 1.5 ad */
414 1.1 ad config_interrupts((struct device *)sc, iop_config_interrupts);
415 1.1 ad
416 1.5 ad /* Configure shutdown hook before we start any device activity. */
417 1.1 ad if (iop_sdh == NULL)
418 1.1 ad iop_sdh = shutdownhook_establish(iop_shutdown, NULL);
419 1.1 ad
420 1.1 ad /* Ensure interrupts are enabled at the IOP. */
421 1.5 ad mask = iop_inl(sc, IOP_REG_INTR_MASK);
422 1.5 ad iop_outl(sc, IOP_REG_INTR_MASK, mask & ~IOP_INTR_OFIFO);
423 1.1 ad
424 1.1 ad if (intrstr != NULL)
425 1.1 ad printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname,
426 1.1 ad intrstr);
427 1.1 ad
428 1.1 ad #ifdef I2ODEBUG
429 1.1 ad printf("%s: queue depths: inbound %d/%d, outbound %d/%d\n",
430 1.10.2.2 nathanw sc->sc_dv.dv_xname, sc->sc_maxib,
431 1.10.2.2 nathanw le32toh(sc->sc_status.maxinboundmframes),
432 1.10.2.2 nathanw sc->sc_maxob, le32toh(sc->sc_status.maxoutboundmframes));
433 1.1 ad #endif
434 1.1 ad
435 1.5 ad lockinit(&sc->sc_conflock, PRIBIO, "iopconf", hz * 30, 0);
436 1.10.2.4 nathanw return;
437 1.10.2.4 nathanw
438 1.10.2.4 nathanw bail_out:
439 1.10.2.4 nathanw if (state > 3) {
440 1.10.2.4 nathanw for (j = 0; j < i; j++)
441 1.10.2.4 nathanw bus_dmamap_destroy(sc->sc_dmat,
442 1.10.2.4 nathanw sc->sc_ims[j].im_xfer[0].ix_map);
443 1.10.2.4 nathanw free(sc->sc_ims, M_DEVBUF);
444 1.10.2.4 nathanw }
445 1.10.2.4 nathanw if (state > 2)
446 1.10.2.4 nathanw bus_dmamap_unload(sc->sc_dmat, sc->sc_scr_dmamap);
447 1.10.2.4 nathanw if (state > 1)
448 1.10.2.4 nathanw bus_dmamem_unmap(sc->sc_dmat, sc->sc_scr, PAGE_SIZE);
449 1.10.2.4 nathanw if (state > 0)
450 1.10.2.4 nathanw bus_dmamem_free(sc->sc_dmat, sc->sc_scr_seg, nsegs);
451 1.10.2.4 nathanw bus_dmamap_destroy(sc->sc_dmat, sc->sc_scr_dmamap);
452 1.1 ad }
453 1.1 ad
454 1.1 ad /*
455 1.5 ad * Perform autoconfiguration tasks.
456 1.1 ad */
457 1.1 ad static void
458 1.1 ad iop_config_interrupts(struct device *self)
459 1.1 ad {
460 1.10.2.6 nathanw struct iop_attach_args ia;
461 1.5 ad struct iop_softc *sc, *iop;
462 1.5 ad struct i2o_systab_entry *ste;
463 1.5 ad int rv, i, niop;
464 1.1 ad
465 1.1 ad sc = (struct iop_softc *)self;
466 1.5 ad LIST_INIT(&sc->sc_iilist);
467 1.5 ad
468 1.5 ad printf("%s: configuring...\n", sc->sc_dv.dv_xname);
469 1.1 ad
470 1.5 ad if (iop_hrt_get(sc) != 0) {
471 1.5 ad printf("%s: unable to retrieve HRT\n", sc->sc_dv.dv_xname);
472 1.5 ad return;
473 1.5 ad }
474 1.1 ad
475 1.5 ad /*
476 1.5 ad * Build the system table.
477 1.5 ad */
478 1.5 ad if (iop_systab == NULL) {
479 1.5 ad for (i = 0, niop = 0; i < iop_cd.cd_ndevs; i++) {
480 1.5 ad if ((iop = device_lookup(&iop_cd, i)) == NULL)
481 1.5 ad continue;
482 1.5 ad if ((iop->sc_flags & IOP_HAVESTATUS) == 0)
483 1.5 ad continue;
484 1.10.2.2 nathanw if (iop_status_get(iop, 1) != 0) {
485 1.5 ad printf("%s: unable to retrieve status\n",
486 1.5 ad sc->sc_dv.dv_xname);
487 1.5 ad iop->sc_flags &= ~IOP_HAVESTATUS;
488 1.5 ad continue;
489 1.5 ad }
490 1.5 ad niop++;
491 1.5 ad }
492 1.5 ad if (niop == 0)
493 1.5 ad return;
494 1.5 ad
495 1.5 ad i = sizeof(struct i2o_systab_entry) * (niop - 1) +
496 1.5 ad sizeof(struct i2o_systab);
497 1.5 ad iop_systab_size = i;
498 1.10.2.10 nathanw iop_systab = malloc(i, M_DEVBUF, M_NOWAIT|M_ZERO);
499 1.5 ad
500 1.5 ad iop_systab->numentries = niop;
501 1.5 ad iop_systab->version = I2O_VERSION_11;
502 1.5 ad
503 1.5 ad for (i = 0, ste = iop_systab->entry; i < iop_cd.cd_ndevs; i++) {
504 1.5 ad if ((iop = device_lookup(&iop_cd, i)) == NULL)
505 1.5 ad continue;
506 1.5 ad if ((iop->sc_flags & IOP_HAVESTATUS) == 0)
507 1.5 ad continue;
508 1.5 ad
509 1.5 ad ste->orgid = iop->sc_status.orgid;
510 1.5 ad ste->iopid = iop->sc_dv.dv_unit + 2;
511 1.5 ad ste->segnumber =
512 1.5 ad htole32(le32toh(iop->sc_status.segnumber) & ~4095);
513 1.5 ad ste->iopcaps = iop->sc_status.iopcaps;
514 1.5 ad ste->inboundmsgframesize =
515 1.5 ad iop->sc_status.inboundmframesize;
516 1.5 ad ste->inboundmsgportaddresslow =
517 1.5 ad htole32(iop->sc_memaddr + IOP_REG_IFIFO);
518 1.5 ad ste++;
519 1.5 ad }
520 1.5 ad }
521 1.5 ad
522 1.10.2.2 nathanw /*
523 1.10.2.2 nathanw * Post the system table to the IOP and bring it to the OPERATIONAL
524 1.10.2.2 nathanw * state.
525 1.10.2.2 nathanw */
526 1.5 ad if (iop_systab_set(sc) != 0) {
527 1.5 ad printf("%s: unable to set system table\n", sc->sc_dv.dv_xname);
528 1.5 ad return;
529 1.5 ad }
530 1.5 ad if (iop_simple_cmd(sc, I2O_TID_IOP, I2O_EXEC_SYS_ENABLE, IOP_ICTX, 1,
531 1.10.2.2 nathanw 30000) != 0) {
532 1.5 ad printf("%s: unable to enable system\n", sc->sc_dv.dv_xname);
533 1.5 ad return;
534 1.5 ad }
535 1.5 ad
536 1.5 ad /*
537 1.5 ad * Set up an event handler for this IOP.
538 1.5 ad */
539 1.5 ad sc->sc_eventii.ii_dv = self;
540 1.5 ad sc->sc_eventii.ii_intr = iop_intr_event;
541 1.10.2.4 nathanw sc->sc_eventii.ii_flags = II_NOTCTX | II_UTILITY;
542 1.5 ad sc->sc_eventii.ii_tid = I2O_TID_IOP;
543 1.10.2.2 nathanw iop_initiator_register(sc, &sc->sc_eventii);
544 1.10.2.2 nathanw
545 1.10.2.2 nathanw rv = iop_util_eventreg(sc, &sc->sc_eventii,
546 1.10.2.2 nathanw I2O_EVENT_EXEC_RESOURCE_LIMITS |
547 1.10.2.2 nathanw I2O_EVENT_EXEC_CONNECTION_FAIL |
548 1.10.2.2 nathanw I2O_EVENT_EXEC_ADAPTER_FAULT |
549 1.10.2.2 nathanw I2O_EVENT_EXEC_POWER_FAIL |
550 1.10.2.2 nathanw I2O_EVENT_EXEC_RESET_PENDING |
551 1.10.2.2 nathanw I2O_EVENT_EXEC_RESET_IMMINENT |
552 1.10.2.2 nathanw I2O_EVENT_EXEC_HARDWARE_FAIL |
553 1.10.2.2 nathanw I2O_EVENT_EXEC_XCT_CHANGE |
554 1.10.2.2 nathanw I2O_EVENT_EXEC_DDM_AVAILIBILITY |
555 1.10.2.2 nathanw I2O_EVENT_GEN_DEVICE_RESET |
556 1.10.2.2 nathanw I2O_EVENT_GEN_STATE_CHANGE |
557 1.10.2.2 nathanw I2O_EVENT_GEN_GENERAL_WARNING);
558 1.10.2.2 nathanw if (rv != 0) {
559 1.5 ad printf("%s: unable to register for events", sc->sc_dv.dv_xname);
560 1.5 ad return;
561 1.5 ad }
562 1.5 ad
563 1.10.2.6 nathanw /*
564 1.10.2.6 nathanw * Attempt to match and attach a product-specific extension.
565 1.10.2.6 nathanw */
566 1.1 ad ia.ia_class = I2O_CLASS_ANY;
567 1.1 ad ia.ia_tid = I2O_TID_IOP;
568 1.1 ad config_found_sm(self, &ia, iop_vendor_print, iop_submatch);
569 1.5 ad
570 1.10.2.6 nathanw /*
571 1.10.2.6 nathanw * Start device configuration.
572 1.10.2.6 nathanw */
573 1.10.2.2 nathanw lockmgr(&sc->sc_conflock, LK_EXCLUSIVE, NULL);
574 1.10.2.2 nathanw if ((rv = iop_reconfigure(sc, 0)) == -1) {
575 1.5 ad printf("%s: configure failed (%d)\n", sc->sc_dv.dv_xname, rv);
576 1.5 ad return;
577 1.5 ad }
578 1.10.2.2 nathanw lockmgr(&sc->sc_conflock, LK_RELEASE, NULL);
579 1.5 ad
580 1.9 ad kthread_create(iop_create_reconf_thread, sc);
581 1.9 ad }
582 1.9 ad
583 1.9 ad /*
584 1.9 ad * Create the reconfiguration thread. Called after the standard kernel
585 1.9 ad * threads have been created.
586 1.9 ad */
587 1.9 ad static void
588 1.9 ad iop_create_reconf_thread(void *cookie)
589 1.9 ad {
590 1.9 ad struct iop_softc *sc;
591 1.9 ad int rv;
592 1.9 ad
593 1.9 ad sc = cookie;
594 1.5 ad sc->sc_flags |= IOP_ONLINE;
595 1.10.2.2 nathanw
596 1.9 ad rv = kthread_create1(iop_reconf_thread, sc, &sc->sc_reconf_proc,
597 1.10.2.2 nathanw "%s", sc->sc_dv.dv_xname);
598 1.10.2.2 nathanw if (rv != 0) {
599 1.9 ad printf("%s: unable to create reconfiguration thread (%d)",
600 1.10.2.2 nathanw sc->sc_dv.dv_xname, rv);
601 1.10.2.2 nathanw return;
602 1.10.2.2 nathanw }
603 1.5 ad }
604 1.5 ad
605 1.5 ad /*
606 1.5 ad * Reconfiguration thread; listens for LCT change notification, and
607 1.10.2.3 nathanw * initiates re-configuration if received.
608 1.5 ad */
609 1.5 ad static void
610 1.9 ad iop_reconf_thread(void *cookie)
611 1.5 ad {
612 1.5 ad struct iop_softc *sc;
613 1.10.2.2 nathanw struct lwp *l;
614 1.5 ad struct i2o_lct lct;
615 1.5 ad u_int32_t chgind;
616 1.10.2.2 nathanw int rv;
617 1.5 ad
618 1.5 ad sc = cookie;
619 1.10.2.2 nathanw chgind = sc->sc_chgind + 1;
620 1.10.2.13 nathanw l = curlwp;
621 1.5 ad
622 1.5 ad for (;;) {
623 1.10.2.2 nathanw DPRINTF(("%s: async reconfig: requested 0x%08x\n",
624 1.10.2.2 nathanw sc->sc_dv.dv_xname, chgind));
625 1.5 ad
626 1.10.2.2 nathanw PHOLD(l);
627 1.10.2.2 nathanw rv = iop_lct_get0(sc, &lct, sizeof(lct), chgind);
628 1.10.2.2 nathanw PRELE(l);
629 1.10.2.2 nathanw
630 1.10.2.2 nathanw DPRINTF(("%s: async reconfig: notified (0x%08x, %d)\n",
631 1.10.2.2 nathanw sc->sc_dv.dv_xname, le32toh(lct.changeindicator), rv));
632 1.10.2.2 nathanw
633 1.10.2.2 nathanw if (rv == 0 &&
634 1.10.2.2 nathanw lockmgr(&sc->sc_conflock, LK_EXCLUSIVE, NULL) == 0) {
635 1.10.2.2 nathanw iop_reconfigure(sc, le32toh(lct.changeindicator));
636 1.10.2.2 nathanw chgind = sc->sc_chgind + 1;
637 1.10.2.2 nathanw lockmgr(&sc->sc_conflock, LK_RELEASE, NULL);
638 1.5 ad }
639 1.5 ad
640 1.9 ad tsleep(iop_reconf_thread, PWAIT, "iopzzz", hz * 5);
641 1.5 ad }
642 1.5 ad }
643 1.5 ad
644 1.5 ad /*
645 1.5 ad * Reconfigure: find new and removed devices.
646 1.5 ad */
647 1.10.2.6 nathanw int
648 1.10.2.2 nathanw iop_reconfigure(struct iop_softc *sc, u_int chgind)
649 1.5 ad {
650 1.5 ad struct iop_msg *im;
651 1.10.2.2 nathanw struct i2o_hba_bus_scan mf;
652 1.5 ad struct i2o_lct_entry *le;
653 1.5 ad struct iop_initiator *ii, *nextii;
654 1.5 ad int rv, tid, i;
655 1.5 ad
656 1.1 ad /*
657 1.5 ad * If the reconfiguration request isn't the result of LCT change
658 1.5 ad * notification, then be more thorough: ask all bus ports to scan
659 1.5 ad * their busses. Wait up to 5 minutes for each bus port to complete
660 1.5 ad * the request.
661 1.1 ad */
662 1.5 ad if (chgind == 0) {
663 1.5 ad if ((rv = iop_lct_get(sc)) != 0) {
664 1.5 ad DPRINTF(("iop_reconfigure: unable to read LCT\n"));
665 1.10.2.2 nathanw return (rv);
666 1.5 ad }
667 1.5 ad
668 1.5 ad le = sc->sc_lct->entry;
669 1.5 ad for (i = 0; i < sc->sc_nlctent; i++, le++) {
670 1.5 ad if ((le16toh(le->classid) & 4095) !=
671 1.5 ad I2O_CLASS_BUS_ADAPTER_PORT)
672 1.5 ad continue;
673 1.10.2.4 nathanw tid = le16toh(le->localtid) & 4095;
674 1.5 ad
675 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT);
676 1.5 ad
677 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_hba_bus_scan);
678 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(tid, I2O_HBA_BUS_SCAN);
679 1.10.2.2 nathanw mf.msgictx = IOP_ICTX;
680 1.10.2.2 nathanw mf.msgtctx = im->im_tctx;
681 1.5 ad
682 1.5 ad DPRINTF(("%s: scanning bus %d\n", sc->sc_dv.dv_xname,
683 1.5 ad tid));
684 1.5 ad
685 1.10.2.2 nathanw rv = iop_msg_post(sc, im, &mf, 5*60*1000);
686 1.10.2.2 nathanw iop_msg_free(sc, im);
687 1.10.2.2 nathanw #ifdef I2ODEBUG
688 1.10.2.2 nathanw if (rv != 0)
689 1.10.2.2 nathanw printf("%s: bus scan failed\n",
690 1.10.2.2 nathanw sc->sc_dv.dv_xname);
691 1.10.2.2 nathanw #endif
692 1.5 ad }
693 1.10.2.2 nathanw } else if (chgind <= sc->sc_chgind) {
694 1.5 ad DPRINTF(("%s: LCT unchanged (async)\n", sc->sc_dv.dv_xname));
695 1.10.2.2 nathanw return (0);
696 1.5 ad }
697 1.5 ad
698 1.5 ad /* Re-read the LCT and determine if it has changed. */
699 1.5 ad if ((rv = iop_lct_get(sc)) != 0) {
700 1.5 ad DPRINTF(("iop_reconfigure: unable to re-read LCT\n"));
701 1.10.2.2 nathanw return (rv);
702 1.5 ad }
703 1.5 ad DPRINTF(("%s: %d LCT entries\n", sc->sc_dv.dv_xname, sc->sc_nlctent));
704 1.5 ad
705 1.10.2.2 nathanw chgind = le32toh(sc->sc_lct->changeindicator);
706 1.10.2.2 nathanw if (chgind == sc->sc_chgind) {
707 1.5 ad DPRINTF(("%s: LCT unchanged\n", sc->sc_dv.dv_xname));
708 1.10.2.2 nathanw return (0);
709 1.5 ad }
710 1.5 ad DPRINTF(("%s: LCT changed\n", sc->sc_dv.dv_xname));
711 1.10.2.2 nathanw sc->sc_chgind = chgind;
712 1.5 ad
713 1.5 ad if (sc->sc_tidmap != NULL)
714 1.5 ad free(sc->sc_tidmap, M_DEVBUF);
715 1.5 ad sc->sc_tidmap = malloc(sc->sc_nlctent * sizeof(struct iop_tidmap),
716 1.10.2.10 nathanw M_DEVBUF, M_NOWAIT|M_ZERO);
717 1.5 ad
718 1.10.2.2 nathanw /* Allow 1 queued command per device while we're configuring. */
719 1.10.2.2 nathanw iop_adjqparam(sc, 1);
720 1.10.2.2 nathanw
721 1.10.2.2 nathanw /*
722 1.10.2.2 nathanw * Match and attach child devices. We configure high-level devices
723 1.10.2.2 nathanw * first so that any claims will propagate throughout the LCT,
724 1.10.2.2 nathanw * hopefully masking off aliased devices as a result.
725 1.10.2.2 nathanw *
726 1.10.2.2 nathanw * Re-reading the LCT at this point is a little dangerous, but we'll
727 1.10.2.2 nathanw * trust the IOP (and the operator) to behave itself...
728 1.10.2.2 nathanw */
729 1.10.2.2 nathanw iop_configure_devices(sc, IC_CONFIGURE | IC_PRIORITY,
730 1.10.2.2 nathanw IC_CONFIGURE | IC_PRIORITY);
731 1.10.2.2 nathanw if ((rv = iop_lct_get(sc)) != 0)
732 1.10.2.2 nathanw DPRINTF(("iop_reconfigure: unable to re-read LCT\n"));
733 1.10.2.2 nathanw iop_configure_devices(sc, IC_CONFIGURE | IC_PRIORITY,
734 1.10.2.2 nathanw IC_CONFIGURE);
735 1.5 ad
736 1.5 ad for (ii = LIST_FIRST(&sc->sc_iilist); ii != NULL; ii = nextii) {
737 1.10.2.2 nathanw nextii = LIST_NEXT(ii, ii_list);
738 1.5 ad
739 1.5 ad /* Detach devices that were configured, but are now gone. */
740 1.5 ad for (i = 0; i < sc->sc_nlctent; i++)
741 1.5 ad if (ii->ii_tid == sc->sc_tidmap[i].it_tid)
742 1.5 ad break;
743 1.5 ad if (i == sc->sc_nlctent ||
744 1.5 ad (sc->sc_tidmap[i].it_flags & IT_CONFIGURED) == 0)
745 1.5 ad config_detach(ii->ii_dv, DETACH_FORCE);
746 1.5 ad
747 1.5 ad /*
748 1.5 ad * Tell initiators that existed before the re-configuration
749 1.5 ad * to re-configure.
750 1.5 ad */
751 1.5 ad if (ii->ii_reconfig == NULL)
752 1.5 ad continue;
753 1.5 ad if ((rv = (*ii->ii_reconfig)(ii->ii_dv)) != 0)
754 1.5 ad printf("%s: %s failed reconfigure (%d)\n",
755 1.5 ad sc->sc_dv.dv_xname, ii->ii_dv->dv_xname, rv);
756 1.5 ad }
757 1.5 ad
758 1.10.2.2 nathanw /* Re-adjust queue parameters and return. */
759 1.10.2.2 nathanw if (sc->sc_nii != 0)
760 1.10.2.2 nathanw iop_adjqparam(sc, (sc->sc_maxib - sc->sc_nuii - IOP_MF_RESERVE)
761 1.10.2.2 nathanw / sc->sc_nii);
762 1.10.2.2 nathanw
763 1.10.2.2 nathanw return (0);
764 1.1 ad }
765 1.1 ad
766 1.1 ad /*
767 1.5 ad * Configure I2O devices into the system.
768 1.1 ad */
769 1.1 ad static void
770 1.10.2.2 nathanw iop_configure_devices(struct iop_softc *sc, int mask, int maskval)
771 1.1 ad {
772 1.1 ad struct iop_attach_args ia;
773 1.5 ad struct iop_initiator *ii;
774 1.1 ad const struct i2o_lct_entry *le;
775 1.9 ad struct device *dv;
776 1.8 ad int i, j, nent;
777 1.10.2.2 nathanw u_int usertid;
778 1.1 ad
779 1.1 ad nent = sc->sc_nlctent;
780 1.1 ad for (i = 0, le = sc->sc_lct->entry; i < nent; i++, le++) {
781 1.10.2.4 nathanw sc->sc_tidmap[i].it_tid = le16toh(le->localtid) & 4095;
782 1.9 ad
783 1.10.2.2 nathanw /* Ignore the device if it's in use. */
784 1.10.2.2 nathanw usertid = le32toh(le->usertid) & 4095;
785 1.10.2.2 nathanw if (usertid != I2O_TID_NONE && usertid != I2O_TID_HOST)
786 1.1 ad continue;
787 1.1 ad
788 1.1 ad ia.ia_class = le16toh(le->classid) & 4095;
789 1.9 ad ia.ia_tid = sc->sc_tidmap[i].it_tid;
790 1.8 ad
791 1.8 ad /* Ignore uninteresting devices. */
792 1.8 ad for (j = 0; j < sizeof(iop_class) / sizeof(iop_class[0]); j++)
793 1.8 ad if (iop_class[j].ic_class == ia.ia_class)
794 1.8 ad break;
795 1.8 ad if (j < sizeof(iop_class) / sizeof(iop_class[0]) &&
796 1.10.2.2 nathanw (iop_class[j].ic_flags & mask) != maskval)
797 1.8 ad continue;
798 1.1 ad
799 1.1 ad /*
800 1.5 ad * Try to configure the device only if it's not already
801 1.5 ad * configured.
802 1.1 ad */
803 1.7 ad LIST_FOREACH(ii, &sc->sc_iilist, ii_list) {
804 1.9 ad if (ia.ia_tid == ii->ii_tid) {
805 1.9 ad sc->sc_tidmap[i].it_flags |= IT_CONFIGURED;
806 1.9 ad strcpy(sc->sc_tidmap[i].it_dvname,
807 1.9 ad ii->ii_dv->dv_xname);
808 1.10.2.2 nathanw break;
809 1.9 ad }
810 1.7 ad }
811 1.5 ad if (ii != NULL)
812 1.5 ad continue;
813 1.5 ad
814 1.9 ad dv = config_found_sm(&sc->sc_dv, &ia, iop_print, iop_submatch);
815 1.9 ad if (dv != NULL) {
816 1.10.2.2 nathanw sc->sc_tidmap[i].it_flags |= IT_CONFIGURED;
817 1.9 ad strcpy(sc->sc_tidmap[i].it_dvname, dv->dv_xname);
818 1.9 ad }
819 1.1 ad }
820 1.1 ad }
821 1.1 ad
822 1.10.2.2 nathanw /*
823 1.10.2.2 nathanw * Adjust queue parameters for all child devices.
824 1.10.2.2 nathanw */
825 1.10.2.2 nathanw static void
826 1.10.2.2 nathanw iop_adjqparam(struct iop_softc *sc, int mpi)
827 1.10.2.2 nathanw {
828 1.10.2.2 nathanw struct iop_initiator *ii;
829 1.10.2.2 nathanw
830 1.10.2.2 nathanw LIST_FOREACH(ii, &sc->sc_iilist, ii_list)
831 1.10.2.2 nathanw if (ii->ii_adjqparam != NULL)
832 1.10.2.2 nathanw (*ii->ii_adjqparam)(ii->ii_dv, mpi);
833 1.10.2.2 nathanw }
834 1.10.2.2 nathanw
835 1.1 ad static void
836 1.1 ad iop_devinfo(int class, char *devinfo)
837 1.1 ad {
838 1.1 ad #ifdef I2OVERBOSE
839 1.1 ad int i;
840 1.1 ad
841 1.1 ad for (i = 0; i < sizeof(iop_class) / sizeof(iop_class[0]); i++)
842 1.1 ad if (class == iop_class[i].ic_class)
843 1.1 ad break;
844 1.1 ad
845 1.1 ad if (i == sizeof(iop_class) / sizeof(iop_class[0]))
846 1.1 ad sprintf(devinfo, "device (class 0x%x)", class);
847 1.1 ad else
848 1.1 ad strcpy(devinfo, iop_class[i].ic_caption);
849 1.1 ad #else
850 1.1 ad
851 1.1 ad sprintf(devinfo, "device (class 0x%x)", class);
852 1.1 ad #endif
853 1.1 ad }
854 1.1 ad
855 1.1 ad static int
856 1.1 ad iop_print(void *aux, const char *pnp)
857 1.1 ad {
858 1.1 ad struct iop_attach_args *ia;
859 1.1 ad char devinfo[256];
860 1.1 ad
861 1.1 ad ia = aux;
862 1.1 ad
863 1.1 ad if (pnp != NULL) {
864 1.1 ad iop_devinfo(ia->ia_class, devinfo);
865 1.1 ad printf("%s at %s", devinfo, pnp);
866 1.1 ad }
867 1.1 ad printf(" tid %d", ia->ia_tid);
868 1.1 ad return (UNCONF);
869 1.1 ad }
870 1.1 ad
871 1.1 ad static int
872 1.1 ad iop_vendor_print(void *aux, const char *pnp)
873 1.1 ad {
874 1.1 ad
875 1.10.2.6 nathanw return (QUIET);
876 1.1 ad }
877 1.1 ad
878 1.1 ad static int
879 1.1 ad iop_submatch(struct device *parent, struct cfdata *cf, void *aux)
880 1.1 ad {
881 1.1 ad struct iop_attach_args *ia;
882 1.1 ad
883 1.1 ad ia = aux;
884 1.1 ad
885 1.1 ad if (cf->iopcf_tid != IOPCF_TID_DEFAULT && cf->iopcf_tid != ia->ia_tid)
886 1.1 ad return (0);
887 1.1 ad
888 1.10.2.15 nathanw return (config_match(parent, cf, aux));
889 1.1 ad }
890 1.1 ad
891 1.1 ad /*
892 1.1 ad * Shut down all configured IOPs.
893 1.1 ad */
894 1.1 ad static void
895 1.1 ad iop_shutdown(void *junk)
896 1.1 ad {
897 1.1 ad struct iop_softc *sc;
898 1.1 ad int i;
899 1.1 ad
900 1.10.2.2 nathanw printf("shutting down iop devices...");
901 1.1 ad
902 1.1 ad for (i = 0; i < iop_cd.cd_ndevs; i++) {
903 1.1 ad if ((sc = device_lookup(&iop_cd, i)) == NULL)
904 1.1 ad continue;
905 1.5 ad if ((sc->sc_flags & IOP_ONLINE) == 0)
906 1.5 ad continue;
907 1.5 ad iop_simple_cmd(sc, I2O_TID_IOP, I2O_EXEC_SYS_QUIESCE, IOP_ICTX,
908 1.5 ad 0, 5000);
909 1.5 ad iop_simple_cmd(sc, I2O_TID_IOP, I2O_EXEC_IOP_CLEAR, IOP_ICTX,
910 1.10.2.2 nathanw 0, 1000);
911 1.1 ad }
912 1.1 ad
913 1.1 ad /* Wait. Some boards could still be flushing, stupidly enough. */
914 1.1 ad delay(5000*1000);
915 1.10.2.6 nathanw printf(" done\n");
916 1.1 ad }
917 1.1 ad
918 1.1 ad /*
919 1.10.2.2 nathanw * Retrieve IOP status.
920 1.1 ad */
921 1.10.2.6 nathanw int
922 1.10.2.2 nathanw iop_status_get(struct iop_softc *sc, int nosleep)
923 1.1 ad {
924 1.10.2.2 nathanw struct i2o_exec_status_get mf;
925 1.10.2.4 nathanw struct i2o_status *st;
926 1.10.2.4 nathanw paddr_t pa;
927 1.10.2.2 nathanw int rv, i;
928 1.1 ad
929 1.10.2.4 nathanw pa = sc->sc_scr_seg->ds_addr;
930 1.10.2.4 nathanw st = (struct i2o_status *)sc->sc_scr;
931 1.10.2.4 nathanw
932 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_exec_status_get);
933 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(I2O_TID_IOP, I2O_EXEC_STATUS_GET);
934 1.10.2.2 nathanw mf.reserved[0] = 0;
935 1.10.2.2 nathanw mf.reserved[1] = 0;
936 1.10.2.2 nathanw mf.reserved[2] = 0;
937 1.10.2.2 nathanw mf.reserved[3] = 0;
938 1.10.2.4 nathanw mf.addrlow = (u_int32_t)pa;
939 1.10.2.4 nathanw mf.addrhigh = (u_int32_t)((u_int64_t)pa >> 32);
940 1.10.2.2 nathanw mf.length = sizeof(sc->sc_status);
941 1.1 ad
942 1.10.2.4 nathanw memset(st, 0, sizeof(*st));
943 1.10.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_scr_dmamap, 0, sizeof(*st),
944 1.10.2.4 nathanw BUS_DMASYNC_PREREAD);
945 1.1 ad
946 1.10.2.2 nathanw if ((rv = iop_post(sc, (u_int32_t *)&mf)) != 0)
947 1.1 ad return (rv);
948 1.1 ad
949 1.10.2.2 nathanw for (i = 25; i != 0; i--) {
950 1.10.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_scr_dmamap, 0,
951 1.10.2.4 nathanw sizeof(*st), BUS_DMASYNC_POSTREAD);
952 1.10.2.4 nathanw if (st->syncbyte == 0xff)
953 1.10.2.2 nathanw break;
954 1.10.2.2 nathanw if (nosleep)
955 1.10.2.2 nathanw DELAY(100*1000);
956 1.10.2.2 nathanw else
957 1.10.2.2 nathanw tsleep(iop_status_get, PWAIT, "iopstat", hz / 10);
958 1.10.2.2 nathanw }
959 1.1 ad
960 1.10.2.9 nathanw if (st->syncbyte != 0xff) {
961 1.10.2.9 nathanw printf("%s: STATUS_GET timed out\n", sc->sc_dv.dv_xname);
962 1.10.2.2 nathanw rv = EIO;
963 1.10.2.9 nathanw } else {
964 1.10.2.4 nathanw memcpy(&sc->sc_status, st, sizeof(sc->sc_status));
965 1.10.2.2 nathanw rv = 0;
966 1.10.2.4 nathanw }
967 1.10.2.4 nathanw
968 1.10.2.2 nathanw return (rv);
969 1.1 ad }
970 1.1 ad
971 1.1 ad /*
972 1.10.2.5 nathanw * Initialize and populate the IOP's outbound FIFO.
973 1.1 ad */
974 1.1 ad static int
975 1.1 ad iop_ofifo_init(struct iop_softc *sc)
976 1.1 ad {
977 1.1 ad bus_addr_t addr;
978 1.5 ad bus_dma_segment_t seg;
979 1.10.2.2 nathanw struct i2o_exec_outbound_init *mf;
980 1.5 ad int i, rseg, rv;
981 1.10.2.4 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)], *sw;
982 1.1 ad
983 1.10.2.4 nathanw sw = (u_int32_t *)sc->sc_scr;
984 1.1 ad
985 1.10.2.2 nathanw mf = (struct i2o_exec_outbound_init *)mb;
986 1.10.2.2 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_exec_outbound_init);
987 1.10.2.2 nathanw mf->msgfunc = I2O_MSGFUNC(I2O_TID_IOP, I2O_EXEC_OUTBOUND_INIT);
988 1.10.2.2 nathanw mf->msgictx = IOP_ICTX;
989 1.10.2.4 nathanw mf->msgtctx = 0;
990 1.10.2.2 nathanw mf->pagesize = PAGE_SIZE;
991 1.10.2.7 nathanw mf->flags = IOP_INIT_CODE | ((sc->sc_framesize >> 2) << 16);
992 1.1 ad
993 1.5 ad /*
994 1.5 ad * The I2O spec says that there are two SGLs: one for the status
995 1.5 ad * word, and one for a list of discarded MFAs. It continues to say
996 1.5 ad * that if you don't want to get the list of MFAs, an IGNORE SGL is
997 1.10.2.2 nathanw * necessary; this isn't the case (and is in fact a bad thing).
998 1.5 ad */
999 1.10.2.4 nathanw mb[sizeof(*mf) / sizeof(u_int32_t) + 0] = sizeof(*sw) |
1000 1.10.2.4 nathanw I2O_SGL_SIMPLE | I2O_SGL_END_BUFFER | I2O_SGL_END;
1001 1.10.2.4 nathanw mb[sizeof(*mf) / sizeof(u_int32_t) + 1] =
1002 1.10.2.4 nathanw (u_int32_t)sc->sc_scr_seg->ds_addr;
1003 1.10.2.4 nathanw mb[0] += 2 << 16;
1004 1.10.2.4 nathanw
1005 1.10.2.4 nathanw *sw = 0;
1006 1.10.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_scr_dmamap, 0, sizeof(*sw),
1007 1.10.2.4 nathanw BUS_DMASYNC_PREREAD);
1008 1.10.2.4 nathanw
1009 1.10.2.4 nathanw if ((rv = iop_post(sc, mb)) != 0)
1010 1.1 ad return (rv);
1011 1.1 ad
1012 1.10.2.4 nathanw POLL(5000,
1013 1.10.2.4 nathanw (bus_dmamap_sync(sc->sc_dmat, sc->sc_scr_dmamap, 0, sizeof(*sw),
1014 1.10.2.4 nathanw BUS_DMASYNC_POSTREAD),
1015 1.10.2.4 nathanw *sw == htole32(I2O_EXEC_OUTBOUND_INIT_COMPLETE)));
1016 1.10.2.4 nathanw
1017 1.10.2.4 nathanw if (*sw != htole32(I2O_EXEC_OUTBOUND_INIT_COMPLETE)) {
1018 1.10.2.4 nathanw printf("%s: outbound FIFO init failed (%d)\n",
1019 1.10.2.4 nathanw sc->sc_dv.dv_xname, le32toh(*sw));
1020 1.5 ad return (EIO);
1021 1.1 ad }
1022 1.1 ad
1023 1.10.2.2 nathanw /* Allocate DMA safe memory for the reply frames. */
1024 1.1 ad if (sc->sc_rep_phys == 0) {
1025 1.10.2.7 nathanw sc->sc_rep_size = sc->sc_maxob * sc->sc_framesize;
1026 1.5 ad
1027 1.5 ad rv = bus_dmamem_alloc(sc->sc_dmat, sc->sc_rep_size, PAGE_SIZE,
1028 1.5 ad 0, &seg, 1, &rseg, BUS_DMA_NOWAIT);
1029 1.5 ad if (rv != 0) {
1030 1.5 ad printf("%s: dma alloc = %d\n", sc->sc_dv.dv_xname,
1031 1.5 ad rv);
1032 1.5 ad return (rv);
1033 1.5 ad }
1034 1.5 ad
1035 1.5 ad rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, sc->sc_rep_size,
1036 1.5 ad &sc->sc_rep, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
1037 1.5 ad if (rv != 0) {
1038 1.5 ad printf("%s: dma map = %d\n", sc->sc_dv.dv_xname, rv);
1039 1.5 ad return (rv);
1040 1.5 ad }
1041 1.5 ad
1042 1.5 ad rv = bus_dmamap_create(sc->sc_dmat, sc->sc_rep_size, 1,
1043 1.5 ad sc->sc_rep_size, 0, BUS_DMA_NOWAIT, &sc->sc_rep_dmamap);
1044 1.5 ad if (rv != 0) {
1045 1.10.2.4 nathanw printf("%s: dma create = %d\n", sc->sc_dv.dv_xname,
1046 1.10.2.4 nathanw rv);
1047 1.5 ad return (rv);
1048 1.5 ad }
1049 1.5 ad
1050 1.10.2.4 nathanw rv = bus_dmamap_load(sc->sc_dmat, sc->sc_rep_dmamap,
1051 1.10.2.4 nathanw sc->sc_rep, sc->sc_rep_size, NULL, BUS_DMA_NOWAIT);
1052 1.5 ad if (rv != 0) {
1053 1.5 ad printf("%s: dma load = %d\n", sc->sc_dv.dv_xname, rv);
1054 1.5 ad return (rv);
1055 1.5 ad }
1056 1.5 ad
1057 1.5 ad sc->sc_rep_phys = sc->sc_rep_dmamap->dm_segs[0].ds_addr;
1058 1.1 ad }
1059 1.1 ad
1060 1.1 ad /* Populate the outbound FIFO. */
1061 1.10.2.2 nathanw for (i = sc->sc_maxob, addr = sc->sc_rep_phys; i != 0; i--) {
1062 1.5 ad iop_outl(sc, IOP_REG_OFIFO, (u_int32_t)addr);
1063 1.10.2.7 nathanw addr += sc->sc_framesize;
1064 1.1 ad }
1065 1.1 ad
1066 1.1 ad return (0);
1067 1.1 ad }
1068 1.1 ad
1069 1.1 ad /*
1070 1.1 ad * Read the specified number of bytes from the IOP's hardware resource table.
1071 1.1 ad */
1072 1.1 ad static int
1073 1.1 ad iop_hrt_get0(struct iop_softc *sc, struct i2o_hrt *hrt, int size)
1074 1.1 ad {
1075 1.1 ad struct iop_msg *im;
1076 1.1 ad int rv;
1077 1.10.2.2 nathanw struct i2o_exec_hrt_get *mf;
1078 1.10.2.2 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1079 1.1 ad
1080 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT);
1081 1.10.2.2 nathanw mf = (struct i2o_exec_hrt_get *)mb;
1082 1.10.2.2 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_exec_hrt_get);
1083 1.10.2.2 nathanw mf->msgfunc = I2O_MSGFUNC(I2O_TID_IOP, I2O_EXEC_HRT_GET);
1084 1.10.2.2 nathanw mf->msgictx = IOP_ICTX;
1085 1.10.2.2 nathanw mf->msgtctx = im->im_tctx;
1086 1.1 ad
1087 1.10.2.4 nathanw iop_msg_map(sc, im, mb, hrt, size, 0, NULL);
1088 1.10.2.2 nathanw rv = iop_msg_post(sc, im, mb, 30000);
1089 1.1 ad iop_msg_unmap(sc, im);
1090 1.10.2.2 nathanw iop_msg_free(sc, im);
1091 1.1 ad return (rv);
1092 1.1 ad }
1093 1.1 ad
1094 1.1 ad /*
1095 1.5 ad * Read the IOP's hardware resource table.
1096 1.1 ad */
1097 1.1 ad static int
1098 1.1 ad iop_hrt_get(struct iop_softc *sc)
1099 1.1 ad {
1100 1.1 ad struct i2o_hrt hrthdr, *hrt;
1101 1.1 ad int size, rv;
1102 1.1 ad
1103 1.10.2.13 nathanw PHOLD(curlwp);
1104 1.10.2.2 nathanw rv = iop_hrt_get0(sc, &hrthdr, sizeof(hrthdr));
1105 1.10.2.13 nathanw PRELE(curlwp);
1106 1.10.2.2 nathanw if (rv != 0)
1107 1.1 ad return (rv);
1108 1.1 ad
1109 1.5 ad DPRINTF(("%s: %d hrt entries\n", sc->sc_dv.dv_xname,
1110 1.5 ad le16toh(hrthdr.numentries)));
1111 1.5 ad
1112 1.5 ad size = sizeof(struct i2o_hrt) +
1113 1.10.2.4 nathanw (le16toh(hrthdr.numentries) - 1) * sizeof(struct i2o_hrt_entry);
1114 1.1 ad hrt = (struct i2o_hrt *)malloc(size, M_DEVBUF, M_NOWAIT);
1115 1.1 ad
1116 1.1 ad if ((rv = iop_hrt_get0(sc, hrt, size)) != 0) {
1117 1.1 ad free(hrt, M_DEVBUF);
1118 1.1 ad return (rv);
1119 1.1 ad }
1120 1.1 ad
1121 1.1 ad if (sc->sc_hrt != NULL)
1122 1.1 ad free(sc->sc_hrt, M_DEVBUF);
1123 1.1 ad sc->sc_hrt = hrt;
1124 1.1 ad return (0);
1125 1.1 ad }
1126 1.1 ad
1127 1.1 ad /*
1128 1.1 ad * Request the specified number of bytes from the IOP's logical
1129 1.5 ad * configuration table. If a change indicator is specified, this
1130 1.10.2.2 nathanw * is a verbatim notification request, so the caller is prepared
1131 1.5 ad * to wait indefinitely.
1132 1.1 ad */
1133 1.1 ad static int
1134 1.5 ad iop_lct_get0(struct iop_softc *sc, struct i2o_lct *lct, int size,
1135 1.5 ad u_int32_t chgind)
1136 1.1 ad {
1137 1.1 ad struct iop_msg *im;
1138 1.10.2.2 nathanw struct i2o_exec_lct_notify *mf;
1139 1.1 ad int rv;
1140 1.10.2.2 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1141 1.1 ad
1142 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT);
1143 1.1 ad memset(lct, 0, size);
1144 1.1 ad
1145 1.10.2.2 nathanw mf = (struct i2o_exec_lct_notify *)mb;
1146 1.10.2.2 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_exec_lct_notify);
1147 1.10.2.2 nathanw mf->msgfunc = I2O_MSGFUNC(I2O_TID_IOP, I2O_EXEC_LCT_NOTIFY);
1148 1.10.2.2 nathanw mf->msgictx = IOP_ICTX;
1149 1.10.2.2 nathanw mf->msgtctx = im->im_tctx;
1150 1.10.2.2 nathanw mf->classid = I2O_CLASS_ANY;
1151 1.10.2.2 nathanw mf->changeindicator = chgind;
1152 1.5 ad
1153 1.9 ad #ifdef I2ODEBUG
1154 1.9 ad printf("iop_lct_get0: reading LCT");
1155 1.9 ad if (chgind != 0)
1156 1.9 ad printf(" (async)");
1157 1.9 ad printf("\n");
1158 1.9 ad #endif
1159 1.1 ad
1160 1.10.2.4 nathanw iop_msg_map(sc, im, mb, lct, size, 0, NULL);
1161 1.10.2.2 nathanw rv = iop_msg_post(sc, im, mb, (chgind == 0 ? 120*1000 : 0));
1162 1.1 ad iop_msg_unmap(sc, im);
1163 1.10.2.2 nathanw iop_msg_free(sc, im);
1164 1.1 ad return (rv);
1165 1.1 ad }
1166 1.1 ad
1167 1.1 ad /*
1168 1.6 ad * Read the IOP's logical configuration table.
1169 1.1 ad */
1170 1.1 ad int
1171 1.1 ad iop_lct_get(struct iop_softc *sc)
1172 1.1 ad {
1173 1.5 ad int esize, size, rv;
1174 1.5 ad struct i2o_lct *lct;
1175 1.1 ad
1176 1.5 ad esize = le32toh(sc->sc_status.expectedlctsize);
1177 1.5 ad lct = (struct i2o_lct *)malloc(esize, M_DEVBUF, M_WAITOK);
1178 1.5 ad if (lct == NULL)
1179 1.1 ad return (ENOMEM);
1180 1.1 ad
1181 1.5 ad if ((rv = iop_lct_get0(sc, lct, esize, 0)) != 0) {
1182 1.1 ad free(lct, M_DEVBUF);
1183 1.1 ad return (rv);
1184 1.1 ad }
1185 1.1 ad
1186 1.5 ad size = le16toh(lct->tablesize) << 2;
1187 1.5 ad if (esize != size) {
1188 1.1 ad free(lct, M_DEVBUF);
1189 1.5 ad lct = (struct i2o_lct *)malloc(size, M_DEVBUF, M_WAITOK);
1190 1.5 ad if (lct == NULL)
1191 1.5 ad return (ENOMEM);
1192 1.5 ad
1193 1.5 ad if ((rv = iop_lct_get0(sc, lct, size, 0)) != 0) {
1194 1.5 ad free(lct, M_DEVBUF);
1195 1.5 ad return (rv);
1196 1.5 ad }
1197 1.1 ad }
1198 1.5 ad
1199 1.5 ad /* Swap in the new LCT. */
1200 1.1 ad if (sc->sc_lct != NULL)
1201 1.1 ad free(sc->sc_lct, M_DEVBUF);
1202 1.1 ad sc->sc_lct = lct;
1203 1.1 ad sc->sc_nlctent = ((le16toh(sc->sc_lct->tablesize) << 2) -
1204 1.1 ad sizeof(struct i2o_lct) + sizeof(struct i2o_lct_entry)) /
1205 1.1 ad sizeof(struct i2o_lct_entry);
1206 1.1 ad return (0);
1207 1.1 ad }
1208 1.1 ad
1209 1.1 ad /*
1210 1.10.2.2 nathanw * Request the specified parameter group from the target. If an initiator
1211 1.10.2.2 nathanw * is specified (a) don't wait for the operation to complete, but instead
1212 1.10.2.2 nathanw * let the initiator's interrupt handler deal with the reply and (b) place a
1213 1.10.2.2 nathanw * pointer to the parameter group op in the wrapper's `im_dvcontext' field.
1214 1.1 ad */
1215 1.1 ad int
1216 1.10.2.5 nathanw iop_field_get_all(struct iop_softc *sc, int tid, int group, void *buf,
1217 1.10.2.5 nathanw int size, struct iop_initiator *ii)
1218 1.1 ad {
1219 1.1 ad struct iop_msg *im;
1220 1.10.2.2 nathanw struct i2o_util_params_op *mf;
1221 1.10.2.2 nathanw struct i2o_reply *rf;
1222 1.10.2.5 nathanw int rv;
1223 1.10.2.2 nathanw struct iop_pgop *pgop;
1224 1.10.2.2 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1225 1.1 ad
1226 1.10.2.4 nathanw im = iop_msg_alloc(sc, (ii == NULL ? IM_WAIT : 0) | IM_NOSTATUS);
1227 1.10.2.2 nathanw if ((pgop = malloc(sizeof(*pgop), M_DEVBUF, M_WAITOK)) == NULL) {
1228 1.10.2.2 nathanw iop_msg_free(sc, im);
1229 1.10.2.2 nathanw return (ENOMEM);
1230 1.10.2.2 nathanw }
1231 1.10.2.2 nathanw if ((rf = malloc(sizeof(*rf), M_DEVBUF, M_WAITOK)) == NULL) {
1232 1.10.2.2 nathanw iop_msg_free(sc, im);
1233 1.10.2.2 nathanw free(pgop, M_DEVBUF);
1234 1.10.2.2 nathanw return (ENOMEM);
1235 1.10.2.2 nathanw }
1236 1.10.2.2 nathanw im->im_dvcontext = pgop;
1237 1.10.2.2 nathanw im->im_rb = rf;
1238 1.1 ad
1239 1.10.2.2 nathanw mf = (struct i2o_util_params_op *)mb;
1240 1.10.2.2 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_util_params_op);
1241 1.10.2.5 nathanw mf->msgfunc = I2O_MSGFUNC(tid, I2O_UTIL_PARAMS_GET);
1242 1.10.2.2 nathanw mf->msgictx = IOP_ICTX;
1243 1.10.2.2 nathanw mf->msgtctx = im->im_tctx;
1244 1.10.2.2 nathanw mf->flags = 0;
1245 1.10.2.2 nathanw
1246 1.10.2.2 nathanw pgop->olh.count = htole16(1);
1247 1.10.2.2 nathanw pgop->olh.reserved = htole16(0);
1248 1.10.2.5 nathanw pgop->oat.operation = htole16(I2O_PARAMS_OP_FIELD_GET);
1249 1.10.2.2 nathanw pgop->oat.fieldcount = htole16(0xffff);
1250 1.10.2.2 nathanw pgop->oat.group = htole16(group);
1251 1.10.2.2 nathanw
1252 1.10.2.2 nathanw if (ii == NULL)
1253 1.10.2.13 nathanw PHOLD(curlwp);
1254 1.1 ad
1255 1.5 ad memset(buf, 0, size);
1256 1.10.2.4 nathanw iop_msg_map(sc, im, mb, pgop, sizeof(*pgop), 1, NULL);
1257 1.10.2.5 nathanw iop_msg_map(sc, im, mb, buf, size, 0, NULL);
1258 1.10.2.2 nathanw rv = iop_msg_post(sc, im, mb, (ii == NULL ? 30000 : 0));
1259 1.10.2.2 nathanw
1260 1.10.2.2 nathanw if (ii == NULL)
1261 1.10.2.13 nathanw PRELE(curlwp);
1262 1.10.2.2 nathanw
1263 1.10.2.2 nathanw /* Detect errors; let partial transfers to count as success. */
1264 1.10.2.2 nathanw if (ii == NULL && rv == 0) {
1265 1.10.2.2 nathanw if (rf->reqstatus == I2O_STATUS_ERROR_PARTIAL_XFER &&
1266 1.10.2.2 nathanw le16toh(rf->detail) == I2O_DSC_UNKNOWN_ERROR)
1267 1.10.2.2 nathanw rv = 0;
1268 1.10.2.2 nathanw else
1269 1.10.2.2 nathanw rv = (rf->reqstatus != 0 ? EIO : 0);
1270 1.10.2.5 nathanw
1271 1.10.2.5 nathanw if (rv != 0)
1272 1.10.2.5 nathanw printf("%s: FIELD_GET failed for tid %d group %d\n",
1273 1.10.2.5 nathanw sc->sc_dv.dv_xname, tid, group);
1274 1.10.2.2 nathanw }
1275 1.10.2.2 nathanw
1276 1.10.2.2 nathanw if (ii == NULL || rv != 0) {
1277 1.10.2.2 nathanw iop_msg_unmap(sc, im);
1278 1.10.2.2 nathanw iop_msg_free(sc, im);
1279 1.10.2.2 nathanw free(pgop, M_DEVBUF);
1280 1.10.2.2 nathanw free(rf, M_DEVBUF);
1281 1.10.2.2 nathanw }
1282 1.1 ad
1283 1.1 ad return (rv);
1284 1.10.2.2 nathanw }
1285 1.1 ad
1286 1.1 ad /*
1287 1.10.2.5 nathanw * Set a single field in a scalar parameter group.
1288 1.10.2.5 nathanw */
1289 1.10.2.5 nathanw int
1290 1.10.2.5 nathanw iop_field_set(struct iop_softc *sc, int tid, int group, void *buf,
1291 1.10.2.5 nathanw int size, int field)
1292 1.10.2.5 nathanw {
1293 1.10.2.5 nathanw struct iop_msg *im;
1294 1.10.2.5 nathanw struct i2o_util_params_op *mf;
1295 1.10.2.5 nathanw struct iop_pgop *pgop;
1296 1.10.2.5 nathanw int rv, totsize;
1297 1.10.2.5 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1298 1.10.2.5 nathanw
1299 1.10.2.5 nathanw totsize = sizeof(*pgop) + size;
1300 1.10.2.5 nathanw
1301 1.10.2.5 nathanw im = iop_msg_alloc(sc, IM_WAIT);
1302 1.10.2.5 nathanw if ((pgop = malloc(totsize, M_DEVBUF, M_WAITOK)) == NULL) {
1303 1.10.2.5 nathanw iop_msg_free(sc, im);
1304 1.10.2.5 nathanw return (ENOMEM);
1305 1.10.2.5 nathanw }
1306 1.10.2.5 nathanw
1307 1.10.2.5 nathanw mf = (struct i2o_util_params_op *)mb;
1308 1.10.2.5 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_util_params_op);
1309 1.10.2.5 nathanw mf->msgfunc = I2O_MSGFUNC(tid, I2O_UTIL_PARAMS_SET);
1310 1.10.2.5 nathanw mf->msgictx = IOP_ICTX;
1311 1.10.2.5 nathanw mf->msgtctx = im->im_tctx;
1312 1.10.2.5 nathanw mf->flags = 0;
1313 1.10.2.5 nathanw
1314 1.10.2.5 nathanw pgop->olh.count = htole16(1);
1315 1.10.2.5 nathanw pgop->olh.reserved = htole16(0);
1316 1.10.2.5 nathanw pgop->oat.operation = htole16(I2O_PARAMS_OP_FIELD_SET);
1317 1.10.2.5 nathanw pgop->oat.fieldcount = htole16(1);
1318 1.10.2.5 nathanw pgop->oat.group = htole16(group);
1319 1.10.2.5 nathanw pgop->oat.fields[0] = htole16(field);
1320 1.10.2.5 nathanw memcpy(pgop + 1, buf, size);
1321 1.10.2.5 nathanw
1322 1.10.2.5 nathanw iop_msg_map(sc, im, mb, pgop, totsize, 1, NULL);
1323 1.10.2.5 nathanw rv = iop_msg_post(sc, im, mb, 30000);
1324 1.10.2.5 nathanw if (rv != 0)
1325 1.10.2.5 nathanw printf("%s: FIELD_SET failed for tid %d group %d\n",
1326 1.10.2.5 nathanw sc->sc_dv.dv_xname, tid, group);
1327 1.10.2.5 nathanw
1328 1.10.2.5 nathanw iop_msg_unmap(sc, im);
1329 1.10.2.5 nathanw iop_msg_free(sc, im);
1330 1.10.2.5 nathanw free(pgop, M_DEVBUF);
1331 1.10.2.5 nathanw return (rv);
1332 1.10.2.5 nathanw }
1333 1.10.2.5 nathanw
1334 1.10.2.5 nathanw /*
1335 1.10.2.5 nathanw * Delete all rows in a tablular parameter group.
1336 1.10.2.5 nathanw */
1337 1.10.2.5 nathanw int
1338 1.10.2.5 nathanw iop_table_clear(struct iop_softc *sc, int tid, int group)
1339 1.10.2.5 nathanw {
1340 1.10.2.5 nathanw struct iop_msg *im;
1341 1.10.2.5 nathanw struct i2o_util_params_op *mf;
1342 1.10.2.5 nathanw struct iop_pgop pgop;
1343 1.10.2.5 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1344 1.10.2.5 nathanw int rv;
1345 1.10.2.5 nathanw
1346 1.10.2.5 nathanw im = iop_msg_alloc(sc, IM_WAIT);
1347 1.10.2.5 nathanw
1348 1.10.2.5 nathanw mf = (struct i2o_util_params_op *)mb;
1349 1.10.2.5 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_util_params_op);
1350 1.10.2.5 nathanw mf->msgfunc = I2O_MSGFUNC(tid, I2O_UTIL_PARAMS_SET);
1351 1.10.2.5 nathanw mf->msgictx = IOP_ICTX;
1352 1.10.2.5 nathanw mf->msgtctx = im->im_tctx;
1353 1.10.2.5 nathanw mf->flags = 0;
1354 1.10.2.5 nathanw
1355 1.10.2.5 nathanw pgop.olh.count = htole16(1);
1356 1.10.2.5 nathanw pgop.olh.reserved = htole16(0);
1357 1.10.2.5 nathanw pgop.oat.operation = htole16(I2O_PARAMS_OP_TABLE_CLEAR);
1358 1.10.2.5 nathanw pgop.oat.fieldcount = htole16(0);
1359 1.10.2.5 nathanw pgop.oat.group = htole16(group);
1360 1.10.2.5 nathanw pgop.oat.fields[0] = htole16(0);
1361 1.10.2.5 nathanw
1362 1.10.2.13 nathanw PHOLD(curlwp);
1363 1.10.2.5 nathanw iop_msg_map(sc, im, mb, &pgop, sizeof(pgop), 1, NULL);
1364 1.10.2.5 nathanw rv = iop_msg_post(sc, im, mb, 30000);
1365 1.10.2.5 nathanw if (rv != 0)
1366 1.10.2.5 nathanw printf("%s: TABLE_CLEAR failed for tid %d group %d\n",
1367 1.10.2.5 nathanw sc->sc_dv.dv_xname, tid, group);
1368 1.10.2.5 nathanw
1369 1.10.2.5 nathanw iop_msg_unmap(sc, im);
1370 1.10.2.13 nathanw PRELE(curlwp);
1371 1.10.2.5 nathanw iop_msg_free(sc, im);
1372 1.10.2.5 nathanw return (rv);
1373 1.10.2.5 nathanw }
1374 1.10.2.5 nathanw
1375 1.10.2.5 nathanw /*
1376 1.10.2.5 nathanw * Add a single row to a tabular parameter group. The row can have only one
1377 1.10.2.5 nathanw * field.
1378 1.10.2.5 nathanw */
1379 1.10.2.5 nathanw int
1380 1.10.2.5 nathanw iop_table_add_row(struct iop_softc *sc, int tid, int group, void *buf,
1381 1.10.2.5 nathanw int size, int row)
1382 1.10.2.5 nathanw {
1383 1.10.2.5 nathanw struct iop_msg *im;
1384 1.10.2.5 nathanw struct i2o_util_params_op *mf;
1385 1.10.2.5 nathanw struct iop_pgop *pgop;
1386 1.10.2.5 nathanw int rv, totsize;
1387 1.10.2.5 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1388 1.10.2.5 nathanw
1389 1.10.2.5 nathanw totsize = sizeof(*pgop) + sizeof(u_int16_t) * 2 + size;
1390 1.10.2.5 nathanw
1391 1.10.2.5 nathanw im = iop_msg_alloc(sc, IM_WAIT);
1392 1.10.2.5 nathanw if ((pgop = malloc(totsize, M_DEVBUF, M_WAITOK)) == NULL) {
1393 1.10.2.5 nathanw iop_msg_free(sc, im);
1394 1.10.2.5 nathanw return (ENOMEM);
1395 1.10.2.5 nathanw }
1396 1.10.2.5 nathanw
1397 1.10.2.5 nathanw mf = (struct i2o_util_params_op *)mb;
1398 1.10.2.5 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_util_params_op);
1399 1.10.2.5 nathanw mf->msgfunc = I2O_MSGFUNC(tid, I2O_UTIL_PARAMS_SET);
1400 1.10.2.5 nathanw mf->msgictx = IOP_ICTX;
1401 1.10.2.5 nathanw mf->msgtctx = im->im_tctx;
1402 1.10.2.5 nathanw mf->flags = 0;
1403 1.10.2.5 nathanw
1404 1.10.2.5 nathanw pgop->olh.count = htole16(1);
1405 1.10.2.5 nathanw pgop->olh.reserved = htole16(0);
1406 1.10.2.5 nathanw pgop->oat.operation = htole16(I2O_PARAMS_OP_ROW_ADD);
1407 1.10.2.5 nathanw pgop->oat.fieldcount = htole16(1);
1408 1.10.2.5 nathanw pgop->oat.group = htole16(group);
1409 1.10.2.5 nathanw pgop->oat.fields[0] = htole16(0); /* FieldIdx */
1410 1.10.2.5 nathanw pgop->oat.fields[1] = htole16(1); /* RowCount */
1411 1.10.2.5 nathanw pgop->oat.fields[2] = htole16(row); /* KeyValue */
1412 1.10.2.5 nathanw memcpy(&pgop->oat.fields[3], buf, size);
1413 1.10.2.5 nathanw
1414 1.10.2.5 nathanw iop_msg_map(sc, im, mb, pgop, totsize, 1, NULL);
1415 1.10.2.5 nathanw rv = iop_msg_post(sc, im, mb, 30000);
1416 1.10.2.5 nathanw if (rv != 0)
1417 1.10.2.5 nathanw printf("%s: ADD_ROW failed for tid %d group %d row %d\n",
1418 1.10.2.5 nathanw sc->sc_dv.dv_xname, tid, group, row);
1419 1.10.2.5 nathanw
1420 1.10.2.5 nathanw iop_msg_unmap(sc, im);
1421 1.10.2.5 nathanw iop_msg_free(sc, im);
1422 1.10.2.5 nathanw free(pgop, M_DEVBUF);
1423 1.10.2.5 nathanw return (rv);
1424 1.10.2.5 nathanw }
1425 1.10.2.5 nathanw
1426 1.10.2.5 nathanw /*
1427 1.5 ad * Execute a simple command (no parameters).
1428 1.1 ad */
1429 1.1 ad int
1430 1.5 ad iop_simple_cmd(struct iop_softc *sc, int tid, int function, int ictx,
1431 1.5 ad int async, int timo)
1432 1.1 ad {
1433 1.1 ad struct iop_msg *im;
1434 1.10.2.2 nathanw struct i2o_msg mf;
1435 1.5 ad int rv, fl;
1436 1.1 ad
1437 1.10.2.2 nathanw fl = (async != 0 ? IM_WAIT : IM_POLL);
1438 1.10.2.4 nathanw im = iop_msg_alloc(sc, fl);
1439 1.1 ad
1440 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_msg);
1441 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(tid, function);
1442 1.10.2.2 nathanw mf.msgictx = ictx;
1443 1.10.2.2 nathanw mf.msgtctx = im->im_tctx;
1444 1.1 ad
1445 1.10.2.2 nathanw rv = iop_msg_post(sc, im, &mf, timo);
1446 1.10.2.2 nathanw iop_msg_free(sc, im);
1447 1.1 ad return (rv);
1448 1.1 ad }
1449 1.1 ad
1450 1.1 ad /*
1451 1.5 ad * Post the system table to the IOP.
1452 1.1 ad */
1453 1.1 ad static int
1454 1.1 ad iop_systab_set(struct iop_softc *sc)
1455 1.1 ad {
1456 1.10.2.2 nathanw struct i2o_exec_sys_tab_set *mf;
1457 1.1 ad struct iop_msg *im;
1458 1.10.2.2 nathanw bus_space_handle_t bsh;
1459 1.10.2.2 nathanw bus_addr_t boo;
1460 1.1 ad u_int32_t mema[2], ioa[2];
1461 1.1 ad int rv;
1462 1.10.2.2 nathanw u_int32_t mb[IOP_MAX_MSG_SIZE / sizeof(u_int32_t)];
1463 1.1 ad
1464 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT);
1465 1.10.2.2 nathanw
1466 1.10.2.2 nathanw mf = (struct i2o_exec_sys_tab_set *)mb;
1467 1.10.2.2 nathanw mf->msgflags = I2O_MSGFLAGS(i2o_exec_sys_tab_set);
1468 1.10.2.2 nathanw mf->msgfunc = I2O_MSGFUNC(I2O_TID_IOP, I2O_EXEC_SYS_TAB_SET);
1469 1.10.2.2 nathanw mf->msgictx = IOP_ICTX;
1470 1.10.2.2 nathanw mf->msgtctx = im->im_tctx;
1471 1.10.2.2 nathanw mf->iopid = (sc->sc_dv.dv_unit + 2) << 12;
1472 1.10.2.2 nathanw mf->segnumber = 0;
1473 1.10.2.2 nathanw
1474 1.10.2.2 nathanw mema[1] = sc->sc_status.desiredprivmemsize;
1475 1.10.2.2 nathanw ioa[1] = sc->sc_status.desiredpriviosize;
1476 1.10.2.2 nathanw
1477 1.10.2.2 nathanw if (mema[1] != 0) {
1478 1.10.2.2 nathanw rv = bus_space_alloc(sc->sc_bus_memt, 0, 0xffffffff,
1479 1.10.2.2 nathanw le32toh(mema[1]), PAGE_SIZE, 0, 0, &boo, &bsh);
1480 1.10.2.2 nathanw mema[0] = htole32(boo);
1481 1.10.2.2 nathanw if (rv != 0) {
1482 1.10.2.2 nathanw printf("%s: can't alloc priv mem space, err = %d\n",
1483 1.10.2.2 nathanw sc->sc_dv.dv_xname, rv);
1484 1.10.2.2 nathanw mema[0] = 0;
1485 1.10.2.2 nathanw mema[1] = 0;
1486 1.10.2.2 nathanw }
1487 1.10.2.2 nathanw }
1488 1.1 ad
1489 1.10.2.2 nathanw if (ioa[1] != 0) {
1490 1.10.2.2 nathanw rv = bus_space_alloc(sc->sc_bus_iot, 0, 0xffff,
1491 1.10.2.2 nathanw le32toh(ioa[1]), 0, 0, 0, &boo, &bsh);
1492 1.10.2.2 nathanw ioa[0] = htole32(boo);
1493 1.10.2.2 nathanw if (rv != 0) {
1494 1.10.2.2 nathanw printf("%s: can't alloc priv i/o space, err = %d\n",
1495 1.10.2.2 nathanw sc->sc_dv.dv_xname, rv);
1496 1.10.2.2 nathanw ioa[0] = 0;
1497 1.10.2.2 nathanw ioa[1] = 0;
1498 1.10.2.2 nathanw }
1499 1.10.2.2 nathanw }
1500 1.1 ad
1501 1.10.2.13 nathanw PHOLD(curlwp);
1502 1.10.2.4 nathanw iop_msg_map(sc, im, mb, iop_systab, iop_systab_size, 1, NULL);
1503 1.10.2.4 nathanw iop_msg_map(sc, im, mb, mema, sizeof(mema), 1, NULL);
1504 1.10.2.4 nathanw iop_msg_map(sc, im, mb, ioa, sizeof(ioa), 1, NULL);
1505 1.10.2.2 nathanw rv = iop_msg_post(sc, im, mb, 5000);
1506 1.1 ad iop_msg_unmap(sc, im);
1507 1.10.2.2 nathanw iop_msg_free(sc, im);
1508 1.10.2.13 nathanw PRELE(curlwp);
1509 1.1 ad return (rv);
1510 1.1 ad }
1511 1.1 ad
1512 1.1 ad /*
1513 1.10.2.2 nathanw * Reset the IOP. Must be called with interrupts disabled.
1514 1.1 ad */
1515 1.1 ad static int
1516 1.1 ad iop_reset(struct iop_softc *sc)
1517 1.1 ad {
1518 1.10.2.4 nathanw u_int32_t mfa, *sw;
1519 1.10.2.2 nathanw struct i2o_exec_iop_reset mf;
1520 1.1 ad int rv;
1521 1.10.2.4 nathanw paddr_t pa;
1522 1.1 ad
1523 1.10.2.4 nathanw sw = (u_int32_t *)sc->sc_scr;
1524 1.10.2.4 nathanw pa = sc->sc_scr_seg->ds_addr;
1525 1.1 ad
1526 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_exec_iop_reset);
1527 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(I2O_TID_IOP, I2O_EXEC_IOP_RESET);
1528 1.10.2.2 nathanw mf.reserved[0] = 0;
1529 1.10.2.2 nathanw mf.reserved[1] = 0;
1530 1.10.2.2 nathanw mf.reserved[2] = 0;
1531 1.10.2.2 nathanw mf.reserved[3] = 0;
1532 1.10.2.4 nathanw mf.statuslow = (u_int32_t)pa;
1533 1.10.2.4 nathanw mf.statushigh = (u_int32_t)((u_int64_t)pa >> 32);
1534 1.10.2.4 nathanw
1535 1.10.2.4 nathanw *sw = htole32(0);
1536 1.10.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_scr_dmamap, 0, sizeof(*sw),
1537 1.10.2.4 nathanw BUS_DMASYNC_PREREAD);
1538 1.1 ad
1539 1.10.2.2 nathanw if ((rv = iop_post(sc, (u_int32_t *)&mf)))
1540 1.1 ad return (rv);
1541 1.1 ad
1542 1.10.2.4 nathanw POLL(2500,
1543 1.10.2.4 nathanw (bus_dmamap_sync(sc->sc_dmat, sc->sc_scr_dmamap, 0, sizeof(*sw),
1544 1.10.2.4 nathanw BUS_DMASYNC_POSTREAD), *sw != 0));
1545 1.10.2.4 nathanw if (*sw != htole32(I2O_RESET_IN_PROGRESS)) {
1546 1.10.2.4 nathanw printf("%s: reset rejected, status 0x%x\n",
1547 1.10.2.4 nathanw sc->sc_dv.dv_xname, le32toh(*sw));
1548 1.1 ad return (EIO);
1549 1.1 ad }
1550 1.1 ad
1551 1.1 ad /*
1552 1.5 ad * IOP is now in the INIT state. Wait no more than 10 seconds for
1553 1.1 ad * the inbound queue to become responsive.
1554 1.1 ad */
1555 1.5 ad POLL(10000, (mfa = iop_inl(sc, IOP_REG_IFIFO)) != IOP_MFA_EMPTY);
1556 1.1 ad if (mfa == IOP_MFA_EMPTY) {
1557 1.1 ad printf("%s: reset failed\n", sc->sc_dv.dv_xname);
1558 1.1 ad return (EIO);
1559 1.1 ad }
1560 1.1 ad
1561 1.1 ad iop_release_mfa(sc, mfa);
1562 1.1 ad return (0);
1563 1.1 ad }
1564 1.1 ad
1565 1.1 ad /*
1566 1.10.2.2 nathanw * Register a new initiator. Must be called with the configuration lock
1567 1.10.2.2 nathanw * held.
1568 1.1 ad */
1569 1.10.2.2 nathanw void
1570 1.1 ad iop_initiator_register(struct iop_softc *sc, struct iop_initiator *ii)
1571 1.1 ad {
1572 1.10.2.2 nathanw static int ictxgen;
1573 1.10.2.2 nathanw int s;
1574 1.5 ad
1575 1.10.2.2 nathanw /* 0 is reserved (by us) for system messages. */
1576 1.10.2.2 nathanw ii->ii_ictx = ++ictxgen;
1577 1.1 ad
1578 1.10.2.2 nathanw /*
1579 1.10.2.2 nathanw * `Utility initiators' don't make it onto the per-IOP initiator list
1580 1.10.2.2 nathanw * (which is used only for configuration), but do get one slot on
1581 1.10.2.2 nathanw * the inbound queue.
1582 1.10.2.2 nathanw */
1583 1.10.2.2 nathanw if ((ii->ii_flags & II_UTILITY) == 0) {
1584 1.10.2.2 nathanw LIST_INSERT_HEAD(&sc->sc_iilist, ii, ii_list);
1585 1.10.2.2 nathanw sc->sc_nii++;
1586 1.10.2.2 nathanw } else
1587 1.10.2.2 nathanw sc->sc_nuii++;
1588 1.1 ad
1589 1.10.2.2 nathanw s = splbio();
1590 1.10.2.2 nathanw LIST_INSERT_HEAD(IOP_ICTXHASH(ii->ii_ictx), ii, ii_hash);
1591 1.10.2.2 nathanw splx(s);
1592 1.1 ad }
1593 1.1 ad
1594 1.1 ad /*
1595 1.10.2.2 nathanw * Unregister an initiator. Must be called with the configuration lock
1596 1.10.2.2 nathanw * held.
1597 1.1 ad */
1598 1.1 ad void
1599 1.1 ad iop_initiator_unregister(struct iop_softc *sc, struct iop_initiator *ii)
1600 1.1 ad {
1601 1.10.2.2 nathanw int s;
1602 1.1 ad
1603 1.10.2.2 nathanw if ((ii->ii_flags & II_UTILITY) == 0) {
1604 1.10.2.2 nathanw LIST_REMOVE(ii, ii_list);
1605 1.10.2.2 nathanw sc->sc_nii--;
1606 1.10.2.2 nathanw } else
1607 1.10.2.2 nathanw sc->sc_nuii--;
1608 1.10.2.2 nathanw
1609 1.10.2.2 nathanw s = splbio();
1610 1.5 ad LIST_REMOVE(ii, ii_hash);
1611 1.10.2.2 nathanw splx(s);
1612 1.1 ad }
1613 1.1 ad
1614 1.1 ad /*
1615 1.10.2.2 nathanw * Handle a reply frame from the IOP.
1616 1.1 ad */
1617 1.1 ad static int
1618 1.5 ad iop_handle_reply(struct iop_softc *sc, u_int32_t rmfa)
1619 1.1 ad {
1620 1.1 ad struct iop_msg *im;
1621 1.1 ad struct i2o_reply *rb;
1622 1.10.2.2 nathanw struct i2o_fault_notify *fn;
1623 1.1 ad struct iop_initiator *ii;
1624 1.5 ad u_int off, ictx, tctx, status, size;
1625 1.1 ad
1626 1.1 ad off = (int)(rmfa - sc->sc_rep_phys);
1627 1.1 ad rb = (struct i2o_reply *)(sc->sc_rep + off);
1628 1.1 ad
1629 1.10.2.4 nathanw /* Perform reply queue DMA synchronisation. */
1630 1.10.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_rep_dmamap, off,
1631 1.10.2.7 nathanw sc->sc_framesize, BUS_DMASYNC_POSTREAD);
1632 1.10.2.2 nathanw if (--sc->sc_curib != 0)
1633 1.1 ad bus_dmamap_sync(sc->sc_dmat, sc->sc_rep_dmamap,
1634 1.1 ad 0, sc->sc_rep_size, BUS_DMASYNC_PREREAD);
1635 1.1 ad
1636 1.1 ad #ifdef I2ODEBUG
1637 1.1 ad if ((le32toh(rb->msgflags) & I2O_MSGFLAGS_64BIT) != 0)
1638 1.5 ad panic("iop_handle_reply: 64-bit reply");
1639 1.1 ad #endif
1640 1.1 ad /*
1641 1.1 ad * Find the initiator.
1642 1.1 ad */
1643 1.1 ad ictx = le32toh(rb->msgictx);
1644 1.1 ad if (ictx == IOP_ICTX)
1645 1.1 ad ii = NULL;
1646 1.1 ad else {
1647 1.5 ad ii = LIST_FIRST(IOP_ICTXHASH(ictx));
1648 1.5 ad for (; ii != NULL; ii = LIST_NEXT(ii, ii_hash))
1649 1.5 ad if (ii->ii_ictx == ictx)
1650 1.5 ad break;
1651 1.5 ad if (ii == NULL) {
1652 1.1 ad #ifdef I2ODEBUG
1653 1.10.2.2 nathanw iop_reply_print(sc, rb);
1654 1.1 ad #endif
1655 1.10.2.2 nathanw printf("%s: WARNING: bad ictx returned (%x)\n",
1656 1.5 ad sc->sc_dv.dv_xname, ictx);
1657 1.5 ad return (-1);
1658 1.5 ad }
1659 1.1 ad }
1660 1.1 ad
1661 1.10.2.2 nathanw /*
1662 1.10.2.3 nathanw * If we received a transport failure notice, we've got to dig the
1663 1.10.2.2 nathanw * transaction context (if any) out of the original message frame,
1664 1.10.2.2 nathanw * and then release the original MFA back to the inbound FIFO.
1665 1.10.2.2 nathanw */
1666 1.10.2.2 nathanw if ((rb->msgflags & I2O_MSGFLAGS_FAIL) != 0) {
1667 1.10.2.2 nathanw status = I2O_STATUS_SUCCESS;
1668 1.10.2.2 nathanw
1669 1.10.2.2 nathanw fn = (struct i2o_fault_notify *)rb;
1670 1.10.2.4 nathanw tctx = iop_inl(sc, fn->lowmfa + 12);
1671 1.10.2.2 nathanw iop_release_mfa(sc, fn->lowmfa);
1672 1.10.2.2 nathanw iop_tfn_print(sc, fn);
1673 1.10.2.2 nathanw } else {
1674 1.10.2.2 nathanw status = rb->reqstatus;
1675 1.10.2.2 nathanw tctx = le32toh(rb->msgtctx);
1676 1.10.2.2 nathanw }
1677 1.1 ad
1678 1.10.2.4 nathanw if (ii == NULL || (ii->ii_flags & II_NOTCTX) == 0) {
1679 1.1 ad /*
1680 1.1 ad * This initiator tracks state using message wrappers.
1681 1.1 ad *
1682 1.1 ad * Find the originating message wrapper, and if requested
1683 1.1 ad * notify the initiator.
1684 1.1 ad */
1685 1.10.2.2 nathanw im = sc->sc_ims + (tctx & IOP_TCTX_MASK);
1686 1.10.2.2 nathanw if ((tctx & IOP_TCTX_MASK) > sc->sc_maxib ||
1687 1.10.2.2 nathanw (im->im_flags & IM_ALLOCED) == 0 ||
1688 1.10.2.2 nathanw tctx != im->im_tctx) {
1689 1.10.2.2 nathanw printf("%s: WARNING: bad tctx returned (0x%08x, %p)\n",
1690 1.10.2.2 nathanw sc->sc_dv.dv_xname, tctx, im);
1691 1.10.2.2 nathanw if (im != NULL)
1692 1.10.2.2 nathanw printf("%s: flags=0x%08x tctx=0x%08x\n",
1693 1.10.2.2 nathanw sc->sc_dv.dv_xname, im->im_flags,
1694 1.10.2.2 nathanw im->im_tctx);
1695 1.5 ad #ifdef I2ODEBUG
1696 1.10.2.2 nathanw if ((rb->msgflags & I2O_MSGFLAGS_FAIL) == 0)
1697 1.10.2.2 nathanw iop_reply_print(sc, rb);
1698 1.5 ad #endif
1699 1.5 ad return (-1);
1700 1.5 ad }
1701 1.10.2.2 nathanw
1702 1.10.2.2 nathanw if ((rb->msgflags & I2O_MSGFLAGS_FAIL) != 0)
1703 1.10.2.2 nathanw im->im_flags |= IM_FAIL;
1704 1.10.2.2 nathanw
1705 1.1 ad #ifdef I2ODEBUG
1706 1.1 ad if ((im->im_flags & IM_REPLIED) != 0)
1707 1.5 ad panic("%s: dup reply", sc->sc_dv.dv_xname);
1708 1.1 ad #endif
1709 1.1 ad im->im_flags |= IM_REPLIED;
1710 1.1 ad
1711 1.1 ad #ifdef I2ODEBUG
1712 1.10.2.2 nathanw if (status != I2O_STATUS_SUCCESS)
1713 1.10.2.2 nathanw iop_reply_print(sc, rb);
1714 1.1 ad #endif
1715 1.10.2.2 nathanw im->im_reqstatus = status;
1716 1.10.2.2 nathanw
1717 1.10.2.2 nathanw /* Copy the reply frame, if requested. */
1718 1.10.2.2 nathanw if (im->im_rb != NULL) {
1719 1.5 ad size = (le32toh(rb->msgflags) >> 14) & ~3;
1720 1.10.2.2 nathanw #ifdef I2ODEBUG
1721 1.10.2.7 nathanw if (size > sc->sc_framesize)
1722 1.10.2.2 nathanw panic("iop_handle_reply: reply too large");
1723 1.10.2.2 nathanw #endif
1724 1.10.2.2 nathanw memcpy(im->im_rb, rb, size);
1725 1.10.2.2 nathanw }
1726 1.10.2.2 nathanw
1727 1.10.2.2 nathanw /* Notify the initiator. */
1728 1.10.2.2 nathanw if ((im->im_flags & IM_WAIT) != 0)
1729 1.1 ad wakeup(im);
1730 1.10.2.2 nathanw else if ((im->im_flags & (IM_POLL | IM_POLL_INTR)) != IM_POLL)
1731 1.1 ad (*ii->ii_intr)(ii->ii_dv, im, rb);
1732 1.1 ad } else {
1733 1.1 ad /*
1734 1.1 ad * This initiator discards message wrappers.
1735 1.1 ad *
1736 1.1 ad * Simply pass the reply frame to the initiator.
1737 1.1 ad */
1738 1.1 ad (*ii->ii_intr)(ii->ii_dv, NULL, rb);
1739 1.1 ad }
1740 1.1 ad
1741 1.1 ad return (status);
1742 1.1 ad }
1743 1.1 ad
1744 1.1 ad /*
1745 1.10.2.2 nathanw * Handle an interrupt from the IOP.
1746 1.1 ad */
1747 1.1 ad int
1748 1.1 ad iop_intr(void *arg)
1749 1.1 ad {
1750 1.1 ad struct iop_softc *sc;
1751 1.5 ad u_int32_t rmfa;
1752 1.1 ad
1753 1.1 ad sc = arg;
1754 1.1 ad
1755 1.5 ad if ((iop_inl(sc, IOP_REG_INTR_STATUS) & IOP_INTR_OFIFO) == 0)
1756 1.5 ad return (0);
1757 1.5 ad
1758 1.5 ad for (;;) {
1759 1.5 ad /* Double read to account for IOP bug. */
1760 1.10.2.2 nathanw if ((rmfa = iop_inl(sc, IOP_REG_OFIFO)) == IOP_MFA_EMPTY) {
1761 1.10.2.2 nathanw rmfa = iop_inl(sc, IOP_REG_OFIFO);
1762 1.10.2.2 nathanw if (rmfa == IOP_MFA_EMPTY)
1763 1.10.2.2 nathanw break;
1764 1.10.2.2 nathanw }
1765 1.5 ad iop_handle_reply(sc, rmfa);
1766 1.10.2.2 nathanw iop_outl(sc, IOP_REG_OFIFO, rmfa);
1767 1.1 ad }
1768 1.1 ad
1769 1.5 ad return (1);
1770 1.5 ad }
1771 1.5 ad
1772 1.5 ad /*
1773 1.5 ad * Handle an event signalled by the executive.
1774 1.5 ad */
1775 1.5 ad static void
1776 1.5 ad iop_intr_event(struct device *dv, struct iop_msg *im, void *reply)
1777 1.5 ad {
1778 1.5 ad struct i2o_util_event_register_reply *rb;
1779 1.5 ad struct iop_softc *sc;
1780 1.5 ad u_int event;
1781 1.5 ad
1782 1.5 ad sc = (struct iop_softc *)dv;
1783 1.5 ad rb = reply;
1784 1.5 ad
1785 1.10.2.2 nathanw if ((rb->msgflags & I2O_MSGFLAGS_FAIL) != 0)
1786 1.5 ad return;
1787 1.5 ad
1788 1.10.2.2 nathanw event = le32toh(rb->event);
1789 1.5 ad printf("%s: event 0x%08x received\n", dv->dv_xname, event);
1790 1.1 ad }
1791 1.1 ad
1792 1.1 ad /*
1793 1.1 ad * Allocate a message wrapper.
1794 1.1 ad */
1795 1.10.2.2 nathanw struct iop_msg *
1796 1.10.2.4 nathanw iop_msg_alloc(struct iop_softc *sc, int flags)
1797 1.1 ad {
1798 1.1 ad struct iop_msg *im;
1799 1.10.2.2 nathanw static u_int tctxgen;
1800 1.10.2.2 nathanw int s, i;
1801 1.1 ad
1802 1.1 ad #ifdef I2ODEBUG
1803 1.1 ad if ((flags & IM_SYSMASK) != 0)
1804 1.1 ad panic("iop_msg_alloc: system flags specified");
1805 1.1 ad #endif
1806 1.1 ad
1807 1.10.2.4 nathanw s = splbio();
1808 1.10.2.2 nathanw im = SLIST_FIRST(&sc->sc_im_freelist);
1809 1.10.2.2 nathanw #if defined(DIAGNOSTIC) || defined(I2ODEBUG)
1810 1.10.2.2 nathanw if (im == NULL)
1811 1.10.2.2 nathanw panic("iop_msg_alloc: no free wrappers");
1812 1.10.2.2 nathanw #endif
1813 1.10.2.2 nathanw SLIST_REMOVE_HEAD(&sc->sc_im_freelist, im_chain);
1814 1.10.2.2 nathanw splx(s);
1815 1.1 ad
1816 1.10.2.2 nathanw im->im_tctx = (im->im_tctx & IOP_TCTX_MASK) | tctxgen;
1817 1.10.2.2 nathanw tctxgen += (1 << IOP_TCTX_SHIFT);
1818 1.1 ad im->im_flags = flags | IM_ALLOCED;
1819 1.10.2.2 nathanw im->im_rb = NULL;
1820 1.10.2.2 nathanw i = 0;
1821 1.10.2.2 nathanw do {
1822 1.10.2.2 nathanw im->im_xfer[i++].ix_size = 0;
1823 1.10.2.2 nathanw } while (i < IOP_MAX_MSG_XFERS);
1824 1.1 ad
1825 1.10.2.2 nathanw return (im);
1826 1.1 ad }
1827 1.1 ad
1828 1.1 ad /*
1829 1.1 ad * Free a message wrapper.
1830 1.1 ad */
1831 1.1 ad void
1832 1.10.2.2 nathanw iop_msg_free(struct iop_softc *sc, struct iop_msg *im)
1833 1.1 ad {
1834 1.1 ad int s;
1835 1.1 ad
1836 1.1 ad #ifdef I2ODEBUG
1837 1.1 ad if ((im->im_flags & IM_ALLOCED) == 0)
1838 1.1 ad panic("iop_msg_free: wrapper not allocated");
1839 1.1 ad #endif
1840 1.1 ad
1841 1.1 ad im->im_flags = 0;
1842 1.10.2.2 nathanw s = splbio();
1843 1.10.2.2 nathanw SLIST_INSERT_HEAD(&sc->sc_im_freelist, im, im_chain);
1844 1.1 ad splx(s);
1845 1.1 ad }
1846 1.1 ad
1847 1.1 ad /*
1848 1.5 ad * Map a data transfer. Write a scatter-gather list into the message frame.
1849 1.1 ad */
1850 1.1 ad int
1851 1.10.2.2 nathanw iop_msg_map(struct iop_softc *sc, struct iop_msg *im, u_int32_t *mb,
1852 1.10.2.4 nathanw void *xferaddr, int xfersize, int out, struct proc *up)
1853 1.1 ad {
1854 1.10.2.2 nathanw bus_dmamap_t dm;
1855 1.10.2.2 nathanw bus_dma_segment_t *ds;
1856 1.1 ad struct iop_xfer *ix;
1857 1.10.2.2 nathanw u_int rv, i, nsegs, flg, off, xn;
1858 1.10.2.2 nathanw u_int32_t *p;
1859 1.5 ad
1860 1.10.2.2 nathanw for (xn = 0, ix = im->im_xfer; xn < IOP_MAX_MSG_XFERS; xn++, ix++)
1861 1.1 ad if (ix->ix_size == 0)
1862 1.1 ad break;
1863 1.10.2.2 nathanw
1864 1.1 ad #ifdef I2ODEBUG
1865 1.10.2.2 nathanw if (xfersize == 0)
1866 1.10.2.2 nathanw panic("iop_msg_map: null transfer");
1867 1.10.2.2 nathanw if (xfersize > IOP_MAX_XFER)
1868 1.10.2.2 nathanw panic("iop_msg_map: transfer too large");
1869 1.10.2.2 nathanw if (xn == IOP_MAX_MSG_XFERS)
1870 1.1 ad panic("iop_msg_map: too many xfers");
1871 1.1 ad #endif
1872 1.1 ad
1873 1.10.2.2 nathanw /*
1874 1.10.2.2 nathanw * Only the first DMA map is static.
1875 1.10.2.2 nathanw */
1876 1.10.2.2 nathanw if (xn != 0) {
1877 1.1 ad rv = bus_dmamap_create(sc->sc_dmat, IOP_MAX_XFER,
1878 1.10.2.2 nathanw IOP_MAX_SEGS, IOP_MAX_XFER, 0,
1879 1.1 ad BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ix->ix_map);
1880 1.1 ad if (rv != 0)
1881 1.1 ad return (rv);
1882 1.1 ad }
1883 1.1 ad
1884 1.10.2.2 nathanw dm = ix->ix_map;
1885 1.10.2.4 nathanw rv = bus_dmamap_load(sc->sc_dmat, dm, xferaddr, xfersize, up,
1886 1.10.2.4 nathanw (up == NULL ? BUS_DMA_NOWAIT : 0));
1887 1.1 ad if (rv != 0)
1888 1.10.2.2 nathanw goto bad;
1889 1.10.2.2 nathanw
1890 1.10.2.2 nathanw /*
1891 1.10.2.2 nathanw * How many SIMPLE SG elements can we fit in this message?
1892 1.10.2.2 nathanw */
1893 1.10.2.2 nathanw off = mb[0] >> 16;
1894 1.10.2.2 nathanw p = mb + off;
1895 1.10.2.7 nathanw nsegs = ((sc->sc_framesize >> 2) - off) >> 1;
1896 1.10.2.2 nathanw
1897 1.10.2.2 nathanw if (dm->dm_nsegs > nsegs) {
1898 1.10.2.2 nathanw bus_dmamap_unload(sc->sc_dmat, ix->ix_map);
1899 1.10.2.2 nathanw rv = EFBIG;
1900 1.10.2.2 nathanw DPRINTF(("iop_msg_map: too many segs\n"));
1901 1.10.2.2 nathanw goto bad;
1902 1.10.2.2 nathanw }
1903 1.10.2.2 nathanw
1904 1.10.2.2 nathanw nsegs = dm->dm_nsegs;
1905 1.10.2.2 nathanw xfersize = 0;
1906 1.1 ad
1907 1.10.2.2 nathanw /*
1908 1.10.2.2 nathanw * Write out the SG list.
1909 1.10.2.2 nathanw */
1910 1.1 ad if (out)
1911 1.10.2.2 nathanw flg = I2O_SGL_SIMPLE | I2O_SGL_DATA_OUT;
1912 1.1 ad else
1913 1.10.2.2 nathanw flg = I2O_SGL_SIMPLE;
1914 1.1 ad
1915 1.10.2.2 nathanw for (i = nsegs, ds = dm->dm_segs; i > 1; i--, p += 2, ds++) {
1916 1.10.2.2 nathanw p[0] = (u_int32_t)ds->ds_len | flg;
1917 1.10.2.2 nathanw p[1] = (u_int32_t)ds->ds_addr;
1918 1.10.2.2 nathanw xfersize += ds->ds_len;
1919 1.1 ad }
1920 1.1 ad
1921 1.10.2.2 nathanw p[0] = (u_int32_t)ds->ds_len | flg | I2O_SGL_END_BUFFER;
1922 1.10.2.2 nathanw p[1] = (u_int32_t)ds->ds_addr;
1923 1.10.2.2 nathanw xfersize += ds->ds_len;
1924 1.10.2.2 nathanw
1925 1.10.2.2 nathanw /* Fix up the transfer record, and sync the map. */
1926 1.10.2.2 nathanw ix->ix_flags = (out ? IX_OUT : IX_IN);
1927 1.10.2.2 nathanw ix->ix_size = xfersize;
1928 1.10.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, ix->ix_map, 0, xfersize,
1929 1.10.2.2 nathanw out ? BUS_DMASYNC_POSTWRITE : BUS_DMASYNC_POSTREAD);
1930 1.10.2.2 nathanw
1931 1.1 ad /*
1932 1.1 ad * If this is the first xfer we've mapped for this message, adjust
1933 1.1 ad * the SGL offset field in the message header.
1934 1.1 ad */
1935 1.2 ad if ((im->im_flags & IM_SGLOFFADJ) == 0) {
1936 1.10.2.2 nathanw mb[0] += (mb[0] >> 12) & 0xf0;
1937 1.2 ad im->im_flags |= IM_SGLOFFADJ;
1938 1.2 ad }
1939 1.10.2.2 nathanw mb[0] += (nsegs << 17);
1940 1.10.2.2 nathanw return (0);
1941 1.10.2.2 nathanw
1942 1.10.2.2 nathanw bad:
1943 1.10.2.2 nathanw if (xn != 0)
1944 1.10.2.2 nathanw bus_dmamap_destroy(sc->sc_dmat, ix->ix_map);
1945 1.10.2.2 nathanw return (rv);
1946 1.10.2.2 nathanw }
1947 1.10.2.2 nathanw
1948 1.10.2.2 nathanw /*
1949 1.10.2.2 nathanw * Map a block I/O data transfer (different in that there's only one per
1950 1.10.2.2 nathanw * message maximum, and PAGE addressing may be used). Write a scatter
1951 1.10.2.2 nathanw * gather list into the message frame.
1952 1.10.2.2 nathanw */
1953 1.10.2.2 nathanw int
1954 1.10.2.2 nathanw iop_msg_map_bio(struct iop_softc *sc, struct iop_msg *im, u_int32_t *mb,
1955 1.10.2.2 nathanw void *xferaddr, int xfersize, int out)
1956 1.10.2.2 nathanw {
1957 1.10.2.2 nathanw bus_dma_segment_t *ds;
1958 1.10.2.2 nathanw bus_dmamap_t dm;
1959 1.10.2.2 nathanw struct iop_xfer *ix;
1960 1.10.2.2 nathanw u_int rv, i, nsegs, off, slen, tlen, flg;
1961 1.10.2.2 nathanw paddr_t saddr, eaddr;
1962 1.10.2.2 nathanw u_int32_t *p;
1963 1.10.2.2 nathanw
1964 1.10.2.2 nathanw #ifdef I2ODEBUG
1965 1.10.2.2 nathanw if (xfersize == 0)
1966 1.10.2.2 nathanw panic("iop_msg_map_bio: null transfer");
1967 1.10.2.2 nathanw if (xfersize > IOP_MAX_XFER)
1968 1.10.2.2 nathanw panic("iop_msg_map_bio: transfer too large");
1969 1.10.2.2 nathanw if ((im->im_flags & IM_SGLOFFADJ) != 0)
1970 1.10.2.2 nathanw panic("iop_msg_map_bio: SGLOFFADJ");
1971 1.10.2.2 nathanw #endif
1972 1.10.2.2 nathanw
1973 1.10.2.2 nathanw ix = im->im_xfer;
1974 1.10.2.2 nathanw dm = ix->ix_map;
1975 1.10.2.4 nathanw rv = bus_dmamap_load(sc->sc_dmat, dm, xferaddr, xfersize, NULL,
1976 1.10.2.4 nathanw BUS_DMA_NOWAIT | BUS_DMA_STREAMING);
1977 1.10.2.2 nathanw if (rv != 0)
1978 1.10.2.2 nathanw return (rv);
1979 1.10.2.2 nathanw
1980 1.10.2.2 nathanw off = mb[0] >> 16;
1981 1.10.2.7 nathanw nsegs = ((sc->sc_framesize >> 2) - off) >> 1;
1982 1.10.2.2 nathanw
1983 1.10.2.2 nathanw /*
1984 1.10.2.2 nathanw * If the transfer is highly fragmented and won't fit using SIMPLE
1985 1.10.2.2 nathanw * elements, use PAGE_LIST elements instead. SIMPLE elements are
1986 1.10.2.2 nathanw * potentially more efficient, both for us and the IOP.
1987 1.10.2.2 nathanw */
1988 1.10.2.2 nathanw if (dm->dm_nsegs > nsegs) {
1989 1.10.2.2 nathanw nsegs = 1;
1990 1.10.2.2 nathanw p = mb + off + 1;
1991 1.10.2.2 nathanw
1992 1.10.2.2 nathanw /* XXX This should be done with a bus_space flag. */
1993 1.10.2.2 nathanw for (i = dm->dm_nsegs, ds = dm->dm_segs; i > 0; i--, ds++) {
1994 1.10.2.2 nathanw slen = ds->ds_len;
1995 1.10.2.2 nathanw saddr = ds->ds_addr;
1996 1.10.2.2 nathanw
1997 1.10.2.2 nathanw while (slen > 0) {
1998 1.10.2.2 nathanw eaddr = (saddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
1999 1.10.2.2 nathanw tlen = min(eaddr - saddr, slen);
2000 1.10.2.2 nathanw slen -= tlen;
2001 1.10.2.2 nathanw *p++ = le32toh(saddr);
2002 1.10.2.2 nathanw saddr = eaddr;
2003 1.10.2.2 nathanw nsegs++;
2004 1.10.2.2 nathanw }
2005 1.10.2.2 nathanw }
2006 1.10.2.2 nathanw
2007 1.10.2.2 nathanw mb[off] = xfersize | I2O_SGL_PAGE_LIST | I2O_SGL_END_BUFFER |
2008 1.10.2.2 nathanw I2O_SGL_END;
2009 1.10.2.2 nathanw if (out)
2010 1.10.2.2 nathanw mb[off] |= I2O_SGL_DATA_OUT;
2011 1.10.2.2 nathanw } else {
2012 1.10.2.2 nathanw p = mb + off;
2013 1.10.2.2 nathanw nsegs = dm->dm_nsegs;
2014 1.10.2.2 nathanw
2015 1.10.2.2 nathanw if (out)
2016 1.10.2.2 nathanw flg = I2O_SGL_SIMPLE | I2O_SGL_DATA_OUT;
2017 1.10.2.2 nathanw else
2018 1.10.2.2 nathanw flg = I2O_SGL_SIMPLE;
2019 1.10.2.2 nathanw
2020 1.10.2.2 nathanw for (i = nsegs, ds = dm->dm_segs; i > 1; i--, p += 2, ds++) {
2021 1.10.2.2 nathanw p[0] = (u_int32_t)ds->ds_len | flg;
2022 1.10.2.2 nathanw p[1] = (u_int32_t)ds->ds_addr;
2023 1.10.2.2 nathanw }
2024 1.10.2.2 nathanw
2025 1.10.2.2 nathanw p[0] = (u_int32_t)ds->ds_len | flg | I2O_SGL_END_BUFFER |
2026 1.10.2.2 nathanw I2O_SGL_END;
2027 1.10.2.2 nathanw p[1] = (u_int32_t)ds->ds_addr;
2028 1.10.2.2 nathanw nsegs <<= 1;
2029 1.10.2.2 nathanw }
2030 1.10.2.2 nathanw
2031 1.10.2.2 nathanw /* Fix up the transfer record, and sync the map. */
2032 1.10.2.2 nathanw ix->ix_flags = (out ? IX_OUT : IX_IN);
2033 1.10.2.2 nathanw ix->ix_size = xfersize;
2034 1.10.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, ix->ix_map, 0, xfersize,
2035 1.10.2.2 nathanw out ? BUS_DMASYNC_POSTWRITE : BUS_DMASYNC_POSTREAD);
2036 1.10.2.2 nathanw
2037 1.10.2.2 nathanw /*
2038 1.10.2.2 nathanw * Adjust the SGL offset and total message size fields. We don't
2039 1.10.2.2 nathanw * set IM_SGLOFFADJ, since it's used only for SIMPLE elements.
2040 1.10.2.2 nathanw */
2041 1.10.2.2 nathanw mb[0] += ((off << 4) + (nsegs << 16));
2042 1.1 ad return (0);
2043 1.1 ad }
2044 1.1 ad
2045 1.1 ad /*
2046 1.1 ad * Unmap all data transfers associated with a message wrapper.
2047 1.1 ad */
2048 1.1 ad void
2049 1.1 ad iop_msg_unmap(struct iop_softc *sc, struct iop_msg *im)
2050 1.1 ad {
2051 1.1 ad struct iop_xfer *ix;
2052 1.1 ad int i;
2053 1.10.2.2 nathanw
2054 1.10.2.2 nathanw #ifdef I2ODEBUG
2055 1.10.2.2 nathanw if (im->im_xfer[0].ix_size == 0)
2056 1.10.2.2 nathanw panic("iop_msg_unmap: no transfers mapped");
2057 1.10.2.2 nathanw #endif
2058 1.10.2.2 nathanw
2059 1.10.2.2 nathanw for (ix = im->im_xfer, i = 0;;) {
2060 1.1 ad bus_dmamap_sync(sc->sc_dmat, ix->ix_map, 0, ix->ix_size,
2061 1.1 ad ix->ix_flags & IX_OUT ? BUS_DMASYNC_POSTWRITE :
2062 1.1 ad BUS_DMASYNC_POSTREAD);
2063 1.1 ad bus_dmamap_unload(sc->sc_dmat, ix->ix_map);
2064 1.1 ad
2065 1.1 ad /* Only the first DMA map is static. */
2066 1.1 ad if (i != 0)
2067 1.1 ad bus_dmamap_destroy(sc->sc_dmat, ix->ix_map);
2068 1.10.2.2 nathanw if ((++ix)->ix_size == 0)
2069 1.10.2.2 nathanw break;
2070 1.10.2.2 nathanw if (++i >= IOP_MAX_MSG_XFERS)
2071 1.10.2.2 nathanw break;
2072 1.1 ad }
2073 1.1 ad }
2074 1.1 ad
2075 1.10.2.2 nathanw /*
2076 1.10.2.2 nathanw * Post a message frame to the IOP's inbound queue.
2077 1.1 ad */
2078 1.1 ad int
2079 1.10.2.2 nathanw iop_post(struct iop_softc *sc, u_int32_t *mb)
2080 1.1 ad {
2081 1.10.2.2 nathanw u_int32_t mfa;
2082 1.10.2.2 nathanw int s;
2083 1.1 ad
2084 1.10.2.4 nathanw #ifdef I2ODEBUG
2085 1.10.2.7 nathanw if ((mb[0] >> 16) > (sc->sc_framesize >> 2))
2086 1.10.2.2 nathanw panic("iop_post: frame too large");
2087 1.10.2.4 nathanw #endif
2088 1.1 ad
2089 1.10.2.4 nathanw s = splbio();
2090 1.1 ad
2091 1.10.2.2 nathanw /* Allocate a slot with the IOP. */
2092 1.10.2.2 nathanw if ((mfa = iop_inl(sc, IOP_REG_IFIFO)) == IOP_MFA_EMPTY)
2093 1.10.2.2 nathanw if ((mfa = iop_inl(sc, IOP_REG_IFIFO)) == IOP_MFA_EMPTY) {
2094 1.10.2.2 nathanw splx(s);
2095 1.10.2.2 nathanw printf("%s: mfa not forthcoming\n",
2096 1.10.2.2 nathanw sc->sc_dv.dv_xname);
2097 1.10.2.2 nathanw return (EAGAIN);
2098 1.10.2.2 nathanw }
2099 1.1 ad
2100 1.10.2.4 nathanw /* Perform reply buffer DMA synchronisation. */
2101 1.10.2.2 nathanw if (sc->sc_curib++ == 0)
2102 1.10.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_rep_dmamap, 0,
2103 1.10.2.2 nathanw sc->sc_rep_size, BUS_DMASYNC_PREREAD);
2104 1.1 ad
2105 1.10.2.2 nathanw /* Copy out the message frame. */
2106 1.10.2.2 nathanw bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, mfa, mb, mb[0] >> 16);
2107 1.10.2.2 nathanw bus_space_barrier(sc->sc_iot, sc->sc_ioh, mfa, (mb[0] >> 14) & ~3,
2108 1.10.2.2 nathanw BUS_SPACE_BARRIER_WRITE);
2109 1.10.2.2 nathanw
2110 1.10.2.2 nathanw /* Post the MFA back to the IOP. */
2111 1.10.2.2 nathanw iop_outl(sc, IOP_REG_IFIFO, mfa);
2112 1.10.2.2 nathanw
2113 1.10.2.2 nathanw splx(s);
2114 1.10.2.2 nathanw return (0);
2115 1.10.2.2 nathanw }
2116 1.10.2.2 nathanw
2117 1.10.2.2 nathanw /*
2118 1.10.2.2 nathanw * Post a message to the IOP and deal with completion.
2119 1.10.2.2 nathanw */
2120 1.10.2.2 nathanw int
2121 1.10.2.2 nathanw iop_msg_post(struct iop_softc *sc, struct iop_msg *im, void *xmb, int timo)
2122 1.10.2.2 nathanw {
2123 1.10.2.2 nathanw u_int32_t *mb;
2124 1.10.2.2 nathanw int rv, s;
2125 1.10.2.2 nathanw
2126 1.10.2.2 nathanw mb = xmb;
2127 1.10.2.2 nathanw
2128 1.10.2.2 nathanw /* Terminate the scatter/gather list chain. */
2129 1.1 ad if ((im->im_flags & IM_SGLOFFADJ) != 0)
2130 1.10.2.2 nathanw mb[(mb[0] >> 16) - 2] |= I2O_SGL_END;
2131 1.1 ad
2132 1.10.2.2 nathanw if ((rv = iop_post(sc, mb)) != 0)
2133 1.10.2.2 nathanw return (rv);
2134 1.1 ad
2135 1.10.2.4 nathanw if ((im->im_flags & (IM_POLL | IM_WAIT)) != 0) {
2136 1.10.2.2 nathanw if ((im->im_flags & IM_POLL) != 0)
2137 1.10.2.2 nathanw iop_msg_poll(sc, im, timo);
2138 1.10.2.2 nathanw else
2139 1.10.2.2 nathanw iop_msg_wait(sc, im, timo);
2140 1.1 ad
2141 1.10.2.2 nathanw s = splbio();
2142 1.10.2.2 nathanw if ((im->im_flags & IM_REPLIED) != 0) {
2143 1.10.2.2 nathanw if ((im->im_flags & IM_NOSTATUS) != 0)
2144 1.10.2.2 nathanw rv = 0;
2145 1.10.2.2 nathanw else if ((im->im_flags & IM_FAIL) != 0)
2146 1.10.2.2 nathanw rv = ENXIO;
2147 1.10.2.2 nathanw else if (im->im_reqstatus != I2O_STATUS_SUCCESS)
2148 1.10.2.2 nathanw rv = EIO;
2149 1.10.2.2 nathanw else
2150 1.10.2.2 nathanw rv = 0;
2151 1.10.2.2 nathanw } else
2152 1.10.2.2 nathanw rv = EBUSY;
2153 1.2 ad splx(s);
2154 1.10.2.2 nathanw } else
2155 1.10.2.2 nathanw rv = 0;
2156 1.10.2.2 nathanw
2157 1.10.2.2 nathanw return (rv);
2158 1.10.2.2 nathanw }
2159 1.10.2.2 nathanw
2160 1.10.2.2 nathanw /*
2161 1.10.2.2 nathanw * Spin until the specified message is replied to.
2162 1.10.2.2 nathanw */
2163 1.10.2.2 nathanw static void
2164 1.10.2.2 nathanw iop_msg_poll(struct iop_softc *sc, struct iop_msg *im, int timo)
2165 1.10.2.2 nathanw {
2166 1.10.2.2 nathanw u_int32_t rmfa;
2167 1.10.2.2 nathanw int s, status;
2168 1.10.2.2 nathanw
2169 1.10.2.4 nathanw s = splbio();
2170 1.1 ad
2171 1.1 ad /* Wait for completion. */
2172 1.1 ad for (timo *= 10; timo != 0; timo--) {
2173 1.5 ad if ((iop_inl(sc, IOP_REG_INTR_STATUS) & IOP_INTR_OFIFO) != 0) {
2174 1.5 ad /* Double read to account for IOP bug. */
2175 1.5 ad rmfa = iop_inl(sc, IOP_REG_OFIFO);
2176 1.5 ad if (rmfa == IOP_MFA_EMPTY)
2177 1.5 ad rmfa = iop_inl(sc, IOP_REG_OFIFO);
2178 1.10.2.2 nathanw if (rmfa != IOP_MFA_EMPTY) {
2179 1.5 ad status = iop_handle_reply(sc, rmfa);
2180 1.10.2.2 nathanw
2181 1.10.2.2 nathanw /*
2182 1.10.2.2 nathanw * Return the reply frame to the IOP's
2183 1.10.2.2 nathanw * outbound FIFO.
2184 1.10.2.2 nathanw */
2185 1.10.2.2 nathanw iop_outl(sc, IOP_REG_OFIFO, rmfa);
2186 1.10.2.2 nathanw }
2187 1.5 ad }
2188 1.1 ad if ((im->im_flags & IM_REPLIED) != 0)
2189 1.1 ad break;
2190 1.1 ad DELAY(100);
2191 1.1 ad }
2192 1.1 ad
2193 1.1 ad if (timo == 0) {
2194 1.5 ad #ifdef I2ODEBUG
2195 1.5 ad printf("%s: poll - no reply\n", sc->sc_dv.dv_xname);
2196 1.10.2.2 nathanw if (iop_status_get(sc, 1) != 0)
2197 1.10.2.2 nathanw printf("iop_msg_poll: unable to retrieve status\n");
2198 1.5 ad else
2199 1.10.2.2 nathanw printf("iop_msg_poll: IOP state = %d\n",
2200 1.5 ad (le32toh(sc->sc_status.segnumber) >> 16) & 0xff);
2201 1.5 ad #endif
2202 1.1 ad }
2203 1.1 ad
2204 1.1 ad splx(s);
2205 1.1 ad }
2206 1.1 ad
2207 1.1 ad /*
2208 1.10.2.2 nathanw * Sleep until the specified message is replied to.
2209 1.1 ad */
2210 1.10.2.2 nathanw static void
2211 1.1 ad iop_msg_wait(struct iop_softc *sc, struct iop_msg *im, int timo)
2212 1.1 ad {
2213 1.10.2.2 nathanw int s, rv;
2214 1.1 ad
2215 1.5 ad s = splbio();
2216 1.5 ad if ((im->im_flags & IM_REPLIED) != 0) {
2217 1.5 ad splx(s);
2218 1.10.2.2 nathanw return;
2219 1.5 ad }
2220 1.10.2.12 nathanw rv = tsleep(im, PRIBIO, "iopmsg", mstohz(timo));
2221 1.5 ad splx(s);
2222 1.10.2.2 nathanw
2223 1.5 ad #ifdef I2ODEBUG
2224 1.5 ad if (rv != 0) {
2225 1.5 ad printf("iop_msg_wait: tsleep() == %d\n", rv);
2226 1.10.2.2 nathanw if (iop_status_get(sc, 0) != 0)
2227 1.5 ad printf("iop_msg_wait: unable to retrieve status\n");
2228 1.5 ad else
2229 1.5 ad printf("iop_msg_wait: IOP state = %d\n",
2230 1.5 ad (le32toh(sc->sc_status.segnumber) >> 16) & 0xff);
2231 1.5 ad }
2232 1.5 ad #endif
2233 1.1 ad }
2234 1.1 ad
2235 1.1 ad /*
2236 1.1 ad * Release an unused message frame back to the IOP's inbound fifo.
2237 1.1 ad */
2238 1.1 ad static void
2239 1.1 ad iop_release_mfa(struct iop_softc *sc, u_int32_t mfa)
2240 1.1 ad {
2241 1.1 ad
2242 1.1 ad /* Use the frame to issue a no-op. */
2243 1.5 ad iop_outl(sc, mfa, I2O_VERSION_11 | (4 << 16));
2244 1.5 ad iop_outl(sc, mfa + 4, I2O_MSGFUNC(I2O_TID_IOP, I2O_UTIL_NOP));
2245 1.5 ad iop_outl(sc, mfa + 8, 0);
2246 1.5 ad iop_outl(sc, mfa + 12, 0);
2247 1.1 ad
2248 1.5 ad iop_outl(sc, IOP_REG_IFIFO, mfa);
2249 1.1 ad }
2250 1.1 ad
2251 1.1 ad #ifdef I2ODEBUG
2252 1.1 ad /*
2253 1.10.2.2 nathanw * Dump a reply frame header.
2254 1.1 ad */
2255 1.1 ad static void
2256 1.10.2.2 nathanw iop_reply_print(struct iop_softc *sc, struct i2o_reply *rb)
2257 1.1 ad {
2258 1.5 ad u_int function, detail;
2259 1.1 ad #ifdef I2OVERBOSE
2260 1.1 ad const char *statusstr;
2261 1.1 ad #endif
2262 1.1 ad
2263 1.5 ad function = (le32toh(rb->msgfunc) >> 24) & 0xff;
2264 1.1 ad detail = le16toh(rb->detail);
2265 1.1 ad
2266 1.5 ad printf("%s: reply:\n", sc->sc_dv.dv_xname);
2267 1.5 ad
2268 1.1 ad #ifdef I2OVERBOSE
2269 1.1 ad if (rb->reqstatus < sizeof(iop_status) / sizeof(iop_status[0]))
2270 1.1 ad statusstr = iop_status[rb->reqstatus];
2271 1.1 ad else
2272 1.1 ad statusstr = "undefined error code";
2273 1.1 ad
2274 1.5 ad printf("%s: function=0x%02x status=0x%02x (%s)\n",
2275 1.5 ad sc->sc_dv.dv_xname, function, rb->reqstatus, statusstr);
2276 1.1 ad #else
2277 1.5 ad printf("%s: function=0x%02x status=0x%02x\n",
2278 1.5 ad sc->sc_dv.dv_xname, function, rb->reqstatus);
2279 1.1 ad #endif
2280 1.5 ad printf("%s: detail=0x%04x ictx=0x%08x tctx=0x%08x\n",
2281 1.5 ad sc->sc_dv.dv_xname, detail, le32toh(rb->msgictx),
2282 1.5 ad le32toh(rb->msgtctx));
2283 1.5 ad printf("%s: tidi=%d tidt=%d flags=0x%02x\n", sc->sc_dv.dv_xname,
2284 1.5 ad (le32toh(rb->msgfunc) >> 12) & 4095, le32toh(rb->msgfunc) & 4095,
2285 1.5 ad (le32toh(rb->msgflags) >> 8) & 0xff);
2286 1.1 ad }
2287 1.1 ad #endif
2288 1.1 ad
2289 1.1 ad /*
2290 1.10.2.2 nathanw * Dump a transport failure reply.
2291 1.10.2.2 nathanw */
2292 1.10.2.2 nathanw static void
2293 1.10.2.2 nathanw iop_tfn_print(struct iop_softc *sc, struct i2o_fault_notify *fn)
2294 1.10.2.2 nathanw {
2295 1.10.2.2 nathanw
2296 1.10.2.2 nathanw printf("%s: WARNING: transport failure:\n", sc->sc_dv.dv_xname);
2297 1.10.2.2 nathanw
2298 1.10.2.7 nathanw printf("%s: ictx=0x%08x tctx=0x%08x\n", sc->sc_dv.dv_xname,
2299 1.10.2.2 nathanw le32toh(fn->msgictx), le32toh(fn->msgtctx));
2300 1.10.2.2 nathanw printf("%s: failurecode=0x%02x severity=0x%02x\n",
2301 1.10.2.2 nathanw sc->sc_dv.dv_xname, fn->failurecode, fn->severity);
2302 1.10.2.2 nathanw printf("%s: highestver=0x%02x lowestver=0x%02x\n",
2303 1.10.2.2 nathanw sc->sc_dv.dv_xname, fn->highestver, fn->lowestver);
2304 1.10.2.2 nathanw }
2305 1.10.2.2 nathanw
2306 1.10.2.2 nathanw /*
2307 1.5 ad * Translate an I2O ASCII field into a C string.
2308 1.1 ad */
2309 1.1 ad void
2310 1.5 ad iop_strvis(struct iop_softc *sc, const char *src, int slen, char *dst, int dlen)
2311 1.1 ad {
2312 1.5 ad int hc, lc, i, nit;
2313 1.1 ad
2314 1.1 ad dlen--;
2315 1.1 ad lc = 0;
2316 1.1 ad hc = 0;
2317 1.1 ad i = 0;
2318 1.5 ad
2319 1.5 ad /*
2320 1.5 ad * DPT use NUL as a space, whereas AMI use it as a terminator. The
2321 1.5 ad * spec has nothing to say about it. Since AMI fields are usually
2322 1.5 ad * filled with junk after the terminator, ...
2323 1.5 ad */
2324 1.5 ad nit = (le16toh(sc->sc_status.orgid) != I2O_ORG_DPT);
2325 1.5 ad
2326 1.5 ad while (slen-- != 0 && dlen-- != 0) {
2327 1.5 ad if (nit && *src == '\0')
2328 1.5 ad break;
2329 1.5 ad else if (*src <= 0x20 || *src >= 0x7f) {
2330 1.1 ad if (hc)
2331 1.1 ad dst[i++] = ' ';
2332 1.1 ad } else {
2333 1.1 ad hc = 1;
2334 1.1 ad dst[i++] = *src;
2335 1.1 ad lc = i;
2336 1.1 ad }
2337 1.1 ad src++;
2338 1.1 ad }
2339 1.1 ad
2340 1.1 ad dst[lc] = '\0';
2341 1.1 ad }
2342 1.1 ad
2343 1.1 ad /*
2344 1.10.2.2 nathanw * Retrieve the DEVICE_IDENTITY parameter group from the target and dump it.
2345 1.10.2.2 nathanw */
2346 1.10.2.2 nathanw int
2347 1.10.2.2 nathanw iop_print_ident(struct iop_softc *sc, int tid)
2348 1.10.2.2 nathanw {
2349 1.10.2.2 nathanw struct {
2350 1.10.2.2 nathanw struct i2o_param_op_results pr;
2351 1.10.2.2 nathanw struct i2o_param_read_results prr;
2352 1.10.2.2 nathanw struct i2o_param_device_identity di;
2353 1.10.2.2 nathanw } __attribute__ ((__packed__)) p;
2354 1.10.2.2 nathanw char buf[32];
2355 1.10.2.2 nathanw int rv;
2356 1.10.2.2 nathanw
2357 1.10.2.5 nathanw rv = iop_field_get_all(sc, tid, I2O_PARAM_DEVICE_IDENTITY, &p,
2358 1.10.2.5 nathanw sizeof(p), NULL);
2359 1.10.2.2 nathanw if (rv != 0)
2360 1.10.2.2 nathanw return (rv);
2361 1.10.2.2 nathanw
2362 1.10.2.2 nathanw iop_strvis(sc, p.di.vendorinfo, sizeof(p.di.vendorinfo), buf,
2363 1.10.2.2 nathanw sizeof(buf));
2364 1.10.2.2 nathanw printf(" <%s, ", buf);
2365 1.10.2.2 nathanw iop_strvis(sc, p.di.productinfo, sizeof(p.di.productinfo), buf,
2366 1.10.2.2 nathanw sizeof(buf));
2367 1.10.2.2 nathanw printf("%s, ", buf);
2368 1.10.2.2 nathanw iop_strvis(sc, p.di.revlevel, sizeof(p.di.revlevel), buf, sizeof(buf));
2369 1.10.2.2 nathanw printf("%s>", buf);
2370 1.10.2.2 nathanw
2371 1.10.2.2 nathanw return (0);
2372 1.10.2.2 nathanw }
2373 1.10.2.2 nathanw
2374 1.10.2.2 nathanw /*
2375 1.5 ad * Claim or unclaim the specified TID.
2376 1.1 ad */
2377 1.1 ad int
2378 1.5 ad iop_util_claim(struct iop_softc *sc, struct iop_initiator *ii, int release,
2379 1.10.2.4 nathanw int flags)
2380 1.1 ad {
2381 1.5 ad struct iop_msg *im;
2382 1.10.2.2 nathanw struct i2o_util_claim mf;
2383 1.5 ad int rv, func;
2384 1.5 ad
2385 1.5 ad func = release ? I2O_UTIL_CLAIM_RELEASE : I2O_UTIL_CLAIM;
2386 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT);
2387 1.5 ad
2388 1.10.2.2 nathanw /* We can use the same structure, as they're identical. */
2389 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_util_claim);
2390 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(ii->ii_tid, func);
2391 1.10.2.2 nathanw mf.msgictx = ii->ii_ictx;
2392 1.10.2.2 nathanw mf.msgtctx = im->im_tctx;
2393 1.10.2.2 nathanw mf.flags = flags;
2394 1.5 ad
2395 1.10.2.2 nathanw rv = iop_msg_post(sc, im, &mf, 5000);
2396 1.10.2.2 nathanw iop_msg_free(sc, im);
2397 1.5 ad return (rv);
2398 1.5 ad }
2399 1.5 ad
2400 1.5 ad /*
2401 1.5 ad * Perform an abort.
2402 1.5 ad */
2403 1.5 ad int iop_util_abort(struct iop_softc *sc, struct iop_initiator *ii, int func,
2404 1.10.2.4 nathanw int tctxabort, int flags)
2405 1.5 ad {
2406 1.5 ad struct iop_msg *im;
2407 1.10.2.2 nathanw struct i2o_util_abort mf;
2408 1.5 ad int rv;
2409 1.5 ad
2410 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT);
2411 1.1 ad
2412 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_util_abort);
2413 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(ii->ii_tid, I2O_UTIL_ABORT);
2414 1.10.2.2 nathanw mf.msgictx = ii->ii_ictx;
2415 1.10.2.2 nathanw mf.msgtctx = im->im_tctx;
2416 1.10.2.2 nathanw mf.flags = (func << 24) | flags;
2417 1.10.2.2 nathanw mf.tctxabort = tctxabort;
2418 1.1 ad
2419 1.10.2.2 nathanw rv = iop_msg_post(sc, im, &mf, 5000);
2420 1.10.2.2 nathanw iop_msg_free(sc, im);
2421 1.5 ad return (rv);
2422 1.1 ad }
2423 1.1 ad
2424 1.1 ad /*
2425 1.10.2.2 nathanw * Enable or disable reception of events for the specified device.
2426 1.1 ad */
2427 1.5 ad int iop_util_eventreg(struct iop_softc *sc, struct iop_initiator *ii, int mask)
2428 1.5 ad {
2429 1.10.2.2 nathanw struct i2o_util_event_register mf;
2430 1.5 ad
2431 1.10.2.2 nathanw mf.msgflags = I2O_MSGFLAGS(i2o_util_event_register);
2432 1.10.2.2 nathanw mf.msgfunc = I2O_MSGFUNC(ii->ii_tid, I2O_UTIL_EVENT_REGISTER);
2433 1.10.2.2 nathanw mf.msgictx = ii->ii_ictx;
2434 1.10.2.4 nathanw mf.msgtctx = 0;
2435 1.10.2.2 nathanw mf.eventmask = mask;
2436 1.5 ad
2437 1.10.2.2 nathanw /* This message is replied to only when events are signalled. */
2438 1.10.2.4 nathanw return (iop_post(sc, (u_int32_t *)&mf));
2439 1.5 ad }
2440 1.5 ad
2441 1.1 ad int
2442 1.5 ad iopopen(dev_t dev, int flag, int mode, struct proc *p)
2443 1.1 ad {
2444 1.5 ad struct iop_softc *sc;
2445 1.5 ad
2446 1.10.2.2 nathanw if ((sc = device_lookup(&iop_cd, minor(dev))) == NULL)
2447 1.10.2.2 nathanw return (ENXIO);
2448 1.10.2.2 nathanw if ((sc->sc_flags & IOP_ONLINE) == 0)
2449 1.1 ad return (ENXIO);
2450 1.5 ad if ((sc->sc_flags & IOP_OPEN) != 0)
2451 1.5 ad return (EBUSY);
2452 1.5 ad sc->sc_flags |= IOP_OPEN;
2453 1.5 ad
2454 1.5 ad return (0);
2455 1.1 ad }
2456 1.1 ad
2457 1.5 ad int
2458 1.5 ad iopclose(dev_t dev, int flag, int mode, struct proc *p)
2459 1.1 ad {
2460 1.5 ad struct iop_softc *sc;
2461 1.1 ad
2462 1.5 ad sc = device_lookup(&iop_cd, minor(dev));
2463 1.10.2.2 nathanw sc->sc_flags &= ~IOP_OPEN;
2464 1.10.2.4 nathanw
2465 1.5 ad return (0);
2466 1.1 ad }
2467 1.1 ad
2468 1.1 ad int
2469 1.5 ad iopioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
2470 1.1 ad {
2471 1.5 ad struct iop_softc *sc;
2472 1.5 ad struct iovec *iov;
2473 1.5 ad int rv, i;
2474 1.5 ad
2475 1.5 ad if (securelevel >= 2)
2476 1.5 ad return (EPERM);
2477 1.5 ad
2478 1.5 ad sc = device_lookup(&iop_cd, minor(dev));
2479 1.5 ad
2480 1.5 ad switch (cmd) {
2481 1.5 ad case IOPIOCPT:
2482 1.10.2.4 nathanw return (iop_passthrough(sc, (struct ioppt *)data, p));
2483 1.9 ad
2484 1.10.2.2 nathanw case IOPIOCGSTATUS:
2485 1.10.2.2 nathanw iov = (struct iovec *)data;
2486 1.10.2.2 nathanw i = sizeof(struct i2o_status);
2487 1.10.2.2 nathanw if (i > iov->iov_len)
2488 1.10.2.2 nathanw i = iov->iov_len;
2489 1.10.2.2 nathanw else
2490 1.10.2.2 nathanw iov->iov_len = i;
2491 1.10.2.2 nathanw if ((rv = iop_status_get(sc, 0)) == 0)
2492 1.10.2.2 nathanw rv = copyout(&sc->sc_status, iov->iov_base, i);
2493 1.10.2.2 nathanw return (rv);
2494 1.5 ad
2495 1.10.2.2 nathanw case IOPIOCGLCT:
2496 1.10.2.2 nathanw case IOPIOCGTIDMAP:
2497 1.10.2.2 nathanw case IOPIOCRECONFIG:
2498 1.10.2.2 nathanw break;
2499 1.5 ad
2500 1.10.2.2 nathanw default:
2501 1.10.2.2 nathanw #if defined(DIAGNOSTIC) || defined(I2ODEBUG)
2502 1.10.2.2 nathanw printf("%s: unknown ioctl %lx\n", sc->sc_dv.dv_xname, cmd);
2503 1.10.2.2 nathanw #endif
2504 1.10.2.2 nathanw return (ENOTTY);
2505 1.10.2.2 nathanw }
2506 1.9 ad
2507 1.10.2.2 nathanw if ((rv = lockmgr(&sc->sc_conflock, LK_SHARED, NULL)) != 0)
2508 1.10.2.2 nathanw return (rv);
2509 1.1 ad
2510 1.10.2.2 nathanw switch (cmd) {
2511 1.5 ad case IOPIOCGLCT:
2512 1.5 ad iov = (struct iovec *)data;
2513 1.10.2.2 nathanw i = le16toh(sc->sc_lct->tablesize) << 2;
2514 1.5 ad if (i > iov->iov_len)
2515 1.5 ad i = iov->iov_len;
2516 1.5 ad else
2517 1.5 ad iov->iov_len = i;
2518 1.10.2.2 nathanw rv = copyout(sc->sc_lct, iov->iov_base, i);
2519 1.5 ad break;
2520 1.5 ad
2521 1.5 ad case IOPIOCRECONFIG:
2522 1.10.2.2 nathanw rv = iop_reconfigure(sc, 0);
2523 1.9 ad break;
2524 1.9 ad
2525 1.9 ad case IOPIOCGTIDMAP:
2526 1.9 ad iov = (struct iovec *)data;
2527 1.10.2.2 nathanw i = sizeof(struct iop_tidmap) * sc->sc_nlctent;
2528 1.10.2.2 nathanw if (i > iov->iov_len)
2529 1.10.2.2 nathanw i = iov->iov_len;
2530 1.10.2.2 nathanw else
2531 1.10.2.2 nathanw iov->iov_len = i;
2532 1.10.2.2 nathanw rv = copyout(sc->sc_tidmap, iov->iov_base, i);
2533 1.5 ad break;
2534 1.10.2.2 nathanw }
2535 1.5 ad
2536 1.10.2.2 nathanw lockmgr(&sc->sc_conflock, LK_RELEASE, NULL);
2537 1.10.2.2 nathanw return (rv);
2538 1.10.2.2 nathanw }
2539 1.10.2.2 nathanw
2540 1.10.2.2 nathanw static int
2541 1.10.2.4 nathanw iop_passthrough(struct iop_softc *sc, struct ioppt *pt, struct proc *p)
2542 1.10.2.2 nathanw {
2543 1.10.2.2 nathanw struct iop_msg *im;
2544 1.10.2.2 nathanw struct i2o_msg *mf;
2545 1.10.2.2 nathanw struct ioppt_buf *ptb;
2546 1.10.2.2 nathanw int rv, i, mapped;
2547 1.10.2.2 nathanw
2548 1.10.2.2 nathanw mf = NULL;
2549 1.10.2.2 nathanw im = NULL;
2550 1.10.2.2 nathanw mapped = 1;
2551 1.10.2.2 nathanw
2552 1.10.2.7 nathanw if (pt->pt_msglen > sc->sc_framesize ||
2553 1.10.2.2 nathanw pt->pt_msglen < sizeof(struct i2o_msg) ||
2554 1.10.2.2 nathanw pt->pt_nbufs > IOP_MAX_MSG_XFERS ||
2555 1.10.2.2 nathanw pt->pt_nbufs < 0 || pt->pt_replylen < 0 ||
2556 1.10.2.2 nathanw pt->pt_timo < 1000 || pt->pt_timo > 5*60*1000)
2557 1.10.2.2 nathanw return (EINVAL);
2558 1.10.2.2 nathanw
2559 1.10.2.2 nathanw for (i = 0; i < pt->pt_nbufs; i++)
2560 1.10.2.2 nathanw if (pt->pt_bufs[i].ptb_datalen > IOP_MAX_XFER) {
2561 1.10.2.2 nathanw rv = ENOMEM;
2562 1.10.2.2 nathanw goto bad;
2563 1.10.2.2 nathanw }
2564 1.10.2.2 nathanw
2565 1.10.2.7 nathanw mf = malloc(sc->sc_framesize, M_DEVBUF, M_WAITOK);
2566 1.10.2.2 nathanw if (mf == NULL)
2567 1.10.2.2 nathanw return (ENOMEM);
2568 1.10.2.2 nathanw
2569 1.10.2.2 nathanw if ((rv = copyin(pt->pt_msg, mf, pt->pt_msglen)) != 0)
2570 1.10.2.2 nathanw goto bad;
2571 1.10.2.2 nathanw
2572 1.10.2.4 nathanw im = iop_msg_alloc(sc, IM_WAIT | IM_NOSTATUS);
2573 1.10.2.2 nathanw im->im_rb = (struct i2o_reply *)mf;
2574 1.10.2.2 nathanw mf->msgictx = IOP_ICTX;
2575 1.10.2.2 nathanw mf->msgtctx = im->im_tctx;
2576 1.10.2.2 nathanw
2577 1.10.2.2 nathanw for (i = 0; i < pt->pt_nbufs; i++) {
2578 1.10.2.2 nathanw ptb = &pt->pt_bufs[i];
2579 1.10.2.4 nathanw rv = iop_msg_map(sc, im, (u_int32_t *)mf, ptb->ptb_data,
2580 1.10.2.4 nathanw ptb->ptb_datalen, ptb->ptb_out != 0, p);
2581 1.10.2.2 nathanw if (rv != 0)
2582 1.10.2.2 nathanw goto bad;
2583 1.10.2.2 nathanw mapped = 1;
2584 1.5 ad }
2585 1.9 ad
2586 1.10.2.2 nathanw if ((rv = iop_msg_post(sc, im, mf, pt->pt_timo)) != 0)
2587 1.10.2.2 nathanw goto bad;
2588 1.10.2.2 nathanw
2589 1.10.2.2 nathanw i = (le32toh(im->im_rb->msgflags) >> 14) & ~3;
2590 1.10.2.7 nathanw if (i > sc->sc_framesize)
2591 1.10.2.7 nathanw i = sc->sc_framesize;
2592 1.10.2.2 nathanw if (i > pt->pt_replylen)
2593 1.10.2.2 nathanw i = pt->pt_replylen;
2594 1.10.2.4 nathanw rv = copyout(im->im_rb, pt->pt_reply, i);
2595 1.10.2.1 nathanw
2596 1.10.2.2 nathanw bad:
2597 1.10.2.2 nathanw if (mapped != 0)
2598 1.10.2.2 nathanw iop_msg_unmap(sc, im);
2599 1.10.2.2 nathanw if (im != NULL)
2600 1.10.2.2 nathanw iop_msg_free(sc, im);
2601 1.10.2.2 nathanw if (mf != NULL)
2602 1.10.2.2 nathanw free(mf, M_DEVBUF);
2603 1.1 ad return (rv);
2604 1.5 ad }
2605