aacreg.h revision 1.3
1 /* $NetBSD: aacreg.h,v 1.3 2005/02/27 00:27:00 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 Scott Long 42 * Copyright (c) 2000 BSDi 43 * Copyright (c) 2000 Niklas Hallqvist 44 * All rights reserved. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * from FreeBSD: aacreg.h,v 1.1 2000/09/13 03:20:34 msmith Exp 68 * via OpenBSD: aacreg.h,v 1.3 2001/06/12 15:40:29 niklas Exp 69 */ 70 71 /* 72 * Data structures defining the interface between the driver and the Adaptec 73 * 'FSA' adapters. Note that many field names and comments here are taken 74 * verbatim from the Adaptec driver source in order to make comparing the 75 * two slightly easier. 76 */ 77 78 #ifndef _PCI_AACREG_H_ 79 #define _PCI_AACREG_H_ 80 81 /* 82 * Misc. magic numbers. 83 */ 84 #define AAC_MAX_CONTAINERS 64 85 #define AAC_BLOCK_SIZE 512 86 87 /* 88 * Communications interface. 89 * 90 * Where datastructure layouts are closely parallel to the Adaptec sample code, 91 * retain their naming conventions (for now) to aid in cross-referencing. 92 */ 93 94 /* 95 * We establish 4 command queues and matching response queues. Queues must 96 * be 16-byte aligned, and are sized as follows: 97 */ 98 #define AAC_HOST_NORM_CMD_ENTRIES 8 /* cmd adapter->host, normal pri */ 99 #define AAC_HOST_HIGH_CMD_ENTRIES 4 /* cmd adapter->host, high pri */ 100 #define AAC_ADAP_NORM_CMD_ENTRIES 512 /* cmd host->adapter, normal pri */ 101 #define AAC_ADAP_HIGH_CMD_ENTRIES 4 /* cmd host->adapter, high pri */ 102 #define AAC_HOST_NORM_RESP_ENTRIES 512 /* resp, adapter->host, normal pri */ 103 #define AAC_HOST_HIGH_RESP_ENTRIES 4 /* resp, adapter->host, high pri */ 104 #define AAC_ADAP_NORM_RESP_ENTRIES 8 /* resp, host->adapter, normal pri */ 105 #define AAC_ADAP_HIGH_RESP_ENTRIES 4 /* resp, host->adapter, high pri */ 106 107 #define AAC_TOTALQ_LENGTH \ 108 (AAC_HOST_HIGH_CMD_ENTRIES + AAC_HOST_NORM_CMD_ENTRIES + \ 109 AAC_ADAP_HIGH_CMD_ENTRIES + AAC_ADAP_NORM_CMD_ENTRIES + \ 110 AAC_HOST_HIGH_RESP_ENTRIES + AAC_HOST_NORM_RESP_ENTRIES + \ 111 AAC_ADAP_HIGH_RESP_ENTRIES + AAC_ADAP_NORM_RESP_ENTRIES) 112 113 #define AAC_QUEUE_COUNT 8 114 #define AAC_QUEUE_ALIGN 16 115 116 struct aac_queue_entry { 117 u_int32_t aq_fib_size; /* FIB size in bytes */ 118 u_int32_t aq_fib_addr; /* receiver-space address of the FIB */ 119 } __attribute__ ((__packed__)); 120 121 #define AAC_PRODUCER_INDEX 0 122 #define AAC_CONSUMER_INDEX 1 123 124 /* 125 * Table of queue indices and queues used to communicate with the 126 * controller. This structure must be aligned to AAC_QUEUE_ALIGN 127 */ 128 struct aac_queue_table { 129 /* queue consumer/producer indexes (layout mandated by adapter) */ 130 u_int32_t qt_qindex[AAC_QUEUE_COUNT][2]; 131 132 /* queue entry structures (layout mandated by adapter) */ 133 struct aac_queue_entry qt_HostNormCmdQueue[AAC_HOST_NORM_CMD_ENTRIES]; 134 struct aac_queue_entry qt_HostHighCmdQueue[AAC_HOST_HIGH_CMD_ENTRIES]; 135 struct aac_queue_entry qt_AdapNormCmdQueue[AAC_ADAP_NORM_CMD_ENTRIES]; 136 struct aac_queue_entry qt_AdapHighCmdQueue[AAC_ADAP_HIGH_CMD_ENTRIES]; 137 struct aac_queue_entry 138 qt_HostNormRespQueue[AAC_HOST_NORM_RESP_ENTRIES]; 139 struct aac_queue_entry 140 qt_HostHighRespQueue[AAC_HOST_HIGH_RESP_ENTRIES]; 141 struct aac_queue_entry 142 qt_AdapNormRespQueue[AAC_ADAP_NORM_RESP_ENTRIES]; 143 struct aac_queue_entry 144 qt_AdapHighRespQueue[AAC_ADAP_HIGH_RESP_ENTRIES]; 145 } __attribute__ ((__packed__)); 146 147 /* 148 * Adapter Init Structure: this is passed to the adapter with the 149 * AAC_MONKER_INITSTRUCT command to point it at our control structures. 150 */ 151 struct aac_adapter_init { 152 u_int32_t InitStructRevision; 153 #define AAC_INIT_STRUCT_REVISION 3 154 u_int32_t MiniPortRevision; 155 u_int32_t FilesystemRevision; 156 u_int32_t CommHeaderAddress; 157 u_int32_t FastIoCommAreaAddress; 158 u_int32_t AdapterFibsPhysicalAddress; 159 void *AdapterFibsVirtualAddress; 160 u_int32_t AdapterFibsSize; 161 u_int32_t AdapterFibAlign; 162 u_int32_t PrintfBufferAddress; 163 u_int32_t PrintfBufferSize; 164 u_int32_t HostPhysMemPages; 165 u_int32_t HostElapsedSeconds; 166 } __attribute__((__packed__)); 167 168 /* 169 * Shared data types 170 */ 171 172 /* 173 * Container types 174 */ 175 #define CT_NONE 0 176 #define CT_VOLUME 1 177 #define CT_MIRROR 2 178 #define CT_STRIPE 3 179 #define CT_RAID5 4 180 #define CT_SSRW 5 181 #define CT_SSRO 6 182 #define CT_MORPH 7 183 #define CT_PASSTHRU 8 184 #define CT_RAID4 9 185 #define CT_RAID10 10 /* stripe of mirror */ 186 #define CT_RAID00 11 /* stripe of stripe */ 187 #define CT_VOLUME_OF_MIRRORS 12 /* volume of mirror */ 188 #define CT_PSEUDO_RAID3 13 /* really raid4 */ 189 190 /* 191 * Host-addressable object types 192 */ 193 #define FT_REG 1 /* regular file */ 194 #define FT_DIR 2 /* directory */ 195 #define FT_BLK 3 /* "block" device - reserved */ 196 #define FT_CHR 4 /* "character special" device - reserved */ 197 #define FT_LNK 5 /* symbolic link */ 198 #define FT_SOCK 6 /* socket */ 199 #define FT_FIFO 7 /* fifo */ 200 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ 201 #define FT_DRIVE 9 /* phys disk - addressable in scsi by bus/target/lun */ 202 #define FT_SLICE 10 /* virtual disk - raw volume - slice */ 203 #define FT_PARTITION 11 /* FSA part, inside slice, container building block */ 204 #define FT_VOLUME 12 /* Container - Volume Set */ 205 #define FT_STRIPE 13 /* Container - Stripe Set */ 206 #define FT_MIRROR 14 /* Container - Mirror Set */ 207 #define FT_RAID5 15 /* Container - Raid 5 Set */ 208 #define FT_DATABASE 16 /* Storage object with "foreign" content manager */ 209 210 /* 211 * Host-side scatter/gather list for 32-bit commands. 212 */ 213 struct aac_sg_entry { 214 u_int32_t SgAddress; 215 u_int32_t SgByteCount; 216 } __attribute__ ((__packed__)); 217 218 struct aac_sg_table { 219 u_int32_t SgCount; 220 struct aac_sg_entry SgEntry[0]; /* XXX */ 221 } __attribute__ ((__packed__)); 222 223 /* 224 * Host-side scatter/gather list for 64-bit commands. 225 */ 226 struct aac_sg_table64 { 227 u_int8_t SgCount; 228 u_int8_t SgSectorsPerPage; 229 u_int16_t SgByteOffset; 230 u_int64_t SgEntry[0]; 231 } __attribute__ ((__packed__)); 232 233 /* 234 * Container creation data 235 */ 236 struct aac_container_creation { 237 u_int8_t ViaBuildNumber; 238 u_int8_t MicroSecond; 239 u_int8_t Via; /* 1 = FSU, 2 = API, etc. */ 240 u_int8_t YearsSince1900; 241 u_int32_t Month:4; /* 1-12 */ 242 u_int32_t Day:6; /* 1-32 */ 243 u_int32_t Hour:6; /* 0-23 */ 244 u_int32_t Minute:6; /* 0-59 */ 245 u_int32_t Second:6; /* 0-59 */ 246 u_int64_t ViaAdapterSerialNumber; 247 } __attribute__ ((__packed__)); 248 249 struct FsaRevision { 250 union { 251 struct { 252 u_int8_t dash; 253 u_int8_t type; 254 u_int8_t minor; 255 u_int8_t major; 256 } comp; 257 u_int32_t ul; 258 } external; 259 u_int32_t buildNumber; 260 } __attribute__((__packed__)); 261 262 /* 263 * Adapter Information 264 */ 265 266 #define CPU_NTSIM 1 267 #define CPU_I960 2 268 #define CPU_ARM 3 269 #define CPU_SPARC 4 270 #define CPU_POWERPC 5 271 #define CPU_ALPHA 6 272 #define CPU_P7 7 273 #define CPU_I960_RX 8 274 #define CPU__last 9 275 276 #define CPUI960_JX 1 277 #define CPUI960_CX 2 278 #define CPUI960_HX 3 279 #define CPUI960_RX 4 280 #define CPUARM_SA110 5 281 #define CPUARM_xxx 6 282 #define CPUPPC_603e 7 283 #define CPUPPC_xxx 8 284 #define CPUI80303 9 285 #define CPUSUBTYPE__last 10 286 287 #define PLAT_NTSIM 1 288 #define PLAT_V3ADU 2 289 #define PLAT_CYCLONE 3 290 #define PLAT_CYCLONE_HD 4 291 #define PLAT_BATBOARD 5 292 #define PLAT_BATBOARD_HD 6 293 #define PLAT_YOLO 7 294 #define PLAT_COBRA 8 295 #define PLAT_ANAHEIM 9 296 #define PLAT_JALAPENO 10 297 #define PLAT_QUEENS 11 298 #define PLAT_JALAPENO_DELL 12 299 #define PLAT_POBLANO 13 300 #define PLAT_POBLANO_OPAL 14 301 #define PLAT_POBLANO_SL0 15 302 #define PLAT_POBLANO_SL1 16 303 #define PLAT_POBLANO_SL2 17 304 #define PLAT_POBLANO_XXX 18 305 #define PLAT_JALAPENO_P2 19 306 #define PLAT_HABANERO 20 307 #define PLAT__last 21 308 309 #define OEM_FLAVOR_ADAPTEC 1 310 #define OEM_FLAVOR_DELL 2 311 #define OEM_FLAVOR_HP 3 312 #define OEM_FLAVOR_IBM 4 313 #define OEM_FLAVOR_CPQ 5 314 #define OEM_FLAVOR_BRAND_X 6 315 #define OEM_FLAVOR_BRAND_Y 7 316 #define OEM_FLAVOR_BRAND_Z 8 317 #define OEM_FLAVOR__last 9 318 319 /* 320 * XXX the aac-2622 with no battery present reports PLATFORM_BAT_OPT_PRESENT 321 */ 322 #define PLATFORM_BAT_REQ_PRESENT 1 /* BATTERY REQUIRED AND PRESENT */ 323 #define PLATFORM_BAT_REQ_NOTPRESENT 2 /* BATTERY REQUIRED AND NOT PRESENT */ 324 #define PLATFORM_BAT_OPT_PRESENT 3 /* BATTERY OPTIONAL AND PRESENT */ 325 #define PLATFORM_BAT_OPT_NOTPRESENT 4 /* BATTERY OPTIONAL AND NOT PRESENT */ 326 #define PLATFORM_BAT_NOT_SUPPORTED 5 /* BATTERY NOT SUPPORTED */ 327 328 /* 329 * Structure used to respond to a RequestAdapterInfo fib. 330 */ 331 struct aac_adapter_info { 332 u_int32_t PlatformBase; /* adapter type */ 333 u_int32_t CpuArchitecture; /* adapter CPU type */ 334 u_int32_t CpuVariant; /* adapter CPU subtype */ 335 u_int32_t ClockSpeed; /* adapter CPU clockspeed */ 336 u_int32_t ExecutionMem; /* adapter Execution Memory size */ 337 u_int32_t BufferMem; /* adapter Data Memory */ 338 u_int32_t TotalMem; /* adapter Total Memory */ 339 struct FsaRevision KernelRevision; /* adapter Kernel SW Revision */ 340 struct FsaRevision MonitorRevision; /* adapter Monitor/Diag SW Rev */ 341 struct FsaRevision HardwareRevision; /* TDB */ 342 struct FsaRevision BIOSRevision; /* adapter BIOS Revision */ 343 u_int32_t ClusteringEnabled; 344 u_int32_t ClusterChannelMask; 345 u_int64_t SerialNumber; 346 u_int32_t batteryPlatform; 347 u_int32_t SupportedOptions; /* supported features of this ctrlr */ 348 u_int32_t OemVariant; 349 } __attribute__((__packed__)); 350 351 /* 352 * Monitor/Kernel interface. 353 */ 354 355 /* 356 * Synchronous commands to the monitor/kernel. 357 */ 358 #define AAC_MONKER_INITSTRUCT 0x05 359 #define AAC_MONKER_SYNCFIB 0x0c 360 #define AAC_MONKER_GETKERNVER 0x11 361 362 /* 363 * Command status values 364 */ 365 #define ST_OK 0 366 #define ST_PERM 1 367 #define ST_NOENT 2 368 #define ST_IO 5 369 #define ST_NXIO 6 370 #define ST_E2BIG 7 371 #define ST_ACCES 13 372 #define ST_EXIST 17 373 #define ST_XDEV 18 374 #define ST_NODEV 19 375 #define ST_NOTDIR 20 376 #define ST_ISDIR 21 377 #define ST_INVAL 22 378 #define ST_FBIG 27 379 #define ST_NOSPC 28 380 #define ST_ROFS 30 381 #define ST_MLINK 31 382 #define ST_WOULDBLOCK 35 383 #define ST_NAMETOOLONG 63 384 #define ST_NOTEMPTY 66 385 #define ST_DQUOT 69 386 #define ST_STALE 70 387 #define ST_REMOTE 71 388 #define ST_BADHANDLE 10001 389 #define ST_NOT_SYNC 10002 390 #define ST_BAD_COOKIE 10003 391 #define ST_NOTSUPP 10004 392 #define ST_TOOSMALL 10005 393 #define ST_SERVERFAULT 10006 394 #define ST_BADTYPE 10007 395 #define ST_JUKEBOX 10008 396 #define ST_NOTMOUNTED 10009 397 #define ST_MAINTMODE 10010 398 #define ST_STALEACL 10011 399 400 /* 401 * Volume manager commands 402 */ 403 #define VM_Null 0 404 #define VM_NameServe 1 405 #define VM_ContainerConfig 2 406 #define VM_Ioctl 3 407 #define VM_FilesystemIoctl 4 408 #define VM_CloseAll 5 409 #define VM_CtBlockRead 6 410 #define VM_CtBlockWrite 7 411 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ 412 #define VM_SliceBlockWrite 9 413 #define VM_DriveBlockRead 10 /* raw access to physical devices */ 414 #define VM_DriveBlockWrite 11 415 #define VM_EnclosureMgt 12 /* enclosure management */ 416 #define VM_Unused 13 /* used to be diskset management */ 417 #define VM_CtBlockVerify 14 418 #define VM_CtPerf 15 /* performance test */ 419 #define VM_CtBlockRead64 16 420 #define VM_CtBlockWrite64 17 421 #define VM_CtBlockVerify64 18 422 423 /* 424 * "Mountable object" 425 */ 426 struct aac_mntobj { 427 u_int32_t ObjectId; 428 char FileSystemName[16]; 429 struct aac_container_creation CreateInfo; 430 u_int32_t Capacity; 431 u_int32_t VolType; 432 u_int32_t ObjType; 433 u_int32_t ContentState; 434 #define AAC_FSCS_READONLY 0x0002 /* XXX need more information than this */ 435 union { 436 u_int32_t pad[8]; 437 } ObjExtension; 438 u_int32_t AlterEgoId; 439 } __attribute__ ((__packed__)); 440 441 struct aac_mntinfo { 442 u_int32_t Command; 443 u_int32_t MntType; 444 u_int32_t MntCount; 445 } __attribute__ ((__packed__)); 446 447 struct aac_mntinforesponse { 448 u_int32_t Status; 449 u_int32_t MntType; 450 u_int32_t MntRespCount; 451 struct aac_mntobj MntTable[1]; 452 } __attribute__ ((__packed__)); 453 454 /* 455 * Write 'stability' options. 456 */ 457 #define CSTABLE 1 458 #define CUNSTABLE 2 459 460 /* 461 * Commit level response for a write request. 462 */ 463 #define CMFILE_SYNC_NVRAM 1 464 #define CMDATA_SYNC_NVRAM 2 465 #define CMFILE_SYNC 3 466 #define CMDATA_SYNC 4 467 #define CMUNSTABLE 5 468 469 /* 470 * Block read/write operations. These structures are packed into the 'data' 471 * area in the FIB. 472 */ 473 struct aac_blockread { 474 u_int32_t Command; /* not FSACommand! */ 475 u_int32_t ContainerId; 476 u_int32_t BlockNumber; 477 u_int32_t ByteCount; 478 struct aac_sg_table SgMap; /* variable size */ 479 } __attribute__ ((__packed__)); 480 481 struct aac_blockread_response { 482 u_int32_t Status; 483 u_int32_t ByteCount; 484 } __attribute__ ((__packed__)); 485 486 struct aac_blockwrite { 487 u_int32_t Command; /* not FSACommand! */ 488 u_int32_t ContainerId; 489 u_int32_t BlockNumber; 490 u_int32_t ByteCount; 491 u_int32_t Stable; 492 struct aac_sg_table SgMap; /* variable size */ 493 } __attribute__ ((__packed__)); 494 495 struct aac_blockwrite_response { 496 u_int32_t Status; 497 u_int32_t ByteCount; 498 u_int32_t Committed; 499 } __attribute__ ((__packed__)); 500 501 struct aac_close_command { 502 u_int32_t Command; 503 u_int32_t ContainerId; 504 } __attribute__ ((__packed__)); 505 506 /* 507 * Register definitions for the Adaptec AAC-364 'Jalapeno I/II' adapters, based 508 * on the SA110 'StrongArm'. 509 */ 510 511 #define AAC_REGSIZE 0x100 512 513 /* doorbell 0 (adapter->host) */ 514 #define AAC_SA_DOORBELL0_CLEAR 0x98 515 #define AAC_SA_DOORBELL0_SET 0x9c 516 #define AAC_SA_DOORBELL0 0x9c 517 #define AAC_SA_MASK0_CLEAR 0xa0 518 #define AAC_SA_MASK0_SET 0xa4 519 520 /* doorbell 1 (host->adapter) */ 521 #define AAC_SA_DOORBELL1_CLEAR 0x9a 522 #define AAC_SA_DOORBELL1_SET 0x9e 523 #define AAC_SA_MASK1_CLEAR 0xa2 524 #define AAC_SA_MASK1_SET 0xa6 525 526 /* mailbox (20 bytes) */ 527 #define AAC_SA_MAILBOX 0xa8 528 #define AAC_SA_FWSTATUS 0xc4 529 530 /* 531 * Register definitions for the Adaptec 'Pablano' adapters, based on the 532 * i960Rx, and other related adapters. 533 */ 534 535 #define AAC_RX_IDBR 0x20 /* inbound doorbell */ 536 #define AAC_RX_IISR 0x24 /* inbound interrupt status */ 537 #define AAC_RX_IIMR 0x28 /* inbound interrupt mask */ 538 #define AAC_RX_ODBR 0x2c /* outbound doorbell */ 539 #define AAC_RX_OISR 0x30 /* outbound interrupt status */ 540 #define AAC_RX_OIMR 0x34 /* outbound interrupt mask */ 541 542 #define AAC_RX_MAILBOX 0x50 /* mailbox (20 bytes) */ 543 #define AAC_RX_FWSTATUS 0x6c 544 545 /* 546 * Common bit definitions for the doorbell registers. 547 */ 548 549 /* 550 * Status bits in the doorbell registers. 551 */ 552 #define AAC_DB_SYNC_COMMAND (1<<0) /* send/completed synchronous FIB */ 553 #define AAC_DB_COMMAND_READY (1<<1) /* posted one or more commands */ 554 #define AAC_DB_RESPONSE_READY (1<<2) /* one or more commands complete */ 555 #define AAC_DB_COMMAND_NOT_FULL (1<<3) /* command queue not full */ 556 #define AAC_DB_RESPONSE_NOT_FULL (1<<4) /* response queue not full */ 557 558 /* 559 * The adapter can request the host print a message by setting the 560 * DB_PRINTF flag in DOORBELL0. The driver responds by collecting the 561 * message from the printf buffer, clearing the DB_PRINTF flag in 562 * DOORBELL0 and setting it in DOORBELL1. 563 * (ODBR and IDBR respectively for the i960Rx adapters) 564 */ 565 #define AAC_DB_PRINTF (1<<5) 566 567 /* 568 * Mask containing the interrupt bits we care about. We don't anticipate 569 * (or want) interrupts not in this mask. 570 */ 571 #define AAC_DB_INTERRUPTS \ 572 (AAC_DB_COMMAND_READY | AAC_DB_RESPONSE_READY | AAC_DB_PRINTF) 573 574 /* 575 * Queue names 576 * 577 * Note that we base these at 0 in order to use them as array indices. Adaptec 578 * used base 1 for some unknown reason, and sorted them in a different order. 579 */ 580 #define AAC_HOST_NORM_CMD_QUEUE 0 581 #define AAC_HOST_HIGH_CMD_QUEUE 1 582 #define AAC_ADAP_NORM_CMD_QUEUE 2 583 #define AAC_ADAP_HIGH_CMD_QUEUE 3 584 #define AAC_HOST_NORM_RESP_QUEUE 4 585 #define AAC_HOST_HIGH_RESP_QUEUE 5 586 #define AAC_ADAP_NORM_RESP_QUEUE 6 587 #define AAC_ADAP_HIGH_RESP_QUEUE 7 588 589 /* 590 * List structure used to chain FIBs (used by the adapter - we hang FIBs off 591 * our private command structure and don't touch these) 592 */ 593 struct aac_fib_list_entry { 594 struct fib_list_entry *Flink; 595 struct fib_list_entry *Blink; 596 } __attribute__((__packed__)); 597 598 /* 599 * FIB (FSA Interface Block?); this is the datastructure passed between the 600 * host and adapter. 601 */ 602 struct aac_fib_header { 603 u_int32_t XferState; 604 u_int16_t Command; 605 u_int8_t StructType; 606 u_int8_t Flags; 607 u_int16_t Size; 608 u_int16_t SenderSize; 609 u_int32_t SenderFibAddress; 610 u_int32_t ReceiverFibAddress; 611 u_int32_t SenderData; 612 union { 613 struct { 614 u_int32_t ReceiverTimeStart; 615 u_int32_t ReceiverTimeDone; 616 } _s; 617 struct aac_fib_list_entry FibLinks; 618 } _u; 619 } __attribute__((__packed__)); 620 621 #define AAC_FIB_DATASIZE (512 - sizeof(struct aac_fib_header)) 622 623 struct aac_fib { 624 struct aac_fib_header Header; 625 u_int8_t data[AAC_FIB_DATASIZE]; 626 } __attribute__((__packed__)); 627 628 /* 629 * FIB commands 630 */ 631 #define TestCommandResponse 1 632 #define TestAdapterCommand 2 633 634 /* Lowlevel and comm commands */ 635 #define LastTestCommand 100 636 #define ReinitHostNormCommandQueue 101 637 #define ReinitHostHighCommandQueue 102 638 #define ReinitHostHighRespQueue 103 639 #define ReinitHostNormRespQueue 104 640 #define ReinitAdapNormCommandQueue 105 641 #define ReinitAdapHighCommandQueue 107 642 #define ReinitAdapHighRespQueue 108 643 #define ReinitAdapNormRespQueue 109 644 #define InterfaceShutdown 110 645 #define DmaCommandFib 120 646 #define StartProfile 121 647 #define TermProfile 122 648 #define SpeedTest 123 649 #define TakeABreakPt 124 650 #define RequestPerfData 125 651 #define SetInterruptDefTimer 126 652 #define SetInterruptDefCount 127 653 #define GetInterruptDefStatus 128 654 #define LastCommCommand 129 655 656 /* filesystem commands */ 657 #define NuFileSystem 300 658 #define UFS 301 659 #define HostFileSystem 302 660 #define LastFileSystemCommand 303 661 662 /* Container Commands */ 663 #define ContainerCommand 500 664 #define ContainerCommand64 501 665 666 /* Cluster Commands */ 667 #define ClusterCommand 550 668 669 /* Scsi Port commands (scsi passthrough) */ 670 #define ScsiPortCommand 600 671 672 /* Misc house keeping and generic adapter initiated commands */ 673 #define AifRequest 700 674 #define CheckRevision 701 675 #define FsaHostShutdown 702 676 #define RequestAdapterInfo 703 677 #define IsAdapterPaused 704 678 #define SendHostTime 705 679 #define LastMiscCommand 706 680 681 /* 682 * FIB types 683 */ 684 #define AAC_FIBTYPE_TFIB 1 685 #define AAC_FIBTYPE_TQE 2 686 #define AAC_FIBTYPE_TCTPERF 3 687 688 /* 689 * FIB transfer state 690 */ 691 #define AAC_FIBSTATE_HOSTOWNED (1<<0) /* owned by the host */ 692 #define AAC_FIBSTATE_ADAPTEROWNED (1<<1) /* owned by the adapter */ 693 #define AAC_FIBSTATE_INITIALISED (1<<2) /* initialised */ 694 #define AAC_FIBSTATE_EMPTY (1<<3) /* empty */ 695 #define AAC_FIBSTATE_FROMPOOL (1<<4) /* allocated from pool */ 696 #define AAC_FIBSTATE_FROMHOST (1<<5) /* sent from the host */ 697 #define AAC_FIBSTATE_FROMADAP (1<<6) /* sent from the adapter */ 698 #define AAC_FIBSTATE_REXPECTED (1<<7) /* response is expected */ 699 #define AAC_FIBSTATE_RNOTEXPECTED (1<<8) /* response is not expected */ 700 #define AAC_FIBSTATE_DONEADAP (1<<9) /* processed by the adapter */ 701 #define AAC_FIBSTATE_DONEHOST (1<<10) /* processed by the host */ 702 #define AAC_FIBSTATE_HIGH (1<<11) /* high priority */ 703 #define AAC_FIBSTATE_NORM (1<<12) /* normal priority */ 704 #define AAC_FIBSTATE_ASYNC (1<<13) 705 #define AAC_FIBSTATE_ASYNCIO (1<<13) /* to be removed */ 706 #define AAC_FIBSTATE_PAGEFILEIO (1<<14) /* to be removed */ 707 #define AAC_FIBSTATE_SHUTDOWN (1<<15) 708 #define AAC_FIBSTATE_LAZYWRITE (1<<16) /* to be removed */ 709 #define AAC_FIBSTATE_ADAPMICROFIB (1<<17) 710 #define AAC_FIBSTATE_BIOSFIB (1<<18) 711 #define AAC_FIBSTATE_FAST_RESPONSE (1<<19) /* fast response capable */ 712 #define AAC_FIBSTATE_APIFIB (1<<20) 713 714 /* 715 * FIB error values 716 */ 717 #define AAC_ERROR_NORMAL 0x00 718 #define AAC_ERROR_PENDING 0x01 719 #define AAC_ERROR_FATAL 0x02 720 #define AAC_ERROR_INVALID_QUEUE 0x03 721 #define AAC_ERROR_NOENTRIES 0x04 722 #define AAC_ERROR_SENDFAILED 0x05 723 #define AAC_ERROR_INVALID_QUEUE_PRIORITY 0x06 724 #define AAC_ERROR_FIB_ALLOCATION_FAILED 0x07 725 #define AAC_ERROR_FIB_DEALLOCATION_FAILED 0x08 726 727 /* 728 * Adapter Status Register 729 * 730 * Phase Staus mailbox is 32bits: 731 * <31:16> = Phase Status 732 * <15:0> = Phase 733 * 734 * The adapter reports its present state through the phase. Only 735 * a single phase should be ever be set. Each phase can have multiple 736 * phase status bits to provide more detailed information about the 737 * state of the adapter. 738 */ 739 #define AAC_SELF_TEST_FAILED 0x00000004 740 #define AAC_UP_AND_RUNNING 0x00000080 741 #define AAC_KERNEL_PANIC 0x00000100 742 743 #endif /* !_PCI_AACREG_H_ */ 744
Indexes created Fri Sep 26 20:09:58 GMT 2025