adv.c revision 1.10 1 1.10 dante /* $NetBSD: adv.c,v 1.10 1999/02/25 20:21:33 dante Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.4 dante * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.4 dante * This product includes software developed by the NetBSD
22 1.4 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.1 dante #include <sys/kernel.h>
44 1.1 dante #include <sys/errno.h>
45 1.1 dante #include <sys/ioctl.h>
46 1.1 dante #include <sys/device.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/buf.h>
49 1.1 dante #include <sys/proc.h>
50 1.1 dante #include <sys/user.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <vm/vm.h>
56 1.1 dante #include <vm/vm_param.h>
57 1.1 dante #include <vm/pmap.h>
58 1.1 dante
59 1.1 dante #include <dev/scsipi/scsi_all.h>
60 1.1 dante #include <dev/scsipi/scsipi_all.h>
61 1.1 dante #include <dev/scsipi/scsiconf.h>
62 1.1 dante
63 1.10 dante #include <dev/ic/advlib.h>
64 1.1 dante #include <dev/ic/adv.h>
65 1.3 thorpej
66 1.3 thorpej #ifndef DDB
67 1.3 thorpej #define Debugger() panic("should call debugger here (adv.c)")
68 1.3 thorpej #endif /* ! DDB */
69 1.1 dante
70 1.6 dante
71 1.6 dante /* #define ASC_DEBUG */
72 1.6 dante
73 1.1 dante /******************************************************************************/
74 1.1 dante
75 1.1 dante
76 1.1 dante static int adv_alloc_ccbs __P((ASC_SOFTC *));
77 1.1 dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
78 1.1 dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
79 1.1 dante static void adv_reset_ccb __P((ADV_CCB *));
80 1.1 dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
81 1.1 dante static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
82 1.1 dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
83 1.1 dante static void adv_start_ccbs __P((ASC_SOFTC *));
84 1.1 dante
85 1.1 dante static u_int8_t *adv_alloc_overrunbuf __P((char *dvname, bus_dma_tag_t));
86 1.1 dante
87 1.1 dante static int adv_scsi_cmd __P((struct scsipi_xfer *));
88 1.1 dante static void advminphys __P((struct buf *));
89 1.1 dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
90 1.1 dante
91 1.1 dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
92 1.1 dante static void adv_timeout __P((void *));
93 1.1 dante static void adv_watchdog __P((void *));
94 1.1 dante
95 1.1 dante
96 1.1 dante /******************************************************************************/
97 1.1 dante
98 1.1 dante
99 1.1 dante /* the below structure is so we have a default dev struct for out link struct */
100 1.1 dante struct scsipi_device adv_dev =
101 1.1 dante {
102 1.1 dante NULL, /* Use default error handler */
103 1.1 dante NULL, /* have a queue, served by this */
104 1.1 dante NULL, /* have no async handler */
105 1.1 dante NULL, /* Use default 'done' routine */
106 1.1 dante };
107 1.1 dante
108 1.1 dante
109 1.1 dante #define ADV_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
110 1.1 dante #define ADV_WATCH_TIMEOUT 1000 /* time to wait for watchdog (mSec) */
111 1.1 dante
112 1.1 dante
113 1.1 dante /******************************************************************************/
114 1.1 dante /* scsipi_xfer queue routines */
115 1.1 dante /******************************************************************************/
116 1.1 dante
117 1.1 dante
118 1.1 dante /******************************************************************************/
119 1.1 dante /* Control Blocks routines */
120 1.1 dante /******************************************************************************/
121 1.1 dante
122 1.1 dante
123 1.1 dante static int
124 1.1 dante adv_alloc_ccbs(sc)
125 1.1 dante ASC_SOFTC *sc;
126 1.1 dante {
127 1.1 dante bus_dma_segment_t seg;
128 1.1 dante int error, rseg;
129 1.1 dante
130 1.1 dante /*
131 1.1 dante * Allocate the control blocks.
132 1.1 dante */
133 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
134 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
135 1.1 dante printf("%s: unable to allocate control structures,"
136 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
137 1.1 dante return (error);
138 1.1 dante }
139 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
140 1.1 dante sizeof(struct adv_control), (caddr_t *) & sc->sc_control,
141 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
142 1.1 dante printf("%s: unable to map control structures, error = %d\n",
143 1.1 dante sc->sc_dev.dv_xname, error);
144 1.1 dante return (error);
145 1.1 dante }
146 1.1 dante /*
147 1.1 dante * Create and load the DMA map used for the control blocks.
148 1.1 dante */
149 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
150 1.1 dante 1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
151 1.1 dante &sc->sc_dmamap_control)) != 0) {
152 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
153 1.1 dante sc->sc_dev.dv_xname, error);
154 1.1 dante return (error);
155 1.1 dante }
156 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
157 1.1 dante sc->sc_control, sizeof(struct adv_control), NULL,
158 1.1 dante BUS_DMA_NOWAIT)) != 0) {
159 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
160 1.1 dante sc->sc_dev.dv_xname, error);
161 1.1 dante return (error);
162 1.1 dante }
163 1.1 dante return (0);
164 1.1 dante }
165 1.1 dante
166 1.1 dante
167 1.1 dante /*
168 1.1 dante * Create a set of ccbs and add them to the free list. Called once
169 1.1 dante * by adv_init(). We return the number of CCBs successfully created.
170 1.1 dante */
171 1.1 dante static int
172 1.1 dante adv_create_ccbs(sc, ccbstore, count)
173 1.1 dante ASC_SOFTC *sc;
174 1.1 dante ADV_CCB *ccbstore;
175 1.1 dante int count;
176 1.1 dante {
177 1.1 dante ADV_CCB *ccb;
178 1.1 dante int i, error;
179 1.1 dante
180 1.1 dante bzero(ccbstore, sizeof(ADV_CCB) * count);
181 1.1 dante for (i = 0; i < count; i++) {
182 1.1 dante ccb = &ccbstore[i];
183 1.1 dante if ((error = adv_init_ccb(sc, ccb)) != 0) {
184 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
185 1.1 dante sc->sc_dev.dv_xname, error);
186 1.1 dante return (i);
187 1.1 dante }
188 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
189 1.1 dante }
190 1.1 dante
191 1.1 dante return (i);
192 1.1 dante }
193 1.1 dante
194 1.1 dante
195 1.1 dante /*
196 1.1 dante * A ccb is put onto the free list.
197 1.1 dante */
198 1.1 dante static void
199 1.1 dante adv_free_ccb(sc, ccb)
200 1.1 dante ASC_SOFTC *sc;
201 1.1 dante ADV_CCB *ccb;
202 1.1 dante {
203 1.1 dante int s;
204 1.1 dante
205 1.1 dante s = splbio();
206 1.1 dante
207 1.1 dante adv_reset_ccb(ccb);
208 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
209 1.1 dante
210 1.1 dante /*
211 1.1 dante * If there were none, wake anybody waiting for one to come free,
212 1.1 dante * starting with queued entries.
213 1.1 dante */
214 1.1 dante if (ccb->chain.tqe_next == 0)
215 1.1 dante wakeup(&sc->sc_free_ccb);
216 1.1 dante
217 1.1 dante splx(s);
218 1.1 dante }
219 1.1 dante
220 1.1 dante
221 1.1 dante static void
222 1.1 dante adv_reset_ccb(ccb)
223 1.1 dante ADV_CCB *ccb;
224 1.1 dante {
225 1.1 dante
226 1.1 dante ccb->flags = 0;
227 1.1 dante }
228 1.1 dante
229 1.1 dante
230 1.1 dante static int
231 1.1 dante adv_init_ccb(sc, ccb)
232 1.1 dante ASC_SOFTC *sc;
233 1.1 dante ADV_CCB *ccb;
234 1.1 dante {
235 1.10 dante int hashnum, error;
236 1.1 dante
237 1.1 dante /*
238 1.1 dante * Create the DMA map for this CCB.
239 1.1 dante */
240 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
241 1.1 dante (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
242 1.1 dante ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
243 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
244 1.1 dante if (error) {
245 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
246 1.1 dante sc->sc_dev.dv_xname, error);
247 1.1 dante return (error);
248 1.1 dante }
249 1.10 dante
250 1.10 dante /*
251 1.10 dante * put in the phystokv hash table
252 1.10 dante * Never gets taken out.
253 1.10 dante */
254 1.10 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
255 1.10 dante ADV_CCB_OFF(ccb);
256 1.10 dante hashnum = CCB_HASH(ccb->hashkey);
257 1.10 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
258 1.10 dante sc->sc_ccbhash[hashnum] = ccb;
259 1.10 dante
260 1.1 dante adv_reset_ccb(ccb);
261 1.1 dante return (0);
262 1.1 dante }
263 1.1 dante
264 1.1 dante
265 1.1 dante /*
266 1.1 dante * Get a free ccb
267 1.1 dante *
268 1.1 dante * If there are none, see if we can allocate a new one
269 1.1 dante */
270 1.1 dante static ADV_CCB *
271 1.1 dante adv_get_ccb(sc, flags)
272 1.1 dante ASC_SOFTC *sc;
273 1.1 dante int flags;
274 1.1 dante {
275 1.1 dante ADV_CCB *ccb = 0;
276 1.1 dante int s;
277 1.1 dante
278 1.1 dante s = splbio();
279 1.1 dante
280 1.1 dante /*
281 1.1 dante * If we can and have to, sleep waiting for one to come free
282 1.1 dante * but only if we can't allocate a new one.
283 1.1 dante */
284 1.1 dante for (;;) {
285 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
286 1.1 dante if (ccb) {
287 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
288 1.1 dante break;
289 1.1 dante }
290 1.1 dante if ((flags & SCSI_NOSLEEP) != 0)
291 1.1 dante goto out;
292 1.1 dante
293 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
294 1.1 dante }
295 1.1 dante
296 1.1 dante ccb->flags |= CCB_ALLOC;
297 1.1 dante
298 1.1 dante out:
299 1.1 dante splx(s);
300 1.1 dante return (ccb);
301 1.1 dante }
302 1.1 dante
303 1.1 dante
304 1.1 dante /*
305 1.10 dante * Given a physical address, find the ccb that it corresponds to.
306 1.10 dante */
307 1.10 dante ADV_CCB *
308 1.10 dante adv_ccb_phys_kv(sc, ccb_phys)
309 1.10 dante ASC_SOFTC *sc;
310 1.10 dante u_long ccb_phys;
311 1.10 dante {
312 1.10 dante int hashnum = CCB_HASH(ccb_phys);
313 1.10 dante ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
314 1.10 dante
315 1.10 dante while (ccb) {
316 1.10 dante if (ccb->hashkey == ccb_phys)
317 1.10 dante break;
318 1.10 dante ccb = ccb->nexthash;
319 1.10 dante }
320 1.10 dante return (ccb);
321 1.10 dante }
322 1.10 dante
323 1.10 dante
324 1.10 dante /*
325 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
326 1.1 dante */
327 1.1 dante static void
328 1.1 dante adv_queue_ccb(sc, ccb)
329 1.1 dante ASC_SOFTC *sc;
330 1.1 dante ADV_CCB *ccb;
331 1.1 dante {
332 1.1 dante
333 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
334 1.1 dante
335 1.1 dante adv_start_ccbs(sc);
336 1.1 dante }
337 1.1 dante
338 1.1 dante
339 1.1 dante static void
340 1.1 dante adv_start_ccbs(sc)
341 1.1 dante ASC_SOFTC *sc;
342 1.1 dante {
343 1.1 dante ADV_CCB *ccb;
344 1.1 dante
345 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
346 1.1 dante if (ccb->flags & CCB_WATCHDOG)
347 1.1 dante untimeout(adv_watchdog, ccb);
348 1.1 dante
349 1.1 dante if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
350 1.1 dante ccb->flags |= CCB_WATCHDOG;
351 1.1 dante timeout(adv_watchdog, ccb,
352 1.1 dante (ADV_WATCH_TIMEOUT * hz) / 1000);
353 1.1 dante break;
354 1.1 dante }
355 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
356 1.1 dante
357 1.1 dante if ((ccb->xs->flags & SCSI_POLL) == 0)
358 1.1 dante timeout(adv_timeout, ccb, (ccb->timeout * hz) / 1000);
359 1.1 dante }
360 1.1 dante }
361 1.1 dante
362 1.1 dante
363 1.1 dante /******************************************************************************/
364 1.1 dante /* DMA able memory allocation routines */
365 1.1 dante /******************************************************************************/
366 1.1 dante
367 1.1 dante
368 1.1 dante /*
369 1.1 dante * Allocate a DMA able memory for overrun_buffer.
370 1.1 dante * This memory can be safely shared among all the AdvanSys boards.
371 1.1 dante */
372 1.1 dante u_int8_t *
373 1.1 dante adv_alloc_overrunbuf(dvname, dmat)
374 1.1 dante char *dvname;
375 1.1 dante bus_dma_tag_t dmat;
376 1.1 dante {
377 1.1 dante static u_int8_t *overrunbuf = NULL;
378 1.1 dante
379 1.1 dante bus_dmamap_t ovrbuf_dmamap;
380 1.1 dante bus_dma_segment_t seg;
381 1.1 dante int rseg, error;
382 1.1 dante
383 1.1 dante
384 1.1 dante /*
385 1.1 dante * if an overrun buffer has been already allocated don't allocate it
386 1.1 dante * again. Instead return the address of the allocated buffer.
387 1.1 dante */
388 1.1 dante if (overrunbuf)
389 1.1 dante return (overrunbuf);
390 1.1 dante
391 1.1 dante
392 1.1 dante if ((error = bus_dmamem_alloc(dmat, ASC_OVERRUN_BSIZE,
393 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
394 1.1 dante printf("%s: unable to allocate overrun buffer, error = %d\n",
395 1.1 dante dvname, error);
396 1.1 dante return (0);
397 1.1 dante }
398 1.1 dante if ((error = bus_dmamem_map(dmat, &seg, rseg, ASC_OVERRUN_BSIZE,
399 1.1 dante (caddr_t *) & overrunbuf, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
400 1.1 dante printf("%s: unable to map overrun buffer, error = %d\n",
401 1.1 dante dvname, error);
402 1.1 dante
403 1.1 dante bus_dmamem_free(dmat, &seg, 1);
404 1.1 dante return (0);
405 1.1 dante }
406 1.1 dante if ((error = bus_dmamap_create(dmat, ASC_OVERRUN_BSIZE, 1,
407 1.1 dante ASC_OVERRUN_BSIZE, 0, BUS_DMA_NOWAIT, &ovrbuf_dmamap)) != 0) {
408 1.1 dante printf("%s: unable to create overrun buffer DMA map,"
409 1.1 dante " error = %d\n", dvname, error);
410 1.1 dante
411 1.1 dante bus_dmamem_unmap(dmat, overrunbuf, ASC_OVERRUN_BSIZE);
412 1.1 dante bus_dmamem_free(dmat, &seg, 1);
413 1.1 dante return (0);
414 1.1 dante }
415 1.1 dante if ((error = bus_dmamap_load(dmat, ovrbuf_dmamap, overrunbuf,
416 1.1 dante ASC_OVERRUN_BSIZE, NULL, BUS_DMA_NOWAIT)) != 0) {
417 1.1 dante printf("%s: unable to load overrun buffer DMA map,"
418 1.1 dante " error = %d\n", dvname, error);
419 1.1 dante
420 1.1 dante bus_dmamap_destroy(dmat, ovrbuf_dmamap);
421 1.1 dante bus_dmamem_unmap(dmat, overrunbuf, ASC_OVERRUN_BSIZE);
422 1.1 dante bus_dmamem_free(dmat, &seg, 1);
423 1.1 dante return (0);
424 1.1 dante }
425 1.1 dante return (overrunbuf);
426 1.1 dante }
427 1.1 dante
428 1.1 dante
429 1.1 dante /******************************************************************************/
430 1.1 dante /* SCSI layer interfacing routines */
431 1.1 dante /******************************************************************************/
432 1.1 dante
433 1.1 dante
434 1.1 dante int
435 1.1 dante adv_init(sc)
436 1.1 dante ASC_SOFTC *sc;
437 1.1 dante {
438 1.1 dante int warn;
439 1.1 dante
440 1.4 dante if (!AscFindSignature(sc->sc_iot, sc->sc_ioh))
441 1.4 dante panic("adv_init: adv_find_signature failed");
442 1.1 dante
443 1.4 dante /*
444 1.4 dante * Read the board configuration
445 1.4 dante */
446 1.4 dante AscInitASC_SOFTC(sc);
447 1.4 dante warn = AscInitFromEEP(sc);
448 1.4 dante if (warn) {
449 1.4 dante printf("%s -get: ", sc->sc_dev.dv_xname);
450 1.4 dante switch (warn) {
451 1.4 dante case -1:
452 1.4 dante printf("Chip is not halted\n");
453 1.4 dante break;
454 1.4 dante
455 1.4 dante case -2:
456 1.4 dante printf("Couldn't get MicroCode Start"
457 1.4 dante " address\n");
458 1.4 dante break;
459 1.4 dante
460 1.4 dante case ASC_WARN_IO_PORT_ROTATE:
461 1.4 dante printf("I/O port address modified\n");
462 1.4 dante break;
463 1.4 dante
464 1.4 dante case ASC_WARN_AUTO_CONFIG:
465 1.4 dante printf("I/O port increment switch enabled\n");
466 1.4 dante break;
467 1.4 dante
468 1.4 dante case ASC_WARN_EEPROM_CHKSUM:
469 1.4 dante printf("EEPROM checksum error\n");
470 1.4 dante break;
471 1.4 dante
472 1.4 dante case ASC_WARN_IRQ_MODIFIED:
473 1.4 dante printf("IRQ modified\n");
474 1.4 dante break;
475 1.4 dante
476 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
477 1.4 dante printf("tag queuing enabled w/o disconnects\n");
478 1.4 dante break;
479 1.1 dante
480 1.4 dante default:
481 1.4 dante printf("unknown warning %d\n", warn);
482 1.1 dante }
483 1.4 dante }
484 1.4 dante if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
485 1.4 dante sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
486 1.4 dante
487 1.4 dante /*
488 1.4 dante * Modify the board configuration
489 1.4 dante */
490 1.4 dante warn = AscInitFromASC_SOFTC(sc);
491 1.4 dante if (warn) {
492 1.4 dante printf("%s -set: ", sc->sc_dev.dv_xname);
493 1.4 dante switch (warn) {
494 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
495 1.4 dante printf("tag queuing enabled w/o disconnects\n");
496 1.4 dante break;
497 1.1 dante
498 1.4 dante case ASC_WARN_AUTO_CONFIG:
499 1.4 dante printf("I/O port increment switch enabled\n");
500 1.4 dante break;
501 1.1 dante
502 1.4 dante default:
503 1.4 dante printf("unknown warning %d\n", warn);
504 1.1 dante }
505 1.4 dante }
506 1.4 dante sc->isr_callback = (ulong) adv_narrow_isr_callback;
507 1.1 dante
508 1.4 dante if (!(sc->overrun_buf = adv_alloc_overrunbuf(sc->sc_dev.dv_xname,
509 1.4 dante sc->sc_dmat))) {
510 1.1 dante return (1);
511 1.1 dante }
512 1.1 dante
513 1.1 dante return (0);
514 1.1 dante }
515 1.1 dante
516 1.1 dante
517 1.1 dante void
518 1.1 dante adv_attach(sc)
519 1.1 dante ASC_SOFTC *sc;
520 1.1 dante {
521 1.1 dante int i, error;
522 1.1 dante
523 1.4 dante /*
524 1.4 dante * Initialize board RISC chip and enable interrupts.
525 1.4 dante */
526 1.4 dante switch (AscInitDriver(sc)) {
527 1.4 dante case 0:
528 1.4 dante /* AllOK */
529 1.4 dante break;
530 1.1 dante
531 1.4 dante case 1:
532 1.4 dante panic("%s: bad signature", sc->sc_dev.dv_xname);
533 1.4 dante break;
534 1.1 dante
535 1.4 dante case 2:
536 1.4 dante panic("%s: unable to load MicroCode",
537 1.4 dante sc->sc_dev.dv_xname);
538 1.4 dante break;
539 1.1 dante
540 1.4 dante case 3:
541 1.4 dante panic("%s: unable to initialize MicroCode",
542 1.4 dante sc->sc_dev.dv_xname);
543 1.4 dante break;
544 1.1 dante
545 1.4 dante default:
546 1.4 dante panic("%s: unable to initialize board RISC chip",
547 1.4 dante sc->sc_dev.dv_xname);
548 1.1 dante }
549 1.1 dante
550 1.7 thorpej /*
551 1.7 thorpej * Fill in the adapter.
552 1.7 thorpej */
553 1.7 thorpej sc->sc_adapter.scsipi_cmd = adv_scsi_cmd;
554 1.7 thorpej sc->sc_adapter.scsipi_minphys = advminphys;
555 1.1 dante
556 1.1 dante /*
557 1.1 dante * fill in the prototype scsipi_link.
558 1.1 dante */
559 1.1 dante sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
560 1.1 dante sc->sc_link.adapter_softc = sc;
561 1.1 dante sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
562 1.7 thorpej sc->sc_link.adapter = &sc->sc_adapter;
563 1.1 dante sc->sc_link.device = &adv_dev;
564 1.1 dante sc->sc_link.openings = 4;
565 1.4 dante sc->sc_link.scsipi_scsi.max_target = 7;
566 1.8 mjacob sc->sc_link.scsipi_scsi.max_lun = 7;
567 1.1 dante sc->sc_link.type = BUS_SCSI;
568 1.1 dante
569 1.1 dante
570 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
571 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
572 1.9 thorpej TAILQ_INIT(&sc->sc_queue);
573 1.1 dante
574 1.1 dante
575 1.1 dante /*
576 1.1 dante * Allocate the Control Blocks.
577 1.1 dante */
578 1.1 dante error = adv_alloc_ccbs(sc);
579 1.1 dante if (error)
580 1.1 dante return; /* (error) */ ;
581 1.1 dante
582 1.1 dante /*
583 1.1 dante * Create and initialize the Control Blocks.
584 1.1 dante */
585 1.1 dante i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
586 1.1 dante if (i == 0) {
587 1.1 dante printf("%s: unable to create control blocks\n",
588 1.1 dante sc->sc_dev.dv_xname);
589 1.1 dante return; /* (ENOMEM) */ ;
590 1.1 dante } else if (i != ADV_MAX_CCB) {
591 1.1 dante printf("%s: WARNING: only %d of %d control blocks created\n",
592 1.1 dante sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
593 1.1 dante }
594 1.1 dante config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
595 1.1 dante }
596 1.1 dante
597 1.1 dante
598 1.1 dante static void
599 1.1 dante advminphys(bp)
600 1.1 dante struct buf *bp;
601 1.1 dante {
602 1.1 dante
603 1.1 dante if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
604 1.1 dante bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
605 1.1 dante minphys(bp);
606 1.1 dante }
607 1.1 dante
608 1.1 dante
609 1.1 dante /*
610 1.1 dante * start a scsi operation given the command and the data address. Also needs
611 1.1 dante * the unit, target and lu.
612 1.1 dante */
613 1.1 dante static int
614 1.1 dante adv_scsi_cmd(xs)
615 1.1 dante struct scsipi_xfer *xs;
616 1.1 dante {
617 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
618 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
619 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
620 1.1 dante ADV_CCB *ccb;
621 1.1 dante int s, flags, error, nsegs;
622 1.1 dante int fromqueue = 1, dontqueue = 0;
623 1.1 dante
624 1.1 dante
625 1.1 dante s = splbio(); /* protect the queue */
626 1.1 dante
627 1.1 dante /*
628 1.1 dante * If we're running the queue from adv_done(), we've been
629 1.1 dante * called with the first queue entry as our argument.
630 1.1 dante */
631 1.9 thorpej if (xs == TAILQ_FIRST(&sc->sc_queue)) {
632 1.9 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
633 1.1 dante fromqueue = 1;
634 1.1 dante } else {
635 1.1 dante
636 1.1 dante /* Polled requests can't be queued for later. */
637 1.1 dante dontqueue = xs->flags & SCSI_POLL;
638 1.1 dante
639 1.1 dante /*
640 1.1 dante * If there are jobs in the queue, run them first.
641 1.1 dante */
642 1.9 thorpej if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
643 1.1 dante /*
644 1.1 dante * If we can't queue, we have to abort, since
645 1.1 dante * we have to preserve order.
646 1.1 dante */
647 1.1 dante if (dontqueue) {
648 1.1 dante splx(s);
649 1.1 dante xs->error = XS_DRIVER_STUFFUP;
650 1.1 dante return (TRY_AGAIN_LATER);
651 1.1 dante }
652 1.1 dante /*
653 1.1 dante * Swap with the first queue entry.
654 1.1 dante */
655 1.9 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
656 1.9 thorpej xs = TAILQ_FIRST(&sc->sc_queue);
657 1.9 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
658 1.1 dante fromqueue = 1;
659 1.1 dante }
660 1.1 dante }
661 1.1 dante
662 1.1 dante
663 1.1 dante /*
664 1.1 dante * get a ccb to use. If the transfer
665 1.1 dante * is from a buf (possibly from interrupt time)
666 1.1 dante * then we can't allow it to sleep
667 1.1 dante */
668 1.1 dante
669 1.1 dante flags = xs->flags;
670 1.1 dante if ((ccb = adv_get_ccb(sc, flags)) == NULL) {
671 1.1 dante /*
672 1.1 dante * If we can't queue, we lose.
673 1.1 dante */
674 1.1 dante if (dontqueue) {
675 1.1 dante splx(s);
676 1.1 dante xs->error = XS_DRIVER_STUFFUP;
677 1.1 dante return (TRY_AGAIN_LATER);
678 1.1 dante }
679 1.1 dante /*
680 1.1 dante * Stuff ourselves into the queue, in front
681 1.1 dante * if we came off in the first place.
682 1.1 dante */
683 1.9 thorpej if (fromqueue)
684 1.9 thorpej TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
685 1.9 thorpej else
686 1.9 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
687 1.1 dante splx(s);
688 1.1 dante return (SUCCESSFULLY_QUEUED);
689 1.1 dante }
690 1.1 dante splx(s); /* done playing with the queue */
691 1.1 dante
692 1.1 dante ccb->xs = xs;
693 1.1 dante ccb->timeout = xs->timeout;
694 1.1 dante
695 1.1 dante /*
696 1.1 dante * Build up the request
697 1.1 dante */
698 1.1 dante memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
699 1.1 dante
700 1.10 dante ccb->scsiq.q2.ccb_ptr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
701 1.10 dante ADV_CCB_OFF(ccb);
702 1.1 dante
703 1.1 dante ccb->scsiq.cdbptr = &xs->cmd->opcode;
704 1.1 dante ccb->scsiq.q2.cdb_len = xs->cmdlen;
705 1.1 dante ccb->scsiq.q1.target_id = ASC_TID_TO_TARGET_ID(sc_link->scsipi_scsi.target);
706 1.1 dante ccb->scsiq.q1.target_lun = sc_link->scsipi_scsi.lun;
707 1.1 dante ccb->scsiq.q2.target_ix = ASC_TIDLUN_TO_IX(sc_link->scsipi_scsi.target,
708 1.1 dante sc_link->scsipi_scsi.lun);
709 1.1 dante ccb->scsiq.q1.sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
710 1.1 dante ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
711 1.1 dante ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
712 1.1 dante
713 1.1 dante /*
714 1.1 dante * If there are any outstanding requests for the current target,
715 1.1 dante * then every 255th request send an ORDERED request. This heuristic
716 1.1 dante * tries to retain the benefit of request sorting while preventing
717 1.1 dante * request starvation. 255 is the max number of tags or pending commands
718 1.1 dante * a device may have outstanding.
719 1.1 dante */
720 1.1 dante sc->reqcnt[sc_link->scsipi_scsi.target]++;
721 1.1 dante if ((sc->reqcnt[sc_link->scsipi_scsi.target] > 0) &&
722 1.1 dante (sc->reqcnt[sc_link->scsipi_scsi.target] % 255) == 0) {
723 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
724 1.1 dante } else {
725 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
726 1.1 dante }
727 1.1 dante
728 1.1 dante
729 1.1 dante if (xs->datalen) {
730 1.1 dante /*
731 1.1 dante * Map the DMA transfer.
732 1.1 dante */
733 1.1 dante #ifdef TFS
734 1.1 dante if (flags & SCSI_DATA_UIO) {
735 1.1 dante error = bus_dmamap_load_uio(dmat,
736 1.1 dante ccb->dmamap_xfer, (struct uio *) xs->data,
737 1.1 dante (flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
738 1.1 dante } else
739 1.1 dante #endif /* TFS */
740 1.1 dante {
741 1.1 dante error = bus_dmamap_load(dmat,
742 1.1 dante ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
743 1.1 dante (flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
744 1.1 dante }
745 1.1 dante
746 1.1 dante if (error) {
747 1.1 dante if (error == EFBIG) {
748 1.1 dante printf("%s: adv_scsi_cmd, more than %d dma"
749 1.1 dante " segments\n",
750 1.1 dante sc->sc_dev.dv_xname, ASC_MAX_SG_LIST);
751 1.1 dante } else {
752 1.1 dante printf("%s: adv_scsi_cmd, error %d loading"
753 1.1 dante " dma map\n",
754 1.1 dante sc->sc_dev.dv_xname, error);
755 1.1 dante }
756 1.1 dante
757 1.1 dante xs->error = XS_DRIVER_STUFFUP;
758 1.1 dante adv_free_ccb(sc, ccb);
759 1.1 dante return (COMPLETE);
760 1.1 dante }
761 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
762 1.1 dante ccb->dmamap_xfer->dm_mapsize,
763 1.1 dante (flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
764 1.1 dante BUS_DMASYNC_PREWRITE);
765 1.1 dante
766 1.1 dante
767 1.1 dante memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
768 1.1 dante
769 1.1 dante for (nsegs = 0; nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
770 1.1 dante
771 1.1 dante ccb->sghead.sg_list[nsegs].addr =
772 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
773 1.1 dante ccb->sghead.sg_list[nsegs].bytes =
774 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
775 1.1 dante }
776 1.1 dante
777 1.1 dante ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
778 1.1 dante ccb->dmamap_xfer->dm_nsegs;
779 1.1 dante
780 1.1 dante ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
781 1.1 dante ccb->scsiq.sg_head = &ccb->sghead;
782 1.1 dante ccb->scsiq.q1.data_addr = 0;
783 1.1 dante ccb->scsiq.q1.data_cnt = 0;
784 1.1 dante } else {
785 1.1 dante /*
786 1.1 dante * No data xfer, use non S/G values.
787 1.1 dante */
788 1.1 dante ccb->scsiq.q1.data_addr = 0;
789 1.1 dante ccb->scsiq.q1.data_cnt = 0;
790 1.1 dante }
791 1.1 dante
792 1.6 dante #ifdef ASC_DEBUG
793 1.6 dante printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX \n",
794 1.6 dante sc_link->scsipi_scsi.target,
795 1.6 dante sc_link->scsipi_scsi.lun, xs->cmd->opcode,
796 1.6 dante (unsigned long)ccb);
797 1.6 dante #endif
798 1.1 dante s = splbio();
799 1.1 dante adv_queue_ccb(sc, ccb);
800 1.1 dante splx(s);
801 1.1 dante
802 1.1 dante /*
803 1.1 dante * Usually return SUCCESSFULLY QUEUED
804 1.1 dante */
805 1.1 dante if ((flags & SCSI_POLL) == 0)
806 1.1 dante return (SUCCESSFULLY_QUEUED);
807 1.1 dante
808 1.1 dante /*
809 1.1 dante * If we can't use interrupts, poll on completion
810 1.1 dante */
811 1.1 dante if (adv_poll(sc, xs, ccb->timeout)) {
812 1.1 dante adv_timeout(ccb);
813 1.1 dante if (adv_poll(sc, xs, ccb->timeout))
814 1.1 dante adv_timeout(ccb);
815 1.1 dante }
816 1.1 dante return (COMPLETE);
817 1.1 dante }
818 1.1 dante
819 1.1 dante
820 1.1 dante int
821 1.1 dante adv_intr(arg)
822 1.1 dante void *arg;
823 1.1 dante {
824 1.1 dante ASC_SOFTC *sc = arg;
825 1.1 dante struct scsipi_xfer *xs;
826 1.1 dante
827 1.6 dante #ifdef ASC_DEBUG
828 1.6 dante int int_pend = FALSE;
829 1.6 dante
830 1.6 dante if(ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh))
831 1.6 dante {
832 1.6 dante int_pend = TRUE;
833 1.6 dante printf("ISR - ");
834 1.6 dante }
835 1.6 dante #endif
836 1.4 dante AscISR(sc);
837 1.6 dante #ifdef ASC_DEBUG
838 1.6 dante if(int_pend)
839 1.6 dante printf("\n");
840 1.6 dante #endif
841 1.1 dante
842 1.1 dante /*
843 1.1 dante * If there are queue entries in the software queue, try to
844 1.1 dante * run the first one. We should be more or less guaranteed
845 1.1 dante * to succeed, since we just freed a CCB.
846 1.1 dante *
847 1.1 dante * NOTE: adv_scsi_cmd() relies on our calling it with
848 1.1 dante * the first entry in the queue.
849 1.1 dante */
850 1.9 thorpej if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
851 1.1 dante (void) adv_scsi_cmd(xs);
852 1.1 dante
853 1.1 dante return (1);
854 1.1 dante }
855 1.1 dante
856 1.1 dante
857 1.1 dante /*
858 1.1 dante * Poll a particular unit, looking for a particular xs
859 1.1 dante */
860 1.1 dante static int
861 1.1 dante adv_poll(sc, xs, count)
862 1.1 dante ASC_SOFTC *sc;
863 1.1 dante struct scsipi_xfer *xs;
864 1.1 dante int count;
865 1.1 dante {
866 1.1 dante
867 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
868 1.1 dante while (count) {
869 1.1 dante adv_intr(sc);
870 1.1 dante if (xs->flags & ITSDONE)
871 1.1 dante return (0);
872 1.1 dante delay(1000); /* only happens in boot so ok */
873 1.1 dante count--;
874 1.1 dante }
875 1.1 dante return (1);
876 1.1 dante }
877 1.1 dante
878 1.1 dante
879 1.1 dante static void
880 1.1 dante adv_timeout(arg)
881 1.1 dante void *arg;
882 1.1 dante {
883 1.1 dante ADV_CCB *ccb = arg;
884 1.1 dante struct scsipi_xfer *xs = ccb->xs;
885 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
886 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
887 1.1 dante int s;
888 1.1 dante
889 1.1 dante scsi_print_addr(sc_link);
890 1.1 dante printf("timed out");
891 1.1 dante
892 1.1 dante s = splbio();
893 1.1 dante
894 1.1 dante /*
895 1.1 dante * If it has been through before, then a previous abort has failed,
896 1.1 dante * don't try abort again, reset the bus instead.
897 1.1 dante */
898 1.1 dante if (ccb->flags & CCB_ABORT) {
899 1.1 dante /* abort timed out */
900 1.1 dante printf(" AGAIN. Resetting Bus\n");
901 1.1 dante /* Lets try resetting the bus! */
902 1.1 dante if (AscResetBus(sc) == ASC_ERROR) {
903 1.1 dante ccb->timeout = sc->scsi_reset_wait;
904 1.1 dante adv_queue_ccb(sc, ccb);
905 1.1 dante }
906 1.1 dante } else {
907 1.1 dante /* abort the operation that has timed out */
908 1.1 dante printf("\n");
909 1.10 dante AscAbortCCB(sc, ccb);
910 1.1 dante ccb->xs->error = XS_TIMEOUT;
911 1.1 dante ccb->timeout = ADV_ABORT_TIMEOUT;
912 1.1 dante ccb->flags |= CCB_ABORT;
913 1.1 dante adv_queue_ccb(sc, ccb);
914 1.1 dante }
915 1.1 dante
916 1.1 dante splx(s);
917 1.1 dante }
918 1.1 dante
919 1.1 dante
920 1.1 dante static void
921 1.1 dante adv_watchdog(arg)
922 1.1 dante void *arg;
923 1.1 dante {
924 1.1 dante ADV_CCB *ccb = arg;
925 1.1 dante struct scsipi_xfer *xs = ccb->xs;
926 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
927 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
928 1.1 dante int s;
929 1.1 dante
930 1.1 dante s = splbio();
931 1.1 dante
932 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
933 1.1 dante adv_start_ccbs(sc);
934 1.1 dante
935 1.1 dante splx(s);
936 1.1 dante }
937 1.1 dante
938 1.1 dante
939 1.1 dante /******************************************************************************/
940 1.10 dante /* NARROW boards Interrupt callbacks */
941 1.1 dante /******************************************************************************/
942 1.1 dante
943 1.1 dante
944 1.1 dante /*
945 1.1 dante * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
946 1.1 dante *
947 1.1 dante * Interrupt callback function for the Narrow SCSI Asc Library.
948 1.1 dante */
949 1.1 dante static void
950 1.1 dante adv_narrow_isr_callback(sc, qdonep)
951 1.1 dante ASC_SOFTC *sc;
952 1.1 dante ASC_QDONE_INFO *qdonep;
953 1.1 dante {
954 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
955 1.10 dante ADV_CCB *ccb;
956 1.10 dante struct scsipi_xfer *xs;
957 1.1 dante struct scsipi_sense_data *s1, *s2;
958 1.1 dante
959 1.10 dante
960 1.10 dante ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
961 1.10 dante xs = ccb->xs;
962 1.1 dante
963 1.6 dante #ifdef ASC_DEBUG
964 1.6 dante printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
965 1.6 dante (unsigned long)ccb,
966 1.6 dante xs->sc_link->scsipi_scsi.target,
967 1.6 dante xs->sc_link->scsipi_scsi.lun, xs->cmd->opcode);
968 1.6 dante #endif
969 1.1 dante untimeout(adv_timeout, ccb);
970 1.1 dante
971 1.1 dante /*
972 1.1 dante * If we were a data transfer, unload the map that described
973 1.1 dante * the data buffer.
974 1.1 dante */
975 1.1 dante if (xs->datalen) {
976 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
977 1.1 dante ccb->dmamap_xfer->dm_mapsize,
978 1.1 dante (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
979 1.1 dante BUS_DMASYNC_POSTWRITE);
980 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
981 1.1 dante }
982 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
983 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
984 1.1 dante Debugger();
985 1.1 dante return;
986 1.1 dante }
987 1.1 dante /*
988 1.1 dante * 'qdonep' contains the command's ending status.
989 1.1 dante */
990 1.6 dante #ifdef ASC_DEBUG
991 1.6 dante printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
992 1.6 dante #endif
993 1.1 dante switch (qdonep->d3.done_stat) {
994 1.1 dante case ASC_QD_NO_ERROR:
995 1.1 dante switch (qdonep->d3.host_stat) {
996 1.1 dante case ASC_QHSTA_NO_ERROR:
997 1.1 dante xs->error = XS_NOERROR;
998 1.1 dante xs->resid = 0;
999 1.1 dante break;
1000 1.1 dante
1001 1.1 dante default:
1002 1.1 dante /* QHSTA error occurred */
1003 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1004 1.1 dante break;
1005 1.1 dante }
1006 1.1 dante
1007 1.1 dante /*
1008 1.1 dante * If an INQUIRY command completed successfully, then call
1009 1.1 dante * the AscInquiryHandling() function to patch bugged boards.
1010 1.1 dante */
1011 1.1 dante if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
1012 1.1 dante (xs->sc_link->scsipi_scsi.lun == 0) &&
1013 1.1 dante (xs->datalen - qdonep->remain_bytes) >= 8) {
1014 1.1 dante AscInquiryHandling(sc,
1015 1.1 dante xs->sc_link->scsipi_scsi.target & 0x7,
1016 1.1 dante (ASC_SCSI_INQUIRY *) xs->data);
1017 1.1 dante }
1018 1.1 dante break;
1019 1.1 dante
1020 1.1 dante case ASC_QD_WITH_ERROR:
1021 1.1 dante switch (qdonep->d3.host_stat) {
1022 1.1 dante case ASC_QHSTA_NO_ERROR:
1023 1.1 dante if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
1024 1.1 dante s1 = &ccb->scsi_sense;
1025 1.1 dante s2 = &xs->sense.scsi_sense;
1026 1.1 dante *s2 = *s1;
1027 1.1 dante xs->error = XS_SENSE;
1028 1.4 dante } else {
1029 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1030 1.4 dante }
1031 1.1 dante break;
1032 1.1 dante
1033 1.1 dante default:
1034 1.1 dante /* QHSTA error occurred */
1035 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1036 1.1 dante break;
1037 1.1 dante }
1038 1.1 dante break;
1039 1.1 dante
1040 1.1 dante case ASC_QD_ABORTED_BY_HOST:
1041 1.1 dante default:
1042 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1043 1.1 dante break;
1044 1.1 dante }
1045 1.1 dante
1046 1.1 dante
1047 1.1 dante adv_free_ccb(sc, ccb);
1048 1.1 dante xs->flags |= ITSDONE;
1049 1.1 dante scsipi_done(xs);
1050 1.1 dante }
1051