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adv.c revision 1.14
      1  1.14  thorpej /*	$NetBSD: adv.c,v 1.14 1999/09/30 23:04:40 thorpej Exp $	*/
      2   1.2    dante 
      3   1.1    dante /*
      4   1.4    dante  * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
      5   1.1    dante  *
      6   1.1    dante  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      7   1.1    dante  * All rights reserved.
      8   1.1    dante  *
      9   1.1    dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10   1.1    dante  *
     11   1.1    dante  * Redistribution and use in source and binary forms, with or without
     12   1.1    dante  * modification, are permitted provided that the following conditions
     13   1.1    dante  * are met:
     14   1.1    dante  * 1. Redistributions of source code must retain the above copyright
     15   1.1    dante  *    notice, this list of conditions and the following disclaimer.
     16   1.1    dante  * 2. Redistributions in binary form must reproduce the above copyright
     17   1.1    dante  *    notice, this list of conditions and the following disclaimer in the
     18   1.1    dante  *    documentation and/or other materials provided with the distribution.
     19   1.1    dante  * 3. All advertising materials mentioning features or use of this software
     20   1.1    dante  *    must display the following acknowledgement:
     21   1.4    dante  *        This product includes software developed by the NetBSD
     22   1.4    dante  *        Foundation, Inc. and its contributors.
     23   1.1    dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24   1.1    dante  *    contributors may be used to endorse or promote products derived
     25   1.1    dante  *    from this software without specific prior written permission.
     26   1.1    dante  *
     27   1.1    dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28   1.1    dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29   1.1    dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30   1.1    dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31   1.1    dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32   1.1    dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33   1.1    dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34   1.1    dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35   1.1    dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36   1.1    dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37   1.1    dante  * POSSIBILITY OF SUCH DAMAGE.
     38   1.1    dante  */
     39   1.1    dante 
     40   1.1    dante #include <sys/types.h>
     41   1.1    dante #include <sys/param.h>
     42   1.1    dante #include <sys/systm.h>
     43   1.1    dante #include <sys/kernel.h>
     44   1.1    dante #include <sys/errno.h>
     45   1.1    dante #include <sys/ioctl.h>
     46   1.1    dante #include <sys/device.h>
     47   1.1    dante #include <sys/malloc.h>
     48   1.1    dante #include <sys/buf.h>
     49   1.1    dante #include <sys/proc.h>
     50   1.1    dante #include <sys/user.h>
     51   1.1    dante 
     52   1.1    dante #include <machine/bus.h>
     53   1.1    dante #include <machine/intr.h>
     54   1.1    dante 
     55   1.1    dante #include <vm/vm.h>
     56   1.1    dante #include <vm/vm_param.h>
     57   1.1    dante #include <vm/pmap.h>
     58   1.1    dante 
     59   1.1    dante #include <dev/scsipi/scsi_all.h>
     60   1.1    dante #include <dev/scsipi/scsipi_all.h>
     61   1.1    dante #include <dev/scsipi/scsiconf.h>
     62   1.1    dante 
     63  1.10    dante #include <dev/ic/advlib.h>
     64   1.1    dante #include <dev/ic/adv.h>
     65   1.3  thorpej 
     66   1.3  thorpej #ifndef DDB
     67   1.3  thorpej #define	Debugger()	panic("should call debugger here (adv.c)")
     68   1.3  thorpej #endif /* ! DDB */
     69   1.1    dante 
     70   1.6    dante 
     71   1.6    dante /* #define ASC_DEBUG */
     72   1.6    dante 
     73   1.1    dante /******************************************************************************/
     74   1.1    dante 
     75   1.1    dante 
     76  1.13  thorpej static int adv_alloc_control_data __P((ASC_SOFTC *));
     77   1.1    dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
     78   1.1    dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
     79   1.1    dante static void adv_reset_ccb __P((ADV_CCB *));
     80   1.1    dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
     81   1.1    dante static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
     82   1.1    dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
     83   1.1    dante static void adv_start_ccbs __P((ASC_SOFTC *));
     84   1.1    dante 
     85   1.1    dante 
     86   1.1    dante static int adv_scsi_cmd __P((struct scsipi_xfer *));
     87   1.1    dante static void advminphys __P((struct buf *));
     88   1.1    dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
     89   1.1    dante 
     90   1.1    dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
     91   1.1    dante static void adv_timeout __P((void *));
     92   1.1    dante static void adv_watchdog __P((void *));
     93   1.1    dante 
     94   1.1    dante 
     95   1.1    dante /******************************************************************************/
     96   1.1    dante 
     97   1.1    dante 
     98   1.1    dante /* the below structure is so we have a default dev struct for out link struct */
     99   1.1    dante struct scsipi_device adv_dev =
    100   1.1    dante {
    101   1.1    dante 	NULL,			/* Use default error handler */
    102   1.1    dante 	NULL,			/* have a queue, served by this */
    103   1.1    dante 	NULL,			/* have no async handler */
    104   1.1    dante 	NULL,			/* Use default 'done' routine */
    105   1.1    dante };
    106   1.1    dante 
    107   1.1    dante 
    108   1.1    dante #define ADV_ABORT_TIMEOUT       2000	/* time to wait for abort (mSec) */
    109   1.1    dante #define ADV_WATCH_TIMEOUT       1000	/* time to wait for watchdog (mSec) */
    110   1.1    dante 
    111   1.1    dante 
    112   1.1    dante /******************************************************************************/
    113   1.1    dante /*                             Control Blocks routines                        */
    114   1.1    dante /******************************************************************************/
    115   1.1    dante 
    116   1.1    dante 
    117   1.1    dante static int
    118  1.13  thorpej adv_alloc_control_data(sc)
    119   1.1    dante 	ASC_SOFTC      *sc;
    120   1.1    dante {
    121   1.1    dante 	bus_dma_segment_t seg;
    122   1.1    dante 	int             error, rseg;
    123   1.1    dante 
    124   1.1    dante 	/*
    125   1.1    dante          * Allocate the control blocks.
    126   1.1    dante          */
    127   1.1    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
    128   1.1    dante 			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    129   1.1    dante 		printf("%s: unable to allocate control structures,"
    130   1.1    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    131   1.1    dante 		return (error);
    132   1.1    dante 	}
    133   1.1    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    134   1.1    dante 		   sizeof(struct adv_control), (caddr_t *) & sc->sc_control,
    135   1.1    dante 				 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    136   1.1    dante 		printf("%s: unable to map control structures, error = %d\n",
    137   1.1    dante 		       sc->sc_dev.dv_xname, error);
    138   1.1    dante 		return (error);
    139   1.1    dante 	}
    140   1.1    dante 	/*
    141   1.1    dante          * Create and load the DMA map used for the control blocks.
    142   1.1    dante          */
    143   1.1    dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
    144   1.1    dante 			   1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
    145   1.1    dante 				       &sc->sc_dmamap_control)) != 0) {
    146   1.1    dante 		printf("%s: unable to create control DMA map, error = %d\n",
    147   1.1    dante 		       sc->sc_dev.dv_xname, error);
    148   1.1    dante 		return (error);
    149   1.1    dante 	}
    150   1.1    dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    151   1.1    dante 			   sc->sc_control, sizeof(struct adv_control), NULL,
    152   1.1    dante 				     BUS_DMA_NOWAIT)) != 0) {
    153   1.1    dante 		printf("%s: unable to load control DMA map, error = %d\n",
    154   1.1    dante 		       sc->sc_dev.dv_xname, error);
    155   1.1    dante 		return (error);
    156   1.1    dante 	}
    157  1.13  thorpej 
    158  1.13  thorpej 	/*
    159  1.13  thorpej 	 * Initialize the overrun_buf address.
    160  1.13  thorpej 	 */
    161  1.13  thorpej 	sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    162  1.13  thorpej 	    offsetof(struct adv_control, overrun_buf);
    163  1.13  thorpej 
    164   1.1    dante 	return (0);
    165   1.1    dante }
    166   1.1    dante 
    167   1.1    dante 
    168   1.1    dante /*
    169   1.1    dante  * Create a set of ccbs and add them to the free list.  Called once
    170   1.1    dante  * by adv_init().  We return the number of CCBs successfully created.
    171   1.1    dante  */
    172   1.1    dante static int
    173   1.1    dante adv_create_ccbs(sc, ccbstore, count)
    174   1.1    dante 	ASC_SOFTC      *sc;
    175   1.1    dante 	ADV_CCB        *ccbstore;
    176   1.1    dante 	int             count;
    177   1.1    dante {
    178   1.1    dante 	ADV_CCB        *ccb;
    179   1.1    dante 	int             i, error;
    180   1.1    dante 
    181   1.1    dante 	bzero(ccbstore, sizeof(ADV_CCB) * count);
    182   1.1    dante 	for (i = 0; i < count; i++) {
    183   1.1    dante 		ccb = &ccbstore[i];
    184   1.1    dante 		if ((error = adv_init_ccb(sc, ccb)) != 0) {
    185   1.1    dante 			printf("%s: unable to initialize ccb, error = %d\n",
    186   1.1    dante 			       sc->sc_dev.dv_xname, error);
    187   1.1    dante 			return (i);
    188   1.1    dante 		}
    189   1.1    dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    190   1.1    dante 	}
    191   1.1    dante 
    192   1.1    dante 	return (i);
    193   1.1    dante }
    194   1.1    dante 
    195   1.1    dante 
    196   1.1    dante /*
    197   1.1    dante  * A ccb is put onto the free list.
    198   1.1    dante  */
    199   1.1    dante static void
    200   1.1    dante adv_free_ccb(sc, ccb)
    201   1.1    dante 	ASC_SOFTC      *sc;
    202   1.1    dante 	ADV_CCB        *ccb;
    203   1.1    dante {
    204   1.1    dante 	int             s;
    205   1.1    dante 
    206   1.1    dante 	s = splbio();
    207   1.1    dante 
    208   1.1    dante 	adv_reset_ccb(ccb);
    209   1.1    dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    210   1.1    dante 
    211   1.1    dante 	/*
    212   1.1    dante          * If there were none, wake anybody waiting for one to come free,
    213   1.1    dante          * starting with queued entries.
    214   1.1    dante          */
    215   1.1    dante 	if (ccb->chain.tqe_next == 0)
    216   1.1    dante 		wakeup(&sc->sc_free_ccb);
    217   1.1    dante 
    218   1.1    dante 	splx(s);
    219   1.1    dante }
    220   1.1    dante 
    221   1.1    dante 
    222   1.1    dante static void
    223   1.1    dante adv_reset_ccb(ccb)
    224   1.1    dante 	ADV_CCB        *ccb;
    225   1.1    dante {
    226   1.1    dante 
    227   1.1    dante 	ccb->flags = 0;
    228   1.1    dante }
    229   1.1    dante 
    230   1.1    dante 
    231   1.1    dante static int
    232   1.1    dante adv_init_ccb(sc, ccb)
    233   1.1    dante 	ASC_SOFTC      *sc;
    234   1.1    dante 	ADV_CCB        *ccb;
    235   1.1    dante {
    236  1.10    dante 	int	hashnum, error;
    237   1.1    dante 
    238   1.1    dante 	/*
    239   1.1    dante          * Create the DMA map for this CCB.
    240   1.1    dante          */
    241   1.1    dante 	error = bus_dmamap_create(sc->sc_dmat,
    242   1.1    dante 				  (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
    243   1.1    dante 			 ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
    244   1.1    dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    245   1.1    dante 	if (error) {
    246   1.1    dante 		printf("%s: unable to create DMA map, error = %d\n",
    247   1.1    dante 		       sc->sc_dev.dv_xname, error);
    248   1.1    dante 		return (error);
    249   1.1    dante 	}
    250  1.10    dante 
    251  1.10    dante 	/*
    252  1.10    dante 	 * put in the phystokv hash table
    253  1.10    dante 	 * Never gets taken out.
    254  1.10    dante 	 */
    255  1.10    dante 	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    256  1.10    dante 	    ADV_CCB_OFF(ccb);
    257  1.10    dante 	hashnum = CCB_HASH(ccb->hashkey);
    258  1.10    dante 	ccb->nexthash = sc->sc_ccbhash[hashnum];
    259  1.10    dante 	sc->sc_ccbhash[hashnum] = ccb;
    260  1.10    dante 
    261   1.1    dante 	adv_reset_ccb(ccb);
    262   1.1    dante 	return (0);
    263   1.1    dante }
    264   1.1    dante 
    265   1.1    dante 
    266   1.1    dante /*
    267   1.1    dante  * Get a free ccb
    268   1.1    dante  *
    269   1.1    dante  * If there are none, see if we can allocate a new one
    270   1.1    dante  */
    271   1.1    dante static ADV_CCB *
    272   1.1    dante adv_get_ccb(sc, flags)
    273   1.1    dante 	ASC_SOFTC      *sc;
    274   1.1    dante 	int             flags;
    275   1.1    dante {
    276   1.1    dante 	ADV_CCB        *ccb = 0;
    277   1.1    dante 	int             s;
    278   1.1    dante 
    279   1.1    dante 	s = splbio();
    280   1.1    dante 
    281   1.1    dante 	/*
    282   1.1    dante          * If we can and have to, sleep waiting for one to come free
    283   1.1    dante          * but only if we can't allocate a new one.
    284   1.1    dante          */
    285   1.1    dante 	for (;;) {
    286   1.1    dante 		ccb = sc->sc_free_ccb.tqh_first;
    287   1.1    dante 		if (ccb) {
    288   1.1    dante 			TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    289   1.1    dante 			break;
    290   1.1    dante 		}
    291  1.14  thorpej 		if ((flags & XS_CTL_NOSLEEP) != 0)
    292   1.1    dante 			goto out;
    293   1.1    dante 
    294   1.1    dante 		tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
    295   1.1    dante 	}
    296   1.1    dante 
    297   1.1    dante 	ccb->flags |= CCB_ALLOC;
    298   1.1    dante 
    299   1.1    dante out:
    300   1.1    dante 	splx(s);
    301   1.1    dante 	return (ccb);
    302   1.1    dante }
    303   1.1    dante 
    304   1.1    dante 
    305   1.1    dante /*
    306  1.10    dante  * Given a physical address, find the ccb that it corresponds to.
    307  1.10    dante  */
    308  1.10    dante ADV_CCB *
    309  1.10    dante adv_ccb_phys_kv(sc, ccb_phys)
    310  1.10    dante 	ASC_SOFTC	*sc;
    311  1.10    dante 	u_long		ccb_phys;
    312  1.10    dante {
    313  1.10    dante 	int hashnum = CCB_HASH(ccb_phys);
    314  1.10    dante 	ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
    315  1.10    dante 
    316  1.10    dante 	while (ccb) {
    317  1.10    dante 		if (ccb->hashkey == ccb_phys)
    318  1.10    dante 			break;
    319  1.10    dante 		ccb = ccb->nexthash;
    320  1.10    dante 	}
    321  1.10    dante 	return (ccb);
    322  1.10    dante }
    323  1.10    dante 
    324  1.10    dante 
    325  1.10    dante /*
    326   1.1    dante  * Queue a CCB to be sent to the controller, and send it if possible.
    327   1.1    dante  */
    328   1.1    dante static void
    329   1.1    dante adv_queue_ccb(sc, ccb)
    330   1.1    dante 	ASC_SOFTC      *sc;
    331   1.1    dante 	ADV_CCB        *ccb;
    332   1.1    dante {
    333   1.1    dante 
    334   1.1    dante 	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    335   1.1    dante 
    336   1.1    dante 	adv_start_ccbs(sc);
    337   1.1    dante }
    338   1.1    dante 
    339   1.1    dante 
    340   1.1    dante static void
    341   1.1    dante adv_start_ccbs(sc)
    342   1.1    dante 	ASC_SOFTC      *sc;
    343   1.1    dante {
    344   1.1    dante 	ADV_CCB        *ccb;
    345   1.1    dante 
    346   1.1    dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    347   1.1    dante 		if (ccb->flags & CCB_WATCHDOG)
    348   1.1    dante 			untimeout(adv_watchdog, ccb);
    349   1.1    dante 
    350   1.1    dante 		if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
    351   1.1    dante 			ccb->flags |= CCB_WATCHDOG;
    352   1.1    dante 			timeout(adv_watchdog, ccb,
    353   1.1    dante 				(ADV_WATCH_TIMEOUT * hz) / 1000);
    354   1.1    dante 			break;
    355   1.1    dante 		}
    356   1.1    dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    357   1.1    dante 
    358  1.14  thorpej 		if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
    359   1.1    dante 			timeout(adv_timeout, ccb, (ccb->timeout * hz) / 1000);
    360   1.1    dante 	}
    361   1.1    dante }
    362   1.1    dante 
    363   1.1    dante 
    364   1.1    dante /******************************************************************************/
    365   1.1    dante /*                         SCSI layer interfacing routines                    */
    366   1.1    dante /******************************************************************************/
    367   1.1    dante 
    368   1.1    dante 
    369   1.1    dante int
    370   1.1    dante adv_init(sc)
    371   1.1    dante 	ASC_SOFTC      *sc;
    372   1.1    dante {
    373   1.1    dante 	int             warn;
    374   1.1    dante 
    375  1.12    dante 	if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
    376  1.12    dante 		printf("adv_init: failed to find signature\n");
    377  1.12    dante 		return (1);
    378  1.12    dante 	}
    379   1.1    dante 
    380   1.4    dante 	/*
    381   1.4    dante          * Read the board configuration
    382   1.4    dante          */
    383   1.4    dante 	AscInitASC_SOFTC(sc);
    384   1.4    dante 	warn = AscInitFromEEP(sc);
    385   1.4    dante 	if (warn) {
    386   1.4    dante 		printf("%s -get: ", sc->sc_dev.dv_xname);
    387   1.4    dante 		switch (warn) {
    388   1.4    dante 		case -1:
    389   1.4    dante 			printf("Chip is not halted\n");
    390   1.4    dante 			break;
    391   1.4    dante 
    392   1.4    dante 		case -2:
    393   1.4    dante 			printf("Couldn't get MicroCode Start"
    394   1.4    dante 			       " address\n");
    395   1.4    dante 			break;
    396   1.4    dante 
    397   1.4    dante 		case ASC_WARN_IO_PORT_ROTATE:
    398   1.4    dante 			printf("I/O port address modified\n");
    399   1.4    dante 			break;
    400   1.4    dante 
    401   1.4    dante 		case ASC_WARN_AUTO_CONFIG:
    402   1.4    dante 			printf("I/O port increment switch enabled\n");
    403   1.4    dante 			break;
    404   1.4    dante 
    405   1.4    dante 		case ASC_WARN_EEPROM_CHKSUM:
    406   1.4    dante 			printf("EEPROM checksum error\n");
    407   1.4    dante 			break;
    408   1.4    dante 
    409   1.4    dante 		case ASC_WARN_IRQ_MODIFIED:
    410   1.4    dante 			printf("IRQ modified\n");
    411   1.4    dante 			break;
    412   1.4    dante 
    413   1.4    dante 		case ASC_WARN_CMD_QNG_CONFLICT:
    414   1.4    dante 			printf("tag queuing enabled w/o disconnects\n");
    415   1.4    dante 			break;
    416   1.1    dante 
    417   1.4    dante 		default:
    418   1.4    dante 			printf("unknown warning %d\n", warn);
    419   1.1    dante 		}
    420   1.4    dante 	}
    421   1.4    dante 	if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
    422   1.4    dante 		sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
    423   1.4    dante 
    424   1.4    dante 	/*
    425   1.4    dante          * Modify the board configuration
    426   1.4    dante          */
    427   1.4    dante 	warn = AscInitFromASC_SOFTC(sc);
    428   1.4    dante 	if (warn) {
    429   1.4    dante 		printf("%s -set: ", sc->sc_dev.dv_xname);
    430   1.4    dante 		switch (warn) {
    431   1.4    dante 		case ASC_WARN_CMD_QNG_CONFLICT:
    432   1.4    dante 			printf("tag queuing enabled w/o disconnects\n");
    433   1.4    dante 			break;
    434   1.1    dante 
    435   1.4    dante 		case ASC_WARN_AUTO_CONFIG:
    436   1.4    dante 			printf("I/O port increment switch enabled\n");
    437   1.4    dante 			break;
    438   1.1    dante 
    439   1.4    dante 		default:
    440   1.4    dante 			printf("unknown warning %d\n", warn);
    441   1.1    dante 		}
    442   1.4    dante 	}
    443  1.11    dante 	sc->isr_callback = (ASC_CALLBACK) adv_narrow_isr_callback;
    444   1.1    dante 
    445   1.1    dante 	return (0);
    446   1.1    dante }
    447   1.1    dante 
    448   1.1    dante 
    449   1.1    dante void
    450   1.1    dante adv_attach(sc)
    451   1.1    dante 	ASC_SOFTC      *sc;
    452   1.1    dante {
    453   1.1    dante 	int             i, error;
    454   1.1    dante 
    455   1.4    dante 	/*
    456   1.4    dante          * Initialize board RISC chip and enable interrupts.
    457   1.4    dante          */
    458   1.4    dante 	switch (AscInitDriver(sc)) {
    459   1.4    dante 	case 0:
    460   1.4    dante 		/* AllOK */
    461   1.4    dante 		break;
    462   1.1    dante 
    463   1.4    dante 	case 1:
    464   1.4    dante 		panic("%s: bad signature", sc->sc_dev.dv_xname);
    465   1.4    dante 		break;
    466   1.1    dante 
    467   1.4    dante 	case 2:
    468   1.4    dante 		panic("%s: unable to load MicroCode",
    469   1.4    dante 		      sc->sc_dev.dv_xname);
    470   1.4    dante 		break;
    471   1.1    dante 
    472   1.4    dante 	case 3:
    473   1.4    dante 		panic("%s: unable to initialize MicroCode",
    474   1.4    dante 		      sc->sc_dev.dv_xname);
    475   1.4    dante 		break;
    476   1.1    dante 
    477   1.4    dante 	default:
    478   1.4    dante 		panic("%s: unable to initialize board RISC chip",
    479   1.4    dante 		      sc->sc_dev.dv_xname);
    480   1.1    dante 	}
    481   1.1    dante 
    482   1.7  thorpej 	/*
    483   1.7  thorpej 	 * Fill in the adapter.
    484   1.7  thorpej 	 */
    485   1.7  thorpej 	sc->sc_adapter.scsipi_cmd = adv_scsi_cmd;
    486   1.7  thorpej 	sc->sc_adapter.scsipi_minphys = advminphys;
    487   1.1    dante 
    488   1.1    dante 	/*
    489   1.1    dante          * fill in the prototype scsipi_link.
    490   1.1    dante          */
    491   1.1    dante 	sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
    492   1.1    dante 	sc->sc_link.adapter_softc = sc;
    493   1.1    dante 	sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
    494   1.7  thorpej 	sc->sc_link.adapter = &sc->sc_adapter;
    495   1.1    dante 	sc->sc_link.device = &adv_dev;
    496   1.1    dante 	sc->sc_link.openings = 4;
    497   1.4    dante 	sc->sc_link.scsipi_scsi.max_target = 7;
    498   1.8   mjacob 	sc->sc_link.scsipi_scsi.max_lun = 7;
    499   1.1    dante 	sc->sc_link.type = BUS_SCSI;
    500   1.1    dante 
    501   1.1    dante 
    502   1.1    dante 	TAILQ_INIT(&sc->sc_free_ccb);
    503   1.1    dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    504   1.9  thorpej 	TAILQ_INIT(&sc->sc_queue);
    505   1.1    dante 
    506   1.1    dante 
    507   1.1    dante 	/*
    508  1.13  thorpej          * Allocate the Control Blocks and the overrun buffer.
    509   1.1    dante          */
    510  1.13  thorpej 	error = adv_alloc_control_data(sc);
    511   1.1    dante 	if (error)
    512  1.12    dante 		return; /* (error) */
    513   1.1    dante 
    514   1.1    dante 	/*
    515   1.1    dante          * Create and initialize the Control Blocks.
    516   1.1    dante          */
    517   1.1    dante 	i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
    518   1.1    dante 	if (i == 0) {
    519   1.1    dante 		printf("%s: unable to create control blocks\n",
    520   1.1    dante 		       sc->sc_dev.dv_xname);
    521   1.1    dante 		return; /* (ENOMEM) */ ;
    522   1.1    dante 	} else if (i != ADV_MAX_CCB) {
    523   1.1    dante 		printf("%s: WARNING: only %d of %d control blocks created\n",
    524   1.1    dante 		       sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
    525   1.1    dante 	}
    526   1.1    dante 	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
    527   1.1    dante }
    528   1.1    dante 
    529   1.1    dante 
    530   1.1    dante static void
    531   1.1    dante advminphys(bp)
    532   1.1    dante 	struct buf     *bp;
    533   1.1    dante {
    534   1.1    dante 
    535   1.1    dante 	if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
    536   1.1    dante 		bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
    537   1.1    dante 	minphys(bp);
    538   1.1    dante }
    539   1.1    dante 
    540   1.1    dante 
    541   1.1    dante /*
    542   1.1    dante  * start a scsi operation given the command and the data address.  Also needs
    543   1.1    dante  * the unit, target and lu.
    544   1.1    dante  */
    545   1.1    dante static int
    546   1.1    dante adv_scsi_cmd(xs)
    547   1.1    dante 	struct scsipi_xfer *xs;
    548   1.1    dante {
    549   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    550   1.1    dante 	ASC_SOFTC      *sc = sc_link->adapter_softc;
    551   1.1    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    552   1.1    dante 	ADV_CCB        *ccb;
    553   1.1    dante 	int             s, flags, error, nsegs;
    554   1.1    dante 	int             fromqueue = 1, dontqueue = 0;
    555   1.1    dante 
    556   1.1    dante 
    557   1.1    dante 	s = splbio();		/* protect the queue */
    558   1.1    dante 
    559   1.1    dante 	/*
    560   1.1    dante          * If we're running the queue from adv_done(), we've been
    561   1.1    dante          * called with the first queue entry as our argument.
    562   1.1    dante          */
    563   1.9  thorpej 	if (xs == TAILQ_FIRST(&sc->sc_queue)) {
    564   1.9  thorpej 		TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    565   1.1    dante 		fromqueue = 1;
    566   1.1    dante 	} else {
    567   1.1    dante 
    568   1.1    dante 		/* Polled requests can't be queued for later. */
    569  1.14  thorpej 		dontqueue = xs->xs_control & XS_CTL_POLL;
    570   1.1    dante 
    571   1.1    dante 		/*
    572   1.1    dante                  * If there are jobs in the queue, run them first.
    573   1.1    dante                  */
    574   1.9  thorpej 		if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
    575   1.1    dante 			/*
    576   1.1    dante                          * If we can't queue, we have to abort, since
    577   1.1    dante                          * we have to preserve order.
    578   1.1    dante                          */
    579   1.1    dante 			if (dontqueue) {
    580   1.1    dante 				splx(s);
    581   1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    582   1.1    dante 				return (TRY_AGAIN_LATER);
    583   1.1    dante 			}
    584   1.1    dante 			/*
    585   1.1    dante                          * Swap with the first queue entry.
    586   1.1    dante                          */
    587   1.9  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    588   1.9  thorpej 			xs = TAILQ_FIRST(&sc->sc_queue);
    589   1.9  thorpej 			TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    590   1.1    dante 			fromqueue = 1;
    591   1.1    dante 		}
    592   1.1    dante 	}
    593   1.1    dante 
    594   1.1    dante 
    595   1.1    dante 	/*
    596   1.1    dante          * get a ccb to use. If the transfer
    597   1.1    dante          * is from a buf (possibly from interrupt time)
    598   1.1    dante          * then we can't allow it to sleep
    599   1.1    dante          */
    600   1.1    dante 
    601  1.14  thorpej 	flags = xs->xs_control;
    602   1.1    dante 	if ((ccb = adv_get_ccb(sc, flags)) == NULL) {
    603   1.1    dante 		/*
    604   1.1    dante                  * If we can't queue, we lose.
    605   1.1    dante                  */
    606   1.1    dante 		if (dontqueue) {
    607   1.1    dante 			splx(s);
    608   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    609   1.1    dante 			return (TRY_AGAIN_LATER);
    610   1.1    dante 		}
    611   1.1    dante 		/*
    612   1.1    dante                  * Stuff ourselves into the queue, in front
    613   1.1    dante                  * if we came off in the first place.
    614   1.1    dante                  */
    615   1.9  thorpej 		if (fromqueue)
    616   1.9  thorpej 			TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
    617   1.9  thorpej 		else
    618   1.9  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    619   1.1    dante 		splx(s);
    620   1.1    dante 		return (SUCCESSFULLY_QUEUED);
    621   1.1    dante 	}
    622   1.1    dante 	splx(s);		/* done playing with the queue */
    623   1.1    dante 
    624   1.1    dante 	ccb->xs = xs;
    625   1.1    dante 	ccb->timeout = xs->timeout;
    626   1.1    dante 
    627   1.1    dante 	/*
    628   1.1    dante          * Build up the request
    629   1.1    dante          */
    630   1.1    dante 	memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
    631   1.1    dante 
    632  1.10    dante 	ccb->scsiq.q2.ccb_ptr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    633  1.10    dante 		    ADV_CCB_OFF(ccb);
    634   1.1    dante 
    635   1.1    dante 	ccb->scsiq.cdbptr = &xs->cmd->opcode;
    636   1.1    dante 	ccb->scsiq.q2.cdb_len = xs->cmdlen;
    637   1.1    dante 	ccb->scsiq.q1.target_id = ASC_TID_TO_TARGET_ID(sc_link->scsipi_scsi.target);
    638   1.1    dante 	ccb->scsiq.q1.target_lun = sc_link->scsipi_scsi.lun;
    639   1.1    dante 	ccb->scsiq.q2.target_ix = ASC_TIDLUN_TO_IX(sc_link->scsipi_scsi.target,
    640   1.1    dante 						   sc_link->scsipi_scsi.lun);
    641   1.1    dante 	ccb->scsiq.q1.sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    642   1.1    dante 		ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
    643   1.1    dante 	ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
    644   1.1    dante 
    645   1.1    dante 	/*
    646   1.1    dante          * If  there  are  any  outstanding  requests  for  the  current target,
    647   1.1    dante          * then  every  255th request  send an  ORDERED request.  This heuristic
    648   1.1    dante          * tries  to  retain  the  benefit  of request  sorting while preventing
    649   1.1    dante          * request starvation. 255 is the max number of tags or pending commands
    650   1.1    dante          * a device may have outstanding.
    651   1.1    dante          */
    652   1.1    dante 	sc->reqcnt[sc_link->scsipi_scsi.target]++;
    653   1.1    dante 	if ((sc->reqcnt[sc_link->scsipi_scsi.target] > 0) &&
    654   1.1    dante 	    (sc->reqcnt[sc_link->scsipi_scsi.target] % 255) == 0) {
    655   1.1    dante 		ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
    656   1.1    dante 	} else {
    657   1.1    dante 		ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
    658   1.1    dante 	}
    659   1.1    dante 
    660   1.1    dante 
    661   1.1    dante 	if (xs->datalen) {
    662   1.1    dante 		/*
    663   1.1    dante                  * Map the DMA transfer.
    664   1.1    dante                  */
    665   1.1    dante #ifdef TFS
    666   1.1    dante 		if (flags & SCSI_DATA_UIO) {
    667   1.1    dante 			error = bus_dmamap_load_uio(dmat,
    668   1.1    dante 				  ccb->dmamap_xfer, (struct uio *) xs->data,
    669  1.14  thorpej 						    (flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    670   1.1    dante 		} else
    671   1.1    dante #endif				/* TFS */
    672   1.1    dante 		{
    673   1.1    dante 			error = bus_dmamap_load(dmat,
    674   1.1    dante 			      ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
    675  1.14  thorpej 						(flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    676   1.1    dante 		}
    677   1.1    dante 
    678   1.1    dante 		if (error) {
    679   1.1    dante 			if (error == EFBIG) {
    680   1.1    dante 				printf("%s: adv_scsi_cmd, more than %d dma"
    681   1.1    dante 				       " segments\n",
    682   1.1    dante 				       sc->sc_dev.dv_xname, ASC_MAX_SG_LIST);
    683   1.1    dante 			} else {
    684   1.1    dante 				printf("%s: adv_scsi_cmd, error %d loading"
    685   1.1    dante 				       " dma map\n",
    686   1.1    dante 				       sc->sc_dev.dv_xname, error);
    687   1.1    dante 			}
    688   1.1    dante 
    689   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    690   1.1    dante 			adv_free_ccb(sc, ccb);
    691   1.1    dante 			return (COMPLETE);
    692   1.1    dante 		}
    693   1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    694   1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    695  1.14  thorpej 			      (flags & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD :
    696   1.1    dante 				BUS_DMASYNC_PREWRITE);
    697   1.1    dante 
    698   1.1    dante 
    699   1.1    dante 		memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
    700   1.1    dante 
    701   1.1    dante 		for (nsegs = 0; nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
    702   1.1    dante 
    703   1.1    dante 			ccb->sghead.sg_list[nsegs].addr =
    704   1.1    dante 				ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
    705   1.1    dante 			ccb->sghead.sg_list[nsegs].bytes =
    706   1.1    dante 				ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
    707   1.1    dante 		}
    708   1.1    dante 
    709   1.1    dante 		ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
    710   1.1    dante 			ccb->dmamap_xfer->dm_nsegs;
    711   1.1    dante 
    712   1.1    dante 		ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
    713   1.1    dante 		ccb->scsiq.sg_head = &ccb->sghead;
    714   1.1    dante 		ccb->scsiq.q1.data_addr = 0;
    715   1.1    dante 		ccb->scsiq.q1.data_cnt = 0;
    716   1.1    dante 	} else {
    717   1.1    dante 		/*
    718   1.1    dante                  * No data xfer, use non S/G values.
    719   1.1    dante                  */
    720   1.1    dante 		ccb->scsiq.q1.data_addr = 0;
    721   1.1    dante 		ccb->scsiq.q1.data_cnt = 0;
    722   1.1    dante 	}
    723   1.1    dante 
    724   1.6    dante #ifdef ASC_DEBUG
    725   1.6    dante 	printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX \n",
    726   1.6    dante 			sc_link->scsipi_scsi.target,
    727   1.6    dante 			sc_link->scsipi_scsi.lun, xs->cmd->opcode,
    728   1.6    dante 			(unsigned long)ccb);
    729   1.6    dante #endif
    730   1.1    dante 	s = splbio();
    731   1.1    dante 	adv_queue_ccb(sc, ccb);
    732   1.1    dante 	splx(s);
    733   1.1    dante 
    734   1.1    dante 	/*
    735   1.1    dante          * Usually return SUCCESSFULLY QUEUED
    736   1.1    dante          */
    737  1.14  thorpej 	if ((flags & XS_CTL_POLL) == 0)
    738   1.1    dante 		return (SUCCESSFULLY_QUEUED);
    739   1.1    dante 
    740   1.1    dante 	/*
    741   1.1    dante          * If we can't use interrupts, poll on completion
    742   1.1    dante          */
    743   1.1    dante 	if (adv_poll(sc, xs, ccb->timeout)) {
    744   1.1    dante 		adv_timeout(ccb);
    745   1.1    dante 		if (adv_poll(sc, xs, ccb->timeout))
    746   1.1    dante 			adv_timeout(ccb);
    747   1.1    dante 	}
    748   1.1    dante 	return (COMPLETE);
    749   1.1    dante }
    750   1.1    dante 
    751   1.1    dante 
    752   1.1    dante int
    753   1.1    dante adv_intr(arg)
    754   1.1    dante 	void           *arg;
    755   1.1    dante {
    756   1.1    dante 	ASC_SOFTC      *sc = arg;
    757   1.1    dante 	struct scsipi_xfer *xs;
    758   1.1    dante 
    759   1.6    dante #ifdef ASC_DEBUG
    760   1.6    dante 	int int_pend = FALSE;
    761   1.6    dante 
    762   1.6    dante 	if(ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh))
    763   1.6    dante 	{
    764   1.6    dante 		int_pend = TRUE;
    765   1.6    dante 		printf("ISR - ");
    766   1.6    dante 	}
    767   1.6    dante #endif
    768   1.4    dante 	AscISR(sc);
    769   1.6    dante #ifdef ASC_DEBUG
    770   1.6    dante 	if(int_pend)
    771   1.6    dante 		printf("\n");
    772   1.6    dante #endif
    773   1.1    dante 
    774   1.1    dante 	/*
    775   1.1    dante          * If there are queue entries in the software queue, try to
    776   1.1    dante          * run the first one.  We should be more or less guaranteed
    777   1.1    dante          * to succeed, since we just freed a CCB.
    778   1.1    dante          *
    779   1.1    dante          * NOTE: adv_scsi_cmd() relies on our calling it with
    780   1.1    dante          * the first entry in the queue.
    781   1.1    dante          */
    782   1.9  thorpej 	if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
    783   1.1    dante 		(void) adv_scsi_cmd(xs);
    784   1.1    dante 
    785   1.1    dante 	return (1);
    786   1.1    dante }
    787   1.1    dante 
    788   1.1    dante 
    789   1.1    dante /*
    790   1.1    dante  * Poll a particular unit, looking for a particular xs
    791   1.1    dante  */
    792   1.1    dante static int
    793   1.1    dante adv_poll(sc, xs, count)
    794   1.1    dante 	ASC_SOFTC      *sc;
    795   1.1    dante 	struct scsipi_xfer *xs;
    796   1.1    dante 	int             count;
    797   1.1    dante {
    798   1.1    dante 
    799   1.1    dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
    800   1.1    dante 	while (count) {
    801   1.1    dante 		adv_intr(sc);
    802  1.14  thorpej 		if (xs->xs_status & XS_STS_DONE)
    803   1.1    dante 			return (0);
    804   1.1    dante 		delay(1000);	/* only happens in boot so ok */
    805   1.1    dante 		count--;
    806   1.1    dante 	}
    807   1.1    dante 	return (1);
    808   1.1    dante }
    809   1.1    dante 
    810   1.1    dante 
    811   1.1    dante static void
    812   1.1    dante adv_timeout(arg)
    813   1.1    dante 	void           *arg;
    814   1.1    dante {
    815   1.1    dante 	ADV_CCB        *ccb = arg;
    816   1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    817   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    818   1.1    dante 	ASC_SOFTC      *sc = sc_link->adapter_softc;
    819   1.1    dante 	int             s;
    820   1.1    dante 
    821   1.1    dante 	scsi_print_addr(sc_link);
    822   1.1    dante 	printf("timed out");
    823   1.1    dante 
    824   1.1    dante 	s = splbio();
    825   1.1    dante 
    826   1.1    dante 	/*
    827   1.1    dante          * If it has been through before, then a previous abort has failed,
    828   1.1    dante          * don't try abort again, reset the bus instead.
    829   1.1    dante          */
    830   1.1    dante 	if (ccb->flags & CCB_ABORT) {
    831   1.1    dante 		/* abort timed out */
    832   1.1    dante 		printf(" AGAIN. Resetting Bus\n");
    833   1.1    dante 		/* Lets try resetting the bus! */
    834   1.1    dante 		if (AscResetBus(sc) == ASC_ERROR) {
    835   1.1    dante 			ccb->timeout = sc->scsi_reset_wait;
    836   1.1    dante 			adv_queue_ccb(sc, ccb);
    837   1.1    dante 		}
    838   1.1    dante 	} else {
    839   1.1    dante 		/* abort the operation that has timed out */
    840   1.1    dante 		printf("\n");
    841  1.10    dante 		AscAbortCCB(sc, ccb);
    842   1.1    dante 		ccb->xs->error = XS_TIMEOUT;
    843   1.1    dante 		ccb->timeout = ADV_ABORT_TIMEOUT;
    844   1.1    dante 		ccb->flags |= CCB_ABORT;
    845   1.1    dante 		adv_queue_ccb(sc, ccb);
    846   1.1    dante 	}
    847   1.1    dante 
    848   1.1    dante 	splx(s);
    849   1.1    dante }
    850   1.1    dante 
    851   1.1    dante 
    852   1.1    dante static void
    853   1.1    dante adv_watchdog(arg)
    854   1.1    dante 	void           *arg;
    855   1.1    dante {
    856   1.1    dante 	ADV_CCB        *ccb = arg;
    857   1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    858   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    859   1.1    dante 	ASC_SOFTC      *sc = sc_link->adapter_softc;
    860   1.1    dante 	int             s;
    861   1.1    dante 
    862   1.1    dante 	s = splbio();
    863   1.1    dante 
    864   1.1    dante 	ccb->flags &= ~CCB_WATCHDOG;
    865   1.1    dante 	adv_start_ccbs(sc);
    866   1.1    dante 
    867   1.1    dante 	splx(s);
    868   1.1    dante }
    869   1.1    dante 
    870   1.1    dante 
    871   1.1    dante /******************************************************************************/
    872  1.10    dante /*                      NARROW boards Interrupt callbacks                     */
    873   1.1    dante /******************************************************************************/
    874   1.1    dante 
    875   1.1    dante 
    876   1.1    dante /*
    877   1.1    dante  * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
    878   1.1    dante  *
    879   1.1    dante  * Interrupt callback function for the Narrow SCSI Asc Library.
    880   1.1    dante  */
    881   1.1    dante static void
    882   1.1    dante adv_narrow_isr_callback(sc, qdonep)
    883   1.1    dante 	ASC_SOFTC      *sc;
    884   1.1    dante 	ASC_QDONE_INFO *qdonep;
    885   1.1    dante {
    886   1.1    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    887  1.10    dante 	ADV_CCB        *ccb;
    888  1.10    dante 	struct scsipi_xfer *xs;
    889   1.1    dante 	struct scsipi_sense_data *s1, *s2;
    890   1.1    dante 
    891  1.10    dante 
    892  1.10    dante 	ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
    893  1.10    dante 	xs = ccb->xs;
    894   1.1    dante 
    895   1.6    dante #ifdef ASC_DEBUG
    896   1.6    dante 	printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
    897   1.6    dante 			(unsigned long)ccb,
    898   1.6    dante 			xs->sc_link->scsipi_scsi.target,
    899   1.6    dante 			xs->sc_link->scsipi_scsi.lun, xs->cmd->opcode);
    900   1.6    dante #endif
    901   1.1    dante 	untimeout(adv_timeout, ccb);
    902   1.1    dante 
    903   1.1    dante 	/*
    904   1.1    dante          * If we were a data transfer, unload the map that described
    905   1.1    dante          * the data buffer.
    906   1.1    dante          */
    907   1.1    dante 	if (xs->datalen) {
    908   1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    909   1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    910  1.14  thorpej 			 (xs->xs_control & XS_CTL_DATA_IN) ?
    911  1.14  thorpej 			 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
    912   1.1    dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
    913   1.1    dante 	}
    914   1.1    dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
    915   1.1    dante 		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
    916   1.1    dante 		Debugger();
    917   1.1    dante 		return;
    918   1.1    dante 	}
    919   1.1    dante 	/*
    920   1.1    dante          * 'qdonep' contains the command's ending status.
    921   1.1    dante          */
    922   1.6    dante #ifdef ASC_DEBUG
    923   1.6    dante 	printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
    924   1.6    dante #endif
    925   1.1    dante 	switch (qdonep->d3.done_stat) {
    926   1.1    dante 	case ASC_QD_NO_ERROR:
    927   1.1    dante 		switch (qdonep->d3.host_stat) {
    928   1.1    dante 		case ASC_QHSTA_NO_ERROR:
    929   1.1    dante 			xs->error = XS_NOERROR;
    930   1.1    dante 			xs->resid = 0;
    931   1.1    dante 			break;
    932   1.1    dante 
    933   1.1    dante 		default:
    934   1.1    dante 			/* QHSTA error occurred */
    935   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    936   1.1    dante 			break;
    937   1.1    dante 		}
    938   1.1    dante 
    939   1.1    dante 		/*
    940   1.1    dante                  * If an INQUIRY command completed successfully, then call
    941   1.1    dante                  * the AscInquiryHandling() function to patch bugged boards.
    942   1.1    dante                  */
    943   1.1    dante 		if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
    944   1.1    dante 		    (xs->sc_link->scsipi_scsi.lun == 0) &&
    945   1.1    dante 		    (xs->datalen - qdonep->remain_bytes) >= 8) {
    946   1.1    dante 			AscInquiryHandling(sc,
    947   1.1    dante 				      xs->sc_link->scsipi_scsi.target & 0x7,
    948   1.1    dante 					   (ASC_SCSI_INQUIRY *) xs->data);
    949   1.1    dante 		}
    950   1.1    dante 		break;
    951   1.1    dante 
    952   1.1    dante 	case ASC_QD_WITH_ERROR:
    953   1.1    dante 		switch (qdonep->d3.host_stat) {
    954   1.1    dante 		case ASC_QHSTA_NO_ERROR:
    955   1.1    dante 			if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
    956   1.1    dante 				s1 = &ccb->scsi_sense;
    957   1.1    dante 				s2 = &xs->sense.scsi_sense;
    958   1.1    dante 				*s2 = *s1;
    959   1.1    dante 				xs->error = XS_SENSE;
    960   1.4    dante 			} else {
    961   1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    962   1.4    dante 			}
    963   1.1    dante 			break;
    964   1.1    dante 
    965   1.1    dante 		default:
    966   1.1    dante 			/* QHSTA error occurred */
    967   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    968   1.1    dante 			break;
    969   1.1    dante 		}
    970   1.1    dante 		break;
    971   1.1    dante 
    972   1.1    dante 	case ASC_QD_ABORTED_BY_HOST:
    973   1.1    dante 	default:
    974   1.1    dante 		xs->error = XS_DRIVER_STUFFUP;
    975   1.1    dante 		break;
    976   1.1    dante 	}
    977   1.1    dante 
    978   1.1    dante 
    979   1.1    dante 	adv_free_ccb(sc, ccb);
    980  1.14  thorpej 	xs->xs_status |= XS_STS_DONE;
    981   1.1    dante 	scsipi_done(xs);
    982   1.1    dante }
    983