adv.c revision 1.14.2.1 1 1.14.2.1 thorpej /* $NetBSD: adv.c,v 1.14.2.1 1999/10/19 17:47:28 thorpej Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.4 dante * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.4 dante * This product includes software developed by the NetBSD
22 1.4 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.1 dante #include <sys/kernel.h>
44 1.1 dante #include <sys/errno.h>
45 1.1 dante #include <sys/ioctl.h>
46 1.1 dante #include <sys/device.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/buf.h>
49 1.1 dante #include <sys/proc.h>
50 1.1 dante #include <sys/user.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <vm/vm.h>
56 1.1 dante #include <vm/vm_param.h>
57 1.1 dante #include <vm/pmap.h>
58 1.1 dante
59 1.1 dante #include <dev/scsipi/scsi_all.h>
60 1.1 dante #include <dev/scsipi/scsipi_all.h>
61 1.1 dante #include <dev/scsipi/scsiconf.h>
62 1.1 dante
63 1.10 dante #include <dev/ic/advlib.h>
64 1.1 dante #include <dev/ic/adv.h>
65 1.3 thorpej
66 1.3 thorpej #ifndef DDB
67 1.3 thorpej #define Debugger() panic("should call debugger here (adv.c)")
68 1.3 thorpej #endif /* ! DDB */
69 1.1 dante
70 1.6 dante
71 1.6 dante /* #define ASC_DEBUG */
72 1.6 dante
73 1.1 dante /******************************************************************************/
74 1.1 dante
75 1.1 dante
76 1.13 thorpej static int adv_alloc_control_data __P((ASC_SOFTC *));
77 1.1 dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
78 1.1 dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
79 1.1 dante static void adv_reset_ccb __P((ADV_CCB *));
80 1.1 dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
81 1.1 dante static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
82 1.1 dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
83 1.1 dante static void adv_start_ccbs __P((ASC_SOFTC *));
84 1.1 dante
85 1.1 dante
86 1.14.2.1 thorpej static void adv_scsipi_request __P((struct scsipi_channel *,
87 1.14.2.1 thorpej scsipi_adapter_req_t, void *));
88 1.1 dante static void advminphys __P((struct buf *));
89 1.1 dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
90 1.1 dante
91 1.1 dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
92 1.1 dante static void adv_timeout __P((void *));
93 1.1 dante static void adv_watchdog __P((void *));
94 1.1 dante
95 1.1 dante
96 1.1 dante /******************************************************************************/
97 1.1 dante
98 1.1 dante #define ADV_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
99 1.1 dante #define ADV_WATCH_TIMEOUT 1000 /* time to wait for watchdog (mSec) */
100 1.1 dante
101 1.1 dante /******************************************************************************/
102 1.1 dante /* Control Blocks routines */
103 1.1 dante /******************************************************************************/
104 1.1 dante
105 1.1 dante
106 1.1 dante static int
107 1.13 thorpej adv_alloc_control_data(sc)
108 1.1 dante ASC_SOFTC *sc;
109 1.1 dante {
110 1.1 dante bus_dma_segment_t seg;
111 1.1 dante int error, rseg;
112 1.1 dante
113 1.1 dante /*
114 1.1 dante * Allocate the control blocks.
115 1.1 dante */
116 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
117 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
118 1.1 dante printf("%s: unable to allocate control structures,"
119 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
120 1.1 dante return (error);
121 1.1 dante }
122 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
123 1.1 dante sizeof(struct adv_control), (caddr_t *) & sc->sc_control,
124 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
125 1.1 dante printf("%s: unable to map control structures, error = %d\n",
126 1.1 dante sc->sc_dev.dv_xname, error);
127 1.1 dante return (error);
128 1.1 dante }
129 1.1 dante /*
130 1.1 dante * Create and load the DMA map used for the control blocks.
131 1.1 dante */
132 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
133 1.1 dante 1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
134 1.1 dante &sc->sc_dmamap_control)) != 0) {
135 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
136 1.1 dante sc->sc_dev.dv_xname, error);
137 1.1 dante return (error);
138 1.1 dante }
139 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
140 1.1 dante sc->sc_control, sizeof(struct adv_control), NULL,
141 1.1 dante BUS_DMA_NOWAIT)) != 0) {
142 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
143 1.1 dante sc->sc_dev.dv_xname, error);
144 1.1 dante return (error);
145 1.1 dante }
146 1.13 thorpej
147 1.13 thorpej /*
148 1.13 thorpej * Initialize the overrun_buf address.
149 1.13 thorpej */
150 1.13 thorpej sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
151 1.13 thorpej offsetof(struct adv_control, overrun_buf);
152 1.13 thorpej
153 1.1 dante return (0);
154 1.1 dante }
155 1.1 dante
156 1.1 dante
157 1.1 dante /*
158 1.1 dante * Create a set of ccbs and add them to the free list. Called once
159 1.1 dante * by adv_init(). We return the number of CCBs successfully created.
160 1.1 dante */
161 1.1 dante static int
162 1.1 dante adv_create_ccbs(sc, ccbstore, count)
163 1.1 dante ASC_SOFTC *sc;
164 1.1 dante ADV_CCB *ccbstore;
165 1.1 dante int count;
166 1.1 dante {
167 1.1 dante ADV_CCB *ccb;
168 1.1 dante int i, error;
169 1.1 dante
170 1.1 dante bzero(ccbstore, sizeof(ADV_CCB) * count);
171 1.1 dante for (i = 0; i < count; i++) {
172 1.1 dante ccb = &ccbstore[i];
173 1.1 dante if ((error = adv_init_ccb(sc, ccb)) != 0) {
174 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
175 1.1 dante sc->sc_dev.dv_xname, error);
176 1.1 dante return (i);
177 1.1 dante }
178 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
179 1.1 dante }
180 1.1 dante
181 1.1 dante return (i);
182 1.1 dante }
183 1.1 dante
184 1.1 dante
185 1.1 dante /*
186 1.1 dante * A ccb is put onto the free list.
187 1.1 dante */
188 1.1 dante static void
189 1.1 dante adv_free_ccb(sc, ccb)
190 1.1 dante ASC_SOFTC *sc;
191 1.1 dante ADV_CCB *ccb;
192 1.1 dante {
193 1.1 dante int s;
194 1.1 dante
195 1.1 dante s = splbio();
196 1.1 dante
197 1.1 dante adv_reset_ccb(ccb);
198 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
199 1.1 dante
200 1.1 dante /*
201 1.1 dante * If there were none, wake anybody waiting for one to come free,
202 1.1 dante * starting with queued entries.
203 1.1 dante */
204 1.1 dante if (ccb->chain.tqe_next == 0)
205 1.1 dante wakeup(&sc->sc_free_ccb);
206 1.1 dante
207 1.1 dante splx(s);
208 1.1 dante }
209 1.1 dante
210 1.1 dante
211 1.1 dante static void
212 1.1 dante adv_reset_ccb(ccb)
213 1.1 dante ADV_CCB *ccb;
214 1.1 dante {
215 1.1 dante
216 1.1 dante ccb->flags = 0;
217 1.1 dante }
218 1.1 dante
219 1.1 dante
220 1.1 dante static int
221 1.1 dante adv_init_ccb(sc, ccb)
222 1.1 dante ASC_SOFTC *sc;
223 1.1 dante ADV_CCB *ccb;
224 1.1 dante {
225 1.10 dante int hashnum, error;
226 1.1 dante
227 1.1 dante /*
228 1.1 dante * Create the DMA map for this CCB.
229 1.1 dante */
230 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
231 1.1 dante (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
232 1.1 dante ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
233 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
234 1.1 dante if (error) {
235 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
236 1.1 dante sc->sc_dev.dv_xname, error);
237 1.1 dante return (error);
238 1.1 dante }
239 1.10 dante
240 1.10 dante /*
241 1.10 dante * put in the phystokv hash table
242 1.10 dante * Never gets taken out.
243 1.10 dante */
244 1.10 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
245 1.10 dante ADV_CCB_OFF(ccb);
246 1.10 dante hashnum = CCB_HASH(ccb->hashkey);
247 1.10 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
248 1.10 dante sc->sc_ccbhash[hashnum] = ccb;
249 1.10 dante
250 1.1 dante adv_reset_ccb(ccb);
251 1.1 dante return (0);
252 1.1 dante }
253 1.1 dante
254 1.1 dante
255 1.1 dante /*
256 1.1 dante * Get a free ccb
257 1.1 dante *
258 1.1 dante * If there are none, see if we can allocate a new one
259 1.1 dante */
260 1.1 dante static ADV_CCB *
261 1.1 dante adv_get_ccb(sc, flags)
262 1.1 dante ASC_SOFTC *sc;
263 1.1 dante int flags;
264 1.1 dante {
265 1.1 dante ADV_CCB *ccb = 0;
266 1.1 dante int s;
267 1.1 dante
268 1.1 dante s = splbio();
269 1.1 dante
270 1.1 dante /*
271 1.1 dante * If we can and have to, sleep waiting for one to come free
272 1.1 dante * but only if we can't allocate a new one.
273 1.1 dante */
274 1.1 dante for (;;) {
275 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
276 1.1 dante if (ccb) {
277 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
278 1.1 dante break;
279 1.1 dante }
280 1.14 thorpej if ((flags & XS_CTL_NOSLEEP) != 0)
281 1.1 dante goto out;
282 1.1 dante
283 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
284 1.1 dante }
285 1.1 dante
286 1.1 dante ccb->flags |= CCB_ALLOC;
287 1.1 dante
288 1.1 dante out:
289 1.1 dante splx(s);
290 1.1 dante return (ccb);
291 1.1 dante }
292 1.1 dante
293 1.1 dante
294 1.1 dante /*
295 1.10 dante * Given a physical address, find the ccb that it corresponds to.
296 1.10 dante */
297 1.10 dante ADV_CCB *
298 1.10 dante adv_ccb_phys_kv(sc, ccb_phys)
299 1.10 dante ASC_SOFTC *sc;
300 1.10 dante u_long ccb_phys;
301 1.10 dante {
302 1.10 dante int hashnum = CCB_HASH(ccb_phys);
303 1.10 dante ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
304 1.10 dante
305 1.10 dante while (ccb) {
306 1.10 dante if (ccb->hashkey == ccb_phys)
307 1.10 dante break;
308 1.10 dante ccb = ccb->nexthash;
309 1.10 dante }
310 1.10 dante return (ccb);
311 1.10 dante }
312 1.10 dante
313 1.10 dante
314 1.10 dante /*
315 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
316 1.1 dante */
317 1.1 dante static void
318 1.1 dante adv_queue_ccb(sc, ccb)
319 1.1 dante ASC_SOFTC *sc;
320 1.1 dante ADV_CCB *ccb;
321 1.1 dante {
322 1.1 dante
323 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
324 1.1 dante
325 1.1 dante adv_start_ccbs(sc);
326 1.1 dante }
327 1.1 dante
328 1.1 dante
329 1.1 dante static void
330 1.1 dante adv_start_ccbs(sc)
331 1.1 dante ASC_SOFTC *sc;
332 1.1 dante {
333 1.1 dante ADV_CCB *ccb;
334 1.1 dante
335 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
336 1.1 dante if (ccb->flags & CCB_WATCHDOG)
337 1.1 dante untimeout(adv_watchdog, ccb);
338 1.1 dante
339 1.1 dante if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
340 1.1 dante ccb->flags |= CCB_WATCHDOG;
341 1.1 dante timeout(adv_watchdog, ccb,
342 1.1 dante (ADV_WATCH_TIMEOUT * hz) / 1000);
343 1.1 dante break;
344 1.1 dante }
345 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
346 1.1 dante
347 1.14 thorpej if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
348 1.1 dante timeout(adv_timeout, ccb, (ccb->timeout * hz) / 1000);
349 1.1 dante }
350 1.1 dante }
351 1.1 dante
352 1.1 dante
353 1.1 dante /******************************************************************************/
354 1.1 dante /* SCSI layer interfacing routines */
355 1.1 dante /******************************************************************************/
356 1.1 dante
357 1.1 dante
358 1.1 dante int
359 1.1 dante adv_init(sc)
360 1.1 dante ASC_SOFTC *sc;
361 1.1 dante {
362 1.1 dante int warn;
363 1.1 dante
364 1.12 dante if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
365 1.12 dante printf("adv_init: failed to find signature\n");
366 1.12 dante return (1);
367 1.12 dante }
368 1.1 dante
369 1.4 dante /*
370 1.4 dante * Read the board configuration
371 1.4 dante */
372 1.4 dante AscInitASC_SOFTC(sc);
373 1.4 dante warn = AscInitFromEEP(sc);
374 1.4 dante if (warn) {
375 1.4 dante printf("%s -get: ", sc->sc_dev.dv_xname);
376 1.4 dante switch (warn) {
377 1.4 dante case -1:
378 1.4 dante printf("Chip is not halted\n");
379 1.4 dante break;
380 1.4 dante
381 1.4 dante case -2:
382 1.4 dante printf("Couldn't get MicroCode Start"
383 1.4 dante " address\n");
384 1.4 dante break;
385 1.4 dante
386 1.4 dante case ASC_WARN_IO_PORT_ROTATE:
387 1.4 dante printf("I/O port address modified\n");
388 1.4 dante break;
389 1.4 dante
390 1.4 dante case ASC_WARN_AUTO_CONFIG:
391 1.4 dante printf("I/O port increment switch enabled\n");
392 1.4 dante break;
393 1.4 dante
394 1.4 dante case ASC_WARN_EEPROM_CHKSUM:
395 1.4 dante printf("EEPROM checksum error\n");
396 1.4 dante break;
397 1.4 dante
398 1.4 dante case ASC_WARN_IRQ_MODIFIED:
399 1.4 dante printf("IRQ modified\n");
400 1.4 dante break;
401 1.4 dante
402 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
403 1.4 dante printf("tag queuing enabled w/o disconnects\n");
404 1.4 dante break;
405 1.1 dante
406 1.4 dante default:
407 1.4 dante printf("unknown warning %d\n", warn);
408 1.1 dante }
409 1.4 dante }
410 1.4 dante if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
411 1.4 dante sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
412 1.4 dante
413 1.4 dante /*
414 1.4 dante * Modify the board configuration
415 1.4 dante */
416 1.4 dante warn = AscInitFromASC_SOFTC(sc);
417 1.4 dante if (warn) {
418 1.4 dante printf("%s -set: ", sc->sc_dev.dv_xname);
419 1.4 dante switch (warn) {
420 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
421 1.4 dante printf("tag queuing enabled w/o disconnects\n");
422 1.4 dante break;
423 1.1 dante
424 1.4 dante case ASC_WARN_AUTO_CONFIG:
425 1.4 dante printf("I/O port increment switch enabled\n");
426 1.4 dante break;
427 1.1 dante
428 1.4 dante default:
429 1.4 dante printf("unknown warning %d\n", warn);
430 1.1 dante }
431 1.4 dante }
432 1.11 dante sc->isr_callback = (ASC_CALLBACK) adv_narrow_isr_callback;
433 1.1 dante
434 1.1 dante return (0);
435 1.1 dante }
436 1.1 dante
437 1.1 dante
438 1.1 dante void
439 1.1 dante adv_attach(sc)
440 1.1 dante ASC_SOFTC *sc;
441 1.1 dante {
442 1.14.2.1 thorpej struct scsipi_adapter *adapt = &sc->sc_adapter;
443 1.14.2.1 thorpej struct scsipi_channel *chan = &sc->sc_channel;
444 1.1 dante int i, error;
445 1.1 dante
446 1.4 dante /*
447 1.4 dante * Initialize board RISC chip and enable interrupts.
448 1.4 dante */
449 1.4 dante switch (AscInitDriver(sc)) {
450 1.4 dante case 0:
451 1.4 dante /* AllOK */
452 1.4 dante break;
453 1.1 dante
454 1.4 dante case 1:
455 1.4 dante panic("%s: bad signature", sc->sc_dev.dv_xname);
456 1.4 dante break;
457 1.1 dante
458 1.4 dante case 2:
459 1.4 dante panic("%s: unable to load MicroCode",
460 1.4 dante sc->sc_dev.dv_xname);
461 1.4 dante break;
462 1.1 dante
463 1.4 dante case 3:
464 1.4 dante panic("%s: unable to initialize MicroCode",
465 1.4 dante sc->sc_dev.dv_xname);
466 1.4 dante break;
467 1.1 dante
468 1.4 dante default:
469 1.4 dante panic("%s: unable to initialize board RISC chip",
470 1.4 dante sc->sc_dev.dv_xname);
471 1.1 dante }
472 1.1 dante
473 1.7 thorpej /*
474 1.14.2.1 thorpej * Fill in the scsipi_adapter.
475 1.7 thorpej */
476 1.14.2.1 thorpej memset(adapt, 0, sizeof(*adapt));
477 1.14.2.1 thorpej adapt->adapt_dev = &sc->sc_dev;
478 1.14.2.1 thorpej adapt->adapt_nchannels = 1;
479 1.14.2.1 thorpej /* adapt_openings initialized below */
480 1.14.2.1 thorpej /* adapt_max_periph initialized below */
481 1.14.2.1 thorpej adapt->adapt_request = adv_scsipi_request;
482 1.14.2.1 thorpej adapt->adapt_minphys = advminphys;
483 1.1 dante
484 1.1 dante /*
485 1.14.2.1 thorpej * Fill in the scsipi_channel.
486 1.14.2.1 thorpej */
487 1.14.2.1 thorpej memset(chan, 0, sizeof(*chan));
488 1.14.2.1 thorpej chan->chan_adapter = adapt;
489 1.14.2.1 thorpej chan->chan_bustype = &scsi_bustype;
490 1.14.2.1 thorpej chan->chan_channel = 0;
491 1.14.2.1 thorpej chan->chan_ntargets = 8;
492 1.14.2.1 thorpej chan->chan_nluns = 8;
493 1.14.2.1 thorpej chan->chan_id = sc->chip_scsi_id;
494 1.1 dante
495 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
496 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
497 1.1 dante
498 1.1 dante /*
499 1.13 thorpej * Allocate the Control Blocks and the overrun buffer.
500 1.1 dante */
501 1.13 thorpej error = adv_alloc_control_data(sc);
502 1.1 dante if (error)
503 1.12 dante return; /* (error) */
504 1.1 dante
505 1.1 dante /*
506 1.1 dante * Create and initialize the Control Blocks.
507 1.1 dante */
508 1.1 dante i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
509 1.1 dante if (i == 0) {
510 1.1 dante printf("%s: unable to create control blocks\n",
511 1.1 dante sc->sc_dev.dv_xname);
512 1.1 dante return; /* (ENOMEM) */ ;
513 1.1 dante } else if (i != ADV_MAX_CCB) {
514 1.1 dante printf("%s: WARNING: only %d of %d control blocks created\n",
515 1.1 dante sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
516 1.1 dante }
517 1.14.2.1 thorpej
518 1.14.2.1 thorpej adapt->adapt_openings = i;
519 1.14.2.1 thorpej adapt->adapt_max_periph = adapt->adapt_openings;
520 1.14.2.1 thorpej
521 1.14.2.1 thorpej config_found(&sc->sc_dev, chan, scsiprint);
522 1.1 dante }
523 1.1 dante
524 1.1 dante
525 1.1 dante static void
526 1.1 dante advminphys(bp)
527 1.1 dante struct buf *bp;
528 1.1 dante {
529 1.1 dante
530 1.1 dante if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
531 1.1 dante bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
532 1.1 dante minphys(bp);
533 1.1 dante }
534 1.1 dante
535 1.1 dante
536 1.1 dante /*
537 1.1 dante * start a scsi operation given the command and the data address. Also needs
538 1.1 dante * the unit, target and lu.
539 1.1 dante */
540 1.14.2.1 thorpej static void
541 1.14.2.1 thorpej adv_scsipi_request(chan, req, arg)
542 1.14.2.1 thorpej struct scsipi_channel *chan;
543 1.14.2.1 thorpej scsipi_adapter_req_t req;
544 1.14.2.1 thorpej void *arg;
545 1.1 dante {
546 1.14.2.1 thorpej struct scsipi_xfer *xs;
547 1.14.2.1 thorpej struct scsipi_periph *periph;
548 1.14.2.1 thorpej ASC_SOFTC *sc = (void *)chan->chan_adapter->adapt_dev;
549 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
550 1.1 dante ADV_CCB *ccb;
551 1.1 dante int s, flags, error, nsegs;
552 1.1 dante
553 1.14.2.1 thorpej switch (req) {
554 1.14.2.1 thorpej case ADAPTER_REQ_RUN_XFER:
555 1.14.2.1 thorpej xs = arg;
556 1.14.2.1 thorpej periph = xs->xs_periph;
557 1.14.2.1 thorpej flags = xs->xs_control;
558 1.1 dante
559 1.1 dante /*
560 1.14.2.1 thorpej * Get a CCB to use.
561 1.14.2.1 thorpej */
562 1.14.2.1 thorpej ccb = adv_get_ccb(sc, flags);
563 1.14.2.1 thorpej #ifdef DIAGNOSTIC
564 1.1 dante /*
565 1.14.2.1 thorpej * This should never happen as we track the resources
566 1.14.2.1 thorpej * in the mid-layer.
567 1.14.2.1 thorpej */
568 1.14.2.1 thorpej if (ccb == NULL) {
569 1.14.2.1 thorpej scsipi_printaddr(periph);
570 1.14.2.1 thorpej printf("unable to allocate ccb\n");
571 1.14.2.1 thorpej panic("adv_scsipi_request");
572 1.1 dante }
573 1.14.2.1 thorpej #endif
574 1.1 dante
575 1.14.2.1 thorpej ccb->xs = xs;
576 1.14.2.1 thorpej ccb->timeout = xs->timeout;
577 1.1 dante
578 1.14.2.1 thorpej /*
579 1.14.2.1 thorpej * Build up the request
580 1.14.2.1 thorpej */
581 1.14.2.1 thorpej memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
582 1.1 dante
583 1.14.2.1 thorpej ccb->scsiq.q2.ccb_ptr =
584 1.14.2.1 thorpej sc->sc_dmamap_control->dm_segs[0].ds_addr +
585 1.10 dante ADV_CCB_OFF(ccb);
586 1.1 dante
587 1.14.2.1 thorpej ccb->scsiq.cdbptr = &xs->cmd->opcode;
588 1.14.2.1 thorpej ccb->scsiq.q2.cdb_len = xs->cmdlen;
589 1.14.2.1 thorpej ccb->scsiq.q1.target_id =
590 1.14.2.1 thorpej ASC_TID_TO_TARGET_ID(periph->periph_target);
591 1.14.2.1 thorpej ccb->scsiq.q1.target_lun = periph->periph_lun;
592 1.14.2.1 thorpej ccb->scsiq.q2.target_ix =
593 1.14.2.1 thorpej ASC_TIDLUN_TO_IX(periph->periph_target,
594 1.14.2.1 thorpej periph->periph_lun);
595 1.14.2.1 thorpej ccb->scsiq.q1.sense_addr =
596 1.14.2.1 thorpej sc->sc_dmamap_control->dm_segs[0].ds_addr +
597 1.14.2.1 thorpej ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
598 1.14.2.1 thorpej ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
599 1.1 dante
600 1.1 dante /*
601 1.14.2.1 thorpej * If there are any outstanding requests for the current
602 1.14.2.1 thorpej * target, then every 255th request send an ORDERED request.
603 1.14.2.1 thorpej * This heuristic tries to retain the benefit of request
604 1.14.2.1 thorpej * sorting while preventing request starvation. 255 is the
605 1.14.2.1 thorpej * max number of tags or pending commands a device may have
606 1.14.2.1 thorpej * outstanding.
607 1.14.2.1 thorpej */
608 1.14.2.1 thorpej sc->reqcnt[periph->periph_target]++;
609 1.14.2.1 thorpej if ((sc->reqcnt[periph->periph_target] > 0) &&
610 1.14.2.1 thorpej (sc->reqcnt[periph->periph_target] % 255) == 0) {
611 1.14.2.1 thorpej ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
612 1.14.2.1 thorpej } else {
613 1.14.2.1 thorpej ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
614 1.14.2.1 thorpej }
615 1.14.2.1 thorpej
616 1.14.2.1 thorpej if (xs->datalen) {
617 1.14.2.1 thorpej /*
618 1.14.2.1 thorpej * Map the DMA transfer.
619 1.14.2.1 thorpej */
620 1.1 dante #ifdef TFS
621 1.14.2.1 thorpej if (flags & SCSI_DATA_UIO) {
622 1.14.2.1 thorpej error = bus_dmamap_load_uio(dmat,
623 1.14.2.1 thorpej ccb->dmamap_xfer, (struct uio *) xs->data,
624 1.14.2.1 thorpej (flags & XS_CTL_NOSLEEP) ?
625 1.14.2.1 thorpej BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
626 1.14.2.1 thorpej } else
627 1.14.2.1 thorpej #endif /* TFS */
628 1.14.2.1 thorpej {
629 1.14.2.1 thorpej error = bus_dmamap_load(dmat, ccb->dmamap_xfer,
630 1.14.2.1 thorpej xs->data, xs->datalen, NULL,
631 1.14.2.1 thorpej (flags & XS_CTL_NOSLEEP) ?
632 1.14.2.1 thorpej BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
633 1.1 dante }
634 1.1 dante
635 1.14.2.1 thorpej if (error) {
636 1.14.2.1 thorpej if (error == EFBIG) {
637 1.14.2.1 thorpej printf("%s: adv_scsipi_request, "
638 1.14.2.1 thorpej "more than %d dma segments\n",
639 1.14.2.1 thorpej sc->sc_dev.dv_xname,
640 1.14.2.1 thorpej ASC_MAX_SG_LIST);
641 1.14.2.1 thorpej } else {
642 1.14.2.1 thorpej printf("%s: adv_scsipi_request, "
643 1.14.2.1 thorpej "error %d loading dma map\n",
644 1.14.2.1 thorpej sc->sc_dev.dv_xname, error);
645 1.14.2.1 thorpej }
646 1.1 dante
647 1.14.2.1 thorpej adv_free_ccb(sc, ccb);
648 1.14.2.1 thorpej xs->error = XS_DRIVER_STUFFUP;
649 1.14.2.1 thorpej scsipi_done(xs);
650 1.14.2.1 thorpej return;
651 1.14.2.1 thorpej }
652 1.14.2.1 thorpej bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
653 1.14.2.1 thorpej ccb->dmamap_xfer->dm_mapsize,
654 1.14.2.1 thorpej (flags & XS_CTL_DATA_IN) ?
655 1.14.2.1 thorpej BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
656 1.14.2.1 thorpej
657 1.14.2.1 thorpej memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
658 1.14.2.1 thorpej
659 1.14.2.1 thorpej for (nsegs = 0;
660 1.14.2.1 thorpej nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
661 1.14.2.1 thorpej ccb->sghead.sg_list[nsegs].addr =
662 1.14.2.1 thorpej ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
663 1.14.2.1 thorpej ccb->sghead.sg_list[nsegs].bytes =
664 1.14.2.1 thorpej ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
665 1.14.2.1 thorpej }
666 1.1 dante
667 1.14.2.1 thorpej ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
668 1.14.2.1 thorpej ccb->dmamap_xfer->dm_nsegs;
669 1.1 dante
670 1.14.2.1 thorpej ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
671 1.14.2.1 thorpej ccb->scsiq.sg_head = &ccb->sghead;
672 1.14.2.1 thorpej ccb->scsiq.q1.data_addr = 0;
673 1.14.2.1 thorpej ccb->scsiq.q1.data_cnt = 0;
674 1.14.2.1 thorpej } else {
675 1.14.2.1 thorpej /*
676 1.14.2.1 thorpej * No data xfer, use non S/G values.
677 1.14.2.1 thorpej */
678 1.14.2.1 thorpej ccb->scsiq.q1.data_addr = 0;
679 1.14.2.1 thorpej ccb->scsiq.q1.data_cnt = 0;
680 1.1 dante }
681 1.1 dante
682 1.6 dante #ifdef ASC_DEBUG
683 1.14.2.1 thorpej printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX \n",
684 1.14.2.1 thorpej periph->periph_target,
685 1.14.2.1 thorpej periph->periph_lun, xs->cmd->opcode,
686 1.14.2.1 thorpej (unsigned long)ccb);
687 1.6 dante #endif
688 1.14.2.1 thorpej s = splbio();
689 1.14.2.1 thorpej adv_queue_ccb(sc, ccb);
690 1.14.2.1 thorpej splx(s);
691 1.1 dante
692 1.14.2.1 thorpej if ((flags & XS_CTL_POLL) == 0)
693 1.14.2.1 thorpej return;
694 1.1 dante
695 1.14.2.1 thorpej /* Not allowed to use interrupts, poll for completion. */
696 1.14.2.1 thorpej if (adv_poll(sc, xs, ccb->timeout)) {
697 1.1 dante adv_timeout(ccb);
698 1.14.2.1 thorpej if (adv_poll(sc, xs, ccb->timeout))
699 1.14.2.1 thorpej adv_timeout(ccb);
700 1.14.2.1 thorpej }
701 1.14.2.1 thorpej return;
702 1.14.2.1 thorpej
703 1.14.2.1 thorpej case ADAPTER_REQ_GROW_RESOURCES:
704 1.14.2.1 thorpej /* XXX Not supported. */
705 1.14.2.1 thorpej return;
706 1.14.2.1 thorpej
707 1.14.2.1 thorpej case ADAPTER_REQ_SET_XFER_MODE:
708 1.14.2.1 thorpej /* XXX XXX XXX */
709 1.14.2.1 thorpej return;
710 1.14.2.1 thorpej
711 1.14.2.1 thorpej case ADAPTER_REQ_GET_XFER_MODE:
712 1.14.2.1 thorpej {
713 1.14.2.1 thorpej u_int8_t sdtr_data;
714 1.14.2.1 thorpej ASC_SCSI_BIT_ID_TYPE tid_bit;
715 1.14.2.1 thorpej
716 1.14.2.1 thorpej periph = arg;
717 1.14.2.1 thorpej tid_bit = ASC_TIX_TO_TARGET_ID(periph->periph_target);
718 1.14.2.1 thorpej
719 1.14.2.1 thorpej periph->periph_mode = 0;
720 1.14.2.1 thorpej periph->periph_period = 0;
721 1.14.2.1 thorpej periph->periph_offset = 0;
722 1.14.2.1 thorpej
723 1.14.2.1 thorpej if (sc->init_sdtr & tid_bit) {
724 1.14.2.1 thorpej periph->periph_mode |= PERIPH_CAP_SYNC;
725 1.14.2.1 thorpej sdtr_data = sc->sdtr_data[periph->periph_target];
726 1.14.2.1 thorpej periph->periph_period =
727 1.14.2.1 thorpej sc->sdtr_period_tbl[(sdtr_data >> 4) &
728 1.14.2.1 thorpej (sc->max_sdtr_index - 1)];
729 1.14.2.1 thorpej periph->periph_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
730 1.14.2.1 thorpej }
731 1.14.2.1 thorpej
732 1.14.2.1 thorpej if (sc->use_tagged_qng & tid_bit)
733 1.14.2.1 thorpej periph->periph_mode |= PERIPH_CAP_TQING;
734 1.14.2.1 thorpej
735 1.14.2.1 thorpej periph->periph_flags |= PERIPH_MODE_VALID;
736 1.14.2.1 thorpej return;
737 1.14.2.1 thorpej }
738 1.1 dante }
739 1.1 dante }
740 1.1 dante
741 1.1 dante int
742 1.1 dante adv_intr(arg)
743 1.1 dante void *arg;
744 1.1 dante {
745 1.1 dante ASC_SOFTC *sc = arg;
746 1.1 dante
747 1.6 dante #ifdef ASC_DEBUG
748 1.6 dante int int_pend = FALSE;
749 1.6 dante
750 1.6 dante if(ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh))
751 1.6 dante {
752 1.6 dante int_pend = TRUE;
753 1.6 dante printf("ISR - ");
754 1.6 dante }
755 1.6 dante #endif
756 1.4 dante AscISR(sc);
757 1.6 dante #ifdef ASC_DEBUG
758 1.6 dante if(int_pend)
759 1.6 dante printf("\n");
760 1.6 dante #endif
761 1.1 dante
762 1.1 dante return (1);
763 1.1 dante }
764 1.1 dante
765 1.1 dante
766 1.1 dante /*
767 1.1 dante * Poll a particular unit, looking for a particular xs
768 1.1 dante */
769 1.1 dante static int
770 1.1 dante adv_poll(sc, xs, count)
771 1.1 dante ASC_SOFTC *sc;
772 1.1 dante struct scsipi_xfer *xs;
773 1.1 dante int count;
774 1.1 dante {
775 1.1 dante
776 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
777 1.1 dante while (count) {
778 1.1 dante adv_intr(sc);
779 1.14 thorpej if (xs->xs_status & XS_STS_DONE)
780 1.1 dante return (0);
781 1.1 dante delay(1000); /* only happens in boot so ok */
782 1.1 dante count--;
783 1.1 dante }
784 1.1 dante return (1);
785 1.1 dante }
786 1.1 dante
787 1.1 dante
788 1.1 dante static void
789 1.1 dante adv_timeout(arg)
790 1.1 dante void *arg;
791 1.1 dante {
792 1.1 dante ADV_CCB *ccb = arg;
793 1.1 dante struct scsipi_xfer *xs = ccb->xs;
794 1.14.2.1 thorpej struct scsipi_periph *periph = xs->xs_periph;
795 1.14.2.1 thorpej ASC_SOFTC *sc =
796 1.14.2.1 thorpej (void *)periph->periph_channel->chan_adapter->adapt_dev;
797 1.1 dante int s;
798 1.1 dante
799 1.14.2.1 thorpej scsipi_printaddr(periph);
800 1.1 dante printf("timed out");
801 1.1 dante
802 1.1 dante s = splbio();
803 1.1 dante
804 1.1 dante /*
805 1.1 dante * If it has been through before, then a previous abort has failed,
806 1.1 dante * don't try abort again, reset the bus instead.
807 1.1 dante */
808 1.1 dante if (ccb->flags & CCB_ABORT) {
809 1.1 dante /* abort timed out */
810 1.1 dante printf(" AGAIN. Resetting Bus\n");
811 1.1 dante /* Lets try resetting the bus! */
812 1.1 dante if (AscResetBus(sc) == ASC_ERROR) {
813 1.1 dante ccb->timeout = sc->scsi_reset_wait;
814 1.1 dante adv_queue_ccb(sc, ccb);
815 1.1 dante }
816 1.1 dante } else {
817 1.1 dante /* abort the operation that has timed out */
818 1.1 dante printf("\n");
819 1.10 dante AscAbortCCB(sc, ccb);
820 1.1 dante ccb->xs->error = XS_TIMEOUT;
821 1.1 dante ccb->timeout = ADV_ABORT_TIMEOUT;
822 1.1 dante ccb->flags |= CCB_ABORT;
823 1.1 dante adv_queue_ccb(sc, ccb);
824 1.1 dante }
825 1.1 dante
826 1.1 dante splx(s);
827 1.1 dante }
828 1.1 dante
829 1.1 dante
830 1.1 dante static void
831 1.1 dante adv_watchdog(arg)
832 1.1 dante void *arg;
833 1.1 dante {
834 1.1 dante ADV_CCB *ccb = arg;
835 1.1 dante struct scsipi_xfer *xs = ccb->xs;
836 1.14.2.1 thorpej struct scsipi_periph *periph = xs->xs_periph;
837 1.14.2.1 thorpej ASC_SOFTC *sc =
838 1.14.2.1 thorpej (void *)periph->periph_channel->chan_adapter->adapt_dev;
839 1.1 dante int s;
840 1.1 dante
841 1.1 dante s = splbio();
842 1.1 dante
843 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
844 1.1 dante adv_start_ccbs(sc);
845 1.1 dante
846 1.1 dante splx(s);
847 1.1 dante }
848 1.1 dante
849 1.1 dante
850 1.1 dante /******************************************************************************/
851 1.10 dante /* NARROW boards Interrupt callbacks */
852 1.1 dante /******************************************************************************/
853 1.1 dante
854 1.1 dante
855 1.1 dante /*
856 1.1 dante * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
857 1.1 dante *
858 1.1 dante * Interrupt callback function for the Narrow SCSI Asc Library.
859 1.1 dante */
860 1.1 dante static void
861 1.1 dante adv_narrow_isr_callback(sc, qdonep)
862 1.1 dante ASC_SOFTC *sc;
863 1.1 dante ASC_QDONE_INFO *qdonep;
864 1.1 dante {
865 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
866 1.10 dante ADV_CCB *ccb;
867 1.10 dante struct scsipi_xfer *xs;
868 1.1 dante struct scsipi_sense_data *s1, *s2;
869 1.1 dante
870 1.10 dante
871 1.10 dante ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
872 1.10 dante xs = ccb->xs;
873 1.1 dante
874 1.6 dante #ifdef ASC_DEBUG
875 1.6 dante printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
876 1.6 dante (unsigned long)ccb,
877 1.14.2.1 thorpej xs->xs_periph->periph_target,
878 1.14.2.1 thorpej xs->xs_periph->periph_lun, xs->cmd->opcode);
879 1.6 dante #endif
880 1.1 dante untimeout(adv_timeout, ccb);
881 1.1 dante
882 1.1 dante /*
883 1.1 dante * If we were a data transfer, unload the map that described
884 1.1 dante * the data buffer.
885 1.1 dante */
886 1.1 dante if (xs->datalen) {
887 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
888 1.1 dante ccb->dmamap_xfer->dm_mapsize,
889 1.14 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
890 1.14 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
891 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
892 1.1 dante }
893 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
894 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
895 1.1 dante Debugger();
896 1.1 dante return;
897 1.1 dante }
898 1.1 dante /*
899 1.1 dante * 'qdonep' contains the command's ending status.
900 1.1 dante */
901 1.6 dante #ifdef ASC_DEBUG
902 1.6 dante printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
903 1.6 dante #endif
904 1.1 dante switch (qdonep->d3.done_stat) {
905 1.1 dante case ASC_QD_NO_ERROR:
906 1.1 dante switch (qdonep->d3.host_stat) {
907 1.1 dante case ASC_QHSTA_NO_ERROR:
908 1.1 dante xs->error = XS_NOERROR;
909 1.1 dante xs->resid = 0;
910 1.1 dante break;
911 1.1 dante
912 1.1 dante default:
913 1.1 dante /* QHSTA error occurred */
914 1.1 dante xs->error = XS_DRIVER_STUFFUP;
915 1.1 dante break;
916 1.1 dante }
917 1.1 dante
918 1.1 dante /*
919 1.1 dante * If an INQUIRY command completed successfully, then call
920 1.1 dante * the AscInquiryHandling() function to patch bugged boards.
921 1.1 dante */
922 1.1 dante if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
923 1.14.2.1 thorpej (xs->xs_periph->periph_lun == 0) &&
924 1.1 dante (xs->datalen - qdonep->remain_bytes) >= 8) {
925 1.1 dante AscInquiryHandling(sc,
926 1.14.2.1 thorpej xs->xs_periph->periph_target & 0x7,
927 1.1 dante (ASC_SCSI_INQUIRY *) xs->data);
928 1.1 dante }
929 1.1 dante break;
930 1.1 dante
931 1.1 dante case ASC_QD_WITH_ERROR:
932 1.1 dante switch (qdonep->d3.host_stat) {
933 1.1 dante case ASC_QHSTA_NO_ERROR:
934 1.1 dante if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
935 1.1 dante s1 = &ccb->scsi_sense;
936 1.1 dante s2 = &xs->sense.scsi_sense;
937 1.1 dante *s2 = *s1;
938 1.1 dante xs->error = XS_SENSE;
939 1.4 dante } else {
940 1.1 dante xs->error = XS_DRIVER_STUFFUP;
941 1.4 dante }
942 1.1 dante break;
943 1.1 dante
944 1.1 dante default:
945 1.1 dante /* QHSTA error occurred */
946 1.1 dante xs->error = XS_DRIVER_STUFFUP;
947 1.1 dante break;
948 1.1 dante }
949 1.1 dante break;
950 1.1 dante
951 1.1 dante case ASC_QD_ABORTED_BY_HOST:
952 1.1 dante default:
953 1.1 dante xs->error = XS_DRIVER_STUFFUP;
954 1.1 dante break;
955 1.1 dante }
956 1.1 dante
957 1.1 dante
958 1.1 dante adv_free_ccb(sc, ccb);
959 1.14 thorpej xs->xs_status |= XS_STS_DONE;
960 1.1 dante scsipi_done(xs);
961 1.1 dante }
962