adv.c revision 1.18 1 1.18 mrg /* $NetBSD: adv.c,v 1.18 2000/06/28 17:12:48 mrg Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.4 dante * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.4 dante * This product includes software developed by the NetBSD
22 1.4 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.16 thorpej #include <sys/callout.h>
44 1.1 dante #include <sys/kernel.h>
45 1.1 dante #include <sys/errno.h>
46 1.1 dante #include <sys/ioctl.h>
47 1.1 dante #include <sys/device.h>
48 1.1 dante #include <sys/malloc.h>
49 1.1 dante #include <sys/buf.h>
50 1.1 dante #include <sys/proc.h>
51 1.1 dante #include <sys/user.h>
52 1.1 dante
53 1.1 dante #include <machine/bus.h>
54 1.1 dante #include <machine/intr.h>
55 1.1 dante
56 1.18 mrg #include <uvm/uvm_extern.h>
57 1.1 dante
58 1.1 dante #include <dev/scsipi/scsi_all.h>
59 1.1 dante #include <dev/scsipi/scsipi_all.h>
60 1.1 dante #include <dev/scsipi/scsiconf.h>
61 1.1 dante
62 1.10 dante #include <dev/ic/advlib.h>
63 1.1 dante #include <dev/ic/adv.h>
64 1.3 thorpej
65 1.3 thorpej #ifndef DDB
66 1.3 thorpej #define Debugger() panic("should call debugger here (adv.c)")
67 1.3 thorpej #endif /* ! DDB */
68 1.1 dante
69 1.6 dante
70 1.6 dante /* #define ASC_DEBUG */
71 1.6 dante
72 1.1 dante /******************************************************************************/
73 1.1 dante
74 1.1 dante
75 1.13 thorpej static int adv_alloc_control_data __P((ASC_SOFTC *));
76 1.1 dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
77 1.1 dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
78 1.1 dante static void adv_reset_ccb __P((ADV_CCB *));
79 1.1 dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
80 1.1 dante static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
81 1.1 dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
82 1.1 dante static void adv_start_ccbs __P((ASC_SOFTC *));
83 1.1 dante
84 1.1 dante
85 1.1 dante static int adv_scsi_cmd __P((struct scsipi_xfer *));
86 1.1 dante static void advminphys __P((struct buf *));
87 1.1 dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
88 1.1 dante
89 1.1 dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
90 1.1 dante static void adv_timeout __P((void *));
91 1.1 dante static void adv_watchdog __P((void *));
92 1.1 dante
93 1.1 dante
94 1.1 dante /******************************************************************************/
95 1.1 dante
96 1.1 dante
97 1.1 dante /* the below structure is so we have a default dev struct for out link struct */
98 1.1 dante struct scsipi_device adv_dev =
99 1.1 dante {
100 1.1 dante NULL, /* Use default error handler */
101 1.1 dante NULL, /* have a queue, served by this */
102 1.1 dante NULL, /* have no async handler */
103 1.1 dante NULL, /* Use default 'done' routine */
104 1.1 dante };
105 1.1 dante
106 1.1 dante
107 1.1 dante #define ADV_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
108 1.1 dante #define ADV_WATCH_TIMEOUT 1000 /* time to wait for watchdog (mSec) */
109 1.1 dante
110 1.1 dante
111 1.1 dante /******************************************************************************/
112 1.1 dante /* Control Blocks routines */
113 1.1 dante /******************************************************************************/
114 1.1 dante
115 1.1 dante
116 1.1 dante static int
117 1.13 thorpej adv_alloc_control_data(sc)
118 1.1 dante ASC_SOFTC *sc;
119 1.1 dante {
120 1.1 dante bus_dma_segment_t seg;
121 1.1 dante int error, rseg;
122 1.1 dante
123 1.1 dante /*
124 1.1 dante * Allocate the control blocks.
125 1.1 dante */
126 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
127 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
128 1.1 dante printf("%s: unable to allocate control structures,"
129 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
130 1.1 dante return (error);
131 1.1 dante }
132 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
133 1.1 dante sizeof(struct adv_control), (caddr_t *) & sc->sc_control,
134 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
135 1.1 dante printf("%s: unable to map control structures, error = %d\n",
136 1.1 dante sc->sc_dev.dv_xname, error);
137 1.1 dante return (error);
138 1.1 dante }
139 1.1 dante /*
140 1.1 dante * Create and load the DMA map used for the control blocks.
141 1.1 dante */
142 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
143 1.1 dante 1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
144 1.1 dante &sc->sc_dmamap_control)) != 0) {
145 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
146 1.1 dante sc->sc_dev.dv_xname, error);
147 1.1 dante return (error);
148 1.1 dante }
149 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
150 1.1 dante sc->sc_control, sizeof(struct adv_control), NULL,
151 1.1 dante BUS_DMA_NOWAIT)) != 0) {
152 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
153 1.1 dante sc->sc_dev.dv_xname, error);
154 1.1 dante return (error);
155 1.1 dante }
156 1.13 thorpej
157 1.13 thorpej /*
158 1.13 thorpej * Initialize the overrun_buf address.
159 1.13 thorpej */
160 1.13 thorpej sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
161 1.13 thorpej offsetof(struct adv_control, overrun_buf);
162 1.13 thorpej
163 1.1 dante return (0);
164 1.1 dante }
165 1.1 dante
166 1.1 dante
167 1.1 dante /*
168 1.1 dante * Create a set of ccbs and add them to the free list. Called once
169 1.1 dante * by adv_init(). We return the number of CCBs successfully created.
170 1.1 dante */
171 1.1 dante static int
172 1.1 dante adv_create_ccbs(sc, ccbstore, count)
173 1.1 dante ASC_SOFTC *sc;
174 1.1 dante ADV_CCB *ccbstore;
175 1.1 dante int count;
176 1.1 dante {
177 1.1 dante ADV_CCB *ccb;
178 1.1 dante int i, error;
179 1.1 dante
180 1.1 dante bzero(ccbstore, sizeof(ADV_CCB) * count);
181 1.1 dante for (i = 0; i < count; i++) {
182 1.1 dante ccb = &ccbstore[i];
183 1.1 dante if ((error = adv_init_ccb(sc, ccb)) != 0) {
184 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
185 1.1 dante sc->sc_dev.dv_xname, error);
186 1.1 dante return (i);
187 1.1 dante }
188 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
189 1.1 dante }
190 1.1 dante
191 1.1 dante return (i);
192 1.1 dante }
193 1.1 dante
194 1.1 dante
195 1.1 dante /*
196 1.1 dante * A ccb is put onto the free list.
197 1.1 dante */
198 1.1 dante static void
199 1.1 dante adv_free_ccb(sc, ccb)
200 1.1 dante ASC_SOFTC *sc;
201 1.1 dante ADV_CCB *ccb;
202 1.1 dante {
203 1.1 dante int s;
204 1.1 dante
205 1.1 dante s = splbio();
206 1.1 dante
207 1.1 dante adv_reset_ccb(ccb);
208 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
209 1.1 dante
210 1.1 dante /*
211 1.1 dante * If there were none, wake anybody waiting for one to come free,
212 1.1 dante * starting with queued entries.
213 1.1 dante */
214 1.1 dante if (ccb->chain.tqe_next == 0)
215 1.1 dante wakeup(&sc->sc_free_ccb);
216 1.1 dante
217 1.1 dante splx(s);
218 1.1 dante }
219 1.1 dante
220 1.1 dante
221 1.1 dante static void
222 1.1 dante adv_reset_ccb(ccb)
223 1.1 dante ADV_CCB *ccb;
224 1.1 dante {
225 1.1 dante
226 1.1 dante ccb->flags = 0;
227 1.1 dante }
228 1.1 dante
229 1.1 dante
230 1.1 dante static int
231 1.1 dante adv_init_ccb(sc, ccb)
232 1.1 dante ASC_SOFTC *sc;
233 1.1 dante ADV_CCB *ccb;
234 1.1 dante {
235 1.10 dante int hashnum, error;
236 1.1 dante
237 1.16 thorpej callout_init(&ccb->ccb_watchdog);
238 1.16 thorpej
239 1.1 dante /*
240 1.1 dante * Create the DMA map for this CCB.
241 1.1 dante */
242 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
243 1.1 dante (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
244 1.1 dante ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
245 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
246 1.1 dante if (error) {
247 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
248 1.1 dante sc->sc_dev.dv_xname, error);
249 1.1 dante return (error);
250 1.1 dante }
251 1.10 dante
252 1.10 dante /*
253 1.10 dante * put in the phystokv hash table
254 1.10 dante * Never gets taken out.
255 1.10 dante */
256 1.10 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
257 1.10 dante ADV_CCB_OFF(ccb);
258 1.10 dante hashnum = CCB_HASH(ccb->hashkey);
259 1.10 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
260 1.10 dante sc->sc_ccbhash[hashnum] = ccb;
261 1.10 dante
262 1.1 dante adv_reset_ccb(ccb);
263 1.1 dante return (0);
264 1.1 dante }
265 1.1 dante
266 1.1 dante
267 1.1 dante /*
268 1.1 dante * Get a free ccb
269 1.1 dante *
270 1.1 dante * If there are none, see if we can allocate a new one
271 1.1 dante */
272 1.1 dante static ADV_CCB *
273 1.1 dante adv_get_ccb(sc, flags)
274 1.1 dante ASC_SOFTC *sc;
275 1.1 dante int flags;
276 1.1 dante {
277 1.1 dante ADV_CCB *ccb = 0;
278 1.1 dante int s;
279 1.1 dante
280 1.1 dante s = splbio();
281 1.1 dante
282 1.1 dante /*
283 1.1 dante * If we can and have to, sleep waiting for one to come free
284 1.1 dante * but only if we can't allocate a new one.
285 1.1 dante */
286 1.1 dante for (;;) {
287 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
288 1.1 dante if (ccb) {
289 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
290 1.1 dante break;
291 1.1 dante }
292 1.14 thorpej if ((flags & XS_CTL_NOSLEEP) != 0)
293 1.1 dante goto out;
294 1.1 dante
295 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
296 1.1 dante }
297 1.1 dante
298 1.1 dante ccb->flags |= CCB_ALLOC;
299 1.1 dante
300 1.1 dante out:
301 1.1 dante splx(s);
302 1.1 dante return (ccb);
303 1.1 dante }
304 1.1 dante
305 1.1 dante
306 1.1 dante /*
307 1.10 dante * Given a physical address, find the ccb that it corresponds to.
308 1.10 dante */
309 1.10 dante ADV_CCB *
310 1.10 dante adv_ccb_phys_kv(sc, ccb_phys)
311 1.10 dante ASC_SOFTC *sc;
312 1.10 dante u_long ccb_phys;
313 1.10 dante {
314 1.10 dante int hashnum = CCB_HASH(ccb_phys);
315 1.10 dante ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
316 1.10 dante
317 1.10 dante while (ccb) {
318 1.10 dante if (ccb->hashkey == ccb_phys)
319 1.10 dante break;
320 1.10 dante ccb = ccb->nexthash;
321 1.10 dante }
322 1.10 dante return (ccb);
323 1.10 dante }
324 1.10 dante
325 1.10 dante
326 1.10 dante /*
327 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
328 1.1 dante */
329 1.1 dante static void
330 1.1 dante adv_queue_ccb(sc, ccb)
331 1.1 dante ASC_SOFTC *sc;
332 1.1 dante ADV_CCB *ccb;
333 1.1 dante {
334 1.1 dante
335 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
336 1.1 dante
337 1.1 dante adv_start_ccbs(sc);
338 1.1 dante }
339 1.1 dante
340 1.1 dante
341 1.1 dante static void
342 1.1 dante adv_start_ccbs(sc)
343 1.1 dante ASC_SOFTC *sc;
344 1.1 dante {
345 1.1 dante ADV_CCB *ccb;
346 1.1 dante
347 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
348 1.1 dante if (ccb->flags & CCB_WATCHDOG)
349 1.16 thorpej callout_stop(&ccb->ccb_watchdog);
350 1.1 dante
351 1.1 dante if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
352 1.1 dante ccb->flags |= CCB_WATCHDOG;
353 1.16 thorpej callout_reset(&ccb->ccb_watchdog,
354 1.16 thorpej (ADV_WATCH_TIMEOUT * hz) / 1000,
355 1.16 thorpej adv_watchdog, ccb);
356 1.1 dante break;
357 1.1 dante }
358 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
359 1.1 dante
360 1.14 thorpej if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
361 1.16 thorpej callout_reset(&ccb->xs->xs_callout,
362 1.16 thorpej (ccb->timeout * hz) / 1000,
363 1.16 thorpej adv_timeout, ccb);
364 1.1 dante }
365 1.1 dante }
366 1.1 dante
367 1.1 dante
368 1.1 dante /******************************************************************************/
369 1.1 dante /* SCSI layer interfacing routines */
370 1.1 dante /******************************************************************************/
371 1.1 dante
372 1.1 dante
373 1.1 dante int
374 1.1 dante adv_init(sc)
375 1.1 dante ASC_SOFTC *sc;
376 1.1 dante {
377 1.1 dante int warn;
378 1.1 dante
379 1.12 dante if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
380 1.12 dante printf("adv_init: failed to find signature\n");
381 1.12 dante return (1);
382 1.12 dante }
383 1.1 dante
384 1.4 dante /*
385 1.4 dante * Read the board configuration
386 1.4 dante */
387 1.4 dante AscInitASC_SOFTC(sc);
388 1.4 dante warn = AscInitFromEEP(sc);
389 1.4 dante if (warn) {
390 1.4 dante printf("%s -get: ", sc->sc_dev.dv_xname);
391 1.4 dante switch (warn) {
392 1.4 dante case -1:
393 1.4 dante printf("Chip is not halted\n");
394 1.4 dante break;
395 1.4 dante
396 1.4 dante case -2:
397 1.4 dante printf("Couldn't get MicroCode Start"
398 1.4 dante " address\n");
399 1.4 dante break;
400 1.4 dante
401 1.4 dante case ASC_WARN_IO_PORT_ROTATE:
402 1.4 dante printf("I/O port address modified\n");
403 1.4 dante break;
404 1.4 dante
405 1.4 dante case ASC_WARN_AUTO_CONFIG:
406 1.4 dante printf("I/O port increment switch enabled\n");
407 1.4 dante break;
408 1.4 dante
409 1.4 dante case ASC_WARN_EEPROM_CHKSUM:
410 1.4 dante printf("EEPROM checksum error\n");
411 1.4 dante break;
412 1.4 dante
413 1.4 dante case ASC_WARN_IRQ_MODIFIED:
414 1.4 dante printf("IRQ modified\n");
415 1.4 dante break;
416 1.4 dante
417 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
418 1.4 dante printf("tag queuing enabled w/o disconnects\n");
419 1.4 dante break;
420 1.1 dante
421 1.4 dante default:
422 1.4 dante printf("unknown warning %d\n", warn);
423 1.1 dante }
424 1.4 dante }
425 1.4 dante if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
426 1.4 dante sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
427 1.4 dante
428 1.4 dante /*
429 1.4 dante * Modify the board configuration
430 1.4 dante */
431 1.4 dante warn = AscInitFromASC_SOFTC(sc);
432 1.4 dante if (warn) {
433 1.4 dante printf("%s -set: ", sc->sc_dev.dv_xname);
434 1.4 dante switch (warn) {
435 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
436 1.4 dante printf("tag queuing enabled w/o disconnects\n");
437 1.4 dante break;
438 1.1 dante
439 1.4 dante case ASC_WARN_AUTO_CONFIG:
440 1.4 dante printf("I/O port increment switch enabled\n");
441 1.4 dante break;
442 1.1 dante
443 1.4 dante default:
444 1.4 dante printf("unknown warning %d\n", warn);
445 1.1 dante }
446 1.4 dante }
447 1.11 dante sc->isr_callback = (ASC_CALLBACK) adv_narrow_isr_callback;
448 1.1 dante
449 1.1 dante return (0);
450 1.1 dante }
451 1.1 dante
452 1.1 dante
453 1.1 dante void
454 1.1 dante adv_attach(sc)
455 1.1 dante ASC_SOFTC *sc;
456 1.1 dante {
457 1.1 dante int i, error;
458 1.1 dante
459 1.4 dante /*
460 1.4 dante * Initialize board RISC chip and enable interrupts.
461 1.4 dante */
462 1.4 dante switch (AscInitDriver(sc)) {
463 1.4 dante case 0:
464 1.4 dante /* AllOK */
465 1.4 dante break;
466 1.1 dante
467 1.4 dante case 1:
468 1.4 dante panic("%s: bad signature", sc->sc_dev.dv_xname);
469 1.4 dante break;
470 1.1 dante
471 1.4 dante case 2:
472 1.4 dante panic("%s: unable to load MicroCode",
473 1.4 dante sc->sc_dev.dv_xname);
474 1.4 dante break;
475 1.1 dante
476 1.4 dante case 3:
477 1.4 dante panic("%s: unable to initialize MicroCode",
478 1.4 dante sc->sc_dev.dv_xname);
479 1.4 dante break;
480 1.1 dante
481 1.4 dante default:
482 1.4 dante panic("%s: unable to initialize board RISC chip",
483 1.4 dante sc->sc_dev.dv_xname);
484 1.1 dante }
485 1.1 dante
486 1.7 thorpej /*
487 1.7 thorpej * Fill in the adapter.
488 1.7 thorpej */
489 1.7 thorpej sc->sc_adapter.scsipi_cmd = adv_scsi_cmd;
490 1.7 thorpej sc->sc_adapter.scsipi_minphys = advminphys;
491 1.1 dante
492 1.1 dante /*
493 1.1 dante * fill in the prototype scsipi_link.
494 1.1 dante */
495 1.1 dante sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
496 1.1 dante sc->sc_link.adapter_softc = sc;
497 1.1 dante sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
498 1.7 thorpej sc->sc_link.adapter = &sc->sc_adapter;
499 1.1 dante sc->sc_link.device = &adv_dev;
500 1.1 dante sc->sc_link.openings = 4;
501 1.4 dante sc->sc_link.scsipi_scsi.max_target = 7;
502 1.8 mjacob sc->sc_link.scsipi_scsi.max_lun = 7;
503 1.1 dante sc->sc_link.type = BUS_SCSI;
504 1.1 dante
505 1.1 dante
506 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
507 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
508 1.9 thorpej TAILQ_INIT(&sc->sc_queue);
509 1.1 dante
510 1.1 dante
511 1.1 dante /*
512 1.13 thorpej * Allocate the Control Blocks and the overrun buffer.
513 1.1 dante */
514 1.13 thorpej error = adv_alloc_control_data(sc);
515 1.1 dante if (error)
516 1.12 dante return; /* (error) */
517 1.1 dante
518 1.1 dante /*
519 1.1 dante * Create and initialize the Control Blocks.
520 1.1 dante */
521 1.1 dante i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
522 1.1 dante if (i == 0) {
523 1.1 dante printf("%s: unable to create control blocks\n",
524 1.1 dante sc->sc_dev.dv_xname);
525 1.1 dante return; /* (ENOMEM) */ ;
526 1.1 dante } else if (i != ADV_MAX_CCB) {
527 1.1 dante printf("%s: WARNING: only %d of %d control blocks created\n",
528 1.1 dante sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
529 1.1 dante }
530 1.1 dante config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
531 1.1 dante }
532 1.1 dante
533 1.1 dante
534 1.1 dante static void
535 1.1 dante advminphys(bp)
536 1.1 dante struct buf *bp;
537 1.1 dante {
538 1.1 dante
539 1.1 dante if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
540 1.1 dante bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
541 1.1 dante minphys(bp);
542 1.1 dante }
543 1.1 dante
544 1.1 dante
545 1.1 dante /*
546 1.1 dante * start a scsi operation given the command and the data address. Also needs
547 1.1 dante * the unit, target and lu.
548 1.1 dante */
549 1.1 dante static int
550 1.1 dante adv_scsi_cmd(xs)
551 1.1 dante struct scsipi_xfer *xs;
552 1.1 dante {
553 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
554 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
555 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
556 1.1 dante ADV_CCB *ccb;
557 1.1 dante int s, flags, error, nsegs;
558 1.15 thorpej int fromqueue = 0, dontqueue = 0, nowait = 0;
559 1.1 dante
560 1.1 dante
561 1.1 dante s = splbio(); /* protect the queue */
562 1.1 dante
563 1.1 dante /*
564 1.1 dante * If we're running the queue from adv_done(), we've been
565 1.1 dante * called with the first queue entry as our argument.
566 1.1 dante */
567 1.9 thorpej if (xs == TAILQ_FIRST(&sc->sc_queue)) {
568 1.9 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
569 1.1 dante fromqueue = 1;
570 1.15 thorpej nowait = 1;
571 1.1 dante } else {
572 1.1 dante
573 1.1 dante /* Polled requests can't be queued for later. */
574 1.14 thorpej dontqueue = xs->xs_control & XS_CTL_POLL;
575 1.1 dante
576 1.1 dante /*
577 1.1 dante * If there are jobs in the queue, run them first.
578 1.1 dante */
579 1.9 thorpej if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
580 1.1 dante /*
581 1.1 dante * If we can't queue, we have to abort, since
582 1.1 dante * we have to preserve order.
583 1.1 dante */
584 1.1 dante if (dontqueue) {
585 1.1 dante splx(s);
586 1.1 dante xs->error = XS_DRIVER_STUFFUP;
587 1.1 dante return (TRY_AGAIN_LATER);
588 1.1 dante }
589 1.1 dante /*
590 1.1 dante * Swap with the first queue entry.
591 1.1 dante */
592 1.9 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
593 1.9 thorpej xs = TAILQ_FIRST(&sc->sc_queue);
594 1.9 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
595 1.1 dante fromqueue = 1;
596 1.1 dante }
597 1.1 dante }
598 1.1 dante
599 1.1 dante
600 1.1 dante /*
601 1.1 dante * get a ccb to use. If the transfer
602 1.1 dante * is from a buf (possibly from interrupt time)
603 1.1 dante * then we can't allow it to sleep
604 1.1 dante */
605 1.1 dante
606 1.14 thorpej flags = xs->xs_control;
607 1.15 thorpej if (nowait)
608 1.15 thorpej flags |= XS_CTL_NOSLEEP;
609 1.1 dante if ((ccb = adv_get_ccb(sc, flags)) == NULL) {
610 1.1 dante /*
611 1.1 dante * If we can't queue, we lose.
612 1.1 dante */
613 1.1 dante if (dontqueue) {
614 1.1 dante splx(s);
615 1.1 dante xs->error = XS_DRIVER_STUFFUP;
616 1.1 dante return (TRY_AGAIN_LATER);
617 1.1 dante }
618 1.1 dante /*
619 1.1 dante * Stuff ourselves into the queue, in front
620 1.1 dante * if we came off in the first place.
621 1.1 dante */
622 1.9 thorpej if (fromqueue)
623 1.9 thorpej TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
624 1.9 thorpej else
625 1.9 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
626 1.1 dante splx(s);
627 1.1 dante return (SUCCESSFULLY_QUEUED);
628 1.1 dante }
629 1.1 dante splx(s); /* done playing with the queue */
630 1.1 dante
631 1.1 dante ccb->xs = xs;
632 1.1 dante ccb->timeout = xs->timeout;
633 1.1 dante
634 1.1 dante /*
635 1.1 dante * Build up the request
636 1.1 dante */
637 1.1 dante memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
638 1.1 dante
639 1.10 dante ccb->scsiq.q2.ccb_ptr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
640 1.10 dante ADV_CCB_OFF(ccb);
641 1.1 dante
642 1.1 dante ccb->scsiq.cdbptr = &xs->cmd->opcode;
643 1.1 dante ccb->scsiq.q2.cdb_len = xs->cmdlen;
644 1.1 dante ccb->scsiq.q1.target_id = ASC_TID_TO_TARGET_ID(sc_link->scsipi_scsi.target);
645 1.1 dante ccb->scsiq.q1.target_lun = sc_link->scsipi_scsi.lun;
646 1.1 dante ccb->scsiq.q2.target_ix = ASC_TIDLUN_TO_IX(sc_link->scsipi_scsi.target,
647 1.1 dante sc_link->scsipi_scsi.lun);
648 1.1 dante ccb->scsiq.q1.sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
649 1.1 dante ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
650 1.1 dante ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
651 1.1 dante
652 1.1 dante /*
653 1.1 dante * If there are any outstanding requests for the current target,
654 1.1 dante * then every 255th request send an ORDERED request. This heuristic
655 1.1 dante * tries to retain the benefit of request sorting while preventing
656 1.1 dante * request starvation. 255 is the max number of tags or pending commands
657 1.1 dante * a device may have outstanding.
658 1.1 dante */
659 1.1 dante sc->reqcnt[sc_link->scsipi_scsi.target]++;
660 1.1 dante if ((sc->reqcnt[sc_link->scsipi_scsi.target] > 0) &&
661 1.1 dante (sc->reqcnt[sc_link->scsipi_scsi.target] % 255) == 0) {
662 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
663 1.1 dante } else {
664 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
665 1.1 dante }
666 1.1 dante
667 1.1 dante
668 1.1 dante if (xs->datalen) {
669 1.1 dante /*
670 1.1 dante * Map the DMA transfer.
671 1.1 dante */
672 1.1 dante #ifdef TFS
673 1.1 dante if (flags & SCSI_DATA_UIO) {
674 1.1 dante error = bus_dmamap_load_uio(dmat,
675 1.1 dante ccb->dmamap_xfer, (struct uio *) xs->data,
676 1.14 thorpej (flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
677 1.1 dante } else
678 1.1 dante #endif /* TFS */
679 1.1 dante {
680 1.1 dante error = bus_dmamap_load(dmat,
681 1.1 dante ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
682 1.14 thorpej (flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
683 1.1 dante }
684 1.1 dante
685 1.1 dante if (error) {
686 1.1 dante if (error == EFBIG) {
687 1.1 dante printf("%s: adv_scsi_cmd, more than %d dma"
688 1.1 dante " segments\n",
689 1.1 dante sc->sc_dev.dv_xname, ASC_MAX_SG_LIST);
690 1.1 dante } else {
691 1.1 dante printf("%s: adv_scsi_cmd, error %d loading"
692 1.1 dante " dma map\n",
693 1.1 dante sc->sc_dev.dv_xname, error);
694 1.1 dante }
695 1.1 dante
696 1.1 dante xs->error = XS_DRIVER_STUFFUP;
697 1.1 dante adv_free_ccb(sc, ccb);
698 1.1 dante return (COMPLETE);
699 1.1 dante }
700 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
701 1.1 dante ccb->dmamap_xfer->dm_mapsize,
702 1.14 thorpej (flags & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD :
703 1.1 dante BUS_DMASYNC_PREWRITE);
704 1.1 dante
705 1.1 dante
706 1.1 dante memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
707 1.1 dante
708 1.1 dante for (nsegs = 0; nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
709 1.1 dante
710 1.1 dante ccb->sghead.sg_list[nsegs].addr =
711 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
712 1.1 dante ccb->sghead.sg_list[nsegs].bytes =
713 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
714 1.1 dante }
715 1.1 dante
716 1.1 dante ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
717 1.1 dante ccb->dmamap_xfer->dm_nsegs;
718 1.1 dante
719 1.1 dante ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
720 1.1 dante ccb->scsiq.sg_head = &ccb->sghead;
721 1.1 dante ccb->scsiq.q1.data_addr = 0;
722 1.1 dante ccb->scsiq.q1.data_cnt = 0;
723 1.1 dante } else {
724 1.1 dante /*
725 1.1 dante * No data xfer, use non S/G values.
726 1.1 dante */
727 1.1 dante ccb->scsiq.q1.data_addr = 0;
728 1.1 dante ccb->scsiq.q1.data_cnt = 0;
729 1.1 dante }
730 1.1 dante
731 1.6 dante #ifdef ASC_DEBUG
732 1.6 dante printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX \n",
733 1.6 dante sc_link->scsipi_scsi.target,
734 1.6 dante sc_link->scsipi_scsi.lun, xs->cmd->opcode,
735 1.6 dante (unsigned long)ccb);
736 1.6 dante #endif
737 1.1 dante s = splbio();
738 1.1 dante adv_queue_ccb(sc, ccb);
739 1.1 dante splx(s);
740 1.1 dante
741 1.1 dante /*
742 1.1 dante * Usually return SUCCESSFULLY QUEUED
743 1.1 dante */
744 1.14 thorpej if ((flags & XS_CTL_POLL) == 0)
745 1.1 dante return (SUCCESSFULLY_QUEUED);
746 1.1 dante
747 1.1 dante /*
748 1.1 dante * If we can't use interrupts, poll on completion
749 1.1 dante */
750 1.1 dante if (adv_poll(sc, xs, ccb->timeout)) {
751 1.1 dante adv_timeout(ccb);
752 1.1 dante if (adv_poll(sc, xs, ccb->timeout))
753 1.1 dante adv_timeout(ccb);
754 1.1 dante }
755 1.1 dante return (COMPLETE);
756 1.1 dante }
757 1.1 dante
758 1.1 dante
759 1.1 dante int
760 1.1 dante adv_intr(arg)
761 1.1 dante void *arg;
762 1.1 dante {
763 1.1 dante ASC_SOFTC *sc = arg;
764 1.1 dante struct scsipi_xfer *xs;
765 1.1 dante
766 1.6 dante #ifdef ASC_DEBUG
767 1.6 dante int int_pend = FALSE;
768 1.6 dante
769 1.6 dante if(ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh))
770 1.6 dante {
771 1.6 dante int_pend = TRUE;
772 1.6 dante printf("ISR - ");
773 1.6 dante }
774 1.6 dante #endif
775 1.4 dante AscISR(sc);
776 1.6 dante #ifdef ASC_DEBUG
777 1.6 dante if(int_pend)
778 1.6 dante printf("\n");
779 1.6 dante #endif
780 1.1 dante
781 1.1 dante /*
782 1.1 dante * If there are queue entries in the software queue, try to
783 1.1 dante * run the first one. We should be more or less guaranteed
784 1.1 dante * to succeed, since we just freed a CCB.
785 1.1 dante *
786 1.1 dante * NOTE: adv_scsi_cmd() relies on our calling it with
787 1.1 dante * the first entry in the queue.
788 1.1 dante */
789 1.9 thorpej if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
790 1.1 dante (void) adv_scsi_cmd(xs);
791 1.1 dante
792 1.1 dante return (1);
793 1.1 dante }
794 1.1 dante
795 1.1 dante
796 1.1 dante /*
797 1.1 dante * Poll a particular unit, looking for a particular xs
798 1.1 dante */
799 1.1 dante static int
800 1.1 dante adv_poll(sc, xs, count)
801 1.1 dante ASC_SOFTC *sc;
802 1.1 dante struct scsipi_xfer *xs;
803 1.1 dante int count;
804 1.1 dante {
805 1.1 dante
806 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
807 1.1 dante while (count) {
808 1.1 dante adv_intr(sc);
809 1.14 thorpej if (xs->xs_status & XS_STS_DONE)
810 1.1 dante return (0);
811 1.1 dante delay(1000); /* only happens in boot so ok */
812 1.1 dante count--;
813 1.1 dante }
814 1.1 dante return (1);
815 1.1 dante }
816 1.1 dante
817 1.1 dante
818 1.1 dante static void
819 1.1 dante adv_timeout(arg)
820 1.1 dante void *arg;
821 1.1 dante {
822 1.1 dante ADV_CCB *ccb = arg;
823 1.1 dante struct scsipi_xfer *xs = ccb->xs;
824 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
825 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
826 1.1 dante int s;
827 1.1 dante
828 1.1 dante scsi_print_addr(sc_link);
829 1.1 dante printf("timed out");
830 1.1 dante
831 1.1 dante s = splbio();
832 1.1 dante
833 1.1 dante /*
834 1.1 dante * If it has been through before, then a previous abort has failed,
835 1.1 dante * don't try abort again, reset the bus instead.
836 1.1 dante */
837 1.1 dante if (ccb->flags & CCB_ABORT) {
838 1.1 dante /* abort timed out */
839 1.1 dante printf(" AGAIN. Resetting Bus\n");
840 1.1 dante /* Lets try resetting the bus! */
841 1.1 dante if (AscResetBus(sc) == ASC_ERROR) {
842 1.1 dante ccb->timeout = sc->scsi_reset_wait;
843 1.1 dante adv_queue_ccb(sc, ccb);
844 1.1 dante }
845 1.1 dante } else {
846 1.1 dante /* abort the operation that has timed out */
847 1.1 dante printf("\n");
848 1.10 dante AscAbortCCB(sc, ccb);
849 1.1 dante ccb->xs->error = XS_TIMEOUT;
850 1.1 dante ccb->timeout = ADV_ABORT_TIMEOUT;
851 1.1 dante ccb->flags |= CCB_ABORT;
852 1.1 dante adv_queue_ccb(sc, ccb);
853 1.1 dante }
854 1.1 dante
855 1.1 dante splx(s);
856 1.1 dante }
857 1.1 dante
858 1.1 dante
859 1.1 dante static void
860 1.1 dante adv_watchdog(arg)
861 1.1 dante void *arg;
862 1.1 dante {
863 1.1 dante ADV_CCB *ccb = arg;
864 1.1 dante struct scsipi_xfer *xs = ccb->xs;
865 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
866 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
867 1.1 dante int s;
868 1.1 dante
869 1.1 dante s = splbio();
870 1.1 dante
871 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
872 1.1 dante adv_start_ccbs(sc);
873 1.1 dante
874 1.1 dante splx(s);
875 1.1 dante }
876 1.1 dante
877 1.1 dante
878 1.1 dante /******************************************************************************/
879 1.10 dante /* NARROW boards Interrupt callbacks */
880 1.1 dante /******************************************************************************/
881 1.1 dante
882 1.1 dante
883 1.1 dante /*
884 1.1 dante * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
885 1.1 dante *
886 1.1 dante * Interrupt callback function for the Narrow SCSI Asc Library.
887 1.1 dante */
888 1.1 dante static void
889 1.1 dante adv_narrow_isr_callback(sc, qdonep)
890 1.1 dante ASC_SOFTC *sc;
891 1.1 dante ASC_QDONE_INFO *qdonep;
892 1.1 dante {
893 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
894 1.10 dante ADV_CCB *ccb;
895 1.10 dante struct scsipi_xfer *xs;
896 1.1 dante struct scsipi_sense_data *s1, *s2;
897 1.1 dante
898 1.10 dante
899 1.10 dante ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
900 1.10 dante xs = ccb->xs;
901 1.1 dante
902 1.6 dante #ifdef ASC_DEBUG
903 1.6 dante printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
904 1.6 dante (unsigned long)ccb,
905 1.6 dante xs->sc_link->scsipi_scsi.target,
906 1.6 dante xs->sc_link->scsipi_scsi.lun, xs->cmd->opcode);
907 1.6 dante #endif
908 1.16 thorpej callout_stop(&ccb->xs->xs_callout);
909 1.1 dante
910 1.1 dante /*
911 1.1 dante * If we were a data transfer, unload the map that described
912 1.1 dante * the data buffer.
913 1.1 dante */
914 1.1 dante if (xs->datalen) {
915 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
916 1.1 dante ccb->dmamap_xfer->dm_mapsize,
917 1.14 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
918 1.14 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
919 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
920 1.1 dante }
921 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
922 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
923 1.1 dante Debugger();
924 1.1 dante return;
925 1.1 dante }
926 1.1 dante /*
927 1.1 dante * 'qdonep' contains the command's ending status.
928 1.1 dante */
929 1.6 dante #ifdef ASC_DEBUG
930 1.6 dante printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
931 1.6 dante #endif
932 1.1 dante switch (qdonep->d3.done_stat) {
933 1.1 dante case ASC_QD_NO_ERROR:
934 1.1 dante switch (qdonep->d3.host_stat) {
935 1.1 dante case ASC_QHSTA_NO_ERROR:
936 1.1 dante xs->error = XS_NOERROR;
937 1.1 dante xs->resid = 0;
938 1.1 dante break;
939 1.1 dante
940 1.1 dante default:
941 1.1 dante /* QHSTA error occurred */
942 1.1 dante xs->error = XS_DRIVER_STUFFUP;
943 1.1 dante break;
944 1.1 dante }
945 1.1 dante
946 1.1 dante /*
947 1.1 dante * If an INQUIRY command completed successfully, then call
948 1.1 dante * the AscInquiryHandling() function to patch bugged boards.
949 1.1 dante */
950 1.1 dante if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
951 1.1 dante (xs->sc_link->scsipi_scsi.lun == 0) &&
952 1.1 dante (xs->datalen - qdonep->remain_bytes) >= 8) {
953 1.1 dante AscInquiryHandling(sc,
954 1.1 dante xs->sc_link->scsipi_scsi.target & 0x7,
955 1.1 dante (ASC_SCSI_INQUIRY *) xs->data);
956 1.1 dante }
957 1.1 dante break;
958 1.1 dante
959 1.1 dante case ASC_QD_WITH_ERROR:
960 1.1 dante switch (qdonep->d3.host_stat) {
961 1.1 dante case ASC_QHSTA_NO_ERROR:
962 1.1 dante if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
963 1.1 dante s1 = &ccb->scsi_sense;
964 1.1 dante s2 = &xs->sense.scsi_sense;
965 1.1 dante *s2 = *s1;
966 1.1 dante xs->error = XS_SENSE;
967 1.4 dante } else {
968 1.1 dante xs->error = XS_DRIVER_STUFFUP;
969 1.4 dante }
970 1.1 dante break;
971 1.1 dante
972 1.1 dante default:
973 1.1 dante /* QHSTA error occurred */
974 1.1 dante xs->error = XS_DRIVER_STUFFUP;
975 1.1 dante break;
976 1.1 dante }
977 1.1 dante break;
978 1.1 dante
979 1.1 dante case ASC_QD_ABORTED_BY_HOST:
980 1.1 dante default:
981 1.1 dante xs->error = XS_DRIVER_STUFFUP;
982 1.1 dante break;
983 1.1 dante }
984 1.1 dante
985 1.1 dante
986 1.1 dante adv_free_ccb(sc, ccb);
987 1.14 thorpej xs->xs_status |= XS_STS_DONE;
988 1.1 dante scsipi_done(xs);
989 1.1 dante }
990