adv.c revision 1.2 1 1.2 dante /* $NetBSD: adv.c,v 1.2 1998/08/29 13:45:56 dante Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.1 dante * Generic driver for the Advanced Systems Inc. SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.1 dante * This product includes software developed by the NetBSD
22 1.1 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.1 dante #include <sys/kernel.h>
44 1.1 dante #include <sys/errno.h>
45 1.1 dante #include <sys/ioctl.h>
46 1.1 dante #include <sys/device.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/buf.h>
49 1.1 dante #include <sys/proc.h>
50 1.1 dante #include <sys/user.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <vm/vm.h>
56 1.1 dante #include <vm/vm_param.h>
57 1.1 dante #include <vm/pmap.h>
58 1.1 dante
59 1.1 dante #include <dev/scsipi/scsi_all.h>
60 1.1 dante #include <dev/scsipi/scsipi_all.h>
61 1.1 dante #include <dev/scsipi/scsiconf.h>
62 1.1 dante
63 1.1 dante #include <dev/ic/adv.h>
64 1.1 dante #include <dev/ic/advlib.h>
65 1.1 dante
66 1.1 dante /******************************************************************************/
67 1.1 dante
68 1.1 dante
69 1.1 dante static void adv_enqueue __P((ASC_SOFTC *, struct scsipi_xfer *, int));
70 1.1 dante static struct scsipi_xfer *adv_dequeue __P((ASC_SOFTC *));
71 1.1 dante
72 1.1 dante static int adv_alloc_ccbs __P((ASC_SOFTC *));
73 1.1 dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
74 1.1 dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
75 1.1 dante static void adv_reset_ccb __P((ADV_CCB *));
76 1.1 dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
77 1.1 dante static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
78 1.1 dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
79 1.1 dante static void adv_start_ccbs __P((ASC_SOFTC *));
80 1.1 dante
81 1.1 dante static u_int8_t *adv_alloc_overrunbuf __P((char *dvname, bus_dma_tag_t));
82 1.1 dante
83 1.1 dante static int adv_scsi_cmd __P((struct scsipi_xfer *));
84 1.1 dante static void advminphys __P((struct buf *));
85 1.1 dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
86 1.1 dante
87 1.1 dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
88 1.1 dante static void adv_timeout __P((void *));
89 1.1 dante static void adv_watchdog __P((void *));
90 1.1 dante
91 1.1 dante
92 1.1 dante /******************************************************************************/
93 1.1 dante
94 1.1 dante
95 1.1 dante struct scsipi_adapter adv_switch =
96 1.1 dante {
97 1.1 dante adv_scsi_cmd, /* called to start/enqueue a SCSI command */
98 1.1 dante advminphys, /* to limit the transfer to max device can do */
99 1.1 dante 0, /* IT SEEMS IT IS NOT USED YET */
100 1.1 dante 0, /* as above... */
101 1.1 dante };
102 1.1 dante
103 1.1 dante
104 1.1 dante /* the below structure is so we have a default dev struct for out link struct */
105 1.1 dante struct scsipi_device adv_dev =
106 1.1 dante {
107 1.1 dante NULL, /* Use default error handler */
108 1.1 dante NULL, /* have a queue, served by this */
109 1.1 dante NULL, /* have no async handler */
110 1.1 dante NULL, /* Use default 'done' routine */
111 1.1 dante };
112 1.1 dante
113 1.1 dante
114 1.1 dante #define ADV_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
115 1.1 dante #define ADV_WATCH_TIMEOUT 1000 /* time to wait for watchdog (mSec) */
116 1.1 dante
117 1.1 dante
118 1.1 dante /******************************************************************************/
119 1.1 dante /* scsipi_xfer queue routines */
120 1.1 dante /******************************************************************************/
121 1.1 dante
122 1.1 dante
123 1.1 dante /*
124 1.1 dante * Insert a scsipi_xfer into the software queue. We overload xs->free_list
125 1.1 dante * to avoid having to allocate additional resources (since we're used
126 1.1 dante * only during resource shortages anyhow.
127 1.1 dante */
128 1.1 dante static void
129 1.1 dante adv_enqueue(sc, xs, infront)
130 1.1 dante ASC_SOFTC *sc;
131 1.1 dante struct scsipi_xfer *xs;
132 1.1 dante int infront;
133 1.1 dante {
134 1.1 dante
135 1.1 dante if (infront || sc->sc_queue.lh_first == NULL) {
136 1.1 dante if (sc->sc_queue.lh_first == NULL)
137 1.1 dante sc->sc_queuelast = xs;
138 1.1 dante LIST_INSERT_HEAD(&sc->sc_queue, xs, free_list);
139 1.1 dante return;
140 1.1 dante }
141 1.1 dante LIST_INSERT_AFTER(sc->sc_queuelast, xs, free_list);
142 1.1 dante sc->sc_queuelast = xs;
143 1.1 dante }
144 1.1 dante
145 1.1 dante
146 1.1 dante /*
147 1.1 dante * Pull a scsipi_xfer off the front of the software queue.
148 1.1 dante */
149 1.1 dante static struct scsipi_xfer *
150 1.1 dante adv_dequeue(sc)
151 1.1 dante ASC_SOFTC *sc;
152 1.1 dante {
153 1.1 dante struct scsipi_xfer *xs;
154 1.1 dante
155 1.1 dante xs = sc->sc_queue.lh_first;
156 1.1 dante LIST_REMOVE(xs, free_list);
157 1.1 dante
158 1.1 dante if (sc->sc_queue.lh_first == NULL)
159 1.1 dante sc->sc_queuelast = NULL;
160 1.1 dante
161 1.1 dante return (xs);
162 1.1 dante }
163 1.1 dante
164 1.1 dante
165 1.1 dante /******************************************************************************/
166 1.1 dante /* Control Blocks routines */
167 1.1 dante /******************************************************************************/
168 1.1 dante
169 1.1 dante
170 1.1 dante static int
171 1.1 dante adv_alloc_ccbs(sc)
172 1.1 dante ASC_SOFTC *sc;
173 1.1 dante {
174 1.1 dante bus_dma_segment_t seg;
175 1.1 dante int error, rseg;
176 1.1 dante
177 1.1 dante /*
178 1.1 dante * Allocate the control blocks.
179 1.1 dante */
180 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
181 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
182 1.1 dante printf("%s: unable to allocate control structures,"
183 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
184 1.1 dante return (error);
185 1.1 dante }
186 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
187 1.1 dante sizeof(struct adv_control), (caddr_t *) & sc->sc_control,
188 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
189 1.1 dante printf("%s: unable to map control structures, error = %d\n",
190 1.1 dante sc->sc_dev.dv_xname, error);
191 1.1 dante return (error);
192 1.1 dante }
193 1.1 dante /*
194 1.1 dante * Create and load the DMA map used for the control blocks.
195 1.1 dante */
196 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
197 1.1 dante 1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
198 1.1 dante &sc->sc_dmamap_control)) != 0) {
199 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
200 1.1 dante sc->sc_dev.dv_xname, error);
201 1.1 dante return (error);
202 1.1 dante }
203 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
204 1.1 dante sc->sc_control, sizeof(struct adv_control), NULL,
205 1.1 dante BUS_DMA_NOWAIT)) != 0) {
206 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
207 1.1 dante sc->sc_dev.dv_xname, error);
208 1.1 dante return (error);
209 1.1 dante }
210 1.1 dante return (0);
211 1.1 dante }
212 1.1 dante
213 1.1 dante
214 1.1 dante /*
215 1.1 dante * Create a set of ccbs and add them to the free list. Called once
216 1.1 dante * by adv_init(). We return the number of CCBs successfully created.
217 1.1 dante */
218 1.1 dante static int
219 1.1 dante adv_create_ccbs(sc, ccbstore, count)
220 1.1 dante ASC_SOFTC *sc;
221 1.1 dante ADV_CCB *ccbstore;
222 1.1 dante int count;
223 1.1 dante {
224 1.1 dante ADV_CCB *ccb;
225 1.1 dante int i, error;
226 1.1 dante
227 1.1 dante bzero(ccbstore, sizeof(ADV_CCB) * count);
228 1.1 dante for (i = 0; i < count; i++) {
229 1.1 dante ccb = &ccbstore[i];
230 1.1 dante if ((error = adv_init_ccb(sc, ccb)) != 0) {
231 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
232 1.1 dante sc->sc_dev.dv_xname, error);
233 1.1 dante return (i);
234 1.1 dante }
235 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
236 1.1 dante }
237 1.1 dante
238 1.1 dante return (i);
239 1.1 dante }
240 1.1 dante
241 1.1 dante
242 1.1 dante /*
243 1.1 dante * A ccb is put onto the free list.
244 1.1 dante */
245 1.1 dante static void
246 1.1 dante adv_free_ccb(sc, ccb)
247 1.1 dante ASC_SOFTC *sc;
248 1.1 dante ADV_CCB *ccb;
249 1.1 dante {
250 1.1 dante int s;
251 1.1 dante
252 1.1 dante s = splbio();
253 1.1 dante
254 1.1 dante adv_reset_ccb(ccb);
255 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
256 1.1 dante
257 1.1 dante /*
258 1.1 dante * If there were none, wake anybody waiting for one to come free,
259 1.1 dante * starting with queued entries.
260 1.1 dante */
261 1.1 dante if (ccb->chain.tqe_next == 0)
262 1.1 dante wakeup(&sc->sc_free_ccb);
263 1.1 dante
264 1.1 dante splx(s);
265 1.1 dante }
266 1.1 dante
267 1.1 dante
268 1.1 dante static void
269 1.1 dante adv_reset_ccb(ccb)
270 1.1 dante ADV_CCB *ccb;
271 1.1 dante {
272 1.1 dante
273 1.1 dante ccb->flags = 0;
274 1.1 dante }
275 1.1 dante
276 1.1 dante
277 1.1 dante static int
278 1.1 dante adv_init_ccb(sc, ccb)
279 1.1 dante ASC_SOFTC *sc;
280 1.1 dante ADV_CCB *ccb;
281 1.1 dante {
282 1.1 dante int error;
283 1.1 dante
284 1.1 dante /*
285 1.1 dante * Create the DMA map for this CCB.
286 1.1 dante */
287 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
288 1.1 dante (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
289 1.1 dante ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
290 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
291 1.1 dante if (error) {
292 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
293 1.1 dante sc->sc_dev.dv_xname, error);
294 1.1 dante return (error);
295 1.1 dante }
296 1.1 dante adv_reset_ccb(ccb);
297 1.1 dante return (0);
298 1.1 dante }
299 1.1 dante
300 1.1 dante
301 1.1 dante /*
302 1.1 dante * Get a free ccb
303 1.1 dante *
304 1.1 dante * If there are none, see if we can allocate a new one
305 1.1 dante */
306 1.1 dante static ADV_CCB *
307 1.1 dante adv_get_ccb(sc, flags)
308 1.1 dante ASC_SOFTC *sc;
309 1.1 dante int flags;
310 1.1 dante {
311 1.1 dante ADV_CCB *ccb = 0;
312 1.1 dante int s;
313 1.1 dante
314 1.1 dante s = splbio();
315 1.1 dante
316 1.1 dante /*
317 1.1 dante * If we can and have to, sleep waiting for one to come free
318 1.1 dante * but only if we can't allocate a new one.
319 1.1 dante */
320 1.1 dante for (;;) {
321 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
322 1.1 dante if (ccb) {
323 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
324 1.1 dante break;
325 1.1 dante }
326 1.1 dante if ((flags & SCSI_NOSLEEP) != 0)
327 1.1 dante goto out;
328 1.1 dante
329 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
330 1.1 dante }
331 1.1 dante
332 1.1 dante ccb->flags |= CCB_ALLOC;
333 1.1 dante
334 1.1 dante out:
335 1.1 dante splx(s);
336 1.1 dante return (ccb);
337 1.1 dante }
338 1.1 dante
339 1.1 dante
340 1.1 dante /*
341 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
342 1.1 dante */
343 1.1 dante static void
344 1.1 dante adv_queue_ccb(sc, ccb)
345 1.1 dante ASC_SOFTC *sc;
346 1.1 dante ADV_CCB *ccb;
347 1.1 dante {
348 1.1 dante
349 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
350 1.1 dante
351 1.1 dante adv_start_ccbs(sc);
352 1.1 dante }
353 1.1 dante
354 1.1 dante
355 1.1 dante static void
356 1.1 dante adv_start_ccbs(sc)
357 1.1 dante ASC_SOFTC *sc;
358 1.1 dante {
359 1.1 dante ADV_CCB *ccb;
360 1.1 dante
361 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
362 1.1 dante if (ccb->flags & CCB_WATCHDOG)
363 1.1 dante untimeout(adv_watchdog, ccb);
364 1.1 dante
365 1.1 dante if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
366 1.1 dante ccb->flags |= CCB_WATCHDOG;
367 1.1 dante timeout(adv_watchdog, ccb,
368 1.1 dante (ADV_WATCH_TIMEOUT * hz) / 1000);
369 1.1 dante break;
370 1.1 dante }
371 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
372 1.1 dante
373 1.1 dante if ((ccb->xs->flags & SCSI_POLL) == 0)
374 1.1 dante timeout(adv_timeout, ccb, (ccb->timeout * hz) / 1000);
375 1.1 dante }
376 1.1 dante }
377 1.1 dante
378 1.1 dante
379 1.1 dante /******************************************************************************/
380 1.1 dante /* DMA able memory allocation routines */
381 1.1 dante /******************************************************************************/
382 1.1 dante
383 1.1 dante
384 1.1 dante /*
385 1.1 dante * Allocate a DMA able memory for overrun_buffer.
386 1.1 dante * This memory can be safely shared among all the AdvanSys boards.
387 1.1 dante */
388 1.1 dante u_int8_t *
389 1.1 dante adv_alloc_overrunbuf(dvname, dmat)
390 1.1 dante char *dvname;
391 1.1 dante bus_dma_tag_t dmat;
392 1.1 dante {
393 1.1 dante static u_int8_t *overrunbuf = NULL;
394 1.1 dante
395 1.1 dante bus_dmamap_t ovrbuf_dmamap;
396 1.1 dante bus_dma_segment_t seg;
397 1.1 dante int rseg, error;
398 1.1 dante
399 1.1 dante
400 1.1 dante /*
401 1.1 dante * if an overrun buffer has been already allocated don't allocate it
402 1.1 dante * again. Instead return the address of the allocated buffer.
403 1.1 dante */
404 1.1 dante if (overrunbuf)
405 1.1 dante return (overrunbuf);
406 1.1 dante
407 1.1 dante
408 1.1 dante if ((error = bus_dmamem_alloc(dmat, ASC_OVERRUN_BSIZE,
409 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
410 1.1 dante printf("%s: unable to allocate overrun buffer, error = %d\n",
411 1.1 dante dvname, error);
412 1.1 dante return (0);
413 1.1 dante }
414 1.1 dante if ((error = bus_dmamem_map(dmat, &seg, rseg, ASC_OVERRUN_BSIZE,
415 1.1 dante (caddr_t *) & overrunbuf, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
416 1.1 dante printf("%s: unable to map overrun buffer, error = %d\n",
417 1.1 dante dvname, error);
418 1.1 dante
419 1.1 dante bus_dmamem_free(dmat, &seg, 1);
420 1.1 dante return (0);
421 1.1 dante }
422 1.1 dante if ((error = bus_dmamap_create(dmat, ASC_OVERRUN_BSIZE, 1,
423 1.1 dante ASC_OVERRUN_BSIZE, 0, BUS_DMA_NOWAIT, &ovrbuf_dmamap)) != 0) {
424 1.1 dante printf("%s: unable to create overrun buffer DMA map,"
425 1.1 dante " error = %d\n", dvname, error);
426 1.1 dante
427 1.1 dante bus_dmamem_unmap(dmat, overrunbuf, ASC_OVERRUN_BSIZE);
428 1.1 dante bus_dmamem_free(dmat, &seg, 1);
429 1.1 dante return (0);
430 1.1 dante }
431 1.1 dante if ((error = bus_dmamap_load(dmat, ovrbuf_dmamap, overrunbuf,
432 1.1 dante ASC_OVERRUN_BSIZE, NULL, BUS_DMA_NOWAIT)) != 0) {
433 1.1 dante printf("%s: unable to load overrun buffer DMA map,"
434 1.1 dante " error = %d\n", dvname, error);
435 1.1 dante
436 1.1 dante bus_dmamap_destroy(dmat, ovrbuf_dmamap);
437 1.1 dante bus_dmamem_unmap(dmat, overrunbuf, ASC_OVERRUN_BSIZE);
438 1.1 dante bus_dmamem_free(dmat, &seg, 1);
439 1.1 dante return (0);
440 1.1 dante }
441 1.1 dante return (overrunbuf);
442 1.1 dante }
443 1.1 dante
444 1.1 dante
445 1.1 dante /******************************************************************************/
446 1.1 dante /* SCSI layer interfacing routines */
447 1.1 dante /******************************************************************************/
448 1.1 dante
449 1.1 dante
450 1.1 dante int
451 1.1 dante adv_init(sc)
452 1.1 dante ASC_SOFTC *sc;
453 1.1 dante {
454 1.1 dante int warn;
455 1.1 dante
456 1.1 dante if (ASC_IS_NARROW_BOARD(sc)) {
457 1.1 dante if (!AscFindSignature(sc->sc_iot, sc->sc_ioh))
458 1.1 dante panic("adv_init: adv_find_signature failed");
459 1.1 dante
460 1.1 dante /*
461 1.1 dante * Read the board configuration
462 1.1 dante */
463 1.1 dante AscInitASC_SOFTC(sc);
464 1.1 dante warn = AscInitFromEEP(sc);
465 1.1 dante if (warn) {
466 1.1 dante printf("%s -get: ", sc->sc_dev.dv_xname);
467 1.1 dante switch (warn) {
468 1.1 dante case -1:
469 1.1 dante printf("Chip is not halted\n");
470 1.1 dante break;
471 1.1 dante
472 1.1 dante case -2:
473 1.1 dante printf("Couldn't get MicroCode Start"
474 1.1 dante " address\n");
475 1.1 dante break;
476 1.1 dante
477 1.1 dante case ASC_WARN_IO_PORT_ROTATE:
478 1.1 dante printf("I/O port address modified\n");
479 1.1 dante break;
480 1.1 dante
481 1.1 dante case ASC_WARN_AUTO_CONFIG:
482 1.1 dante printf("I/O port increment switch enabled\n");
483 1.1 dante break;
484 1.1 dante
485 1.1 dante case ASC_WARN_EEPROM_CHKSUM:
486 1.1 dante printf("EEPROM checksum error\n");
487 1.1 dante break;
488 1.1 dante
489 1.1 dante case ASC_WARN_IRQ_MODIFIED:
490 1.1 dante printf("IRQ modified\n");
491 1.1 dante break;
492 1.1 dante
493 1.1 dante case ASC_WARN_CMD_QNG_CONFLICT:
494 1.1 dante printf("tag queuing enabled w/o disconnects\n");
495 1.1 dante break;
496 1.1 dante
497 1.1 dante default:
498 1.1 dante printf("unknown warning %d\n", warn);
499 1.1 dante }
500 1.1 dante }
501 1.1 dante if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
502 1.1 dante sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
503 1.1 dante
504 1.1 dante /*
505 1.1 dante * Modify the board configuration
506 1.1 dante */
507 1.1 dante warn = AscInitFromASC_SOFTC(sc);
508 1.1 dante if (warn) {
509 1.1 dante printf("%s -set: ", sc->sc_dev.dv_xname);
510 1.1 dante switch (warn) {
511 1.1 dante case ASC_WARN_CMD_QNG_CONFLICT:
512 1.1 dante printf("tag queuing enabled w/o disconnects\n");
513 1.1 dante break;
514 1.1 dante
515 1.1 dante case ASC_WARN_AUTO_CONFIG:
516 1.1 dante printf("I/O port increment switch enabled\n");
517 1.1 dante break;
518 1.1 dante
519 1.1 dante default:
520 1.1 dante printf("unknown warning %d\n", warn);
521 1.1 dante }
522 1.1 dante }
523 1.1 dante sc->isr_callback = (ulong) adv_narrow_isr_callback;
524 1.1 dante
525 1.1 dante if (!(sc->overrun_buf = adv_alloc_overrunbuf(sc->sc_dev.dv_xname,
526 1.1 dante sc->sc_dmat))) {
527 1.1 dante return (1);
528 1.1 dante }
529 1.1 dante } else
530 1.1 dante //IS_WIDE_BOARD
531 1.1 dante {
532 1.1 dante printf("%s: Wide boards are not supported yet\n",
533 1.1 dante sc->sc_dev.dv_xname);
534 1.1 dante return (1);
535 1.1 dante }
536 1.1 dante
537 1.1 dante return (0);
538 1.1 dante }
539 1.1 dante
540 1.1 dante
541 1.1 dante void
542 1.1 dante adv_attach(sc)
543 1.1 dante ASC_SOFTC *sc;
544 1.1 dante {
545 1.1 dante int i, error;
546 1.1 dante
547 1.1 dante if (ASC_IS_NARROW_BOARD(sc)) {
548 1.1 dante /*
549 1.1 dante * Initialize board RISC chip and enable interrupts.
550 1.1 dante */
551 1.1 dante switch (AscInitDriver(sc)) {
552 1.1 dante case 0:
553 1.1 dante /* AllOK */
554 1.1 dante break;
555 1.1 dante
556 1.1 dante case 1:
557 1.1 dante panic("%s: bad signature", sc->sc_dev.dv_xname);
558 1.1 dante break;
559 1.1 dante
560 1.1 dante case 2:
561 1.1 dante panic("%s: unable to load MicroCode",
562 1.1 dante sc->sc_dev.dv_xname);
563 1.1 dante break;
564 1.1 dante
565 1.1 dante case 3:
566 1.1 dante panic("%s: unable to initialize MicroCode",
567 1.1 dante sc->sc_dev.dv_xname);
568 1.1 dante break;
569 1.1 dante
570 1.1 dante default:
571 1.1 dante panic("%s: unable to initialize board RISC chip",
572 1.1 dante sc->sc_dev.dv_xname);
573 1.1 dante }
574 1.1 dante } else
575 1.1 dante //Wide Boards
576 1.1 dante {
577 1.1 dante /* ToDo */
578 1.1 dante }
579 1.1 dante
580 1.1 dante
581 1.1 dante /*
582 1.1 dante * fill in the prototype scsipi_link.
583 1.1 dante */
584 1.1 dante sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
585 1.1 dante sc->sc_link.adapter_softc = sc;
586 1.1 dante sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
587 1.1 dante sc->sc_link.adapter = &adv_switch;
588 1.1 dante sc->sc_link.device = &adv_dev;
589 1.1 dante sc->sc_link.openings = 4;
590 1.1 dante sc->sc_link.scsipi_scsi.max_target = ASC_IS_NARROW_BOARD(sc) ? 7 : 15;
591 1.1 dante sc->sc_link.type = BUS_SCSI;
592 1.1 dante
593 1.1 dante
594 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
595 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
596 1.1 dante LIST_INIT(&sc->sc_queue);
597 1.1 dante
598 1.1 dante
599 1.1 dante /*
600 1.1 dante * Allocate the Control Blocks.
601 1.1 dante */
602 1.1 dante error = adv_alloc_ccbs(sc);
603 1.1 dante if (error)
604 1.1 dante return; /* (error) */ ;
605 1.1 dante
606 1.1 dante /*
607 1.1 dante * Create and initialize the Control Blocks.
608 1.1 dante */
609 1.1 dante i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
610 1.1 dante if (i == 0) {
611 1.1 dante printf("%s: unable to create control blocks\n",
612 1.1 dante sc->sc_dev.dv_xname);
613 1.1 dante return; /* (ENOMEM) */ ;
614 1.1 dante } else if (i != ADV_MAX_CCB) {
615 1.1 dante printf("%s: WARNING: only %d of %d control blocks created\n",
616 1.1 dante sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
617 1.1 dante }
618 1.1 dante config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
619 1.1 dante }
620 1.1 dante
621 1.1 dante
622 1.1 dante static void
623 1.1 dante advminphys(bp)
624 1.1 dante struct buf *bp;
625 1.1 dante {
626 1.1 dante
627 1.1 dante if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
628 1.1 dante bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
629 1.1 dante minphys(bp);
630 1.1 dante }
631 1.1 dante
632 1.1 dante
633 1.1 dante /*
634 1.1 dante * start a scsi operation given the command and the data address. Also needs
635 1.1 dante * the unit, target and lu.
636 1.1 dante */
637 1.1 dante static int
638 1.1 dante adv_scsi_cmd(xs)
639 1.1 dante struct scsipi_xfer *xs;
640 1.1 dante {
641 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
642 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
643 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
644 1.1 dante ADV_CCB *ccb;
645 1.1 dante int s, flags, error, nsegs;
646 1.1 dante int fromqueue = 1, dontqueue = 0;
647 1.1 dante
648 1.1 dante
649 1.1 dante s = splbio(); /* protect the queue */
650 1.1 dante
651 1.1 dante /*
652 1.1 dante * If we're running the queue from adv_done(), we've been
653 1.1 dante * called with the first queue entry as our argument.
654 1.1 dante */
655 1.1 dante if (xs == sc->sc_queue.lh_first) {
656 1.1 dante xs = adv_dequeue(sc);
657 1.1 dante fromqueue = 1;
658 1.1 dante } else {
659 1.1 dante
660 1.1 dante /* Polled requests can't be queued for later. */
661 1.1 dante dontqueue = xs->flags & SCSI_POLL;
662 1.1 dante
663 1.1 dante /*
664 1.1 dante * If there are jobs in the queue, run them first.
665 1.1 dante */
666 1.1 dante if (sc->sc_queue.lh_first != NULL) {
667 1.1 dante /*
668 1.1 dante * If we can't queue, we have to abort, since
669 1.1 dante * we have to preserve order.
670 1.1 dante */
671 1.1 dante if (dontqueue) {
672 1.1 dante splx(s);
673 1.1 dante xs->error = XS_DRIVER_STUFFUP;
674 1.1 dante return (TRY_AGAIN_LATER);
675 1.1 dante }
676 1.1 dante /*
677 1.1 dante * Swap with the first queue entry.
678 1.1 dante */
679 1.1 dante adv_enqueue(sc, xs, 0);
680 1.1 dante xs = adv_dequeue(sc);
681 1.1 dante fromqueue = 1;
682 1.1 dante }
683 1.1 dante }
684 1.1 dante
685 1.1 dante
686 1.1 dante /*
687 1.1 dante * get a ccb to use. If the transfer
688 1.1 dante * is from a buf (possibly from interrupt time)
689 1.1 dante * then we can't allow it to sleep
690 1.1 dante */
691 1.1 dante
692 1.1 dante flags = xs->flags;
693 1.1 dante if ((ccb = adv_get_ccb(sc, flags)) == NULL) {
694 1.1 dante /*
695 1.1 dante * If we can't queue, we lose.
696 1.1 dante */
697 1.1 dante if (dontqueue) {
698 1.1 dante splx(s);
699 1.1 dante xs->error = XS_DRIVER_STUFFUP;
700 1.1 dante return (TRY_AGAIN_LATER);
701 1.1 dante }
702 1.1 dante /*
703 1.1 dante * Stuff ourselves into the queue, in front
704 1.1 dante * if we came off in the first place.
705 1.1 dante */
706 1.1 dante adv_enqueue(sc, xs, fromqueue);
707 1.1 dante splx(s);
708 1.1 dante return (SUCCESSFULLY_QUEUED);
709 1.1 dante }
710 1.1 dante splx(s); /* done playing with the queue */
711 1.1 dante
712 1.1 dante ccb->xs = xs;
713 1.1 dante ccb->timeout = xs->timeout;
714 1.1 dante
715 1.1 dante /*
716 1.1 dante * Build up the request
717 1.1 dante */
718 1.1 dante memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
719 1.1 dante
720 1.1 dante ccb->scsiq.q2.ccb_ptr = (ulong) ccb;
721 1.1 dante
722 1.1 dante ccb->scsiq.cdbptr = &xs->cmd->opcode;
723 1.1 dante ccb->scsiq.q2.cdb_len = xs->cmdlen;
724 1.1 dante ccb->scsiq.q1.target_id = ASC_TID_TO_TARGET_ID(sc_link->scsipi_scsi.target);
725 1.1 dante ccb->scsiq.q1.target_lun = sc_link->scsipi_scsi.lun;
726 1.1 dante ccb->scsiq.q2.target_ix = ASC_TIDLUN_TO_IX(sc_link->scsipi_scsi.target,
727 1.1 dante sc_link->scsipi_scsi.lun);
728 1.1 dante ccb->scsiq.q1.sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
729 1.1 dante ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
730 1.1 dante ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
731 1.1 dante
732 1.1 dante /*
733 1.1 dante * If there are any outstanding requests for the current target,
734 1.1 dante * then every 255th request send an ORDERED request. This heuristic
735 1.1 dante * tries to retain the benefit of request sorting while preventing
736 1.1 dante * request starvation. 255 is the max number of tags or pending commands
737 1.1 dante * a device may have outstanding.
738 1.1 dante */
739 1.1 dante sc->reqcnt[sc_link->scsipi_scsi.target]++;
740 1.1 dante if ((sc->reqcnt[sc_link->scsipi_scsi.target] > 0) &&
741 1.1 dante (sc->reqcnt[sc_link->scsipi_scsi.target] % 255) == 0) {
742 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
743 1.1 dante } else {
744 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
745 1.1 dante }
746 1.1 dante
747 1.1 dante
748 1.1 dante if (xs->datalen) {
749 1.1 dante /*
750 1.1 dante * Map the DMA transfer.
751 1.1 dante */
752 1.1 dante #ifdef TFS
753 1.1 dante if (flags & SCSI_DATA_UIO) {
754 1.1 dante error = bus_dmamap_load_uio(dmat,
755 1.1 dante ccb->dmamap_xfer, (struct uio *) xs->data,
756 1.1 dante (flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
757 1.1 dante } else
758 1.1 dante #endif /* TFS */
759 1.1 dante {
760 1.1 dante error = bus_dmamap_load(dmat,
761 1.1 dante ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
762 1.1 dante (flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
763 1.1 dante }
764 1.1 dante
765 1.1 dante if (error) {
766 1.1 dante if (error == EFBIG) {
767 1.1 dante printf("%s: adv_scsi_cmd, more than %d dma"
768 1.1 dante " segments\n",
769 1.1 dante sc->sc_dev.dv_xname, ASC_MAX_SG_LIST);
770 1.1 dante } else {
771 1.1 dante printf("%s: adv_scsi_cmd, error %d loading"
772 1.1 dante " dma map\n",
773 1.1 dante sc->sc_dev.dv_xname, error);
774 1.1 dante }
775 1.1 dante
776 1.1 dante xs->error = XS_DRIVER_STUFFUP;
777 1.1 dante adv_free_ccb(sc, ccb);
778 1.1 dante return (COMPLETE);
779 1.1 dante }
780 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
781 1.1 dante ccb->dmamap_xfer->dm_mapsize,
782 1.1 dante (flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
783 1.1 dante BUS_DMASYNC_PREWRITE);
784 1.1 dante
785 1.1 dante
786 1.1 dante memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
787 1.1 dante
788 1.1 dante for (nsegs = 0; nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
789 1.1 dante
790 1.1 dante ccb->sghead.sg_list[nsegs].addr =
791 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
792 1.1 dante ccb->sghead.sg_list[nsegs].bytes =
793 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
794 1.1 dante }
795 1.1 dante
796 1.1 dante ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
797 1.1 dante ccb->dmamap_xfer->dm_nsegs;
798 1.1 dante
799 1.1 dante ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
800 1.1 dante ccb->scsiq.sg_head = &ccb->sghead;
801 1.1 dante ccb->scsiq.q1.data_addr = 0;
802 1.1 dante ccb->scsiq.q1.data_cnt = 0;
803 1.1 dante } else {
804 1.1 dante /*
805 1.1 dante * No data xfer, use non S/G values.
806 1.1 dante */
807 1.1 dante ccb->scsiq.q1.data_addr = 0;
808 1.1 dante ccb->scsiq.q1.data_cnt = 0;
809 1.1 dante }
810 1.1 dante
811 1.1 dante s = splbio();
812 1.1 dante adv_queue_ccb(sc, ccb);
813 1.1 dante splx(s);
814 1.1 dante
815 1.1 dante /*
816 1.1 dante * Usually return SUCCESSFULLY QUEUED
817 1.1 dante */
818 1.1 dante if ((flags & SCSI_POLL) == 0)
819 1.1 dante return (SUCCESSFULLY_QUEUED);
820 1.1 dante
821 1.1 dante /*
822 1.1 dante * If we can't use interrupts, poll on completion
823 1.1 dante */
824 1.1 dante if (adv_poll(sc, xs, ccb->timeout)) {
825 1.1 dante adv_timeout(ccb);
826 1.1 dante if (adv_poll(sc, xs, ccb->timeout))
827 1.1 dante adv_timeout(ccb);
828 1.1 dante }
829 1.1 dante return (COMPLETE);
830 1.1 dante }
831 1.1 dante
832 1.1 dante
833 1.1 dante int
834 1.1 dante adv_intr(arg)
835 1.1 dante void *arg;
836 1.1 dante {
837 1.1 dante ASC_SOFTC *sc = arg;
838 1.1 dante struct scsipi_xfer *xs;
839 1.1 dante
840 1.1 dante if (ASC_IS_NARROW_BOARD(sc)) {
841 1.1 dante AscISR(sc);
842 1.1 dante } else
843 1.1 dante //Wide Boards
844 1.1 dante {
845 1.1 dante /* ToDo AdvISR */
846 1.1 dante }
847 1.1 dante
848 1.1 dante /*
849 1.1 dante * If there are queue entries in the software queue, try to
850 1.1 dante * run the first one. We should be more or less guaranteed
851 1.1 dante * to succeed, since we just freed a CCB.
852 1.1 dante *
853 1.1 dante * NOTE: adv_scsi_cmd() relies on our calling it with
854 1.1 dante * the first entry in the queue.
855 1.1 dante */
856 1.1 dante if ((xs = sc->sc_queue.lh_first) != NULL)
857 1.1 dante (void) adv_scsi_cmd(xs);
858 1.1 dante
859 1.1 dante return (1);
860 1.1 dante }
861 1.1 dante
862 1.1 dante
863 1.1 dante /*
864 1.1 dante * Poll a particular unit, looking for a particular xs
865 1.1 dante */
866 1.1 dante static int
867 1.1 dante adv_poll(sc, xs, count)
868 1.1 dante ASC_SOFTC *sc;
869 1.1 dante struct scsipi_xfer *xs;
870 1.1 dante int count;
871 1.1 dante {
872 1.1 dante
873 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
874 1.1 dante while (count) {
875 1.1 dante adv_intr(sc);
876 1.1 dante if (xs->flags & ITSDONE)
877 1.1 dante return (0);
878 1.1 dante delay(1000); /* only happens in boot so ok */
879 1.1 dante count--;
880 1.1 dante }
881 1.1 dante return (1);
882 1.1 dante }
883 1.1 dante
884 1.1 dante
885 1.1 dante static void
886 1.1 dante adv_timeout(arg)
887 1.1 dante void *arg;
888 1.1 dante {
889 1.1 dante ADV_CCB *ccb = arg;
890 1.1 dante struct scsipi_xfer *xs = ccb->xs;
891 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
892 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
893 1.1 dante int s;
894 1.1 dante
895 1.1 dante scsi_print_addr(sc_link);
896 1.1 dante printf("timed out");
897 1.1 dante
898 1.1 dante s = splbio();
899 1.1 dante
900 1.1 dante /*
901 1.1 dante * If it has been through before, then a previous abort has failed,
902 1.1 dante * don't try abort again, reset the bus instead.
903 1.1 dante */
904 1.1 dante if (ccb->flags & CCB_ABORT) {
905 1.1 dante /* abort timed out */
906 1.1 dante printf(" AGAIN. Resetting Bus\n");
907 1.1 dante /* Lets try resetting the bus! */
908 1.1 dante if (AscResetBus(sc) == ASC_ERROR) {
909 1.1 dante ccb->timeout = sc->scsi_reset_wait;
910 1.1 dante adv_queue_ccb(sc, ccb);
911 1.1 dante }
912 1.1 dante } else {
913 1.1 dante /* abort the operation that has timed out */
914 1.1 dante printf("\n");
915 1.1 dante AscAbortCCB(sc, (u_int32_t) ccb);
916 1.1 dante ccb->xs->error = XS_TIMEOUT;
917 1.1 dante ccb->timeout = ADV_ABORT_TIMEOUT;
918 1.1 dante ccb->flags |= CCB_ABORT;
919 1.1 dante adv_queue_ccb(sc, ccb);
920 1.1 dante }
921 1.1 dante
922 1.1 dante splx(s);
923 1.1 dante }
924 1.1 dante
925 1.1 dante
926 1.1 dante static void
927 1.1 dante adv_watchdog(arg)
928 1.1 dante void *arg;
929 1.1 dante {
930 1.1 dante ADV_CCB *ccb = arg;
931 1.1 dante struct scsipi_xfer *xs = ccb->xs;
932 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
933 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
934 1.1 dante int s;
935 1.1 dante
936 1.1 dante s = splbio();
937 1.1 dante
938 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
939 1.1 dante adv_start_ccbs(sc);
940 1.1 dante
941 1.1 dante splx(s);
942 1.1 dante }
943 1.1 dante
944 1.1 dante
945 1.1 dante /******************************************************************************/
946 1.1 dante /* NARROW and WIDE boards Interrupt callbacks */
947 1.1 dante /******************************************************************************/
948 1.1 dante
949 1.1 dante
950 1.1 dante /*
951 1.1 dante * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
952 1.1 dante *
953 1.1 dante * Interrupt callback function for the Narrow SCSI Asc Library.
954 1.1 dante */
955 1.1 dante static void
956 1.1 dante adv_narrow_isr_callback(sc, qdonep)
957 1.1 dante ASC_SOFTC *sc;
958 1.1 dante ASC_QDONE_INFO *qdonep;
959 1.1 dante {
960 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
961 1.1 dante ADV_CCB *ccb = (ADV_CCB *) qdonep->d2.ccb_ptr;
962 1.1 dante struct scsipi_xfer *xs = ccb->xs;
963 1.1 dante struct scsipi_sense_data *s1, *s2;
964 1.1 dante
965 1.1 dante
966 1.1 dante untimeout(adv_timeout, ccb);
967 1.1 dante
968 1.1 dante /*
969 1.1 dante * If we were a data transfer, unload the map that described
970 1.1 dante * the data buffer.
971 1.1 dante */
972 1.1 dante if (xs->datalen) {
973 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
974 1.1 dante ccb->dmamap_xfer->dm_mapsize,
975 1.1 dante (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
976 1.1 dante BUS_DMASYNC_POSTWRITE);
977 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
978 1.1 dante }
979 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
980 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
981 1.1 dante Debugger();
982 1.1 dante return;
983 1.1 dante }
984 1.1 dante /*
985 1.1 dante * 'qdonep' contains the command's ending status.
986 1.1 dante */
987 1.1 dante switch (qdonep->d3.done_stat) {
988 1.1 dante case ASC_QD_NO_ERROR:
989 1.1 dante switch (qdonep->d3.host_stat) {
990 1.1 dante case ASC_QHSTA_NO_ERROR:
991 1.1 dante xs->error = XS_NOERROR;
992 1.1 dante xs->resid = 0;
993 1.1 dante break;
994 1.1 dante
995 1.1 dante default:
996 1.1 dante /* QHSTA error occurred */
997 1.1 dante xs->error = XS_DRIVER_STUFFUP;
998 1.1 dante break;
999 1.1 dante }
1000 1.1 dante
1001 1.1 dante /*
1002 1.1 dante * If an INQUIRY command completed successfully, then call
1003 1.1 dante * the AscInquiryHandling() function to patch bugged boards.
1004 1.1 dante */
1005 1.1 dante if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
1006 1.1 dante (xs->sc_link->scsipi_scsi.lun == 0) &&
1007 1.1 dante (xs->datalen - qdonep->remain_bytes) >= 8) {
1008 1.1 dante AscInquiryHandling(sc,
1009 1.1 dante xs->sc_link->scsipi_scsi.target & 0x7,
1010 1.1 dante (ASC_SCSI_INQUIRY *) xs->data);
1011 1.1 dante }
1012 1.1 dante break;
1013 1.1 dante
1014 1.1 dante case ASC_QD_WITH_ERROR:
1015 1.1 dante switch (qdonep->d3.host_stat) {
1016 1.1 dante case ASC_QHSTA_NO_ERROR:
1017 1.1 dante if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
1018 1.1 dante s1 = &ccb->scsi_sense;
1019 1.1 dante s2 = &xs->sense.scsi_sense;
1020 1.1 dante *s2 = *s1;
1021 1.1 dante xs->error = XS_SENSE;
1022 1.1 dante } else
1023 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1024 1.1 dante break;
1025 1.1 dante
1026 1.1 dante default:
1027 1.1 dante /* QHSTA error occurred */
1028 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1029 1.1 dante break;
1030 1.1 dante }
1031 1.1 dante break;
1032 1.1 dante
1033 1.1 dante case ASC_QD_ABORTED_BY_HOST:
1034 1.1 dante default:
1035 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1036 1.1 dante break;
1037 1.1 dante }
1038 1.1 dante
1039 1.1 dante
1040 1.1 dante adv_free_ccb(sc, ccb);
1041 1.1 dante xs->flags |= ITSDONE;
1042 1.1 dante scsipi_done(xs);
1043 1.1 dante }
1044