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adv.c revision 1.20.2.5
      1  1.20.2.5  nathanw /*	$NetBSD: adv.c,v 1.20.2.5 2002/01/08 00:29:28 nathanw Exp $	*/
      2       1.2    dante 
      3       1.1    dante /*
      4       1.4    dante  * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
      5       1.1    dante  *
      6       1.1    dante  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      7       1.1    dante  * All rights reserved.
      8       1.1    dante  *
      9       1.1    dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10       1.1    dante  *
     11       1.1    dante  * Redistribution and use in source and binary forms, with or without
     12       1.1    dante  * modification, are permitted provided that the following conditions
     13       1.1    dante  * are met:
     14       1.1    dante  * 1. Redistributions of source code must retain the above copyright
     15       1.1    dante  *    notice, this list of conditions and the following disclaimer.
     16       1.1    dante  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1    dante  *    notice, this list of conditions and the following disclaimer in the
     18       1.1    dante  *    documentation and/or other materials provided with the distribution.
     19       1.1    dante  * 3. All advertising materials mentioning features or use of this software
     20       1.1    dante  *    must display the following acknowledgement:
     21       1.4    dante  *        This product includes software developed by the NetBSD
     22       1.4    dante  *        Foundation, Inc. and its contributors.
     23       1.1    dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24       1.1    dante  *    contributors may be used to endorse or promote products derived
     25       1.1    dante  *    from this software without specific prior written permission.
     26       1.1    dante  *
     27       1.1    dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28       1.1    dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29       1.1    dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30       1.1    dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31       1.1    dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32       1.1    dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33       1.1    dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34       1.1    dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35       1.1    dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36       1.1    dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37       1.1    dante  * POSSIBILITY OF SUCH DAMAGE.
     38       1.1    dante  */
     39  1.20.2.4  nathanw 
     40  1.20.2.4  nathanw #include <sys/cdefs.h>
     41  1.20.2.5  nathanw __KERNEL_RCSID(0, "$NetBSD: adv.c,v 1.20.2.5 2002/01/08 00:29:28 nathanw Exp $");
     42       1.1    dante 
     43       1.1    dante #include <sys/param.h>
     44       1.1    dante #include <sys/systm.h>
     45      1.16  thorpej #include <sys/callout.h>
     46       1.1    dante #include <sys/kernel.h>
     47       1.1    dante #include <sys/errno.h>
     48       1.1    dante #include <sys/ioctl.h>
     49       1.1    dante #include <sys/device.h>
     50       1.1    dante #include <sys/malloc.h>
     51       1.1    dante #include <sys/buf.h>
     52       1.1    dante #include <sys/proc.h>
     53       1.1    dante #include <sys/user.h>
     54       1.1    dante 
     55       1.1    dante #include <machine/bus.h>
     56       1.1    dante #include <machine/intr.h>
     57       1.1    dante 
     58      1.18      mrg #include <uvm/uvm_extern.h>
     59       1.1    dante 
     60       1.1    dante #include <dev/scsipi/scsi_all.h>
     61       1.1    dante #include <dev/scsipi/scsipi_all.h>
     62       1.1    dante #include <dev/scsipi/scsiconf.h>
     63       1.1    dante 
     64      1.10    dante #include <dev/ic/advlib.h>
     65       1.1    dante #include <dev/ic/adv.h>
     66       1.3  thorpej 
     67       1.3  thorpej #ifndef DDB
     68       1.3  thorpej #define	Debugger()	panic("should call debugger here (adv.c)")
     69       1.3  thorpej #endif /* ! DDB */
     70       1.1    dante 
     71       1.6    dante 
     72       1.6    dante /* #define ASC_DEBUG */
     73       1.6    dante 
     74       1.1    dante /******************************************************************************/
     75       1.1    dante 
     76       1.1    dante 
     77      1.13  thorpej static int adv_alloc_control_data __P((ASC_SOFTC *));
     78  1.20.2.1  nathanw static void adv_free_control_data __P((ASC_SOFTC *));
     79       1.1    dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
     80       1.1    dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
     81       1.1    dante static void adv_reset_ccb __P((ADV_CCB *));
     82       1.1    dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
     83  1.20.2.2  nathanw static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *));
     84       1.1    dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
     85       1.1    dante static void adv_start_ccbs __P((ASC_SOFTC *));
     86       1.1    dante 
     87       1.1    dante 
     88  1.20.2.2  nathanw static void adv_scsipi_request __P((struct scsipi_channel *,
     89  1.20.2.2  nathanw 	scsipi_adapter_req_t, void *));
     90       1.1    dante static void advminphys __P((struct buf *));
     91       1.1    dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
     92       1.1    dante 
     93       1.1    dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
     94       1.1    dante static void adv_timeout __P((void *));
     95       1.1    dante static void adv_watchdog __P((void *));
     96       1.1    dante 
     97       1.1    dante 
     98       1.1    dante /******************************************************************************/
     99       1.1    dante 
    100       1.1    dante #define ADV_ABORT_TIMEOUT       2000	/* time to wait for abort (mSec) */
    101       1.1    dante #define ADV_WATCH_TIMEOUT       1000	/* time to wait for watchdog (mSec) */
    102       1.1    dante 
    103       1.1    dante /******************************************************************************/
    104       1.1    dante /*                             Control Blocks routines                        */
    105       1.1    dante /******************************************************************************/
    106       1.1    dante 
    107       1.1    dante 
    108       1.1    dante static int
    109      1.13  thorpej adv_alloc_control_data(sc)
    110       1.1    dante 	ASC_SOFTC      *sc;
    111       1.1    dante {
    112  1.20.2.1  nathanw 	int error;
    113       1.1    dante 
    114       1.1    dante 	/*
    115  1.20.2.2  nathanw  	* Allocate the control blocks.
    116  1.20.2.2  nathanw 	 */
    117       1.1    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
    118  1.20.2.1  nathanw 			   PAGE_SIZE, 0, &sc->sc_control_seg, 1,
    119  1.20.2.1  nathanw 			   &sc->sc_control_nsegs, BUS_DMA_NOWAIT)) != 0) {
    120       1.1    dante 		printf("%s: unable to allocate control structures,"
    121       1.1    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    122       1.1    dante 		return (error);
    123       1.1    dante 	}
    124  1.20.2.1  nathanw 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_control_seg,
    125  1.20.2.1  nathanw 			   sc->sc_control_nsegs, sizeof(struct adv_control),
    126  1.20.2.1  nathanw 			   (caddr_t *) & sc->sc_control,
    127  1.20.2.1  nathanw 			   BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    128       1.1    dante 		printf("%s: unable to map control structures, error = %d\n",
    129       1.1    dante 		       sc->sc_dev.dv_xname, error);
    130       1.1    dante 		return (error);
    131       1.1    dante 	}
    132       1.1    dante 	/*
    133  1.20.2.2  nathanw 	 * Create and load the DMA map used for the control blocks.
    134  1.20.2.2  nathanw 	 */
    135       1.1    dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
    136       1.1    dante 			   1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
    137       1.1    dante 				       &sc->sc_dmamap_control)) != 0) {
    138       1.1    dante 		printf("%s: unable to create control DMA map, error = %d\n",
    139       1.1    dante 		       sc->sc_dev.dv_xname, error);
    140       1.1    dante 		return (error);
    141       1.1    dante 	}
    142       1.1    dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    143       1.1    dante 			   sc->sc_control, sizeof(struct adv_control), NULL,
    144       1.1    dante 				     BUS_DMA_NOWAIT)) != 0) {
    145       1.1    dante 		printf("%s: unable to load control DMA map, error = %d\n",
    146       1.1    dante 		       sc->sc_dev.dv_xname, error);
    147       1.1    dante 		return (error);
    148       1.1    dante 	}
    149      1.13  thorpej 
    150      1.13  thorpej 	/*
    151      1.13  thorpej 	 * Initialize the overrun_buf address.
    152      1.13  thorpej 	 */
    153      1.13  thorpej 	sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    154      1.13  thorpej 	    offsetof(struct adv_control, overrun_buf);
    155      1.13  thorpej 
    156       1.1    dante 	return (0);
    157       1.1    dante }
    158       1.1    dante 
    159  1.20.2.1  nathanw static void
    160  1.20.2.1  nathanw adv_free_control_data(sc)
    161  1.20.2.1  nathanw 	ASC_SOFTC *sc;
    162  1.20.2.1  nathanw {
    163  1.20.2.1  nathanw 
    164  1.20.2.1  nathanw 	bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_control);
    165  1.20.2.1  nathanw 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_control);
    166  1.20.2.1  nathanw 	sc->sc_dmamap_control = NULL;
    167  1.20.2.1  nathanw 
    168  1.20.2.1  nathanw 	bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_control,
    169  1.20.2.1  nathanw 	    sizeof(struct adv_control));
    170  1.20.2.1  nathanw 	bus_dmamem_free(sc->sc_dmat, &sc->sc_control_seg,
    171  1.20.2.1  nathanw 	    sc->sc_control_nsegs);
    172  1.20.2.1  nathanw }
    173       1.1    dante 
    174       1.1    dante /*
    175       1.1    dante  * Create a set of ccbs and add them to the free list.  Called once
    176       1.1    dante  * by adv_init().  We return the number of CCBs successfully created.
    177       1.1    dante  */
    178       1.1    dante static int
    179       1.1    dante adv_create_ccbs(sc, ccbstore, count)
    180       1.1    dante 	ASC_SOFTC      *sc;
    181       1.1    dante 	ADV_CCB        *ccbstore;
    182       1.1    dante 	int             count;
    183       1.1    dante {
    184       1.1    dante 	ADV_CCB        *ccb;
    185       1.1    dante 	int             i, error;
    186       1.1    dante 
    187  1.20.2.3  nathanw 	memset(ccbstore, 0, sizeof(ADV_CCB) * count);
    188       1.1    dante 	for (i = 0; i < count; i++) {
    189       1.1    dante 		ccb = &ccbstore[i];
    190       1.1    dante 		if ((error = adv_init_ccb(sc, ccb)) != 0) {
    191       1.1    dante 			printf("%s: unable to initialize ccb, error = %d\n",
    192       1.1    dante 			       sc->sc_dev.dv_xname, error);
    193       1.1    dante 			return (i);
    194       1.1    dante 		}
    195       1.1    dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    196       1.1    dante 	}
    197       1.1    dante 
    198       1.1    dante 	return (i);
    199       1.1    dante }
    200       1.1    dante 
    201       1.1    dante 
    202       1.1    dante /*
    203       1.1    dante  * A ccb is put onto the free list.
    204       1.1    dante  */
    205       1.1    dante static void
    206       1.1    dante adv_free_ccb(sc, ccb)
    207       1.1    dante 	ASC_SOFTC      *sc;
    208       1.1    dante 	ADV_CCB        *ccb;
    209       1.1    dante {
    210       1.1    dante 	int             s;
    211       1.1    dante 
    212       1.1    dante 	s = splbio();
    213       1.1    dante 	adv_reset_ccb(ccb);
    214       1.1    dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    215       1.1    dante 	splx(s);
    216       1.1    dante }
    217       1.1    dante 
    218       1.1    dante 
    219       1.1    dante static void
    220       1.1    dante adv_reset_ccb(ccb)
    221       1.1    dante 	ADV_CCB        *ccb;
    222       1.1    dante {
    223       1.1    dante 
    224       1.1    dante 	ccb->flags = 0;
    225       1.1    dante }
    226       1.1    dante 
    227       1.1    dante 
    228       1.1    dante static int
    229       1.1    dante adv_init_ccb(sc, ccb)
    230       1.1    dante 	ASC_SOFTC      *sc;
    231       1.1    dante 	ADV_CCB        *ccb;
    232       1.1    dante {
    233      1.10    dante 	int	hashnum, error;
    234       1.1    dante 
    235      1.16  thorpej 	callout_init(&ccb->ccb_watchdog);
    236      1.16  thorpej 
    237       1.1    dante 	/*
    238  1.20.2.2  nathanw 	 * Create the DMA map for this CCB.
    239  1.20.2.2  nathanw 	 */
    240       1.1    dante 	error = bus_dmamap_create(sc->sc_dmat,
    241       1.1    dante 				  (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
    242       1.1    dante 			 ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
    243       1.1    dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    244       1.1    dante 	if (error) {
    245       1.1    dante 		printf("%s: unable to create DMA map, error = %d\n",
    246       1.1    dante 		       sc->sc_dev.dv_xname, error);
    247       1.1    dante 		return (error);
    248       1.1    dante 	}
    249      1.10    dante 
    250      1.10    dante 	/*
    251      1.10    dante 	 * put in the phystokv hash table
    252      1.10    dante 	 * Never gets taken out.
    253      1.10    dante 	 */
    254      1.10    dante 	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    255      1.10    dante 	    ADV_CCB_OFF(ccb);
    256      1.10    dante 	hashnum = CCB_HASH(ccb->hashkey);
    257      1.10    dante 	ccb->nexthash = sc->sc_ccbhash[hashnum];
    258      1.10    dante 	sc->sc_ccbhash[hashnum] = ccb;
    259      1.10    dante 
    260       1.1    dante 	adv_reset_ccb(ccb);
    261       1.1    dante 	return (0);
    262       1.1    dante }
    263       1.1    dante 
    264       1.1    dante 
    265       1.1    dante /*
    266       1.1    dante  * Get a free ccb
    267       1.1    dante  *
    268       1.1    dante  * If there are none, see if we can allocate a new one
    269       1.1    dante  */
    270       1.1    dante static ADV_CCB *
    271  1.20.2.2  nathanw adv_get_ccb(sc)
    272       1.1    dante 	ASC_SOFTC      *sc;
    273       1.1    dante {
    274       1.1    dante 	ADV_CCB        *ccb = 0;
    275       1.1    dante 	int             s;
    276       1.1    dante 
    277       1.1    dante 	s = splbio();
    278  1.20.2.2  nathanw 	ccb = TAILQ_FIRST(&sc->sc_free_ccb);
    279  1.20.2.2  nathanw 	if (ccb != NULL) {
    280  1.20.2.2  nathanw 		TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    281  1.20.2.2  nathanw 		ccb->flags |= CCB_ALLOC;
    282       1.1    dante 	}
    283       1.1    dante 	splx(s);
    284       1.1    dante 	return (ccb);
    285       1.1    dante }
    286       1.1    dante 
    287       1.1    dante 
    288       1.1    dante /*
    289      1.10    dante  * Given a physical address, find the ccb that it corresponds to.
    290      1.10    dante  */
    291      1.10    dante ADV_CCB *
    292      1.10    dante adv_ccb_phys_kv(sc, ccb_phys)
    293      1.10    dante 	ASC_SOFTC	*sc;
    294      1.10    dante 	u_long		ccb_phys;
    295      1.10    dante {
    296      1.10    dante 	int hashnum = CCB_HASH(ccb_phys);
    297      1.10    dante 	ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
    298      1.10    dante 
    299      1.10    dante 	while (ccb) {
    300      1.10    dante 		if (ccb->hashkey == ccb_phys)
    301      1.10    dante 			break;
    302      1.10    dante 		ccb = ccb->nexthash;
    303      1.10    dante 	}
    304      1.10    dante 	return (ccb);
    305      1.10    dante }
    306      1.10    dante 
    307      1.10    dante 
    308      1.10    dante /*
    309       1.1    dante  * Queue a CCB to be sent to the controller, and send it if possible.
    310       1.1    dante  */
    311       1.1    dante static void
    312       1.1    dante adv_queue_ccb(sc, ccb)
    313       1.1    dante 	ASC_SOFTC      *sc;
    314       1.1    dante 	ADV_CCB        *ccb;
    315       1.1    dante {
    316       1.1    dante 
    317       1.1    dante 	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    318       1.1    dante 
    319       1.1    dante 	adv_start_ccbs(sc);
    320       1.1    dante }
    321       1.1    dante 
    322       1.1    dante 
    323       1.1    dante static void
    324       1.1    dante adv_start_ccbs(sc)
    325       1.1    dante 	ASC_SOFTC      *sc;
    326       1.1    dante {
    327       1.1    dante 	ADV_CCB        *ccb;
    328       1.1    dante 
    329       1.1    dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    330       1.1    dante 		if (ccb->flags & CCB_WATCHDOG)
    331      1.16  thorpej 			callout_stop(&ccb->ccb_watchdog);
    332       1.1    dante 
    333       1.1    dante 		if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
    334       1.1    dante 			ccb->flags |= CCB_WATCHDOG;
    335      1.16  thorpej 			callout_reset(&ccb->ccb_watchdog,
    336      1.16  thorpej 			    (ADV_WATCH_TIMEOUT * hz) / 1000,
    337      1.16  thorpej 			    adv_watchdog, ccb);
    338       1.1    dante 			break;
    339       1.1    dante 		}
    340       1.1    dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    341       1.1    dante 
    342      1.14  thorpej 		if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
    343      1.16  thorpej 			callout_reset(&ccb->xs->xs_callout,
    344  1.20.2.1  nathanw 			    ((u_int64_t)ccb->timeout * (u_int64_t)hz) / 1000,
    345      1.16  thorpej 			    adv_timeout, ccb);
    346       1.1    dante 	}
    347       1.1    dante }
    348       1.1    dante 
    349       1.1    dante 
    350       1.1    dante /******************************************************************************/
    351       1.1    dante /*                         SCSI layer interfacing routines                    */
    352       1.1    dante /******************************************************************************/
    353       1.1    dante 
    354       1.1    dante 
    355       1.1    dante int
    356       1.1    dante adv_init(sc)
    357       1.1    dante 	ASC_SOFTC      *sc;
    358       1.1    dante {
    359       1.1    dante 	int             warn;
    360       1.1    dante 
    361      1.12    dante 	if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
    362      1.12    dante 		printf("adv_init: failed to find signature\n");
    363      1.12    dante 		return (1);
    364      1.12    dante 	}
    365       1.1    dante 
    366       1.4    dante 	/*
    367  1.20.2.2  nathanw 	 * Read the board configuration
    368  1.20.2.2  nathanw 	 */
    369       1.4    dante 	AscInitASC_SOFTC(sc);
    370       1.4    dante 	warn = AscInitFromEEP(sc);
    371       1.4    dante 	if (warn) {
    372       1.4    dante 		printf("%s -get: ", sc->sc_dev.dv_xname);
    373       1.4    dante 		switch (warn) {
    374       1.4    dante 		case -1:
    375       1.4    dante 			printf("Chip is not halted\n");
    376       1.4    dante 			break;
    377       1.4    dante 
    378       1.4    dante 		case -2:
    379       1.4    dante 			printf("Couldn't get MicroCode Start"
    380       1.4    dante 			       " address\n");
    381       1.4    dante 			break;
    382       1.4    dante 
    383       1.4    dante 		case ASC_WARN_IO_PORT_ROTATE:
    384       1.4    dante 			printf("I/O port address modified\n");
    385       1.4    dante 			break;
    386       1.4    dante 
    387       1.4    dante 		case ASC_WARN_AUTO_CONFIG:
    388       1.4    dante 			printf("I/O port increment switch enabled\n");
    389       1.4    dante 			break;
    390       1.4    dante 
    391       1.4    dante 		case ASC_WARN_EEPROM_CHKSUM:
    392       1.4    dante 			printf("EEPROM checksum error\n");
    393       1.4    dante 			break;
    394       1.4    dante 
    395       1.4    dante 		case ASC_WARN_IRQ_MODIFIED:
    396       1.4    dante 			printf("IRQ modified\n");
    397       1.4    dante 			break;
    398       1.4    dante 
    399       1.4    dante 		case ASC_WARN_CMD_QNG_CONFLICT:
    400       1.4    dante 			printf("tag queuing enabled w/o disconnects\n");
    401       1.4    dante 			break;
    402       1.1    dante 
    403       1.4    dante 		default:
    404       1.4    dante 			printf("unknown warning %d\n", warn);
    405       1.1    dante 		}
    406       1.4    dante 	}
    407       1.4    dante 	if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
    408       1.4    dante 		sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
    409       1.4    dante 
    410       1.4    dante 	/*
    411  1.20.2.2  nathanw 	 * Modify the board configuration
    412  1.20.2.2  nathanw 	 */
    413       1.4    dante 	warn = AscInitFromASC_SOFTC(sc);
    414       1.4    dante 	if (warn) {
    415       1.4    dante 		printf("%s -set: ", sc->sc_dev.dv_xname);
    416       1.4    dante 		switch (warn) {
    417       1.4    dante 		case ASC_WARN_CMD_QNG_CONFLICT:
    418       1.4    dante 			printf("tag queuing enabled w/o disconnects\n");
    419       1.4    dante 			break;
    420       1.1    dante 
    421       1.4    dante 		case ASC_WARN_AUTO_CONFIG:
    422       1.4    dante 			printf("I/O port increment switch enabled\n");
    423       1.4    dante 			break;
    424       1.1    dante 
    425       1.4    dante 		default:
    426       1.4    dante 			printf("unknown warning %d\n", warn);
    427       1.1    dante 		}
    428       1.4    dante 	}
    429      1.11    dante 	sc->isr_callback = (ASC_CALLBACK) adv_narrow_isr_callback;
    430       1.1    dante 
    431       1.1    dante 	return (0);
    432       1.1    dante }
    433       1.1    dante 
    434       1.1    dante 
    435       1.1    dante void
    436       1.1    dante adv_attach(sc)
    437       1.1    dante 	ASC_SOFTC      *sc;
    438       1.1    dante {
    439  1.20.2.2  nathanw 	struct scsipi_adapter *adapt = &sc->sc_adapter;
    440  1.20.2.2  nathanw 	struct scsipi_channel *chan = &sc->sc_channel;
    441       1.1    dante 	int             i, error;
    442       1.1    dante 
    443       1.4    dante 	/*
    444  1.20.2.2  nathanw 	 * Initialize board RISC chip and enable interrupts.
    445  1.20.2.2  nathanw 	 */
    446       1.4    dante 	switch (AscInitDriver(sc)) {
    447       1.4    dante 	case 0:
    448       1.4    dante 		/* AllOK */
    449       1.4    dante 		break;
    450       1.1    dante 
    451       1.4    dante 	case 1:
    452       1.4    dante 		panic("%s: bad signature", sc->sc_dev.dv_xname);
    453       1.4    dante 		break;
    454       1.1    dante 
    455       1.4    dante 	case 2:
    456       1.4    dante 		panic("%s: unable to load MicroCode",
    457       1.4    dante 		      sc->sc_dev.dv_xname);
    458       1.4    dante 		break;
    459       1.1    dante 
    460       1.4    dante 	case 3:
    461       1.4    dante 		panic("%s: unable to initialize MicroCode",
    462       1.4    dante 		      sc->sc_dev.dv_xname);
    463       1.4    dante 		break;
    464       1.1    dante 
    465       1.4    dante 	default:
    466       1.4    dante 		panic("%s: unable to initialize board RISC chip",
    467       1.4    dante 		      sc->sc_dev.dv_xname);
    468       1.1    dante 	}
    469       1.1    dante 
    470       1.7  thorpej 	/*
    471  1.20.2.2  nathanw 	 * Fill in the scsipi_adapter.
    472       1.7  thorpej 	 */
    473  1.20.2.2  nathanw 	memset(adapt, 0, sizeof(*adapt));
    474  1.20.2.2  nathanw 	adapt->adapt_dev = &sc->sc_dev;
    475  1.20.2.2  nathanw 	adapt->adapt_nchannels = 1;
    476  1.20.2.2  nathanw 	/* adapt_openings initialized below */
    477  1.20.2.2  nathanw 	/* adapt_max_periph initialized below */
    478  1.20.2.2  nathanw 	adapt->adapt_request = adv_scsipi_request;
    479  1.20.2.2  nathanw 	adapt->adapt_minphys = advminphys;
    480       1.1    dante 
    481       1.1    dante 	/*
    482  1.20.2.2  nathanw 	 * Fill in the scsipi_channel.
    483  1.20.2.2  nathanw 	 */
    484  1.20.2.2  nathanw 	memset(chan, 0, sizeof(*chan));
    485  1.20.2.2  nathanw 	chan->chan_adapter = adapt;
    486  1.20.2.2  nathanw 	chan->chan_bustype = &scsi_bustype;
    487  1.20.2.2  nathanw 	chan->chan_channel = 0;
    488  1.20.2.2  nathanw 	chan->chan_ntargets = 8;
    489  1.20.2.2  nathanw 	chan->chan_nluns = 8;
    490  1.20.2.2  nathanw 	chan->chan_id = sc->chip_scsi_id;
    491       1.1    dante 
    492       1.1    dante 	TAILQ_INIT(&sc->sc_free_ccb);
    493       1.1    dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    494       1.1    dante 
    495       1.1    dante 	/*
    496  1.20.2.2  nathanw 	 * Allocate the Control Blocks and the overrun buffer.
    497  1.20.2.2  nathanw 	 */
    498      1.13  thorpej 	error = adv_alloc_control_data(sc);
    499       1.1    dante 	if (error)
    500      1.12    dante 		return; /* (error) */
    501       1.1    dante 
    502       1.1    dante 	/*
    503  1.20.2.2  nathanw 	 * Create and initialize the Control Blocks.
    504  1.20.2.2  nathanw 	 */
    505       1.1    dante 	i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
    506       1.1    dante 	if (i == 0) {
    507       1.1    dante 		printf("%s: unable to create control blocks\n",
    508       1.1    dante 		       sc->sc_dev.dv_xname);
    509       1.1    dante 		return; /* (ENOMEM) */ ;
    510       1.1    dante 	} else if (i != ADV_MAX_CCB) {
    511       1.1    dante 		printf("%s: WARNING: only %d of %d control blocks created\n",
    512       1.1    dante 		       sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
    513       1.1    dante 	}
    514  1.20.2.2  nathanw 
    515  1.20.2.2  nathanw 	adapt->adapt_openings = i;
    516  1.20.2.2  nathanw 	adapt->adapt_max_periph = adapt->adapt_openings;
    517  1.20.2.2  nathanw 
    518  1.20.2.2  nathanw 	sc->sc_child = config_found(&sc->sc_dev, chan, scsiprint);
    519       1.1    dante }
    520       1.1    dante 
    521  1.20.2.1  nathanw int
    522  1.20.2.1  nathanw adv_detach(sc, flags)
    523  1.20.2.1  nathanw 	ASC_SOFTC *sc;
    524  1.20.2.1  nathanw 	int flags;
    525  1.20.2.1  nathanw {
    526  1.20.2.1  nathanw 	int rv = 0;
    527  1.20.2.1  nathanw 
    528  1.20.2.1  nathanw 	if (sc->sc_child != NULL)
    529  1.20.2.1  nathanw 		rv = config_detach(sc->sc_child, flags);
    530  1.20.2.1  nathanw 
    531  1.20.2.1  nathanw 	adv_free_control_data(sc);
    532  1.20.2.1  nathanw 
    533  1.20.2.1  nathanw 	return (rv);
    534  1.20.2.1  nathanw }
    535       1.1    dante 
    536       1.1    dante static void
    537       1.1    dante advminphys(bp)
    538       1.1    dante 	struct buf     *bp;
    539       1.1    dante {
    540       1.1    dante 
    541       1.1    dante 	if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
    542       1.1    dante 		bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
    543       1.1    dante 	minphys(bp);
    544       1.1    dante }
    545       1.1    dante 
    546       1.1    dante 
    547       1.1    dante /*
    548       1.1    dante  * start a scsi operation given the command and the data address.  Also needs
    549       1.1    dante  * the unit, target and lu.
    550       1.1    dante  */
    551       1.1    dante 
    552  1.20.2.2  nathanw static void
    553  1.20.2.2  nathanw adv_scsipi_request(chan, req, arg)
    554  1.20.2.2  nathanw  	struct scsipi_channel *chan;
    555  1.20.2.2  nathanw  	scsipi_adapter_req_t req;
    556  1.20.2.2  nathanw  	void *arg;
    557  1.20.2.2  nathanw {
    558  1.20.2.2  nathanw  	struct scsipi_xfer *xs;
    559  1.20.2.2  nathanw  	struct scsipi_periph *periph;
    560  1.20.2.2  nathanw  	ASC_SOFTC      *sc = (void *)chan->chan_adapter->adapt_dev;
    561  1.20.2.2  nathanw  	bus_dma_tag_t   dmat = sc->sc_dmat;
    562  1.20.2.2  nathanw  	ADV_CCB        *ccb;
    563  1.20.2.2  nathanw  	int             s, flags, error, nsegs;
    564  1.20.2.2  nathanw 
    565  1.20.2.2  nathanw  	switch (req) {
    566  1.20.2.2  nathanw  	case ADAPTER_REQ_RUN_XFER:
    567  1.20.2.2  nathanw  		xs = arg;
    568  1.20.2.2  nathanw  		periph = xs->xs_periph;
    569  1.20.2.2  nathanw  		flags = xs->xs_control;
    570  1.20.2.2  nathanw 
    571  1.20.2.2  nathanw  		/*
    572  1.20.2.2  nathanw  		 * Get a CCB to use.
    573  1.20.2.2  nathanw  		 */
    574  1.20.2.2  nathanw  		ccb = adv_get_ccb(sc);
    575  1.20.2.2  nathanw #ifdef DIAGNOSTIC
    576  1.20.2.2  nathanw  		/*
    577  1.20.2.2  nathanw  		 * This should never happen as we track the resources
    578  1.20.2.2  nathanw  		 * in the mid-layer.
    579  1.20.2.2  nathanw  		 */
    580  1.20.2.2  nathanw  		if (ccb == NULL) {
    581  1.20.2.2  nathanw  			scsipi_printaddr(periph);
    582  1.20.2.2  nathanw  			printf("unable to allocate ccb\n");
    583  1.20.2.2  nathanw  			panic("adv_scsipi_request");
    584  1.20.2.2  nathanw  		}
    585  1.20.2.2  nathanw #endif
    586  1.20.2.2  nathanw 
    587  1.20.2.2  nathanw  		ccb->xs = xs;
    588  1.20.2.2  nathanw  		ccb->timeout = xs->timeout;
    589  1.20.2.2  nathanw 
    590  1.20.2.2  nathanw  		/*
    591  1.20.2.2  nathanw  		 * Build up the request
    592  1.20.2.2  nathanw  		 */
    593  1.20.2.2  nathanw  		memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
    594  1.20.2.2  nathanw 
    595  1.20.2.2  nathanw  		ccb->scsiq.q2.ccb_ptr =
    596  1.20.2.2  nathanw  		    sc->sc_dmamap_control->dm_segs[0].ds_addr +
    597  1.20.2.2  nathanw  		    ADV_CCB_OFF(ccb);
    598  1.20.2.2  nathanw 
    599  1.20.2.2  nathanw  		ccb->scsiq.cdbptr = &xs->cmd->opcode;
    600  1.20.2.2  nathanw  		ccb->scsiq.q2.cdb_len = xs->cmdlen;
    601  1.20.2.2  nathanw  		ccb->scsiq.q1.target_id =
    602  1.20.2.2  nathanw  		    ASC_TID_TO_TARGET_ID(periph->periph_target);
    603  1.20.2.2  nathanw  		ccb->scsiq.q1.target_lun = periph->periph_lun;
    604  1.20.2.2  nathanw  		ccb->scsiq.q2.target_ix =
    605  1.20.2.2  nathanw  		    ASC_TIDLUN_TO_IX(periph->periph_target,
    606  1.20.2.2  nathanw  		    periph->periph_lun);
    607  1.20.2.2  nathanw  		ccb->scsiq.q1.sense_addr =
    608  1.20.2.2  nathanw  		    sc->sc_dmamap_control->dm_segs[0].ds_addr +
    609  1.20.2.2  nathanw  		    ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
    610  1.20.2.2  nathanw  		ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
    611  1.20.2.2  nathanw 
    612  1.20.2.2  nathanw  		/*
    613  1.20.2.2  nathanw  		 * If there are any outstanding requests for the current
    614  1.20.2.2  nathanw  		 * target, then every 255th request send an ORDERED request.
    615  1.20.2.2  nathanw  		 * This heuristic tries to retain the benefit of request
    616  1.20.2.2  nathanw  		 * sorting while preventing request starvation. 255 is the
    617  1.20.2.2  nathanw  		 * max number of tags or pending commands a device may have
    618  1.20.2.2  nathanw  		 * outstanding.
    619  1.20.2.2  nathanw  		 */
    620  1.20.2.2  nathanw  		sc->reqcnt[periph->periph_target]++;
    621  1.20.2.2  nathanw  		if (((sc->reqcnt[periph->periph_target] > 0) &&
    622  1.20.2.2  nathanw  		    (sc->reqcnt[periph->periph_target] % 255) == 0) ||
    623  1.20.2.2  nathanw 		    xs->bp == NULL || (xs->bp->b_flags & B_ASYNC) == 0) {
    624  1.20.2.2  nathanw  			ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
    625  1.20.2.2  nathanw  		} else {
    626  1.20.2.2  nathanw  			ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
    627  1.20.2.2  nathanw  		}
    628  1.20.2.2  nathanw 
    629  1.20.2.2  nathanw  		if (xs->datalen) {
    630  1.20.2.2  nathanw  			/*
    631  1.20.2.2  nathanw  			 * Map the DMA transfer.
    632  1.20.2.2  nathanw  			 */
    633       1.1    dante #ifdef TFS
    634  1.20.2.2  nathanw  			if (flags & SCSI_DATA_UIO) {
    635  1.20.2.2  nathanw  				error = bus_dmamap_load_uio(dmat,
    636  1.20.2.2  nathanw  				    ccb->dmamap_xfer, (struct uio *) xs->data,
    637  1.20.2.2  nathanw 				    ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
    638  1.20.2.3  nathanw 				     BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
    639  1.20.2.3  nathanw 				     ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
    640  1.20.2.3  nathanw 				      BUS_DMA_WRITE));
    641  1.20.2.2  nathanw  			} else
    642  1.20.2.2  nathanw #endif /* TFS */
    643  1.20.2.2  nathanw  			{
    644  1.20.2.2  nathanw  				error = bus_dmamap_load(dmat, ccb->dmamap_xfer,
    645  1.20.2.2  nathanw  				    xs->data, xs->datalen, NULL,
    646  1.20.2.2  nathanw 				    ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
    647  1.20.2.3  nathanw 				     BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
    648  1.20.2.3  nathanw 				     ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
    649  1.20.2.3  nathanw 				      BUS_DMA_WRITE));
    650  1.20.2.2  nathanw  			}
    651  1.20.2.2  nathanw 
    652  1.20.2.2  nathanw  			switch (error) {
    653  1.20.2.2  nathanw  			case 0:
    654  1.20.2.2  nathanw  				break;
    655  1.20.2.2  nathanw 
    656  1.20.2.2  nathanw 
    657  1.20.2.2  nathanw  			case ENOMEM:
    658  1.20.2.2  nathanw  			case EAGAIN:
    659  1.20.2.2  nathanw  				xs->error = XS_RESOURCE_SHORTAGE;
    660  1.20.2.2  nathanw  				goto out_bad;
    661  1.20.2.2  nathanw 
    662  1.20.2.2  nathanw  			default:
    663  1.20.2.2  nathanw  				xs->error = XS_DRIVER_STUFFUP;
    664  1.20.2.2  nathanw 				if (error == EFBIG) {
    665  1.20.2.2  nathanw 					printf("%s: adv_scsi_cmd, more than %d"
    666  1.20.2.2  nathanw 					    " dma segments\n",
    667  1.20.2.2  nathanw 					    sc->sc_dev.dv_xname,
    668  1.20.2.2  nathanw 					    ASC_MAX_SG_LIST);
    669  1.20.2.2  nathanw 				} else {
    670  1.20.2.2  nathanw 					printf("%s: adv_scsi_cmd, error %d"
    671  1.20.2.2  nathanw 					    " loading dma map\n",
    672  1.20.2.2  nathanw 					    sc->sc_dev.dv_xname, error);
    673  1.20.2.2  nathanw 				}
    674  1.20.2.2  nathanw 
    675  1.20.2.2  nathanw out_bad:
    676  1.20.2.2  nathanw  				adv_free_ccb(sc, ccb);
    677  1.20.2.2  nathanw  				scsipi_done(xs);
    678  1.20.2.2  nathanw  				return;
    679  1.20.2.2  nathanw  			}
    680  1.20.2.2  nathanw  			bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    681  1.20.2.2  nathanw  			    ccb->dmamap_xfer->dm_mapsize,
    682  1.20.2.2  nathanw  			    (flags & XS_CTL_DATA_IN) ?
    683  1.20.2.2  nathanw  			     BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
    684  1.20.2.2  nathanw 
    685  1.20.2.2  nathanw  			memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
    686  1.20.2.2  nathanw 
    687  1.20.2.2  nathanw  			for (nsegs = 0;
    688  1.20.2.2  nathanw  			     nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
    689  1.20.2.2  nathanw  				ccb->sghead.sg_list[nsegs].addr =
    690  1.20.2.2  nathanw  				    ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
    691  1.20.2.2  nathanw  				ccb->sghead.sg_list[nsegs].bytes =
    692  1.20.2.2  nathanw  				    ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
    693  1.20.2.2  nathanw  			}
    694  1.20.2.2  nathanw 
    695  1.20.2.2  nathanw  			ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
    696  1.20.2.2  nathanw  			    ccb->dmamap_xfer->dm_nsegs;
    697  1.20.2.2  nathanw 
    698  1.20.2.2  nathanw  			ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
    699  1.20.2.2  nathanw  			ccb->scsiq.sg_head = &ccb->sghead;
    700  1.20.2.2  nathanw  			ccb->scsiq.q1.data_addr = 0;
    701  1.20.2.2  nathanw  			ccb->scsiq.q1.data_cnt = 0;
    702  1.20.2.2  nathanw  		} else {
    703  1.20.2.2  nathanw  			/*
    704  1.20.2.2  nathanw  			 * No data xfer, use non S/G values.
    705  1.20.2.2  nathanw  			 */
    706  1.20.2.2  nathanw  			ccb->scsiq.q1.data_addr = 0;
    707  1.20.2.2  nathanw  			ccb->scsiq.q1.data_cnt = 0;
    708  1.20.2.2  nathanw  		}
    709  1.20.2.2  nathanw 
    710       1.6    dante #ifdef ASC_DEBUG
    711  1.20.2.2  nathanw  		printf("id = 0, lun = 0, cmd = 0, ccb = 0x0 \n",
    712  1.20.2.2  nathanw  		    periph->periph_target,
    713  1.20.2.2  nathanw  		    periph->periph_lun, xs->cmd->opcode,
    714  1.20.2.2  nathanw  		    (unsigned long)ccb);
    715       1.6    dante #endif
    716  1.20.2.2  nathanw  		s = splbio();
    717  1.20.2.2  nathanw  		adv_queue_ccb(sc, ccb);
    718  1.20.2.2  nathanw  		splx(s);
    719  1.20.2.2  nathanw 
    720  1.20.2.2  nathanw  		if ((flags & XS_CTL_POLL) == 0)
    721  1.20.2.2  nathanw  			return;
    722  1.20.2.2  nathanw 
    723  1.20.2.2  nathanw  		/* Not allowed to use interrupts, poll for completion. */
    724  1.20.2.2  nathanw  		if (adv_poll(sc, xs, ccb->timeout)) {
    725  1.20.2.2  nathanw  			adv_timeout(ccb);
    726  1.20.2.2  nathanw  			if (adv_poll(sc, xs, ccb->timeout))
    727  1.20.2.2  nathanw  				adv_timeout(ccb);
    728  1.20.2.2  nathanw  		}
    729  1.20.2.2  nathanw  		return;
    730  1.20.2.2  nathanw 
    731  1.20.2.2  nathanw  	case ADAPTER_REQ_GROW_RESOURCES:
    732  1.20.2.2  nathanw  		/* XXX Not supported. */
    733  1.20.2.2  nathanw  		return;
    734  1.20.2.2  nathanw 
    735  1.20.2.2  nathanw  	case ADAPTER_REQ_SET_XFER_MODE:
    736  1.20.2.2  nathanw  	    {
    737  1.20.2.2  nathanw  		/*
    738  1.20.2.2  nathanw  		 * We can't really set the mode, but we know how to
    739  1.20.2.2  nathanw  		 * query what the firmware negotiated.
    740  1.20.2.2  nathanw  		 */
    741  1.20.2.2  nathanw  		struct scsipi_xfer_mode *xm = arg;
    742  1.20.2.2  nathanw  		u_int8_t sdtr_data;
    743  1.20.2.2  nathanw  		ASC_SCSI_BIT_ID_TYPE tid_bit;
    744  1.20.2.2  nathanw 
    745  1.20.2.2  nathanw  		tid_bit = ASC_TIX_TO_TARGET_ID(xm->xm_target);
    746  1.20.2.2  nathanw 
    747  1.20.2.2  nathanw  		xm->xm_mode = 0;
    748  1.20.2.2  nathanw  		xm->xm_period = 0;
    749  1.20.2.2  nathanw  		xm->xm_offset = 0;
    750  1.20.2.2  nathanw 
    751  1.20.2.2  nathanw  		if (sc->init_sdtr & tid_bit) {
    752  1.20.2.2  nathanw  			xm->xm_mode |= PERIPH_CAP_SYNC;
    753  1.20.2.2  nathanw  			sdtr_data = sc->sdtr_data[xm->xm_target];
    754  1.20.2.2  nathanw  			xm->xm_period =
    755  1.20.2.2  nathanw  			    sc->sdtr_period_tbl[(sdtr_data >> 4) &
    756  1.20.2.2  nathanw  			    (sc->max_sdtr_index - 1)];
    757  1.20.2.2  nathanw  			xm->xm_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
    758  1.20.2.2  nathanw  		}
    759  1.20.2.2  nathanw 
    760  1.20.2.2  nathanw  		if (sc->use_tagged_qng & tid_bit)
    761  1.20.2.2  nathanw  			xm->xm_mode |= PERIPH_CAP_TQING;
    762  1.20.2.2  nathanw 
    763  1.20.2.2  nathanw  		scsipi_async_event(chan, ASYNC_EVENT_XFER_MODE, xm);
    764  1.20.2.2  nathanw  		return;
    765  1.20.2.2  nathanw  	    }
    766  1.20.2.2  nathanw  	}
    767       1.1    dante }
    768       1.1    dante 
    769       1.1    dante int
    770       1.1    dante adv_intr(arg)
    771       1.1    dante 	void           *arg;
    772       1.1    dante {
    773       1.1    dante 	ASC_SOFTC      *sc = arg;
    774       1.1    dante 
    775       1.6    dante #ifdef ASC_DEBUG
    776       1.6    dante 	int int_pend = FALSE;
    777       1.6    dante 
    778       1.6    dante 	if(ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh))
    779       1.6    dante 	{
    780       1.6    dante 		int_pend = TRUE;
    781       1.6    dante 		printf("ISR - ");
    782       1.6    dante 	}
    783       1.6    dante #endif
    784       1.4    dante 	AscISR(sc);
    785       1.6    dante #ifdef ASC_DEBUG
    786       1.6    dante 	if(int_pend)
    787       1.6    dante 		printf("\n");
    788       1.6    dante #endif
    789       1.1    dante 
    790       1.1    dante 	return (1);
    791       1.1    dante }
    792       1.1    dante 
    793       1.1    dante 
    794       1.1    dante /*
    795       1.1    dante  * Poll a particular unit, looking for a particular xs
    796       1.1    dante  */
    797       1.1    dante static int
    798       1.1    dante adv_poll(sc, xs, count)
    799       1.1    dante 	ASC_SOFTC      *sc;
    800       1.1    dante 	struct scsipi_xfer *xs;
    801       1.1    dante 	int             count;
    802       1.1    dante {
    803       1.1    dante 
    804       1.1    dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
    805       1.1    dante 	while (count) {
    806       1.1    dante 		adv_intr(sc);
    807      1.14  thorpej 		if (xs->xs_status & XS_STS_DONE)
    808       1.1    dante 			return (0);
    809       1.1    dante 		delay(1000);	/* only happens in boot so ok */
    810       1.1    dante 		count--;
    811       1.1    dante 	}
    812       1.1    dante 	return (1);
    813       1.1    dante }
    814       1.1    dante 
    815       1.1    dante 
    816       1.1    dante static void
    817       1.1    dante adv_timeout(arg)
    818       1.1    dante 	void           *arg;
    819       1.1    dante {
    820       1.1    dante 	ADV_CCB        *ccb = arg;
    821       1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    822  1.20.2.2  nathanw 	struct scsipi_periph *periph = xs->xs_periph;
    823  1.20.2.2  nathanw 	ASC_SOFTC      *sc =
    824  1.20.2.2  nathanw 	    (void *)periph->periph_channel->chan_adapter->adapt_dev;
    825       1.1    dante 	int             s;
    826       1.1    dante 
    827  1.20.2.2  nathanw 	scsipi_printaddr(periph);
    828       1.1    dante 	printf("timed out");
    829       1.1    dante 
    830       1.1    dante 	s = splbio();
    831       1.1    dante 
    832       1.1    dante 	/*
    833  1.20.2.2  nathanw 	 * If it has been through before, then a previous abort has failed,
    834  1.20.2.2  nathanw 	 * don't try abort again, reset the bus instead.
    835  1.20.2.2  nathanw 	 */
    836       1.1    dante 	if (ccb->flags & CCB_ABORT) {
    837       1.1    dante 		/* abort timed out */
    838       1.1    dante 		printf(" AGAIN. Resetting Bus\n");
    839       1.1    dante 		/* Lets try resetting the bus! */
    840       1.1    dante 		if (AscResetBus(sc) == ASC_ERROR) {
    841       1.1    dante 			ccb->timeout = sc->scsi_reset_wait;
    842       1.1    dante 			adv_queue_ccb(sc, ccb);
    843       1.1    dante 		}
    844       1.1    dante 	} else {
    845       1.1    dante 		/* abort the operation that has timed out */
    846       1.1    dante 		printf("\n");
    847      1.10    dante 		AscAbortCCB(sc, ccb);
    848       1.1    dante 		ccb->xs->error = XS_TIMEOUT;
    849       1.1    dante 		ccb->timeout = ADV_ABORT_TIMEOUT;
    850       1.1    dante 		ccb->flags |= CCB_ABORT;
    851       1.1    dante 		adv_queue_ccb(sc, ccb);
    852       1.1    dante 	}
    853       1.1    dante 
    854       1.1    dante 	splx(s);
    855       1.1    dante }
    856       1.1    dante 
    857       1.1    dante 
    858       1.1    dante static void
    859       1.1    dante adv_watchdog(arg)
    860       1.1    dante 	void           *arg;
    861       1.1    dante {
    862       1.1    dante 	ADV_CCB        *ccb = arg;
    863       1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    864  1.20.2.2  nathanw 	struct scsipi_periph *periph = xs->xs_periph;
    865  1.20.2.2  nathanw 	ASC_SOFTC      *sc =
    866  1.20.2.2  nathanw 	    (void *)periph->periph_channel->chan_adapter->adapt_dev;
    867       1.1    dante 	int             s;
    868       1.1    dante 
    869       1.1    dante 	s = splbio();
    870       1.1    dante 
    871       1.1    dante 	ccb->flags &= ~CCB_WATCHDOG;
    872       1.1    dante 	adv_start_ccbs(sc);
    873       1.1    dante 
    874       1.1    dante 	splx(s);
    875       1.1    dante }
    876       1.1    dante 
    877       1.1    dante 
    878       1.1    dante /******************************************************************************/
    879      1.10    dante /*                      NARROW boards Interrupt callbacks                     */
    880       1.1    dante /******************************************************************************/
    881       1.1    dante 
    882       1.1    dante 
    883       1.1    dante /*
    884       1.1    dante  * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
    885       1.1    dante  *
    886       1.1    dante  * Interrupt callback function for the Narrow SCSI Asc Library.
    887       1.1    dante  */
    888       1.1    dante static void
    889       1.1    dante adv_narrow_isr_callback(sc, qdonep)
    890       1.1    dante 	ASC_SOFTC      *sc;
    891       1.1    dante 	ASC_QDONE_INFO *qdonep;
    892       1.1    dante {
    893       1.1    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    894      1.10    dante 	ADV_CCB        *ccb;
    895      1.10    dante 	struct scsipi_xfer *xs;
    896       1.1    dante 	struct scsipi_sense_data *s1, *s2;
    897       1.1    dante 
    898      1.10    dante 
    899      1.10    dante 	ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
    900      1.10    dante 	xs = ccb->xs;
    901       1.1    dante 
    902       1.6    dante #ifdef ASC_DEBUG
    903       1.6    dante 	printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
    904       1.6    dante 			(unsigned long)ccb,
    905  1.20.2.2  nathanw 			xs->xs_periph->periph_target,
    906  1.20.2.2  nathanw 			xs->xs_periph->periph_lun, xs->cmd->opcode);
    907       1.6    dante #endif
    908      1.16  thorpej 	callout_stop(&ccb->xs->xs_callout);
    909       1.1    dante 
    910       1.1    dante 	/*
    911  1.20.2.2  nathanw 	 * If we were a data transfer, unload the map that described
    912  1.20.2.2  nathanw 	 * the data buffer.
    913  1.20.2.2  nathanw 	 */
    914       1.1    dante 	if (xs->datalen) {
    915       1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    916       1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    917      1.14  thorpej 			 (xs->xs_control & XS_CTL_DATA_IN) ?
    918      1.14  thorpej 			 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
    919       1.1    dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
    920       1.1    dante 	}
    921       1.1    dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
    922       1.1    dante 		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
    923       1.1    dante 		Debugger();
    924       1.1    dante 		return;
    925       1.1    dante 	}
    926       1.1    dante 	/*
    927  1.20.2.2  nathanw 	 * 'qdonep' contains the command's ending status.
    928  1.20.2.2  nathanw 	 */
    929       1.6    dante #ifdef ASC_DEBUG
    930       1.6    dante 	printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
    931       1.6    dante #endif
    932       1.1    dante 	switch (qdonep->d3.done_stat) {
    933       1.1    dante 	case ASC_QD_NO_ERROR:
    934       1.1    dante 		switch (qdonep->d3.host_stat) {
    935       1.1    dante 		case ASC_QHSTA_NO_ERROR:
    936       1.1    dante 			xs->error = XS_NOERROR;
    937       1.1    dante 			xs->resid = 0;
    938       1.1    dante 			break;
    939       1.1    dante 
    940       1.1    dante 		default:
    941       1.1    dante 			/* QHSTA error occurred */
    942       1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    943       1.1    dante 			break;
    944       1.1    dante 		}
    945       1.1    dante 
    946       1.1    dante 		/*
    947  1.20.2.2  nathanw 	         * If an INQUIRY command completed successfully, then call
    948  1.20.2.2  nathanw 	         * the AscInquiryHandling() function to patch bugged boards.
    949  1.20.2.2  nathanw 	         */
    950       1.1    dante 		if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
    951  1.20.2.2  nathanw 		    (xs->xs_periph->periph_lun == 0) &&
    952       1.1    dante 		    (xs->datalen - qdonep->remain_bytes) >= 8) {
    953       1.1    dante 			AscInquiryHandling(sc,
    954  1.20.2.2  nathanw 				      xs->xs_periph->periph_target & 0x7,
    955       1.1    dante 					   (ASC_SCSI_INQUIRY *) xs->data);
    956       1.1    dante 		}
    957       1.1    dante 		break;
    958       1.1    dante 
    959       1.1    dante 	case ASC_QD_WITH_ERROR:
    960       1.1    dante 		switch (qdonep->d3.host_stat) {
    961       1.1    dante 		case ASC_QHSTA_NO_ERROR:
    962       1.1    dante 			if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
    963       1.1    dante 				s1 = &ccb->scsi_sense;
    964       1.1    dante 				s2 = &xs->sense.scsi_sense;
    965       1.1    dante 				*s2 = *s1;
    966       1.1    dante 				xs->error = XS_SENSE;
    967       1.4    dante 			} else {
    968       1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    969       1.4    dante 			}
    970       1.1    dante 			break;
    971       1.1    dante 
    972  1.20.2.2  nathanw 		case ASC_QHSTA_M_SEL_TIMEOUT:
    973  1.20.2.2  nathanw 			xs->error = XS_SELTIMEOUT;
    974  1.20.2.2  nathanw 			break;
    975  1.20.2.2  nathanw 
    976       1.1    dante 		default:
    977       1.1    dante 			/* QHSTA error occurred */
    978       1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    979       1.1    dante 			break;
    980       1.1    dante 		}
    981       1.1    dante 		break;
    982       1.1    dante 
    983       1.1    dante 	case ASC_QD_ABORTED_BY_HOST:
    984       1.1    dante 	default:
    985       1.1    dante 		xs->error = XS_DRIVER_STUFFUP;
    986       1.1    dante 		break;
    987       1.1    dante 	}
    988       1.1    dante 
    989       1.1    dante 
    990       1.1    dante 	adv_free_ccb(sc, ccb);
    991       1.1    dante 	scsipi_done(xs);
    992       1.1    dante }
    993