adv.c revision 1.22 1 1.22 thorpej /* $NetBSD: adv.c,v 1.22 2001/03/08 06:49:49 thorpej Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.4 dante * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.4 dante * This product includes software developed by the NetBSD
22 1.4 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.16 thorpej #include <sys/callout.h>
44 1.1 dante #include <sys/kernel.h>
45 1.1 dante #include <sys/errno.h>
46 1.1 dante #include <sys/ioctl.h>
47 1.1 dante #include <sys/device.h>
48 1.1 dante #include <sys/malloc.h>
49 1.1 dante #include <sys/buf.h>
50 1.1 dante #include <sys/proc.h>
51 1.1 dante #include <sys/user.h>
52 1.1 dante
53 1.1 dante #include <machine/bus.h>
54 1.1 dante #include <machine/intr.h>
55 1.1 dante
56 1.18 mrg #include <uvm/uvm_extern.h>
57 1.1 dante
58 1.1 dante #include <dev/scsipi/scsi_all.h>
59 1.1 dante #include <dev/scsipi/scsipi_all.h>
60 1.1 dante #include <dev/scsipi/scsiconf.h>
61 1.1 dante
62 1.10 dante #include <dev/ic/advlib.h>
63 1.1 dante #include <dev/ic/adv.h>
64 1.3 thorpej
65 1.3 thorpej #ifndef DDB
66 1.3 thorpej #define Debugger() panic("should call debugger here (adv.c)")
67 1.3 thorpej #endif /* ! DDB */
68 1.1 dante
69 1.6 dante
70 1.6 dante /* #define ASC_DEBUG */
71 1.6 dante
72 1.1 dante /******************************************************************************/
73 1.1 dante
74 1.1 dante
75 1.13 thorpej static int adv_alloc_control_data __P((ASC_SOFTC *));
76 1.22 thorpej static void adv_free_control_data __P((ASC_SOFTC *));
77 1.1 dante static int adv_create_ccbs __P((ASC_SOFTC *, ADV_CCB *, int));
78 1.1 dante static void adv_free_ccb __P((ASC_SOFTC *, ADV_CCB *));
79 1.1 dante static void adv_reset_ccb __P((ADV_CCB *));
80 1.1 dante static int adv_init_ccb __P((ASC_SOFTC *, ADV_CCB *));
81 1.1 dante static ADV_CCB *adv_get_ccb __P((ASC_SOFTC *, int));
82 1.1 dante static void adv_queue_ccb __P((ASC_SOFTC *, ADV_CCB *));
83 1.1 dante static void adv_start_ccbs __P((ASC_SOFTC *));
84 1.1 dante
85 1.1 dante
86 1.1 dante static int adv_scsi_cmd __P((struct scsipi_xfer *));
87 1.1 dante static void advminphys __P((struct buf *));
88 1.1 dante static void adv_narrow_isr_callback __P((ASC_SOFTC *, ASC_QDONE_INFO *));
89 1.1 dante
90 1.1 dante static int adv_poll __P((ASC_SOFTC *, struct scsipi_xfer *, int));
91 1.1 dante static void adv_timeout __P((void *));
92 1.1 dante static void adv_watchdog __P((void *));
93 1.1 dante
94 1.1 dante
95 1.1 dante /******************************************************************************/
96 1.1 dante
97 1.1 dante
98 1.1 dante /* the below structure is so we have a default dev struct for out link struct */
99 1.1 dante struct scsipi_device adv_dev =
100 1.1 dante {
101 1.1 dante NULL, /* Use default error handler */
102 1.1 dante NULL, /* have a queue, served by this */
103 1.1 dante NULL, /* have no async handler */
104 1.1 dante NULL, /* Use default 'done' routine */
105 1.1 dante };
106 1.1 dante
107 1.1 dante
108 1.1 dante #define ADV_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
109 1.1 dante #define ADV_WATCH_TIMEOUT 1000 /* time to wait for watchdog (mSec) */
110 1.1 dante
111 1.1 dante
112 1.1 dante /******************************************************************************/
113 1.1 dante /* Control Blocks routines */
114 1.1 dante /******************************************************************************/
115 1.1 dante
116 1.1 dante
117 1.1 dante static int
118 1.13 thorpej adv_alloc_control_data(sc)
119 1.1 dante ASC_SOFTC *sc;
120 1.1 dante {
121 1.22 thorpej int error;
122 1.1 dante
123 1.1 dante /*
124 1.1 dante * Allocate the control blocks.
125 1.1 dante */
126 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
127 1.22 thorpej PAGE_SIZE, 0, &sc->sc_control_seg, 1,
128 1.22 thorpej &sc->sc_control_nsegs, BUS_DMA_NOWAIT)) != 0) {
129 1.1 dante printf("%s: unable to allocate control structures,"
130 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
131 1.1 dante return (error);
132 1.1 dante }
133 1.22 thorpej if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_control_seg,
134 1.22 thorpej sc->sc_control_nsegs, sizeof(struct adv_control),
135 1.22 thorpej (caddr_t *) & sc->sc_control,
136 1.22 thorpej BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
137 1.1 dante printf("%s: unable to map control structures, error = %d\n",
138 1.1 dante sc->sc_dev.dv_xname, error);
139 1.1 dante return (error);
140 1.1 dante }
141 1.1 dante /*
142 1.1 dante * Create and load the DMA map used for the control blocks.
143 1.1 dante */
144 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
145 1.1 dante 1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
146 1.1 dante &sc->sc_dmamap_control)) != 0) {
147 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
148 1.1 dante sc->sc_dev.dv_xname, error);
149 1.1 dante return (error);
150 1.1 dante }
151 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
152 1.1 dante sc->sc_control, sizeof(struct adv_control), NULL,
153 1.1 dante BUS_DMA_NOWAIT)) != 0) {
154 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
155 1.1 dante sc->sc_dev.dv_xname, error);
156 1.1 dante return (error);
157 1.1 dante }
158 1.13 thorpej
159 1.13 thorpej /*
160 1.13 thorpej * Initialize the overrun_buf address.
161 1.13 thorpej */
162 1.13 thorpej sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
163 1.13 thorpej offsetof(struct adv_control, overrun_buf);
164 1.13 thorpej
165 1.1 dante return (0);
166 1.1 dante }
167 1.1 dante
168 1.22 thorpej static void
169 1.22 thorpej adv_free_control_data(sc)
170 1.22 thorpej ASC_SOFTC *sc;
171 1.22 thorpej {
172 1.22 thorpej
173 1.22 thorpej bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_control);
174 1.22 thorpej bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_control);
175 1.22 thorpej sc->sc_dmamap_control = NULL;
176 1.22 thorpej
177 1.22 thorpej bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_control,
178 1.22 thorpej sizeof(struct adv_control));
179 1.22 thorpej bus_dmamem_free(sc->sc_dmat, &sc->sc_control_seg,
180 1.22 thorpej sc->sc_control_nsegs);
181 1.22 thorpej }
182 1.1 dante
183 1.1 dante /*
184 1.1 dante * Create a set of ccbs and add them to the free list. Called once
185 1.1 dante * by adv_init(). We return the number of CCBs successfully created.
186 1.1 dante */
187 1.1 dante static int
188 1.1 dante adv_create_ccbs(sc, ccbstore, count)
189 1.1 dante ASC_SOFTC *sc;
190 1.1 dante ADV_CCB *ccbstore;
191 1.1 dante int count;
192 1.1 dante {
193 1.1 dante ADV_CCB *ccb;
194 1.1 dante int i, error;
195 1.1 dante
196 1.1 dante bzero(ccbstore, sizeof(ADV_CCB) * count);
197 1.1 dante for (i = 0; i < count; i++) {
198 1.1 dante ccb = &ccbstore[i];
199 1.1 dante if ((error = adv_init_ccb(sc, ccb)) != 0) {
200 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
201 1.1 dante sc->sc_dev.dv_xname, error);
202 1.1 dante return (i);
203 1.1 dante }
204 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
205 1.1 dante }
206 1.1 dante
207 1.1 dante return (i);
208 1.1 dante }
209 1.1 dante
210 1.1 dante
211 1.1 dante /*
212 1.1 dante * A ccb is put onto the free list.
213 1.1 dante */
214 1.1 dante static void
215 1.1 dante adv_free_ccb(sc, ccb)
216 1.1 dante ASC_SOFTC *sc;
217 1.1 dante ADV_CCB *ccb;
218 1.1 dante {
219 1.1 dante int s;
220 1.1 dante
221 1.1 dante s = splbio();
222 1.1 dante
223 1.1 dante adv_reset_ccb(ccb);
224 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
225 1.1 dante
226 1.1 dante /*
227 1.1 dante * If there were none, wake anybody waiting for one to come free,
228 1.1 dante * starting with queued entries.
229 1.1 dante */
230 1.1 dante if (ccb->chain.tqe_next == 0)
231 1.1 dante wakeup(&sc->sc_free_ccb);
232 1.1 dante
233 1.1 dante splx(s);
234 1.1 dante }
235 1.1 dante
236 1.1 dante
237 1.1 dante static void
238 1.1 dante adv_reset_ccb(ccb)
239 1.1 dante ADV_CCB *ccb;
240 1.1 dante {
241 1.1 dante
242 1.1 dante ccb->flags = 0;
243 1.1 dante }
244 1.1 dante
245 1.1 dante
246 1.1 dante static int
247 1.1 dante adv_init_ccb(sc, ccb)
248 1.1 dante ASC_SOFTC *sc;
249 1.1 dante ADV_CCB *ccb;
250 1.1 dante {
251 1.10 dante int hashnum, error;
252 1.1 dante
253 1.16 thorpej callout_init(&ccb->ccb_watchdog);
254 1.16 thorpej
255 1.1 dante /*
256 1.1 dante * Create the DMA map for this CCB.
257 1.1 dante */
258 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
259 1.1 dante (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
260 1.1 dante ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
261 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
262 1.1 dante if (error) {
263 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
264 1.1 dante sc->sc_dev.dv_xname, error);
265 1.1 dante return (error);
266 1.1 dante }
267 1.10 dante
268 1.10 dante /*
269 1.10 dante * put in the phystokv hash table
270 1.10 dante * Never gets taken out.
271 1.10 dante */
272 1.10 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
273 1.10 dante ADV_CCB_OFF(ccb);
274 1.10 dante hashnum = CCB_HASH(ccb->hashkey);
275 1.10 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
276 1.10 dante sc->sc_ccbhash[hashnum] = ccb;
277 1.10 dante
278 1.1 dante adv_reset_ccb(ccb);
279 1.1 dante return (0);
280 1.1 dante }
281 1.1 dante
282 1.1 dante
283 1.1 dante /*
284 1.1 dante * Get a free ccb
285 1.1 dante *
286 1.1 dante * If there are none, see if we can allocate a new one
287 1.1 dante */
288 1.1 dante static ADV_CCB *
289 1.1 dante adv_get_ccb(sc, flags)
290 1.1 dante ASC_SOFTC *sc;
291 1.1 dante int flags;
292 1.1 dante {
293 1.1 dante ADV_CCB *ccb = 0;
294 1.1 dante int s;
295 1.1 dante
296 1.1 dante s = splbio();
297 1.1 dante
298 1.1 dante /*
299 1.1 dante * If we can and have to, sleep waiting for one to come free
300 1.1 dante * but only if we can't allocate a new one.
301 1.1 dante */
302 1.1 dante for (;;) {
303 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
304 1.1 dante if (ccb) {
305 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
306 1.1 dante break;
307 1.1 dante }
308 1.14 thorpej if ((flags & XS_CTL_NOSLEEP) != 0)
309 1.1 dante goto out;
310 1.1 dante
311 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "advccb", 0);
312 1.1 dante }
313 1.1 dante
314 1.1 dante ccb->flags |= CCB_ALLOC;
315 1.1 dante
316 1.1 dante out:
317 1.1 dante splx(s);
318 1.1 dante return (ccb);
319 1.1 dante }
320 1.1 dante
321 1.1 dante
322 1.1 dante /*
323 1.10 dante * Given a physical address, find the ccb that it corresponds to.
324 1.10 dante */
325 1.10 dante ADV_CCB *
326 1.10 dante adv_ccb_phys_kv(sc, ccb_phys)
327 1.10 dante ASC_SOFTC *sc;
328 1.10 dante u_long ccb_phys;
329 1.10 dante {
330 1.10 dante int hashnum = CCB_HASH(ccb_phys);
331 1.10 dante ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
332 1.10 dante
333 1.10 dante while (ccb) {
334 1.10 dante if (ccb->hashkey == ccb_phys)
335 1.10 dante break;
336 1.10 dante ccb = ccb->nexthash;
337 1.10 dante }
338 1.10 dante return (ccb);
339 1.10 dante }
340 1.10 dante
341 1.10 dante
342 1.10 dante /*
343 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
344 1.1 dante */
345 1.1 dante static void
346 1.1 dante adv_queue_ccb(sc, ccb)
347 1.1 dante ASC_SOFTC *sc;
348 1.1 dante ADV_CCB *ccb;
349 1.1 dante {
350 1.1 dante
351 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
352 1.1 dante
353 1.1 dante adv_start_ccbs(sc);
354 1.1 dante }
355 1.1 dante
356 1.1 dante
357 1.1 dante static void
358 1.1 dante adv_start_ccbs(sc)
359 1.1 dante ASC_SOFTC *sc;
360 1.1 dante {
361 1.1 dante ADV_CCB *ccb;
362 1.1 dante
363 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
364 1.1 dante if (ccb->flags & CCB_WATCHDOG)
365 1.16 thorpej callout_stop(&ccb->ccb_watchdog);
366 1.1 dante
367 1.1 dante if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
368 1.1 dante ccb->flags |= CCB_WATCHDOG;
369 1.16 thorpej callout_reset(&ccb->ccb_watchdog,
370 1.16 thorpej (ADV_WATCH_TIMEOUT * hz) / 1000,
371 1.16 thorpej adv_watchdog, ccb);
372 1.1 dante break;
373 1.1 dante }
374 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
375 1.1 dante
376 1.14 thorpej if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
377 1.16 thorpej callout_reset(&ccb->xs->xs_callout,
378 1.16 thorpej (ccb->timeout * hz) / 1000,
379 1.16 thorpej adv_timeout, ccb);
380 1.1 dante }
381 1.1 dante }
382 1.1 dante
383 1.1 dante
384 1.1 dante /******************************************************************************/
385 1.1 dante /* SCSI layer interfacing routines */
386 1.1 dante /******************************************************************************/
387 1.1 dante
388 1.1 dante
389 1.1 dante int
390 1.1 dante adv_init(sc)
391 1.1 dante ASC_SOFTC *sc;
392 1.1 dante {
393 1.1 dante int warn;
394 1.1 dante
395 1.12 dante if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
396 1.12 dante printf("adv_init: failed to find signature\n");
397 1.12 dante return (1);
398 1.12 dante }
399 1.1 dante
400 1.4 dante /*
401 1.4 dante * Read the board configuration
402 1.4 dante */
403 1.4 dante AscInitASC_SOFTC(sc);
404 1.4 dante warn = AscInitFromEEP(sc);
405 1.4 dante if (warn) {
406 1.4 dante printf("%s -get: ", sc->sc_dev.dv_xname);
407 1.4 dante switch (warn) {
408 1.4 dante case -1:
409 1.4 dante printf("Chip is not halted\n");
410 1.4 dante break;
411 1.4 dante
412 1.4 dante case -2:
413 1.4 dante printf("Couldn't get MicroCode Start"
414 1.4 dante " address\n");
415 1.4 dante break;
416 1.4 dante
417 1.4 dante case ASC_WARN_IO_PORT_ROTATE:
418 1.4 dante printf("I/O port address modified\n");
419 1.4 dante break;
420 1.4 dante
421 1.4 dante case ASC_WARN_AUTO_CONFIG:
422 1.4 dante printf("I/O port increment switch enabled\n");
423 1.4 dante break;
424 1.4 dante
425 1.4 dante case ASC_WARN_EEPROM_CHKSUM:
426 1.4 dante printf("EEPROM checksum error\n");
427 1.4 dante break;
428 1.4 dante
429 1.4 dante case ASC_WARN_IRQ_MODIFIED:
430 1.4 dante printf("IRQ modified\n");
431 1.4 dante break;
432 1.4 dante
433 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
434 1.4 dante printf("tag queuing enabled w/o disconnects\n");
435 1.4 dante break;
436 1.1 dante
437 1.4 dante default:
438 1.4 dante printf("unknown warning %d\n", warn);
439 1.1 dante }
440 1.4 dante }
441 1.4 dante if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
442 1.4 dante sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
443 1.4 dante
444 1.4 dante /*
445 1.4 dante * Modify the board configuration
446 1.4 dante */
447 1.4 dante warn = AscInitFromASC_SOFTC(sc);
448 1.4 dante if (warn) {
449 1.4 dante printf("%s -set: ", sc->sc_dev.dv_xname);
450 1.4 dante switch (warn) {
451 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
452 1.4 dante printf("tag queuing enabled w/o disconnects\n");
453 1.4 dante break;
454 1.1 dante
455 1.4 dante case ASC_WARN_AUTO_CONFIG:
456 1.4 dante printf("I/O port increment switch enabled\n");
457 1.4 dante break;
458 1.1 dante
459 1.4 dante default:
460 1.4 dante printf("unknown warning %d\n", warn);
461 1.1 dante }
462 1.4 dante }
463 1.11 dante sc->isr_callback = (ASC_CALLBACK) adv_narrow_isr_callback;
464 1.1 dante
465 1.1 dante return (0);
466 1.1 dante }
467 1.1 dante
468 1.1 dante
469 1.1 dante void
470 1.1 dante adv_attach(sc)
471 1.1 dante ASC_SOFTC *sc;
472 1.1 dante {
473 1.1 dante int i, error;
474 1.1 dante
475 1.4 dante /*
476 1.4 dante * Initialize board RISC chip and enable interrupts.
477 1.4 dante */
478 1.4 dante switch (AscInitDriver(sc)) {
479 1.4 dante case 0:
480 1.4 dante /* AllOK */
481 1.4 dante break;
482 1.1 dante
483 1.4 dante case 1:
484 1.4 dante panic("%s: bad signature", sc->sc_dev.dv_xname);
485 1.4 dante break;
486 1.1 dante
487 1.4 dante case 2:
488 1.4 dante panic("%s: unable to load MicroCode",
489 1.4 dante sc->sc_dev.dv_xname);
490 1.4 dante break;
491 1.1 dante
492 1.4 dante case 3:
493 1.4 dante panic("%s: unable to initialize MicroCode",
494 1.4 dante sc->sc_dev.dv_xname);
495 1.4 dante break;
496 1.1 dante
497 1.4 dante default:
498 1.4 dante panic("%s: unable to initialize board RISC chip",
499 1.4 dante sc->sc_dev.dv_xname);
500 1.1 dante }
501 1.1 dante
502 1.7 thorpej /*
503 1.7 thorpej * Fill in the adapter.
504 1.7 thorpej */
505 1.7 thorpej sc->sc_adapter.scsipi_cmd = adv_scsi_cmd;
506 1.7 thorpej sc->sc_adapter.scsipi_minphys = advminphys;
507 1.1 dante
508 1.1 dante /*
509 1.1 dante * fill in the prototype scsipi_link.
510 1.1 dante */
511 1.1 dante sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
512 1.1 dante sc->sc_link.adapter_softc = sc;
513 1.1 dante sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
514 1.7 thorpej sc->sc_link.adapter = &sc->sc_adapter;
515 1.1 dante sc->sc_link.device = &adv_dev;
516 1.1 dante sc->sc_link.openings = 4;
517 1.4 dante sc->sc_link.scsipi_scsi.max_target = 7;
518 1.8 mjacob sc->sc_link.scsipi_scsi.max_lun = 7;
519 1.1 dante sc->sc_link.type = BUS_SCSI;
520 1.1 dante
521 1.1 dante
522 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
523 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
524 1.9 thorpej TAILQ_INIT(&sc->sc_queue);
525 1.1 dante
526 1.1 dante
527 1.1 dante /*
528 1.13 thorpej * Allocate the Control Blocks and the overrun buffer.
529 1.1 dante */
530 1.13 thorpej error = adv_alloc_control_data(sc);
531 1.1 dante if (error)
532 1.12 dante return; /* (error) */
533 1.1 dante
534 1.1 dante /*
535 1.1 dante * Create and initialize the Control Blocks.
536 1.1 dante */
537 1.1 dante i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
538 1.1 dante if (i == 0) {
539 1.1 dante printf("%s: unable to create control blocks\n",
540 1.1 dante sc->sc_dev.dv_xname);
541 1.1 dante return; /* (ENOMEM) */ ;
542 1.1 dante } else if (i != ADV_MAX_CCB) {
543 1.1 dante printf("%s: WARNING: only %d of %d control blocks created\n",
544 1.1 dante sc->sc_dev.dv_xname, i, ADV_MAX_CCB);
545 1.1 dante }
546 1.22 thorpej sc->sc_child = config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
547 1.1 dante }
548 1.1 dante
549 1.22 thorpej int
550 1.22 thorpej adv_detach(sc, flags)
551 1.22 thorpej ASC_SOFTC *sc;
552 1.22 thorpej int flags;
553 1.22 thorpej {
554 1.22 thorpej int rv = 0;
555 1.22 thorpej
556 1.22 thorpej if (sc->sc_child != NULL)
557 1.22 thorpej rv = config_detach(sc->sc_child, flags);
558 1.22 thorpej
559 1.22 thorpej adv_free_control_data(sc);
560 1.22 thorpej
561 1.22 thorpej return (rv);
562 1.22 thorpej }
563 1.1 dante
564 1.1 dante static void
565 1.1 dante advminphys(bp)
566 1.1 dante struct buf *bp;
567 1.1 dante {
568 1.1 dante
569 1.1 dante if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
570 1.1 dante bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
571 1.1 dante minphys(bp);
572 1.1 dante }
573 1.1 dante
574 1.1 dante
575 1.1 dante /*
576 1.1 dante * start a scsi operation given the command and the data address. Also needs
577 1.1 dante * the unit, target and lu.
578 1.1 dante */
579 1.1 dante static int
580 1.1 dante adv_scsi_cmd(xs)
581 1.1 dante struct scsipi_xfer *xs;
582 1.1 dante {
583 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
584 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
585 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
586 1.1 dante ADV_CCB *ccb;
587 1.1 dante int s, flags, error, nsegs;
588 1.15 thorpej int fromqueue = 0, dontqueue = 0, nowait = 0;
589 1.1 dante
590 1.1 dante
591 1.1 dante s = splbio(); /* protect the queue */
592 1.1 dante
593 1.1 dante /*
594 1.1 dante * If we're running the queue from adv_done(), we've been
595 1.1 dante * called with the first queue entry as our argument.
596 1.1 dante */
597 1.9 thorpej if (xs == TAILQ_FIRST(&sc->sc_queue)) {
598 1.9 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
599 1.1 dante fromqueue = 1;
600 1.15 thorpej nowait = 1;
601 1.1 dante } else {
602 1.1 dante
603 1.1 dante /* Polled requests can't be queued for later. */
604 1.14 thorpej dontqueue = xs->xs_control & XS_CTL_POLL;
605 1.1 dante
606 1.1 dante /*
607 1.1 dante * If there are jobs in the queue, run them first.
608 1.1 dante */
609 1.9 thorpej if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
610 1.1 dante /*
611 1.1 dante * If we can't queue, we have to abort, since
612 1.1 dante * we have to preserve order.
613 1.1 dante */
614 1.1 dante if (dontqueue) {
615 1.1 dante splx(s);
616 1.1 dante xs->error = XS_DRIVER_STUFFUP;
617 1.1 dante return (TRY_AGAIN_LATER);
618 1.1 dante }
619 1.1 dante /*
620 1.1 dante * Swap with the first queue entry.
621 1.1 dante */
622 1.9 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
623 1.9 thorpej xs = TAILQ_FIRST(&sc->sc_queue);
624 1.9 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
625 1.1 dante fromqueue = 1;
626 1.1 dante }
627 1.1 dante }
628 1.1 dante
629 1.1 dante
630 1.1 dante /*
631 1.1 dante * get a ccb to use. If the transfer
632 1.1 dante * is from a buf (possibly from interrupt time)
633 1.1 dante * then we can't allow it to sleep
634 1.1 dante */
635 1.1 dante
636 1.14 thorpej flags = xs->xs_control;
637 1.15 thorpej if (nowait)
638 1.15 thorpej flags |= XS_CTL_NOSLEEP;
639 1.1 dante if ((ccb = adv_get_ccb(sc, flags)) == NULL) {
640 1.1 dante /*
641 1.1 dante * If we can't queue, we lose.
642 1.1 dante */
643 1.1 dante if (dontqueue) {
644 1.1 dante splx(s);
645 1.1 dante xs->error = XS_DRIVER_STUFFUP;
646 1.1 dante return (TRY_AGAIN_LATER);
647 1.1 dante }
648 1.1 dante /*
649 1.1 dante * Stuff ourselves into the queue, in front
650 1.1 dante * if we came off in the first place.
651 1.1 dante */
652 1.9 thorpej if (fromqueue)
653 1.9 thorpej TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
654 1.9 thorpej else
655 1.9 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
656 1.1 dante splx(s);
657 1.1 dante return (SUCCESSFULLY_QUEUED);
658 1.1 dante }
659 1.1 dante splx(s); /* done playing with the queue */
660 1.1 dante
661 1.1 dante ccb->xs = xs;
662 1.1 dante ccb->timeout = xs->timeout;
663 1.1 dante
664 1.1 dante /*
665 1.1 dante * Build up the request
666 1.1 dante */
667 1.1 dante memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
668 1.1 dante
669 1.10 dante ccb->scsiq.q2.ccb_ptr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
670 1.10 dante ADV_CCB_OFF(ccb);
671 1.1 dante
672 1.1 dante ccb->scsiq.cdbptr = &xs->cmd->opcode;
673 1.1 dante ccb->scsiq.q2.cdb_len = xs->cmdlen;
674 1.1 dante ccb->scsiq.q1.target_id = ASC_TID_TO_TARGET_ID(sc_link->scsipi_scsi.target);
675 1.1 dante ccb->scsiq.q1.target_lun = sc_link->scsipi_scsi.lun;
676 1.1 dante ccb->scsiq.q2.target_ix = ASC_TIDLUN_TO_IX(sc_link->scsipi_scsi.target,
677 1.1 dante sc_link->scsipi_scsi.lun);
678 1.1 dante ccb->scsiq.q1.sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
679 1.1 dante ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
680 1.1 dante ccb->scsiq.q1.sense_len = sizeof(struct scsipi_sense_data);
681 1.1 dante
682 1.1 dante /*
683 1.1 dante * If there are any outstanding requests for the current target,
684 1.1 dante * then every 255th request send an ORDERED request. This heuristic
685 1.1 dante * tries to retain the benefit of request sorting while preventing
686 1.1 dante * request starvation. 255 is the max number of tags or pending commands
687 1.1 dante * a device may have outstanding.
688 1.1 dante */
689 1.1 dante sc->reqcnt[sc_link->scsipi_scsi.target]++;
690 1.1 dante if ((sc->reqcnt[sc_link->scsipi_scsi.target] > 0) &&
691 1.1 dante (sc->reqcnt[sc_link->scsipi_scsi.target] % 255) == 0) {
692 1.1 dante ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
693 1.1 dante } else {
694 1.19 tls if((xs->bp != NULL) && xs->bp->b_flags & B_ASYNC)
695 1.19 tls ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
696 1.19 tls else
697 1.19 tls ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
698 1.1 dante }
699 1.1 dante
700 1.1 dante
701 1.1 dante if (xs->datalen) {
702 1.1 dante /*
703 1.1 dante * Map the DMA transfer.
704 1.1 dante */
705 1.1 dante #ifdef TFS
706 1.1 dante if (flags & SCSI_DATA_UIO) {
707 1.21 thorpej error = bus_dmamap_load_uio(dmat, ccb->dmamap_xfer,
708 1.21 thorpej (struct uio *) xs->data,
709 1.21 thorpej ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
710 1.21 thorpej BUS_DMA_WAITOK) | BUS_DMA_STREAMING);
711 1.1 dante } else
712 1.1 dante #endif /* TFS */
713 1.1 dante {
714 1.21 thorpej error = bus_dmamap_load(dmat, ccb->dmamap_xfer,
715 1.21 thorpej xs->data, xs->datalen, NULL,
716 1.21 thorpej ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
717 1.21 thorpej BUS_DMA_WAITOK) | BUS_DMA_STREAMING);
718 1.1 dante }
719 1.1 dante
720 1.1 dante if (error) {
721 1.1 dante if (error == EFBIG) {
722 1.1 dante printf("%s: adv_scsi_cmd, more than %d dma"
723 1.1 dante " segments\n",
724 1.1 dante sc->sc_dev.dv_xname, ASC_MAX_SG_LIST);
725 1.1 dante } else {
726 1.1 dante printf("%s: adv_scsi_cmd, error %d loading"
727 1.1 dante " dma map\n",
728 1.1 dante sc->sc_dev.dv_xname, error);
729 1.1 dante }
730 1.1 dante
731 1.1 dante xs->error = XS_DRIVER_STUFFUP;
732 1.1 dante adv_free_ccb(sc, ccb);
733 1.1 dante return (COMPLETE);
734 1.1 dante }
735 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
736 1.1 dante ccb->dmamap_xfer->dm_mapsize,
737 1.14 thorpej (flags & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD :
738 1.1 dante BUS_DMASYNC_PREWRITE);
739 1.1 dante
740 1.1 dante
741 1.1 dante memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
742 1.1 dante
743 1.1 dante for (nsegs = 0; nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
744 1.1 dante
745 1.1 dante ccb->sghead.sg_list[nsegs].addr =
746 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
747 1.1 dante ccb->sghead.sg_list[nsegs].bytes =
748 1.1 dante ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
749 1.1 dante }
750 1.1 dante
751 1.1 dante ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
752 1.1 dante ccb->dmamap_xfer->dm_nsegs;
753 1.1 dante
754 1.1 dante ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
755 1.1 dante ccb->scsiq.sg_head = &ccb->sghead;
756 1.1 dante ccb->scsiq.q1.data_addr = 0;
757 1.1 dante ccb->scsiq.q1.data_cnt = 0;
758 1.1 dante } else {
759 1.1 dante /*
760 1.1 dante * No data xfer, use non S/G values.
761 1.1 dante */
762 1.1 dante ccb->scsiq.q1.data_addr = 0;
763 1.1 dante ccb->scsiq.q1.data_cnt = 0;
764 1.1 dante }
765 1.1 dante
766 1.6 dante #ifdef ASC_DEBUG
767 1.6 dante printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX \n",
768 1.6 dante sc_link->scsipi_scsi.target,
769 1.6 dante sc_link->scsipi_scsi.lun, xs->cmd->opcode,
770 1.6 dante (unsigned long)ccb);
771 1.6 dante #endif
772 1.1 dante s = splbio();
773 1.1 dante adv_queue_ccb(sc, ccb);
774 1.1 dante splx(s);
775 1.1 dante
776 1.1 dante /*
777 1.1 dante * Usually return SUCCESSFULLY QUEUED
778 1.1 dante */
779 1.14 thorpej if ((flags & XS_CTL_POLL) == 0)
780 1.1 dante return (SUCCESSFULLY_QUEUED);
781 1.1 dante
782 1.1 dante /*
783 1.1 dante * If we can't use interrupts, poll on completion
784 1.1 dante */
785 1.1 dante if (adv_poll(sc, xs, ccb->timeout)) {
786 1.1 dante adv_timeout(ccb);
787 1.1 dante if (adv_poll(sc, xs, ccb->timeout))
788 1.1 dante adv_timeout(ccb);
789 1.1 dante }
790 1.1 dante return (COMPLETE);
791 1.1 dante }
792 1.1 dante
793 1.1 dante
794 1.1 dante int
795 1.1 dante adv_intr(arg)
796 1.1 dante void *arg;
797 1.1 dante {
798 1.1 dante ASC_SOFTC *sc = arg;
799 1.1 dante struct scsipi_xfer *xs;
800 1.1 dante
801 1.6 dante #ifdef ASC_DEBUG
802 1.6 dante int int_pend = FALSE;
803 1.6 dante
804 1.6 dante if(ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh))
805 1.6 dante {
806 1.6 dante int_pend = TRUE;
807 1.6 dante printf("ISR - ");
808 1.6 dante }
809 1.6 dante #endif
810 1.4 dante AscISR(sc);
811 1.6 dante #ifdef ASC_DEBUG
812 1.6 dante if(int_pend)
813 1.6 dante printf("\n");
814 1.6 dante #endif
815 1.1 dante
816 1.1 dante /*
817 1.1 dante * If there are queue entries in the software queue, try to
818 1.1 dante * run the first one. We should be more or less guaranteed
819 1.1 dante * to succeed, since we just freed a CCB.
820 1.1 dante *
821 1.1 dante * NOTE: adv_scsi_cmd() relies on our calling it with
822 1.1 dante * the first entry in the queue.
823 1.1 dante */
824 1.9 thorpej if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
825 1.1 dante (void) adv_scsi_cmd(xs);
826 1.1 dante
827 1.1 dante return (1);
828 1.1 dante }
829 1.1 dante
830 1.1 dante
831 1.1 dante /*
832 1.1 dante * Poll a particular unit, looking for a particular xs
833 1.1 dante */
834 1.1 dante static int
835 1.1 dante adv_poll(sc, xs, count)
836 1.1 dante ASC_SOFTC *sc;
837 1.1 dante struct scsipi_xfer *xs;
838 1.1 dante int count;
839 1.1 dante {
840 1.1 dante
841 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
842 1.1 dante while (count) {
843 1.1 dante adv_intr(sc);
844 1.14 thorpej if (xs->xs_status & XS_STS_DONE)
845 1.1 dante return (0);
846 1.1 dante delay(1000); /* only happens in boot so ok */
847 1.1 dante count--;
848 1.1 dante }
849 1.1 dante return (1);
850 1.1 dante }
851 1.1 dante
852 1.1 dante
853 1.1 dante static void
854 1.1 dante adv_timeout(arg)
855 1.1 dante void *arg;
856 1.1 dante {
857 1.1 dante ADV_CCB *ccb = arg;
858 1.1 dante struct scsipi_xfer *xs = ccb->xs;
859 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
860 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
861 1.1 dante int s;
862 1.1 dante
863 1.1 dante scsi_print_addr(sc_link);
864 1.1 dante printf("timed out");
865 1.1 dante
866 1.1 dante s = splbio();
867 1.1 dante
868 1.1 dante /*
869 1.1 dante * If it has been through before, then a previous abort has failed,
870 1.1 dante * don't try abort again, reset the bus instead.
871 1.1 dante */
872 1.1 dante if (ccb->flags & CCB_ABORT) {
873 1.1 dante /* abort timed out */
874 1.1 dante printf(" AGAIN. Resetting Bus\n");
875 1.1 dante /* Lets try resetting the bus! */
876 1.1 dante if (AscResetBus(sc) == ASC_ERROR) {
877 1.1 dante ccb->timeout = sc->scsi_reset_wait;
878 1.1 dante adv_queue_ccb(sc, ccb);
879 1.1 dante }
880 1.1 dante } else {
881 1.1 dante /* abort the operation that has timed out */
882 1.1 dante printf("\n");
883 1.10 dante AscAbortCCB(sc, ccb);
884 1.1 dante ccb->xs->error = XS_TIMEOUT;
885 1.1 dante ccb->timeout = ADV_ABORT_TIMEOUT;
886 1.1 dante ccb->flags |= CCB_ABORT;
887 1.1 dante adv_queue_ccb(sc, ccb);
888 1.1 dante }
889 1.1 dante
890 1.1 dante splx(s);
891 1.1 dante }
892 1.1 dante
893 1.1 dante
894 1.1 dante static void
895 1.1 dante adv_watchdog(arg)
896 1.1 dante void *arg;
897 1.1 dante {
898 1.1 dante ADV_CCB *ccb = arg;
899 1.1 dante struct scsipi_xfer *xs = ccb->xs;
900 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
901 1.1 dante ASC_SOFTC *sc = sc_link->adapter_softc;
902 1.1 dante int s;
903 1.1 dante
904 1.1 dante s = splbio();
905 1.1 dante
906 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
907 1.1 dante adv_start_ccbs(sc);
908 1.1 dante
909 1.1 dante splx(s);
910 1.1 dante }
911 1.1 dante
912 1.1 dante
913 1.1 dante /******************************************************************************/
914 1.10 dante /* NARROW boards Interrupt callbacks */
915 1.1 dante /******************************************************************************/
916 1.1 dante
917 1.1 dante
918 1.1 dante /*
919 1.1 dante * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
920 1.1 dante *
921 1.1 dante * Interrupt callback function for the Narrow SCSI Asc Library.
922 1.1 dante */
923 1.1 dante static void
924 1.1 dante adv_narrow_isr_callback(sc, qdonep)
925 1.1 dante ASC_SOFTC *sc;
926 1.1 dante ASC_QDONE_INFO *qdonep;
927 1.1 dante {
928 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
929 1.10 dante ADV_CCB *ccb;
930 1.10 dante struct scsipi_xfer *xs;
931 1.1 dante struct scsipi_sense_data *s1, *s2;
932 1.1 dante
933 1.10 dante
934 1.10 dante ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
935 1.10 dante xs = ccb->xs;
936 1.1 dante
937 1.6 dante #ifdef ASC_DEBUG
938 1.6 dante printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
939 1.6 dante (unsigned long)ccb,
940 1.6 dante xs->sc_link->scsipi_scsi.target,
941 1.6 dante xs->sc_link->scsipi_scsi.lun, xs->cmd->opcode);
942 1.6 dante #endif
943 1.16 thorpej callout_stop(&ccb->xs->xs_callout);
944 1.1 dante
945 1.1 dante /*
946 1.1 dante * If we were a data transfer, unload the map that described
947 1.1 dante * the data buffer.
948 1.1 dante */
949 1.1 dante if (xs->datalen) {
950 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
951 1.1 dante ccb->dmamap_xfer->dm_mapsize,
952 1.14 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
953 1.14 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
954 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
955 1.1 dante }
956 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
957 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
958 1.1 dante Debugger();
959 1.1 dante return;
960 1.1 dante }
961 1.1 dante /*
962 1.1 dante * 'qdonep' contains the command's ending status.
963 1.1 dante */
964 1.6 dante #ifdef ASC_DEBUG
965 1.6 dante printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
966 1.6 dante #endif
967 1.1 dante switch (qdonep->d3.done_stat) {
968 1.1 dante case ASC_QD_NO_ERROR:
969 1.1 dante switch (qdonep->d3.host_stat) {
970 1.1 dante case ASC_QHSTA_NO_ERROR:
971 1.1 dante xs->error = XS_NOERROR;
972 1.1 dante xs->resid = 0;
973 1.1 dante break;
974 1.1 dante
975 1.1 dante default:
976 1.1 dante /* QHSTA error occurred */
977 1.1 dante xs->error = XS_DRIVER_STUFFUP;
978 1.1 dante break;
979 1.1 dante }
980 1.1 dante
981 1.1 dante /*
982 1.1 dante * If an INQUIRY command completed successfully, then call
983 1.1 dante * the AscInquiryHandling() function to patch bugged boards.
984 1.1 dante */
985 1.1 dante if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
986 1.1 dante (xs->sc_link->scsipi_scsi.lun == 0) &&
987 1.1 dante (xs->datalen - qdonep->remain_bytes) >= 8) {
988 1.1 dante AscInquiryHandling(sc,
989 1.1 dante xs->sc_link->scsipi_scsi.target & 0x7,
990 1.1 dante (ASC_SCSI_INQUIRY *) xs->data);
991 1.1 dante }
992 1.1 dante break;
993 1.1 dante
994 1.1 dante case ASC_QD_WITH_ERROR:
995 1.1 dante switch (qdonep->d3.host_stat) {
996 1.1 dante case ASC_QHSTA_NO_ERROR:
997 1.1 dante if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
998 1.1 dante s1 = &ccb->scsi_sense;
999 1.1 dante s2 = &xs->sense.scsi_sense;
1000 1.1 dante *s2 = *s1;
1001 1.1 dante xs->error = XS_SENSE;
1002 1.4 dante } else {
1003 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1004 1.4 dante }
1005 1.1 dante break;
1006 1.1 dante
1007 1.1 dante default:
1008 1.1 dante /* QHSTA error occurred */
1009 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1010 1.1 dante break;
1011 1.1 dante }
1012 1.1 dante break;
1013 1.1 dante
1014 1.1 dante case ASC_QD_ABORTED_BY_HOST:
1015 1.1 dante default:
1016 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1017 1.1 dante break;
1018 1.1 dante }
1019 1.1 dante
1020 1.1 dante
1021 1.1 dante adv_free_ccb(sc, ccb);
1022 1.14 thorpej xs->xs_status |= XS_STS_DONE;
1023 1.1 dante scsipi_done(xs);
1024 1.1 dante }
1025