Home | History | Annotate | Line # | Download | only in ic
adv.c revision 1.48.6.1
      1  1.48.6.1    martin /*	$NetBSD: adv.c,v 1.48.6.1 2019/12/18 20:04:33 martin Exp $	*/
      2       1.2     dante 
      3       1.1     dante /*
      4       1.4     dante  * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
      5       1.1     dante  *
      6       1.1     dante  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      7       1.1     dante  * All rights reserved.
      8       1.1     dante  *
      9       1.1     dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10       1.1     dante  *
     11       1.1     dante  * Redistribution and use in source and binary forms, with or without
     12       1.1     dante  * modification, are permitted provided that the following conditions
     13       1.1     dante  * are met:
     14       1.1     dante  * 1. Redistributions of source code must retain the above copyright
     15       1.1     dante  *    notice, this list of conditions and the following disclaimer.
     16       1.1     dante  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1     dante  *    notice, this list of conditions and the following disclaimer in the
     18       1.1     dante  *    documentation and/or other materials provided with the distribution.
     19       1.1     dante  *
     20       1.1     dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21       1.1     dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22       1.1     dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23       1.1     dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24       1.1     dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25       1.1     dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26       1.1     dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27       1.1     dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28       1.1     dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29       1.1     dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30       1.1     dante  * POSSIBILITY OF SUCH DAMAGE.
     31       1.1     dante  */
     32      1.29     lukem 
     33      1.29     lukem #include <sys/cdefs.h>
     34  1.48.6.1    martin __KERNEL_RCSID(0, "$NetBSD: adv.c,v 1.48.6.1 2019/12/18 20:04:33 martin Exp $");
     35       1.1     dante 
     36       1.1     dante #include <sys/param.h>
     37       1.1     dante #include <sys/systm.h>
     38      1.16   thorpej #include <sys/callout.h>
     39       1.1     dante #include <sys/kernel.h>
     40       1.1     dante #include <sys/errno.h>
     41       1.1     dante #include <sys/ioctl.h>
     42       1.1     dante #include <sys/device.h>
     43       1.1     dante #include <sys/malloc.h>
     44       1.1     dante #include <sys/buf.h>
     45       1.1     dante #include <sys/proc.h>
     46       1.1     dante 
     47      1.41        ad #include <sys/bus.h>
     48      1.41        ad #include <sys/intr.h>
     49       1.1     dante 
     50       1.1     dante #include <dev/scsipi/scsi_all.h>
     51       1.1     dante #include <dev/scsipi/scsipi_all.h>
     52       1.1     dante #include <dev/scsipi/scsiconf.h>
     53       1.1     dante 
     54      1.10     dante #include <dev/ic/advlib.h>
     55       1.1     dante #include <dev/ic/adv.h>
     56       1.3   thorpej 
     57       1.3   thorpej #ifndef DDB
     58       1.3   thorpej #define	Debugger()	panic("should call debugger here (adv.c)")
     59       1.3   thorpej #endif /* ! DDB */
     60       1.1     dante 
     61       1.6     dante 
     62       1.6     dante /* #define ASC_DEBUG */
     63       1.6     dante 
     64       1.1     dante /******************************************************************************/
     65       1.1     dante 
     66       1.1     dante 
     67      1.34     perry static int adv_alloc_control_data(ASC_SOFTC *);
     68      1.34     perry static void adv_free_control_data(ASC_SOFTC *);
     69      1.34     perry static int adv_create_ccbs(ASC_SOFTC *, ADV_CCB *, int);
     70      1.34     perry static void adv_free_ccb(ASC_SOFTC *, ADV_CCB *);
     71      1.34     perry static void adv_reset_ccb(ADV_CCB *);
     72      1.34     perry static int adv_init_ccb(ASC_SOFTC *, ADV_CCB *);
     73      1.34     perry static ADV_CCB *adv_get_ccb(ASC_SOFTC *);
     74      1.34     perry static void adv_queue_ccb(ASC_SOFTC *, ADV_CCB *);
     75      1.34     perry static void adv_start_ccbs(ASC_SOFTC *);
     76      1.34     perry 
     77      1.34     perry 
     78      1.34     perry static void adv_scsipi_request(struct scsipi_channel *,
     79      1.34     perry 	scsipi_adapter_req_t, void *);
     80      1.34     perry static void advminphys(struct buf *);
     81      1.34     perry static void adv_narrow_isr_callback(ASC_SOFTC *, ASC_QDONE_INFO *);
     82      1.34     perry 
     83      1.34     perry static int adv_poll(ASC_SOFTC *, struct scsipi_xfer *, int);
     84      1.34     perry static void adv_timeout(void *);
     85      1.34     perry static void adv_watchdog(void *);
     86       1.1     dante 
     87       1.1     dante 
     88       1.1     dante /******************************************************************************/
     89       1.1     dante 
     90       1.1     dante #define ADV_ABORT_TIMEOUT       2000	/* time to wait for abort (mSec) */
     91       1.1     dante #define ADV_WATCH_TIMEOUT       1000	/* time to wait for watchdog (mSec) */
     92       1.1     dante 
     93       1.1     dante /******************************************************************************/
     94       1.1     dante /*                             Control Blocks routines                        */
     95       1.1     dante /******************************************************************************/
     96       1.1     dante 
     97       1.1     dante 
     98       1.1     dante static int
     99      1.43       dsl adv_alloc_control_data(ASC_SOFTC *sc)
    100       1.1     dante {
    101      1.22   thorpej 	int error;
    102       1.1     dante 
    103       1.1     dante 	/*
    104      1.24    bouyer  	* Allocate the control blocks.
    105      1.24    bouyer 	 */
    106       1.1     dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
    107      1.22   thorpej 			   PAGE_SIZE, 0, &sc->sc_control_seg, 1,
    108      1.22   thorpej 			   &sc->sc_control_nsegs, BUS_DMA_NOWAIT)) != 0) {
    109      1.47   msaitoh 		aprint_error_dev(sc->sc_dev, "unable to allocate control "
    110      1.47   msaitoh 		    "structures, error = %d\n", error);
    111       1.1     dante 		return (error);
    112       1.1     dante 	}
    113      1.22   thorpej 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_control_seg,
    114      1.22   thorpej 			   sc->sc_control_nsegs, sizeof(struct adv_control),
    115      1.39  christos 			   (void **) & sc->sc_control,
    116      1.22   thorpej 			   BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    117      1.47   msaitoh 		aprint_error_dev(sc->sc_dev,
    118      1.47   msaitoh 		    "unable to map control structures, error = %d\n", error);
    119       1.1     dante 		return (error);
    120       1.1     dante 	}
    121       1.1     dante 	/*
    122      1.24    bouyer 	 * Create and load the DMA map used for the control blocks.
    123      1.24    bouyer 	 */
    124       1.1     dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
    125       1.1     dante 			   1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
    126       1.1     dante 				       &sc->sc_dmamap_control)) != 0) {
    127      1.47   msaitoh 		aprint_error_dev(sc->sc_dev,
    128      1.47   msaitoh 		    "unable to create control DMA map, error = %d\n", error);
    129       1.1     dante 		return (error);
    130       1.1     dante 	}
    131       1.1     dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    132       1.1     dante 			   sc->sc_control, sizeof(struct adv_control), NULL,
    133       1.1     dante 				     BUS_DMA_NOWAIT)) != 0) {
    134      1.47   msaitoh 		aprint_error_dev(sc->sc_dev,
    135      1.47   msaitoh 		    "unable to load control DMA map, error = %d\n", error);
    136       1.1     dante 		return (error);
    137       1.1     dante 	}
    138      1.13   thorpej 
    139      1.13   thorpej 	/*
    140      1.13   thorpej 	 * Initialize the overrun_buf address.
    141      1.13   thorpej 	 */
    142      1.13   thorpej 	sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    143      1.13   thorpej 	    offsetof(struct adv_control, overrun_buf);
    144      1.13   thorpej 
    145       1.1     dante 	return (0);
    146       1.1     dante }
    147       1.1     dante 
    148      1.22   thorpej static void
    149      1.43       dsl adv_free_control_data(ASC_SOFTC *sc)
    150      1.22   thorpej {
    151      1.22   thorpej 
    152      1.22   thorpej 	bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_control);
    153      1.22   thorpej 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_control);
    154      1.22   thorpej 	sc->sc_dmamap_control = NULL;
    155      1.22   thorpej 
    156      1.39  christos 	bus_dmamem_unmap(sc->sc_dmat, (void *) sc->sc_control,
    157      1.22   thorpej 	    sizeof(struct adv_control));
    158      1.22   thorpej 	bus_dmamem_free(sc->sc_dmat, &sc->sc_control_seg,
    159      1.22   thorpej 	    sc->sc_control_nsegs);
    160      1.22   thorpej }
    161       1.1     dante 
    162       1.1     dante /*
    163       1.1     dante  * Create a set of ccbs and add them to the free list.  Called once
    164       1.1     dante  * by adv_init().  We return the number of CCBs successfully created.
    165       1.1     dante  */
    166       1.1     dante static int
    167      1.43       dsl adv_create_ccbs(ASC_SOFTC *sc, ADV_CCB *ccbstore, int count)
    168       1.1     dante {
    169       1.1     dante 	ADV_CCB        *ccb;
    170       1.1     dante 	int             i, error;
    171       1.1     dante 
    172      1.27   thorpej 	memset(ccbstore, 0, sizeof(ADV_CCB) * count);
    173       1.1     dante 	for (i = 0; i < count; i++) {
    174       1.1     dante 		ccb = &ccbstore[i];
    175       1.1     dante 		if ((error = adv_init_ccb(sc, ccb)) != 0) {
    176      1.47   msaitoh 			aprint_error_dev(sc->sc_dev,
    177      1.47   msaitoh 			    "unable to initialize ccb, error = %d\n", error);
    178       1.1     dante 			return (i);
    179       1.1     dante 		}
    180       1.1     dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    181       1.1     dante 	}
    182       1.1     dante 
    183       1.1     dante 	return (i);
    184       1.1     dante }
    185       1.1     dante 
    186       1.1     dante 
    187       1.1     dante /*
    188       1.1     dante  * A ccb is put onto the free list.
    189       1.1     dante  */
    190       1.1     dante static void
    191      1.43       dsl adv_free_ccb(ASC_SOFTC *sc, ADV_CCB *ccb)
    192       1.1     dante {
    193       1.1     dante 	int             s;
    194       1.1     dante 
    195       1.1     dante 	s = splbio();
    196       1.1     dante 	adv_reset_ccb(ccb);
    197       1.1     dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    198       1.1     dante 	splx(s);
    199       1.1     dante }
    200       1.1     dante 
    201       1.1     dante 
    202       1.1     dante static void
    203      1.43       dsl adv_reset_ccb(ADV_CCB *ccb)
    204       1.1     dante {
    205       1.1     dante 
    206       1.1     dante 	ccb->flags = 0;
    207       1.1     dante }
    208       1.1     dante 
    209       1.1     dante 
    210       1.1     dante static int
    211      1.43       dsl adv_init_ccb(ASC_SOFTC *sc, ADV_CCB *ccb)
    212       1.1     dante {
    213      1.10     dante 	int	hashnum, error;
    214       1.1     dante 
    215      1.40        ad 	callout_init(&ccb->ccb_watchdog, 0);
    216      1.16   thorpej 
    217       1.1     dante 	/*
    218      1.24    bouyer 	 * Create the DMA map for this CCB.
    219      1.24    bouyer 	 */
    220       1.1     dante 	error = bus_dmamap_create(sc->sc_dmat,
    221       1.1     dante 				  (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
    222       1.1     dante 			 ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
    223       1.1     dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    224       1.1     dante 	if (error) {
    225      1.47   msaitoh 		aprint_error_dev(sc->sc_dev,
    226      1.47   msaitoh 		    "unable to create DMA map, error = %d\n", error);
    227       1.1     dante 		return (error);
    228       1.1     dante 	}
    229      1.10     dante 
    230      1.10     dante 	/*
    231      1.10     dante 	 * put in the phystokv hash table
    232      1.10     dante 	 * Never gets taken out.
    233      1.10     dante 	 */
    234      1.10     dante 	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    235      1.10     dante 	    ADV_CCB_OFF(ccb);
    236      1.10     dante 	hashnum = CCB_HASH(ccb->hashkey);
    237      1.10     dante 	ccb->nexthash = sc->sc_ccbhash[hashnum];
    238      1.10     dante 	sc->sc_ccbhash[hashnum] = ccb;
    239      1.10     dante 
    240       1.1     dante 	adv_reset_ccb(ccb);
    241       1.1     dante 	return (0);
    242       1.1     dante }
    243       1.1     dante 
    244       1.1     dante 
    245       1.1     dante /*
    246       1.1     dante  * Get a free ccb
    247       1.1     dante  *
    248       1.1     dante  * If there are none, see if we can allocate a new one
    249       1.1     dante  */
    250       1.1     dante static ADV_CCB *
    251      1.43       dsl adv_get_ccb(ASC_SOFTC *sc)
    252       1.1     dante {
    253       1.1     dante 	ADV_CCB        *ccb = 0;
    254       1.1     dante 	int             s;
    255       1.1     dante 
    256       1.1     dante 	s = splbio();
    257      1.24    bouyer 	ccb = TAILQ_FIRST(&sc->sc_free_ccb);
    258      1.24    bouyer 	if (ccb != NULL) {
    259      1.24    bouyer 		TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    260      1.24    bouyer 		ccb->flags |= CCB_ALLOC;
    261       1.1     dante 	}
    262       1.1     dante 	splx(s);
    263       1.1     dante 	return (ccb);
    264       1.1     dante }
    265       1.1     dante 
    266       1.1     dante 
    267       1.1     dante /*
    268      1.10     dante  * Given a physical address, find the ccb that it corresponds to.
    269      1.10     dante  */
    270      1.10     dante ADV_CCB *
    271      1.43       dsl adv_ccb_phys_kv(ASC_SOFTC *sc, u_long ccb_phys)
    272      1.10     dante {
    273      1.10     dante 	int hashnum = CCB_HASH(ccb_phys);
    274      1.10     dante 	ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
    275      1.10     dante 
    276      1.10     dante 	while (ccb) {
    277      1.10     dante 		if (ccb->hashkey == ccb_phys)
    278      1.10     dante 			break;
    279      1.10     dante 		ccb = ccb->nexthash;
    280      1.10     dante 	}
    281      1.10     dante 	return (ccb);
    282      1.10     dante }
    283      1.10     dante 
    284      1.10     dante 
    285      1.10     dante /*
    286       1.1     dante  * Queue a CCB to be sent to the controller, and send it if possible.
    287       1.1     dante  */
    288       1.1     dante static void
    289      1.43       dsl adv_queue_ccb(ASC_SOFTC *sc, ADV_CCB *ccb)
    290       1.1     dante {
    291       1.1     dante 
    292       1.1     dante 	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    293       1.1     dante 
    294       1.1     dante 	adv_start_ccbs(sc);
    295       1.1     dante }
    296       1.1     dante 
    297       1.1     dante 
    298       1.1     dante static void
    299      1.43       dsl adv_start_ccbs(ASC_SOFTC *sc)
    300       1.1     dante {
    301       1.1     dante 	ADV_CCB        *ccb;
    302       1.1     dante 
    303       1.1     dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    304       1.1     dante 		if (ccb->flags & CCB_WATCHDOG)
    305      1.16   thorpej 			callout_stop(&ccb->ccb_watchdog);
    306       1.1     dante 
    307       1.1     dante 		if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
    308       1.1     dante 			ccb->flags |= CCB_WATCHDOG;
    309      1.16   thorpej 			callout_reset(&ccb->ccb_watchdog,
    310      1.16   thorpej 			    (ADV_WATCH_TIMEOUT * hz) / 1000,
    311      1.16   thorpej 			    adv_watchdog, ccb);
    312       1.1     dante 			break;
    313       1.1     dante 		}
    314       1.1     dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    315       1.1     dante 
    316      1.14   thorpej 		if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
    317      1.16   thorpej 			callout_reset(&ccb->xs->xs_callout,
    318      1.31    bouyer 			    mstohz(ccb->timeout), adv_timeout, ccb);
    319       1.1     dante 	}
    320       1.1     dante }
    321       1.1     dante 
    322       1.1     dante 
    323       1.1     dante /******************************************************************************/
    324       1.1     dante /*                         SCSI layer interfacing routines                    */
    325       1.1     dante /******************************************************************************/
    326       1.1     dante 
    327       1.1     dante 
    328       1.1     dante int
    329      1.43       dsl adv_init(ASC_SOFTC *sc)
    330       1.1     dante {
    331       1.1     dante 	int             warn;
    332       1.1     dante 
    333      1.12     dante 	if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
    334      1.32   thorpej 		aprint_error("adv_init: failed to find signature\n");
    335      1.12     dante 		return (1);
    336      1.12     dante 	}
    337       1.1     dante 
    338       1.4     dante 	/*
    339      1.24    bouyer 	 * Read the board configuration
    340      1.24    bouyer 	 */
    341       1.4     dante 	AscInitASC_SOFTC(sc);
    342       1.4     dante 	warn = AscInitFromEEP(sc);
    343       1.4     dante 	if (warn) {
    344      1.46       chs 		aprint_error_dev(sc->sc_dev, "-get: ");
    345       1.4     dante 		switch (warn) {
    346       1.4     dante 		case -1:
    347      1.32   thorpej 			aprint_normal("Chip is not halted\n");
    348       1.4     dante 			break;
    349       1.4     dante 
    350       1.4     dante 		case -2:
    351      1.32   thorpej 			aprint_normal("Couldn't get MicroCode Start"
    352       1.4     dante 			       " address\n");
    353       1.4     dante 			break;
    354       1.4     dante 
    355       1.4     dante 		case ASC_WARN_IO_PORT_ROTATE:
    356      1.32   thorpej 			aprint_normal("I/O port address modified\n");
    357       1.4     dante 			break;
    358       1.4     dante 
    359       1.4     dante 		case ASC_WARN_AUTO_CONFIG:
    360      1.32   thorpej 			aprint_normal("I/O port increment switch enabled\n");
    361       1.4     dante 			break;
    362       1.4     dante 
    363       1.4     dante 		case ASC_WARN_EEPROM_CHKSUM:
    364      1.32   thorpej 			aprint_normal("EEPROM checksum error\n");
    365       1.4     dante 			break;
    366       1.4     dante 
    367       1.4     dante 		case ASC_WARN_IRQ_MODIFIED:
    368      1.32   thorpej 			aprint_normal("IRQ modified\n");
    369       1.4     dante 			break;
    370       1.4     dante 
    371       1.4     dante 		case ASC_WARN_CMD_QNG_CONFLICT:
    372      1.32   thorpej 			aprint_normal("tag queuing enabled w/o disconnects\n");
    373       1.4     dante 			break;
    374       1.1     dante 
    375       1.4     dante 		default:
    376      1.32   thorpej 			aprint_normal("unknown warning %d\n", warn);
    377       1.1     dante 		}
    378       1.4     dante 	}
    379       1.4     dante 	if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
    380       1.4     dante 		sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
    381       1.4     dante 
    382       1.4     dante 	/*
    383      1.24    bouyer 	 * Modify the board configuration
    384      1.24    bouyer 	 */
    385       1.4     dante 	warn = AscInitFromASC_SOFTC(sc);
    386       1.4     dante 	if (warn) {
    387      1.46       chs 		aprint_error_dev(sc->sc_dev, "-set: ");
    388       1.4     dante 		switch (warn) {
    389       1.4     dante 		case ASC_WARN_CMD_QNG_CONFLICT:
    390      1.32   thorpej 			aprint_normal("tag queuing enabled w/o disconnects\n");
    391       1.4     dante 			break;
    392       1.1     dante 
    393       1.4     dante 		case ASC_WARN_AUTO_CONFIG:
    394      1.32   thorpej 			aprint_normal("I/O port increment switch enabled\n");
    395       1.4     dante 			break;
    396       1.1     dante 
    397       1.4     dante 		default:
    398      1.32   thorpej 			aprint_normal("unknown warning %d\n", warn);
    399       1.1     dante 		}
    400       1.4     dante 	}
    401      1.11     dante 	sc->isr_callback = (ASC_CALLBACK) adv_narrow_isr_callback;
    402       1.1     dante 
    403       1.1     dante 	return (0);
    404       1.1     dante }
    405       1.1     dante 
    406       1.1     dante 
    407       1.1     dante void
    408      1.43       dsl adv_attach(ASC_SOFTC *sc)
    409       1.1     dante {
    410      1.24    bouyer 	struct scsipi_adapter *adapt = &sc->sc_adapter;
    411      1.24    bouyer 	struct scsipi_channel *chan = &sc->sc_channel;
    412       1.1     dante 	int             i, error;
    413       1.1     dante 
    414       1.4     dante 	/*
    415      1.24    bouyer 	 * Initialize board RISC chip and enable interrupts.
    416      1.24    bouyer 	 */
    417       1.4     dante 	switch (AscInitDriver(sc)) {
    418       1.4     dante 	case 0:
    419       1.4     dante 		/* AllOK */
    420       1.4     dante 		break;
    421       1.1     dante 
    422       1.4     dante 	case 1:
    423      1.46       chs 		panic("%s: bad signature", device_xname(sc->sc_dev));
    424       1.4     dante 		break;
    425       1.1     dante 
    426       1.4     dante 	case 2:
    427       1.4     dante 		panic("%s: unable to load MicroCode",
    428      1.46       chs 		      device_xname(sc->sc_dev));
    429       1.4     dante 		break;
    430       1.1     dante 
    431       1.4     dante 	case 3:
    432       1.4     dante 		panic("%s: unable to initialize MicroCode",
    433      1.46       chs 		      device_xname(sc->sc_dev));
    434       1.4     dante 		break;
    435       1.1     dante 
    436       1.4     dante 	default:
    437       1.4     dante 		panic("%s: unable to initialize board RISC chip",
    438      1.46       chs 		      device_xname(sc->sc_dev));
    439       1.1     dante 	}
    440       1.1     dante 
    441       1.7   thorpej 	/*
    442      1.24    bouyer 	 * Fill in the scsipi_adapter.
    443       1.7   thorpej 	 */
    444      1.24    bouyer 	memset(adapt, 0, sizeof(*adapt));
    445      1.46       chs 	adapt->adapt_dev = sc->sc_dev;
    446      1.24    bouyer 	adapt->adapt_nchannels = 1;
    447      1.24    bouyer 	/* adapt_openings initialized below */
    448      1.24    bouyer 	/* adapt_max_periph initialized below */
    449      1.24    bouyer 	adapt->adapt_request = adv_scsipi_request;
    450      1.24    bouyer 	adapt->adapt_minphys = advminphys;
    451       1.1     dante 
    452       1.1     dante 	/*
    453      1.24    bouyer 	 * Fill in the scsipi_channel.
    454      1.24    bouyer 	 */
    455      1.24    bouyer 	memset(chan, 0, sizeof(*chan));
    456      1.24    bouyer 	chan->chan_adapter = adapt;
    457      1.24    bouyer 	chan->chan_bustype = &scsi_bustype;
    458      1.24    bouyer 	chan->chan_channel = 0;
    459      1.24    bouyer 	chan->chan_ntargets = 8;
    460      1.24    bouyer 	chan->chan_nluns = 8;
    461      1.24    bouyer 	chan->chan_id = sc->chip_scsi_id;
    462       1.1     dante 
    463       1.1     dante 	TAILQ_INIT(&sc->sc_free_ccb);
    464       1.1     dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    465       1.1     dante 
    466       1.1     dante 	/*
    467      1.24    bouyer 	 * Allocate the Control Blocks and the overrun buffer.
    468      1.24    bouyer 	 */
    469      1.13   thorpej 	error = adv_alloc_control_data(sc);
    470       1.1     dante 	if (error)
    471      1.12     dante 		return; /* (error) */
    472       1.1     dante 
    473       1.1     dante 	/*
    474      1.24    bouyer 	 * Create and initialize the Control Blocks.
    475      1.24    bouyer 	 */
    476       1.1     dante 	i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
    477       1.1     dante 	if (i == 0) {
    478      1.47   msaitoh 		aprint_error_dev(sc->sc_dev,
    479      1.47   msaitoh 		    "unable to create control blocks\n");
    480       1.1     dante 		return; /* (ENOMEM) */ ;
    481       1.1     dante 	} else if (i != ADV_MAX_CCB) {
    482      1.47   msaitoh 		aprint_error_dev(sc->sc_dev,
    483      1.42    cegger 		    "WARNING: only %d of %d control blocks created\n",
    484      1.42    cegger 		    i, ADV_MAX_CCB);
    485       1.1     dante 	}
    486      1.24    bouyer 
    487      1.24    bouyer 	adapt->adapt_openings = i;
    488      1.24    bouyer 	adapt->adapt_max_periph = adapt->adapt_openings;
    489      1.24    bouyer 
    490      1.46       chs 	sc->sc_child = config_found(sc->sc_dev, chan, scsiprint);
    491       1.1     dante }
    492       1.1     dante 
    493      1.22   thorpej int
    494      1.43       dsl adv_detach(ASC_SOFTC *sc, int flags)
    495      1.22   thorpej {
    496      1.22   thorpej 	int rv = 0;
    497      1.22   thorpej 
    498      1.22   thorpej 	if (sc->sc_child != NULL)
    499      1.22   thorpej 		rv = config_detach(sc->sc_child, flags);
    500      1.22   thorpej 
    501      1.22   thorpej 	adv_free_control_data(sc);
    502      1.22   thorpej 
    503      1.22   thorpej 	return (rv);
    504      1.22   thorpej }
    505       1.1     dante 
    506       1.1     dante static void
    507      1.43       dsl advminphys(struct buf *bp)
    508       1.1     dante {
    509       1.1     dante 
    510       1.1     dante 	if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
    511       1.1     dante 		bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
    512       1.1     dante 	minphys(bp);
    513       1.1     dante }
    514       1.1     dante 
    515       1.1     dante 
    516       1.1     dante /*
    517       1.1     dante  * start a scsi operation given the command and the data address.  Also needs
    518       1.1     dante  * the unit, target and lu.
    519       1.1     dante  */
    520       1.1     dante 
    521      1.24    bouyer static void
    522      1.47   msaitoh adv_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
    523      1.47   msaitoh     void *arg)
    524      1.24    bouyer {
    525      1.24    bouyer  	struct scsipi_xfer *xs;
    526      1.24    bouyer  	struct scsipi_periph *periph;
    527      1.46       chs  	ASC_SOFTC      *sc = device_private(chan->chan_adapter->adapt_dev);
    528      1.24    bouyer  	bus_dma_tag_t   dmat = sc->sc_dmat;
    529      1.24    bouyer  	ADV_CCB        *ccb;
    530      1.24    bouyer  	int             s, flags, error, nsegs;
    531      1.36     perry 
    532      1.24    bouyer  	switch (req) {
    533      1.24    bouyer  	case ADAPTER_REQ_RUN_XFER:
    534      1.24    bouyer  		xs = arg;
    535      1.24    bouyer  		periph = xs->xs_periph;
    536      1.24    bouyer  		flags = xs->xs_control;
    537      1.36     perry 
    538      1.24    bouyer  		/*
    539      1.24    bouyer  		 * Get a CCB to use.
    540      1.24    bouyer  		 */
    541      1.24    bouyer  		ccb = adv_get_ccb(sc);
    542      1.24    bouyer #ifdef DIAGNOSTIC
    543      1.24    bouyer  		/*
    544      1.24    bouyer  		 * This should never happen as we track the resources
    545      1.24    bouyer  		 * in the mid-layer.
    546      1.24    bouyer  		 */
    547      1.24    bouyer  		if (ccb == NULL) {
    548      1.24    bouyer  			scsipi_printaddr(periph);
    549      1.24    bouyer  			printf("unable to allocate ccb\n");
    550      1.24    bouyer  			panic("adv_scsipi_request");
    551      1.24    bouyer  		}
    552      1.24    bouyer #endif
    553      1.36     perry 
    554      1.24    bouyer  		ccb->xs = xs;
    555      1.24    bouyer  		ccb->timeout = xs->timeout;
    556      1.36     perry 
    557      1.24    bouyer  		/*
    558      1.24    bouyer  		 * Build up the request
    559      1.24    bouyer  		 */
    560      1.24    bouyer  		memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
    561      1.36     perry 
    562      1.24    bouyer  		ccb->scsiq.q2.ccb_ptr =
    563      1.24    bouyer  		    sc->sc_dmamap_control->dm_segs[0].ds_addr +
    564      1.24    bouyer  		    ADV_CCB_OFF(ccb);
    565      1.36     perry 
    566      1.24    bouyer  		ccb->scsiq.cdbptr = &xs->cmd->opcode;
    567      1.24    bouyer  		ccb->scsiq.q2.cdb_len = xs->cmdlen;
    568      1.24    bouyer  		ccb->scsiq.q1.target_id =
    569      1.24    bouyer  		    ASC_TID_TO_TARGET_ID(periph->periph_target);
    570      1.24    bouyer  		ccb->scsiq.q1.target_lun = periph->periph_lun;
    571      1.24    bouyer  		ccb->scsiq.q2.target_ix =
    572      1.24    bouyer  		    ASC_TIDLUN_TO_IX(periph->periph_target,
    573      1.24    bouyer  		    periph->periph_lun);
    574      1.24    bouyer  		ccb->scsiq.q1.sense_addr =
    575      1.24    bouyer  		    sc->sc_dmamap_control->dm_segs[0].ds_addr +
    576      1.24    bouyer  		    ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
    577      1.35   thorpej  		ccb->scsiq.q1.sense_len = sizeof(struct scsi_sense_data);
    578      1.36     perry 
    579      1.24    bouyer  		/*
    580      1.24    bouyer  		 * If there are any outstanding requests for the current
    581      1.24    bouyer  		 * target, then every 255th request send an ORDERED request.
    582      1.24    bouyer  		 * This heuristic tries to retain the benefit of request
    583      1.24    bouyer  		 * sorting while preventing request starvation. 255 is the
    584      1.24    bouyer  		 * max number of tags or pending commands a device may have
    585      1.24    bouyer  		 * outstanding.
    586      1.24    bouyer  		 */
    587      1.24    bouyer  		sc->reqcnt[periph->periph_target]++;
    588      1.24    bouyer  		if (((sc->reqcnt[periph->periph_target] > 0) &&
    589      1.24    bouyer  		    (sc->reqcnt[periph->periph_target] % 255) == 0) ||
    590      1.24    bouyer 		    xs->bp == NULL || (xs->bp->b_flags & B_ASYNC) == 0) {
    591      1.24    bouyer  			ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
    592      1.24    bouyer  		} else {
    593      1.24    bouyer  			ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
    594      1.24    bouyer  		}
    595      1.36     perry 
    596      1.24    bouyer  		if (xs->datalen) {
    597      1.24    bouyer  			/*
    598      1.24    bouyer  			 * Map the DMA transfer.
    599      1.24    bouyer  			 */
    600       1.1     dante #ifdef TFS
    601      1.24    bouyer  			if (flags & SCSI_DATA_UIO) {
    602      1.24    bouyer  				error = bus_dmamap_load_uio(dmat,
    603      1.24    bouyer  				    ccb->dmamap_xfer, (struct uio *) xs->data,
    604      1.24    bouyer 				    ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
    605      1.28   thorpej 				     BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
    606      1.28   thorpej 				     ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
    607      1.28   thorpej 				      BUS_DMA_WRITE));
    608      1.24    bouyer  			} else
    609      1.24    bouyer #endif /* TFS */
    610      1.24    bouyer  			{
    611      1.24    bouyer  				error = bus_dmamap_load(dmat, ccb->dmamap_xfer,
    612      1.24    bouyer  				    xs->data, xs->datalen, NULL,
    613      1.24    bouyer 				    ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
    614      1.28   thorpej 				     BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
    615      1.28   thorpej 				     ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
    616      1.28   thorpej 				      BUS_DMA_WRITE));
    617      1.24    bouyer  			}
    618      1.36     perry 
    619      1.24    bouyer  			switch (error) {
    620      1.24    bouyer  			case 0:
    621      1.24    bouyer  				break;
    622      1.24    bouyer 
    623      1.36     perry 
    624      1.24    bouyer  			case ENOMEM:
    625      1.24    bouyer  			case EAGAIN:
    626      1.24    bouyer  				xs->error = XS_RESOURCE_SHORTAGE;
    627      1.24    bouyer  				goto out_bad;
    628      1.36     perry 
    629      1.24    bouyer  			default:
    630      1.24    bouyer  				xs->error = XS_DRIVER_STUFFUP;
    631      1.24    bouyer 				if (error == EFBIG) {
    632      1.47   msaitoh 					aprint_error_dev(sc->sc_dev,
    633      1.47   msaitoh 					    "adv_scsi_cmd, more than %d"
    634      1.33       wiz 					    " DMA segments\n",
    635      1.24    bouyer 					    ASC_MAX_SG_LIST);
    636      1.24    bouyer 				} else {
    637      1.47   msaitoh 					aprint_error_dev(sc->sc_dev,
    638      1.47   msaitoh 					    "adv_scsi_cmd, error %d"
    639      1.47   msaitoh 					    " loading DMA map\n", error);
    640      1.24    bouyer 				}
    641      1.24    bouyer 
    642      1.24    bouyer out_bad:
    643      1.24    bouyer  				adv_free_ccb(sc, ccb);
    644      1.24    bouyer  				scsipi_done(xs);
    645      1.24    bouyer  				return;
    646      1.24    bouyer  			}
    647      1.24    bouyer  			bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    648      1.24    bouyer  			    ccb->dmamap_xfer->dm_mapsize,
    649      1.24    bouyer  			    (flags & XS_CTL_DATA_IN) ?
    650      1.24    bouyer  			     BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
    651      1.36     perry 
    652      1.24    bouyer  			memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
    653      1.36     perry 
    654      1.24    bouyer  			for (nsegs = 0;
    655      1.24    bouyer  			     nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
    656      1.24    bouyer  				ccb->sghead.sg_list[nsegs].addr =
    657      1.24    bouyer  				    ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
    658      1.24    bouyer  				ccb->sghead.sg_list[nsegs].bytes =
    659      1.24    bouyer  				    ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
    660      1.24    bouyer  			}
    661      1.36     perry 
    662      1.24    bouyer  			ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
    663      1.24    bouyer  			    ccb->dmamap_xfer->dm_nsegs;
    664      1.36     perry 
    665      1.24    bouyer  			ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
    666      1.24    bouyer  			ccb->scsiq.sg_head = &ccb->sghead;
    667      1.24    bouyer  			ccb->scsiq.q1.data_addr = 0;
    668      1.24    bouyer  			ccb->scsiq.q1.data_cnt = 0;
    669      1.24    bouyer  		} else {
    670      1.24    bouyer  			/*
    671      1.24    bouyer  			 * No data xfer, use non S/G values.
    672      1.24    bouyer  			 */
    673      1.24    bouyer  			ccb->scsiq.q1.data_addr = 0;
    674      1.24    bouyer  			ccb->scsiq.q1.data_cnt = 0;
    675      1.24    bouyer  		}
    676      1.36     perry 
    677       1.6     dante #ifdef ASC_DEBUG
    678      1.38  christos  		printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX\n",
    679      1.24    bouyer  		    periph->periph_target,
    680      1.24    bouyer  		    periph->periph_lun, xs->cmd->opcode,
    681      1.24    bouyer  		    (unsigned long)ccb);
    682       1.6     dante #endif
    683      1.24    bouyer  		s = splbio();
    684      1.24    bouyer  		adv_queue_ccb(sc, ccb);
    685      1.24    bouyer  		splx(s);
    686      1.36     perry 
    687      1.24    bouyer  		if ((flags & XS_CTL_POLL) == 0)
    688      1.24    bouyer  			return;
    689      1.36     perry 
    690      1.24    bouyer  		/* Not allowed to use interrupts, poll for completion. */
    691      1.24    bouyer  		if (adv_poll(sc, xs, ccb->timeout)) {
    692      1.24    bouyer  			adv_timeout(ccb);
    693      1.24    bouyer  			if (adv_poll(sc, xs, ccb->timeout))
    694      1.24    bouyer  				adv_timeout(ccb);
    695      1.24    bouyer  		}
    696      1.24    bouyer  		return;
    697      1.36     perry 
    698      1.24    bouyer  	case ADAPTER_REQ_GROW_RESOURCES:
    699      1.24    bouyer  		/* XXX Not supported. */
    700      1.24    bouyer  		return;
    701      1.36     perry 
    702      1.24    bouyer  	case ADAPTER_REQ_SET_XFER_MODE:
    703      1.24    bouyer  	    {
    704      1.24    bouyer  		/*
    705      1.24    bouyer  		 * We can't really set the mode, but we know how to
    706      1.24    bouyer  		 * query what the firmware negotiated.
    707      1.24    bouyer  		 */
    708      1.24    bouyer  		struct scsipi_xfer_mode *xm = arg;
    709      1.24    bouyer  		u_int8_t sdtr_data;
    710      1.24    bouyer  		ASC_SCSI_BIT_ID_TYPE tid_bit;
    711      1.36     perry 
    712      1.24    bouyer  		tid_bit = ASC_TIX_TO_TARGET_ID(xm->xm_target);
    713      1.36     perry 
    714      1.24    bouyer  		xm->xm_mode = 0;
    715      1.24    bouyer  		xm->xm_period = 0;
    716      1.24    bouyer  		xm->xm_offset = 0;
    717      1.36     perry 
    718      1.24    bouyer  		if (sc->init_sdtr & tid_bit) {
    719      1.24    bouyer  			xm->xm_mode |= PERIPH_CAP_SYNC;
    720      1.24    bouyer  			sdtr_data = sc->sdtr_data[xm->xm_target];
    721      1.24    bouyer  			xm->xm_period =
    722      1.24    bouyer  			    sc->sdtr_period_tbl[(sdtr_data >> 4) &
    723      1.24    bouyer  			    (sc->max_sdtr_index - 1)];
    724      1.24    bouyer  			xm->xm_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
    725      1.24    bouyer  		}
    726      1.36     perry 
    727      1.24    bouyer  		if (sc->use_tagged_qng & tid_bit)
    728      1.24    bouyer  			xm->xm_mode |= PERIPH_CAP_TQING;
    729      1.36     perry 
    730      1.24    bouyer  		scsipi_async_event(chan, ASYNC_EVENT_XFER_MODE, xm);
    731      1.24    bouyer  		return;
    732      1.24    bouyer  	    }
    733      1.24    bouyer  	}
    734       1.1     dante }
    735       1.1     dante 
    736       1.1     dante int
    737      1.43       dsl adv_intr(void *arg)
    738       1.1     dante {
    739       1.1     dante 	ASC_SOFTC      *sc = arg;
    740       1.1     dante 
    741       1.6     dante #ifdef ASC_DEBUG
    742       1.6     dante 	int int_pend = FALSE;
    743       1.6     dante 
    744      1.47   msaitoh 	if (ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh)) {
    745       1.6     dante 		int_pend = TRUE;
    746       1.6     dante 		printf("ISR - ");
    747       1.6     dante 	}
    748       1.6     dante #endif
    749       1.4     dante 	AscISR(sc);
    750       1.6     dante #ifdef ASC_DEBUG
    751       1.6     dante 	if(int_pend)
    752       1.6     dante 		printf("\n");
    753       1.6     dante #endif
    754       1.1     dante 
    755       1.1     dante 	return (1);
    756       1.1     dante }
    757       1.1     dante 
    758       1.1     dante 
    759       1.1     dante /*
    760       1.1     dante  * Poll a particular unit, looking for a particular xs
    761       1.1     dante  */
    762       1.1     dante static int
    763      1.43       dsl adv_poll(ASC_SOFTC *sc, struct scsipi_xfer *xs, int count)
    764       1.1     dante {
    765       1.1     dante 
    766       1.1     dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
    767       1.1     dante 	while (count) {
    768       1.1     dante 		adv_intr(sc);
    769      1.14   thorpej 		if (xs->xs_status & XS_STS_DONE)
    770       1.1     dante 			return (0);
    771       1.1     dante 		delay(1000);	/* only happens in boot so ok */
    772       1.1     dante 		count--;
    773       1.1     dante 	}
    774       1.1     dante 	return (1);
    775       1.1     dante }
    776       1.1     dante 
    777       1.1     dante 
    778       1.1     dante static void
    779      1.43       dsl adv_timeout(void *arg)
    780       1.1     dante {
    781       1.1     dante 	ADV_CCB        *ccb = arg;
    782       1.1     dante 	struct scsipi_xfer *xs = ccb->xs;
    783      1.24    bouyer 	struct scsipi_periph *periph = xs->xs_periph;
    784      1.24    bouyer 	ASC_SOFTC      *sc =
    785      1.46       chs 	    device_private(periph->periph_channel->chan_adapter->adapt_dev);
    786       1.1     dante 	int             s;
    787       1.1     dante 
    788      1.24    bouyer 	scsipi_printaddr(periph);
    789       1.1     dante 	printf("timed out");
    790       1.1     dante 
    791       1.1     dante 	s = splbio();
    792       1.1     dante 
    793       1.1     dante 	/*
    794      1.24    bouyer 	 * If it has been through before, then a previous abort has failed,
    795      1.24    bouyer 	 * don't try abort again, reset the bus instead.
    796      1.24    bouyer 	 */
    797       1.1     dante 	if (ccb->flags & CCB_ABORT) {
    798       1.1     dante 		/* abort timed out */
    799       1.1     dante 		printf(" AGAIN. Resetting Bus\n");
    800       1.1     dante 		/* Lets try resetting the bus! */
    801       1.1     dante 		if (AscResetBus(sc) == ASC_ERROR) {
    802       1.1     dante 			ccb->timeout = sc->scsi_reset_wait;
    803       1.1     dante 			adv_queue_ccb(sc, ccb);
    804       1.1     dante 		}
    805       1.1     dante 	} else {
    806       1.1     dante 		/* abort the operation that has timed out */
    807       1.1     dante 		printf("\n");
    808      1.10     dante 		AscAbortCCB(sc, ccb);
    809       1.1     dante 		ccb->xs->error = XS_TIMEOUT;
    810       1.1     dante 		ccb->timeout = ADV_ABORT_TIMEOUT;
    811       1.1     dante 		ccb->flags |= CCB_ABORT;
    812       1.1     dante 		adv_queue_ccb(sc, ccb);
    813       1.1     dante 	}
    814       1.1     dante 
    815       1.1     dante 	splx(s);
    816       1.1     dante }
    817       1.1     dante 
    818       1.1     dante 
    819       1.1     dante static void
    820      1.43       dsl adv_watchdog(void *arg)
    821       1.1     dante {
    822       1.1     dante 	ADV_CCB        *ccb = arg;
    823       1.1     dante 	struct scsipi_xfer *xs = ccb->xs;
    824      1.24    bouyer 	struct scsipi_periph *periph = xs->xs_periph;
    825      1.24    bouyer 	ASC_SOFTC      *sc =
    826      1.46       chs 	    device_private(periph->periph_channel->chan_adapter->adapt_dev);
    827       1.1     dante 	int             s;
    828       1.1     dante 
    829       1.1     dante 	s = splbio();
    830       1.1     dante 
    831       1.1     dante 	ccb->flags &= ~CCB_WATCHDOG;
    832       1.1     dante 	adv_start_ccbs(sc);
    833       1.1     dante 
    834       1.1     dante 	splx(s);
    835       1.1     dante }
    836       1.1     dante 
    837       1.1     dante 
    838       1.1     dante /******************************************************************************/
    839      1.10     dante /*                      NARROW boards Interrupt callbacks                     */
    840       1.1     dante /******************************************************************************/
    841       1.1     dante 
    842       1.1     dante 
    843       1.1     dante /*
    844       1.1     dante  * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
    845       1.1     dante  *
    846       1.1     dante  * Interrupt callback function for the Narrow SCSI Asc Library.
    847       1.1     dante  */
    848       1.1     dante static void
    849      1.43       dsl adv_narrow_isr_callback(ASC_SOFTC *sc, ASC_QDONE_INFO *qdonep)
    850       1.1     dante {
    851       1.1     dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    852      1.10     dante 	ADV_CCB        *ccb;
    853      1.10     dante 	struct scsipi_xfer *xs;
    854      1.35   thorpej 	struct scsi_sense_data *s1, *s2;
    855       1.1     dante 
    856      1.10     dante 
    857      1.10     dante 	ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
    858      1.10     dante 	xs = ccb->xs;
    859       1.1     dante 
    860       1.6     dante #ifdef ASC_DEBUG
    861       1.6     dante 	printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
    862       1.6     dante 			(unsigned long)ccb,
    863      1.24    bouyer 			xs->xs_periph->periph_target,
    864      1.24    bouyer 			xs->xs_periph->periph_lun, xs->cmd->opcode);
    865       1.6     dante #endif
    866      1.16   thorpej 	callout_stop(&ccb->xs->xs_callout);
    867       1.1     dante 
    868       1.1     dante 	/*
    869      1.24    bouyer 	 * If we were a data transfer, unload the map that described
    870      1.24    bouyer 	 * the data buffer.
    871      1.24    bouyer 	 */
    872       1.1     dante 	if (xs->datalen) {
    873       1.1     dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    874       1.1     dante 				ccb->dmamap_xfer->dm_mapsize,
    875      1.14   thorpej 			 (xs->xs_control & XS_CTL_DATA_IN) ?
    876      1.14   thorpej 			 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
    877       1.1     dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
    878       1.1     dante 	}
    879       1.1     dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
    880      1.46       chs 		aprint_error_dev(sc->sc_dev, "exiting ccb not allocated!\n");
    881       1.1     dante 		Debugger();
    882       1.1     dante 		return;
    883       1.1     dante 	}
    884       1.1     dante 	/*
    885      1.24    bouyer 	 * 'qdonep' contains the command's ending status.
    886      1.24    bouyer 	 */
    887       1.6     dante #ifdef ASC_DEBUG
    888       1.6     dante 	printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
    889       1.6     dante #endif
    890       1.1     dante 	switch (qdonep->d3.done_stat) {
    891       1.1     dante 	case ASC_QD_NO_ERROR:
    892       1.1     dante 		switch (qdonep->d3.host_stat) {
    893       1.1     dante 		case ASC_QHSTA_NO_ERROR:
    894       1.1     dante 			xs->error = XS_NOERROR;
    895      1.48       rin 			/*
    896      1.48       rin 			 * XXX
    897      1.48       rin 			 * According to the original Linux driver, xs->resid
    898      1.48       rin 			 * should be qdonep->remain_bytes. However, its value
    899      1.48       rin 			 * is bogus, which seems like a H/W bug. The best thing
    900      1.48       rin 			 * we can do would be to ignore it, assuming that all
    901      1.48       rin 			 * data has been successfully transferred...
    902      1.48       rin 			 */
    903       1.1     dante 			xs->resid = 0;
    904       1.1     dante 			break;
    905       1.1     dante 
    906       1.1     dante 		default:
    907       1.1     dante 			/* QHSTA error occurred */
    908       1.1     dante 			xs->error = XS_DRIVER_STUFFUP;
    909       1.1     dante 			break;
    910       1.1     dante 		}
    911       1.1     dante 
    912       1.1     dante 		/*
    913      1.24    bouyer 	         * If an INQUIRY command completed successfully, then call
    914      1.24    bouyer 	         * the AscInquiryHandling() function to patch bugged boards.
    915      1.24    bouyer 	         */
    916       1.1     dante 		if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
    917      1.24    bouyer 		    (xs->xs_periph->periph_lun == 0) &&
    918       1.1     dante 		    (xs->datalen - qdonep->remain_bytes) >= 8) {
    919       1.1     dante 			AscInquiryHandling(sc,
    920      1.24    bouyer 				      xs->xs_periph->periph_target & 0x7,
    921       1.1     dante 					   (ASC_SCSI_INQUIRY *) xs->data);
    922       1.1     dante 		}
    923       1.1     dante 		break;
    924       1.1     dante 
    925       1.1     dante 	case ASC_QD_WITH_ERROR:
    926       1.1     dante 		switch (qdonep->d3.host_stat) {
    927       1.1     dante 		case ASC_QHSTA_NO_ERROR:
    928       1.1     dante 			if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
    929       1.1     dante 				s1 = &ccb->scsi_sense;
    930       1.1     dante 				s2 = &xs->sense.scsi_sense;
    931       1.1     dante 				*s2 = *s1;
    932       1.1     dante 				xs->error = XS_SENSE;
    933       1.4     dante 			} else {
    934       1.1     dante 				xs->error = XS_DRIVER_STUFFUP;
    935       1.4     dante 			}
    936      1.25    briggs 			break;
    937      1.25    briggs 
    938      1.25    briggs 		case ASC_QHSTA_M_SEL_TIMEOUT:
    939      1.26    briggs 			xs->error = XS_SELTIMEOUT;
    940       1.1     dante 			break;
    941       1.1     dante 
    942       1.1     dante 		default:
    943       1.1     dante 			/* QHSTA error occurred */
    944       1.1     dante 			xs->error = XS_DRIVER_STUFFUP;
    945       1.1     dante 			break;
    946       1.1     dante 		}
    947       1.1     dante 		break;
    948       1.1     dante 
    949       1.1     dante 	case ASC_QD_ABORTED_BY_HOST:
    950       1.1     dante 	default:
    951       1.1     dante 		xs->error = XS_DRIVER_STUFFUP;
    952       1.1     dante 		break;
    953       1.1     dante 	}
    954       1.1     dante 
    955       1.1     dante 	adv_free_ccb(sc, ccb);
    956       1.1     dante 	scsipi_done(xs);
    957       1.1     dante }
    958