adv.c revision 1.49 1 1.49 uwe /* $NetBSD: adv.c,v 1.49 2019/10/06 00:48:19 uwe Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.4 dante * Generic driver for the Advanced Systems Inc. Narrow SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.4 dante * This product includes software developed by the NetBSD
22 1.4 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.29 lukem
40 1.29 lukem #include <sys/cdefs.h>
41 1.49 uwe __KERNEL_RCSID(0, "$NetBSD: adv.c,v 1.49 2019/10/06 00:48:19 uwe Exp $");
42 1.1 dante
43 1.1 dante #include <sys/param.h>
44 1.1 dante #include <sys/systm.h>
45 1.16 thorpej #include <sys/callout.h>
46 1.1 dante #include <sys/kernel.h>
47 1.1 dante #include <sys/errno.h>
48 1.1 dante #include <sys/ioctl.h>
49 1.1 dante #include <sys/device.h>
50 1.1 dante #include <sys/malloc.h>
51 1.1 dante #include <sys/buf.h>
52 1.1 dante #include <sys/proc.h>
53 1.1 dante
54 1.41 ad #include <sys/bus.h>
55 1.41 ad #include <sys/intr.h>
56 1.1 dante
57 1.1 dante #include <dev/scsipi/scsi_all.h>
58 1.1 dante #include <dev/scsipi/scsipi_all.h>
59 1.1 dante #include <dev/scsipi/scsiconf.h>
60 1.1 dante
61 1.10 dante #include <dev/ic/advlib.h>
62 1.1 dante #include <dev/ic/adv.h>
63 1.3 thorpej
64 1.3 thorpej #ifndef DDB
65 1.3 thorpej #define Debugger() panic("should call debugger here (adv.c)")
66 1.3 thorpej #endif /* ! DDB */
67 1.1 dante
68 1.6 dante
69 1.6 dante /* #define ASC_DEBUG */
70 1.6 dante
71 1.1 dante /******************************************************************************/
72 1.1 dante
73 1.1 dante
74 1.34 perry static int adv_alloc_control_data(ASC_SOFTC *);
75 1.34 perry static void adv_free_control_data(ASC_SOFTC *);
76 1.34 perry static int adv_create_ccbs(ASC_SOFTC *, ADV_CCB *, int);
77 1.34 perry static void adv_free_ccb(ASC_SOFTC *, ADV_CCB *);
78 1.34 perry static void adv_reset_ccb(ADV_CCB *);
79 1.34 perry static int adv_init_ccb(ASC_SOFTC *, ADV_CCB *);
80 1.34 perry static ADV_CCB *adv_get_ccb(ASC_SOFTC *);
81 1.34 perry static void adv_queue_ccb(ASC_SOFTC *, ADV_CCB *);
82 1.34 perry static void adv_start_ccbs(ASC_SOFTC *);
83 1.34 perry
84 1.34 perry
85 1.34 perry static void adv_scsipi_request(struct scsipi_channel *,
86 1.34 perry scsipi_adapter_req_t, void *);
87 1.34 perry static void advminphys(struct buf *);
88 1.34 perry static void adv_narrow_isr_callback(ASC_SOFTC *, ASC_QDONE_INFO *);
89 1.34 perry
90 1.34 perry static int adv_poll(ASC_SOFTC *, struct scsipi_xfer *, int);
91 1.34 perry static void adv_timeout(void *);
92 1.34 perry static void adv_watchdog(void *);
93 1.1 dante
94 1.1 dante
95 1.1 dante /******************************************************************************/
96 1.1 dante
97 1.1 dante #define ADV_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
98 1.1 dante #define ADV_WATCH_TIMEOUT 1000 /* time to wait for watchdog (mSec) */
99 1.1 dante
100 1.1 dante /******************************************************************************/
101 1.1 dante /* Control Blocks routines */
102 1.1 dante /******************************************************************************/
103 1.1 dante
104 1.1 dante
105 1.1 dante static int
106 1.43 dsl adv_alloc_control_data(ASC_SOFTC *sc)
107 1.1 dante {
108 1.22 thorpej int error;
109 1.1 dante
110 1.1 dante /*
111 1.24 bouyer * Allocate the control blocks.
112 1.24 bouyer */
113 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adv_control),
114 1.22 thorpej PAGE_SIZE, 0, &sc->sc_control_seg, 1,
115 1.22 thorpej &sc->sc_control_nsegs, BUS_DMA_NOWAIT)) != 0) {
116 1.47 msaitoh aprint_error_dev(sc->sc_dev, "unable to allocate control "
117 1.47 msaitoh "structures, error = %d\n", error);
118 1.1 dante return (error);
119 1.1 dante }
120 1.22 thorpej if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_control_seg,
121 1.22 thorpej sc->sc_control_nsegs, sizeof(struct adv_control),
122 1.39 christos (void **) & sc->sc_control,
123 1.22 thorpej BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
124 1.47 msaitoh aprint_error_dev(sc->sc_dev,
125 1.47 msaitoh "unable to map control structures, error = %d\n", error);
126 1.1 dante return (error);
127 1.1 dante }
128 1.1 dante /*
129 1.24 bouyer * Create and load the DMA map used for the control blocks.
130 1.24 bouyer */
131 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adv_control),
132 1.1 dante 1, sizeof(struct adv_control), 0, BUS_DMA_NOWAIT,
133 1.1 dante &sc->sc_dmamap_control)) != 0) {
134 1.47 msaitoh aprint_error_dev(sc->sc_dev,
135 1.47 msaitoh "unable to create control DMA map, error = %d\n", error);
136 1.1 dante return (error);
137 1.1 dante }
138 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
139 1.1 dante sc->sc_control, sizeof(struct adv_control), NULL,
140 1.1 dante BUS_DMA_NOWAIT)) != 0) {
141 1.47 msaitoh aprint_error_dev(sc->sc_dev,
142 1.47 msaitoh "unable to load control DMA map, error = %d\n", error);
143 1.1 dante return (error);
144 1.1 dante }
145 1.13 thorpej
146 1.13 thorpej /*
147 1.13 thorpej * Initialize the overrun_buf address.
148 1.13 thorpej */
149 1.13 thorpej sc->overrun_buf = sc->sc_dmamap_control->dm_segs[0].ds_addr +
150 1.13 thorpej offsetof(struct adv_control, overrun_buf);
151 1.13 thorpej
152 1.1 dante return (0);
153 1.1 dante }
154 1.1 dante
155 1.22 thorpej static void
156 1.43 dsl adv_free_control_data(ASC_SOFTC *sc)
157 1.22 thorpej {
158 1.22 thorpej
159 1.22 thorpej bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_control);
160 1.22 thorpej bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_control);
161 1.22 thorpej sc->sc_dmamap_control = NULL;
162 1.22 thorpej
163 1.39 christos bus_dmamem_unmap(sc->sc_dmat, (void *) sc->sc_control,
164 1.22 thorpej sizeof(struct adv_control));
165 1.22 thorpej bus_dmamem_free(sc->sc_dmat, &sc->sc_control_seg,
166 1.22 thorpej sc->sc_control_nsegs);
167 1.22 thorpej }
168 1.1 dante
169 1.1 dante /*
170 1.1 dante * Create a set of ccbs and add them to the free list. Called once
171 1.1 dante * by adv_init(). We return the number of CCBs successfully created.
172 1.1 dante */
173 1.1 dante static int
174 1.43 dsl adv_create_ccbs(ASC_SOFTC *sc, ADV_CCB *ccbstore, int count)
175 1.1 dante {
176 1.1 dante ADV_CCB *ccb;
177 1.1 dante int i, error;
178 1.1 dante
179 1.27 thorpej memset(ccbstore, 0, sizeof(ADV_CCB) * count);
180 1.1 dante for (i = 0; i < count; i++) {
181 1.1 dante ccb = &ccbstore[i];
182 1.1 dante if ((error = adv_init_ccb(sc, ccb)) != 0) {
183 1.47 msaitoh aprint_error_dev(sc->sc_dev,
184 1.47 msaitoh "unable to initialize ccb, error = %d\n", error);
185 1.1 dante return (i);
186 1.1 dante }
187 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
188 1.1 dante }
189 1.1 dante
190 1.1 dante return (i);
191 1.1 dante }
192 1.1 dante
193 1.1 dante
194 1.1 dante /*
195 1.1 dante * A ccb is put onto the free list.
196 1.1 dante */
197 1.1 dante static void
198 1.43 dsl adv_free_ccb(ASC_SOFTC *sc, ADV_CCB *ccb)
199 1.1 dante {
200 1.1 dante int s;
201 1.1 dante
202 1.1 dante s = splbio();
203 1.1 dante adv_reset_ccb(ccb);
204 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
205 1.1 dante splx(s);
206 1.1 dante }
207 1.1 dante
208 1.1 dante
209 1.1 dante static void
210 1.43 dsl adv_reset_ccb(ADV_CCB *ccb)
211 1.1 dante {
212 1.1 dante
213 1.1 dante ccb->flags = 0;
214 1.1 dante }
215 1.1 dante
216 1.1 dante
217 1.1 dante static int
218 1.43 dsl adv_init_ccb(ASC_SOFTC *sc, ADV_CCB *ccb)
219 1.1 dante {
220 1.10 dante int hashnum, error;
221 1.1 dante
222 1.40 ad callout_init(&ccb->ccb_watchdog, 0);
223 1.16 thorpej
224 1.1 dante /*
225 1.24 bouyer * Create the DMA map for this CCB.
226 1.24 bouyer */
227 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
228 1.1 dante (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
229 1.1 dante ASC_MAX_SG_LIST, (ASC_MAX_SG_LIST - 1) * PAGE_SIZE,
230 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
231 1.1 dante if (error) {
232 1.47 msaitoh aprint_error_dev(sc->sc_dev,
233 1.47 msaitoh "unable to create DMA map, error = %d\n", error);
234 1.1 dante return (error);
235 1.1 dante }
236 1.10 dante
237 1.10 dante /*
238 1.10 dante * put in the phystokv hash table
239 1.10 dante * Never gets taken out.
240 1.10 dante */
241 1.10 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
242 1.10 dante ADV_CCB_OFF(ccb);
243 1.10 dante hashnum = CCB_HASH(ccb->hashkey);
244 1.10 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
245 1.10 dante sc->sc_ccbhash[hashnum] = ccb;
246 1.10 dante
247 1.1 dante adv_reset_ccb(ccb);
248 1.1 dante return (0);
249 1.1 dante }
250 1.1 dante
251 1.1 dante
252 1.1 dante /*
253 1.1 dante * Get a free ccb
254 1.1 dante *
255 1.1 dante * If there are none, see if we can allocate a new one
256 1.1 dante */
257 1.1 dante static ADV_CCB *
258 1.43 dsl adv_get_ccb(ASC_SOFTC *sc)
259 1.1 dante {
260 1.1 dante ADV_CCB *ccb = 0;
261 1.1 dante int s;
262 1.1 dante
263 1.1 dante s = splbio();
264 1.24 bouyer ccb = TAILQ_FIRST(&sc->sc_free_ccb);
265 1.24 bouyer if (ccb != NULL) {
266 1.24 bouyer TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
267 1.24 bouyer ccb->flags |= CCB_ALLOC;
268 1.1 dante }
269 1.1 dante splx(s);
270 1.1 dante return (ccb);
271 1.1 dante }
272 1.1 dante
273 1.1 dante
274 1.1 dante /*
275 1.10 dante * Given a physical address, find the ccb that it corresponds to.
276 1.10 dante */
277 1.10 dante ADV_CCB *
278 1.43 dsl adv_ccb_phys_kv(ASC_SOFTC *sc, u_long ccb_phys)
279 1.10 dante {
280 1.10 dante int hashnum = CCB_HASH(ccb_phys);
281 1.10 dante ADV_CCB *ccb = sc->sc_ccbhash[hashnum];
282 1.10 dante
283 1.10 dante while (ccb) {
284 1.10 dante if (ccb->hashkey == ccb_phys)
285 1.10 dante break;
286 1.10 dante ccb = ccb->nexthash;
287 1.10 dante }
288 1.10 dante return (ccb);
289 1.10 dante }
290 1.10 dante
291 1.10 dante
292 1.10 dante /*
293 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
294 1.1 dante */
295 1.1 dante static void
296 1.43 dsl adv_queue_ccb(ASC_SOFTC *sc, ADV_CCB *ccb)
297 1.1 dante {
298 1.1 dante
299 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
300 1.1 dante
301 1.1 dante adv_start_ccbs(sc);
302 1.1 dante }
303 1.1 dante
304 1.1 dante
305 1.1 dante static void
306 1.43 dsl adv_start_ccbs(ASC_SOFTC *sc)
307 1.1 dante {
308 1.1 dante ADV_CCB *ccb;
309 1.1 dante
310 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
311 1.1 dante if (ccb->flags & CCB_WATCHDOG)
312 1.16 thorpej callout_stop(&ccb->ccb_watchdog);
313 1.1 dante
314 1.1 dante if (AscExeScsiQueue(sc, &ccb->scsiq) == ASC_BUSY) {
315 1.1 dante ccb->flags |= CCB_WATCHDOG;
316 1.16 thorpej callout_reset(&ccb->ccb_watchdog,
317 1.16 thorpej (ADV_WATCH_TIMEOUT * hz) / 1000,
318 1.16 thorpej adv_watchdog, ccb);
319 1.1 dante break;
320 1.1 dante }
321 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
322 1.1 dante
323 1.14 thorpej if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
324 1.16 thorpej callout_reset(&ccb->xs->xs_callout,
325 1.31 bouyer mstohz(ccb->timeout), adv_timeout, ccb);
326 1.1 dante }
327 1.1 dante }
328 1.1 dante
329 1.1 dante
330 1.1 dante /******************************************************************************/
331 1.1 dante /* SCSI layer interfacing routines */
332 1.1 dante /******************************************************************************/
333 1.1 dante
334 1.1 dante
335 1.1 dante int
336 1.43 dsl adv_init(ASC_SOFTC *sc)
337 1.1 dante {
338 1.1 dante int warn;
339 1.1 dante
340 1.12 dante if (!AscFindSignature(sc->sc_iot, sc->sc_ioh)) {
341 1.32 thorpej aprint_error("adv_init: failed to find signature\n");
342 1.12 dante return (1);
343 1.12 dante }
344 1.1 dante
345 1.4 dante /*
346 1.24 bouyer * Read the board configuration
347 1.24 bouyer */
348 1.4 dante AscInitASC_SOFTC(sc);
349 1.4 dante warn = AscInitFromEEP(sc);
350 1.4 dante if (warn) {
351 1.46 chs aprint_error_dev(sc->sc_dev, "-get: ");
352 1.4 dante switch (warn) {
353 1.4 dante case -1:
354 1.32 thorpej aprint_normal("Chip is not halted\n");
355 1.4 dante break;
356 1.4 dante
357 1.4 dante case -2:
358 1.32 thorpej aprint_normal("Couldn't get MicroCode Start"
359 1.4 dante " address\n");
360 1.4 dante break;
361 1.4 dante
362 1.4 dante case ASC_WARN_IO_PORT_ROTATE:
363 1.32 thorpej aprint_normal("I/O port address modified\n");
364 1.4 dante break;
365 1.4 dante
366 1.4 dante case ASC_WARN_AUTO_CONFIG:
367 1.32 thorpej aprint_normal("I/O port increment switch enabled\n");
368 1.4 dante break;
369 1.4 dante
370 1.4 dante case ASC_WARN_EEPROM_CHKSUM:
371 1.32 thorpej aprint_normal("EEPROM checksum error\n");
372 1.4 dante break;
373 1.4 dante
374 1.4 dante case ASC_WARN_IRQ_MODIFIED:
375 1.32 thorpej aprint_normal("IRQ modified\n");
376 1.4 dante break;
377 1.4 dante
378 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
379 1.32 thorpej aprint_normal("tag queuing enabled w/o disconnects\n");
380 1.4 dante break;
381 1.1 dante
382 1.4 dante default:
383 1.32 thorpej aprint_normal("unknown warning %d\n", warn);
384 1.1 dante }
385 1.4 dante }
386 1.4 dante if (sc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
387 1.4 dante sc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
388 1.4 dante
389 1.4 dante /*
390 1.24 bouyer * Modify the board configuration
391 1.24 bouyer */
392 1.4 dante warn = AscInitFromASC_SOFTC(sc);
393 1.4 dante if (warn) {
394 1.46 chs aprint_error_dev(sc->sc_dev, "-set: ");
395 1.4 dante switch (warn) {
396 1.4 dante case ASC_WARN_CMD_QNG_CONFLICT:
397 1.32 thorpej aprint_normal("tag queuing enabled w/o disconnects\n");
398 1.4 dante break;
399 1.1 dante
400 1.4 dante case ASC_WARN_AUTO_CONFIG:
401 1.32 thorpej aprint_normal("I/O port increment switch enabled\n");
402 1.4 dante break;
403 1.1 dante
404 1.4 dante default:
405 1.32 thorpej aprint_normal("unknown warning %d\n", warn);
406 1.1 dante }
407 1.4 dante }
408 1.49 uwe sc->isr_callback = adv_narrow_isr_callback;
409 1.1 dante
410 1.1 dante return (0);
411 1.1 dante }
412 1.1 dante
413 1.1 dante
414 1.1 dante void
415 1.43 dsl adv_attach(ASC_SOFTC *sc)
416 1.1 dante {
417 1.24 bouyer struct scsipi_adapter *adapt = &sc->sc_adapter;
418 1.24 bouyer struct scsipi_channel *chan = &sc->sc_channel;
419 1.1 dante int i, error;
420 1.1 dante
421 1.4 dante /*
422 1.24 bouyer * Initialize board RISC chip and enable interrupts.
423 1.24 bouyer */
424 1.4 dante switch (AscInitDriver(sc)) {
425 1.4 dante case 0:
426 1.4 dante /* AllOK */
427 1.4 dante break;
428 1.1 dante
429 1.4 dante case 1:
430 1.46 chs panic("%s: bad signature", device_xname(sc->sc_dev));
431 1.4 dante break;
432 1.1 dante
433 1.4 dante case 2:
434 1.4 dante panic("%s: unable to load MicroCode",
435 1.46 chs device_xname(sc->sc_dev));
436 1.4 dante break;
437 1.1 dante
438 1.4 dante case 3:
439 1.4 dante panic("%s: unable to initialize MicroCode",
440 1.46 chs device_xname(sc->sc_dev));
441 1.4 dante break;
442 1.1 dante
443 1.4 dante default:
444 1.4 dante panic("%s: unable to initialize board RISC chip",
445 1.46 chs device_xname(sc->sc_dev));
446 1.1 dante }
447 1.1 dante
448 1.7 thorpej /*
449 1.24 bouyer * Fill in the scsipi_adapter.
450 1.7 thorpej */
451 1.24 bouyer memset(adapt, 0, sizeof(*adapt));
452 1.46 chs adapt->adapt_dev = sc->sc_dev;
453 1.24 bouyer adapt->adapt_nchannels = 1;
454 1.24 bouyer /* adapt_openings initialized below */
455 1.24 bouyer /* adapt_max_periph initialized below */
456 1.24 bouyer adapt->adapt_request = adv_scsipi_request;
457 1.24 bouyer adapt->adapt_minphys = advminphys;
458 1.1 dante
459 1.1 dante /*
460 1.24 bouyer * Fill in the scsipi_channel.
461 1.24 bouyer */
462 1.24 bouyer memset(chan, 0, sizeof(*chan));
463 1.24 bouyer chan->chan_adapter = adapt;
464 1.24 bouyer chan->chan_bustype = &scsi_bustype;
465 1.24 bouyer chan->chan_channel = 0;
466 1.24 bouyer chan->chan_ntargets = 8;
467 1.24 bouyer chan->chan_nluns = 8;
468 1.24 bouyer chan->chan_id = sc->chip_scsi_id;
469 1.1 dante
470 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
471 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
472 1.1 dante
473 1.1 dante /*
474 1.24 bouyer * Allocate the Control Blocks and the overrun buffer.
475 1.24 bouyer */
476 1.13 thorpej error = adv_alloc_control_data(sc);
477 1.1 dante if (error)
478 1.12 dante return; /* (error) */
479 1.1 dante
480 1.1 dante /*
481 1.24 bouyer * Create and initialize the Control Blocks.
482 1.24 bouyer */
483 1.1 dante i = adv_create_ccbs(sc, sc->sc_control->ccbs, ADV_MAX_CCB);
484 1.1 dante if (i == 0) {
485 1.47 msaitoh aprint_error_dev(sc->sc_dev,
486 1.47 msaitoh "unable to create control blocks\n");
487 1.1 dante return; /* (ENOMEM) */ ;
488 1.1 dante } else if (i != ADV_MAX_CCB) {
489 1.47 msaitoh aprint_error_dev(sc->sc_dev,
490 1.42 cegger "WARNING: only %d of %d control blocks created\n",
491 1.42 cegger i, ADV_MAX_CCB);
492 1.1 dante }
493 1.24 bouyer
494 1.24 bouyer adapt->adapt_openings = i;
495 1.24 bouyer adapt->adapt_max_periph = adapt->adapt_openings;
496 1.24 bouyer
497 1.46 chs sc->sc_child = config_found(sc->sc_dev, chan, scsiprint);
498 1.1 dante }
499 1.1 dante
500 1.22 thorpej int
501 1.43 dsl adv_detach(ASC_SOFTC *sc, int flags)
502 1.22 thorpej {
503 1.22 thorpej int rv = 0;
504 1.22 thorpej
505 1.22 thorpej if (sc->sc_child != NULL)
506 1.22 thorpej rv = config_detach(sc->sc_child, flags);
507 1.22 thorpej
508 1.22 thorpej adv_free_control_data(sc);
509 1.22 thorpej
510 1.22 thorpej return (rv);
511 1.22 thorpej }
512 1.1 dante
513 1.1 dante static void
514 1.43 dsl advminphys(struct buf *bp)
515 1.1 dante {
516 1.1 dante
517 1.1 dante if (bp->b_bcount > ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE))
518 1.1 dante bp->b_bcount = ((ASC_MAX_SG_LIST - 1) * PAGE_SIZE);
519 1.1 dante minphys(bp);
520 1.1 dante }
521 1.1 dante
522 1.1 dante
523 1.1 dante /*
524 1.1 dante * start a scsi operation given the command and the data address. Also needs
525 1.1 dante * the unit, target and lu.
526 1.1 dante */
527 1.1 dante
528 1.24 bouyer static void
529 1.47 msaitoh adv_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
530 1.47 msaitoh void *arg)
531 1.24 bouyer {
532 1.24 bouyer struct scsipi_xfer *xs;
533 1.24 bouyer struct scsipi_periph *periph;
534 1.46 chs ASC_SOFTC *sc = device_private(chan->chan_adapter->adapt_dev);
535 1.24 bouyer bus_dma_tag_t dmat = sc->sc_dmat;
536 1.24 bouyer ADV_CCB *ccb;
537 1.24 bouyer int s, flags, error, nsegs;
538 1.36 perry
539 1.24 bouyer switch (req) {
540 1.24 bouyer case ADAPTER_REQ_RUN_XFER:
541 1.24 bouyer xs = arg;
542 1.24 bouyer periph = xs->xs_periph;
543 1.24 bouyer flags = xs->xs_control;
544 1.36 perry
545 1.24 bouyer /*
546 1.24 bouyer * Get a CCB to use.
547 1.24 bouyer */
548 1.24 bouyer ccb = adv_get_ccb(sc);
549 1.24 bouyer #ifdef DIAGNOSTIC
550 1.24 bouyer /*
551 1.24 bouyer * This should never happen as we track the resources
552 1.24 bouyer * in the mid-layer.
553 1.24 bouyer */
554 1.24 bouyer if (ccb == NULL) {
555 1.24 bouyer scsipi_printaddr(periph);
556 1.24 bouyer printf("unable to allocate ccb\n");
557 1.24 bouyer panic("adv_scsipi_request");
558 1.24 bouyer }
559 1.24 bouyer #endif
560 1.36 perry
561 1.24 bouyer ccb->xs = xs;
562 1.24 bouyer ccb->timeout = xs->timeout;
563 1.36 perry
564 1.24 bouyer /*
565 1.24 bouyer * Build up the request
566 1.24 bouyer */
567 1.24 bouyer memset(&ccb->scsiq, 0, sizeof(ASC_SCSI_Q));
568 1.36 perry
569 1.24 bouyer ccb->scsiq.q2.ccb_ptr =
570 1.24 bouyer sc->sc_dmamap_control->dm_segs[0].ds_addr +
571 1.24 bouyer ADV_CCB_OFF(ccb);
572 1.36 perry
573 1.24 bouyer ccb->scsiq.cdbptr = &xs->cmd->opcode;
574 1.24 bouyer ccb->scsiq.q2.cdb_len = xs->cmdlen;
575 1.24 bouyer ccb->scsiq.q1.target_id =
576 1.24 bouyer ASC_TID_TO_TARGET_ID(periph->periph_target);
577 1.24 bouyer ccb->scsiq.q1.target_lun = periph->periph_lun;
578 1.24 bouyer ccb->scsiq.q2.target_ix =
579 1.24 bouyer ASC_TIDLUN_TO_IX(periph->periph_target,
580 1.24 bouyer periph->periph_lun);
581 1.24 bouyer ccb->scsiq.q1.sense_addr =
582 1.24 bouyer sc->sc_dmamap_control->dm_segs[0].ds_addr +
583 1.24 bouyer ADV_CCB_OFF(ccb) + offsetof(struct adv_ccb, scsi_sense);
584 1.35 thorpej ccb->scsiq.q1.sense_len = sizeof(struct scsi_sense_data);
585 1.36 perry
586 1.24 bouyer /*
587 1.24 bouyer * If there are any outstanding requests for the current
588 1.24 bouyer * target, then every 255th request send an ORDERED request.
589 1.24 bouyer * This heuristic tries to retain the benefit of request
590 1.24 bouyer * sorting while preventing request starvation. 255 is the
591 1.24 bouyer * max number of tags or pending commands a device may have
592 1.24 bouyer * outstanding.
593 1.24 bouyer */
594 1.24 bouyer sc->reqcnt[periph->periph_target]++;
595 1.24 bouyer if (((sc->reqcnt[periph->periph_target] > 0) &&
596 1.24 bouyer (sc->reqcnt[periph->periph_target] % 255) == 0) ||
597 1.24 bouyer xs->bp == NULL || (xs->bp->b_flags & B_ASYNC) == 0) {
598 1.24 bouyer ccb->scsiq.q2.tag_code = M2_QTAG_MSG_ORDERED;
599 1.24 bouyer } else {
600 1.24 bouyer ccb->scsiq.q2.tag_code = M2_QTAG_MSG_SIMPLE;
601 1.24 bouyer }
602 1.36 perry
603 1.24 bouyer if (xs->datalen) {
604 1.24 bouyer /*
605 1.24 bouyer * Map the DMA transfer.
606 1.24 bouyer */
607 1.1 dante #ifdef TFS
608 1.24 bouyer if (flags & SCSI_DATA_UIO) {
609 1.24 bouyer error = bus_dmamap_load_uio(dmat,
610 1.24 bouyer ccb->dmamap_xfer, (struct uio *) xs->data,
611 1.24 bouyer ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
612 1.28 thorpej BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
613 1.28 thorpej ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
614 1.28 thorpej BUS_DMA_WRITE));
615 1.24 bouyer } else
616 1.24 bouyer #endif /* TFS */
617 1.24 bouyer {
618 1.24 bouyer error = bus_dmamap_load(dmat, ccb->dmamap_xfer,
619 1.24 bouyer xs->data, xs->datalen, NULL,
620 1.24 bouyer ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
621 1.28 thorpej BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
622 1.28 thorpej ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
623 1.28 thorpej BUS_DMA_WRITE));
624 1.24 bouyer }
625 1.36 perry
626 1.24 bouyer switch (error) {
627 1.24 bouyer case 0:
628 1.24 bouyer break;
629 1.24 bouyer
630 1.36 perry
631 1.24 bouyer case ENOMEM:
632 1.24 bouyer case EAGAIN:
633 1.24 bouyer xs->error = XS_RESOURCE_SHORTAGE;
634 1.24 bouyer goto out_bad;
635 1.36 perry
636 1.24 bouyer default:
637 1.24 bouyer xs->error = XS_DRIVER_STUFFUP;
638 1.24 bouyer if (error == EFBIG) {
639 1.47 msaitoh aprint_error_dev(sc->sc_dev,
640 1.47 msaitoh "adv_scsi_cmd, more than %d"
641 1.33 wiz " DMA segments\n",
642 1.24 bouyer ASC_MAX_SG_LIST);
643 1.24 bouyer } else {
644 1.47 msaitoh aprint_error_dev(sc->sc_dev,
645 1.47 msaitoh "adv_scsi_cmd, error %d"
646 1.47 msaitoh " loading DMA map\n", error);
647 1.24 bouyer }
648 1.24 bouyer
649 1.24 bouyer out_bad:
650 1.24 bouyer adv_free_ccb(sc, ccb);
651 1.24 bouyer scsipi_done(xs);
652 1.24 bouyer return;
653 1.24 bouyer }
654 1.24 bouyer bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
655 1.24 bouyer ccb->dmamap_xfer->dm_mapsize,
656 1.24 bouyer (flags & XS_CTL_DATA_IN) ?
657 1.24 bouyer BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
658 1.36 perry
659 1.24 bouyer memset(&ccb->sghead, 0, sizeof(ASC_SG_HEAD));
660 1.36 perry
661 1.24 bouyer for (nsegs = 0;
662 1.24 bouyer nsegs < ccb->dmamap_xfer->dm_nsegs; nsegs++) {
663 1.24 bouyer ccb->sghead.sg_list[nsegs].addr =
664 1.24 bouyer ccb->dmamap_xfer->dm_segs[nsegs].ds_addr;
665 1.24 bouyer ccb->sghead.sg_list[nsegs].bytes =
666 1.24 bouyer ccb->dmamap_xfer->dm_segs[nsegs].ds_len;
667 1.24 bouyer }
668 1.36 perry
669 1.24 bouyer ccb->sghead.entry_cnt = ccb->scsiq.q1.sg_queue_cnt =
670 1.24 bouyer ccb->dmamap_xfer->dm_nsegs;
671 1.36 perry
672 1.24 bouyer ccb->scsiq.q1.cntl |= ASC_QC_SG_HEAD;
673 1.24 bouyer ccb->scsiq.sg_head = &ccb->sghead;
674 1.24 bouyer ccb->scsiq.q1.data_addr = 0;
675 1.24 bouyer ccb->scsiq.q1.data_cnt = 0;
676 1.24 bouyer } else {
677 1.24 bouyer /*
678 1.24 bouyer * No data xfer, use non S/G values.
679 1.24 bouyer */
680 1.24 bouyer ccb->scsiq.q1.data_addr = 0;
681 1.24 bouyer ccb->scsiq.q1.data_cnt = 0;
682 1.24 bouyer }
683 1.36 perry
684 1.6 dante #ifdef ASC_DEBUG
685 1.38 christos printf("id = %d, lun = %d, cmd = %d, ccb = 0x%lX\n",
686 1.24 bouyer periph->periph_target,
687 1.24 bouyer periph->periph_lun, xs->cmd->opcode,
688 1.24 bouyer (unsigned long)ccb);
689 1.6 dante #endif
690 1.24 bouyer s = splbio();
691 1.24 bouyer adv_queue_ccb(sc, ccb);
692 1.24 bouyer splx(s);
693 1.36 perry
694 1.24 bouyer if ((flags & XS_CTL_POLL) == 0)
695 1.24 bouyer return;
696 1.36 perry
697 1.24 bouyer /* Not allowed to use interrupts, poll for completion. */
698 1.24 bouyer if (adv_poll(sc, xs, ccb->timeout)) {
699 1.24 bouyer adv_timeout(ccb);
700 1.24 bouyer if (adv_poll(sc, xs, ccb->timeout))
701 1.24 bouyer adv_timeout(ccb);
702 1.24 bouyer }
703 1.24 bouyer return;
704 1.36 perry
705 1.24 bouyer case ADAPTER_REQ_GROW_RESOURCES:
706 1.24 bouyer /* XXX Not supported. */
707 1.24 bouyer return;
708 1.36 perry
709 1.24 bouyer case ADAPTER_REQ_SET_XFER_MODE:
710 1.24 bouyer {
711 1.24 bouyer /*
712 1.24 bouyer * We can't really set the mode, but we know how to
713 1.24 bouyer * query what the firmware negotiated.
714 1.24 bouyer */
715 1.24 bouyer struct scsipi_xfer_mode *xm = arg;
716 1.24 bouyer u_int8_t sdtr_data;
717 1.24 bouyer ASC_SCSI_BIT_ID_TYPE tid_bit;
718 1.36 perry
719 1.24 bouyer tid_bit = ASC_TIX_TO_TARGET_ID(xm->xm_target);
720 1.36 perry
721 1.24 bouyer xm->xm_mode = 0;
722 1.24 bouyer xm->xm_period = 0;
723 1.24 bouyer xm->xm_offset = 0;
724 1.36 perry
725 1.24 bouyer if (sc->init_sdtr & tid_bit) {
726 1.24 bouyer xm->xm_mode |= PERIPH_CAP_SYNC;
727 1.24 bouyer sdtr_data = sc->sdtr_data[xm->xm_target];
728 1.24 bouyer xm->xm_period =
729 1.24 bouyer sc->sdtr_period_tbl[(sdtr_data >> 4) &
730 1.24 bouyer (sc->max_sdtr_index - 1)];
731 1.24 bouyer xm->xm_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
732 1.24 bouyer }
733 1.36 perry
734 1.24 bouyer if (sc->use_tagged_qng & tid_bit)
735 1.24 bouyer xm->xm_mode |= PERIPH_CAP_TQING;
736 1.36 perry
737 1.24 bouyer scsipi_async_event(chan, ASYNC_EVENT_XFER_MODE, xm);
738 1.24 bouyer return;
739 1.24 bouyer }
740 1.24 bouyer }
741 1.1 dante }
742 1.1 dante
743 1.1 dante int
744 1.43 dsl adv_intr(void *arg)
745 1.1 dante {
746 1.1 dante ASC_SOFTC *sc = arg;
747 1.1 dante
748 1.6 dante #ifdef ASC_DEBUG
749 1.6 dante int int_pend = FALSE;
750 1.6 dante
751 1.47 msaitoh if (ASC_IS_INT_PENDING(sc->sc_iot, sc->sc_ioh)) {
752 1.6 dante int_pend = TRUE;
753 1.6 dante printf("ISR - ");
754 1.6 dante }
755 1.6 dante #endif
756 1.4 dante AscISR(sc);
757 1.6 dante #ifdef ASC_DEBUG
758 1.6 dante if(int_pend)
759 1.6 dante printf("\n");
760 1.6 dante #endif
761 1.1 dante
762 1.1 dante return (1);
763 1.1 dante }
764 1.1 dante
765 1.1 dante
766 1.1 dante /*
767 1.1 dante * Poll a particular unit, looking for a particular xs
768 1.1 dante */
769 1.1 dante static int
770 1.43 dsl adv_poll(ASC_SOFTC *sc, struct scsipi_xfer *xs, int count)
771 1.1 dante {
772 1.1 dante
773 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
774 1.1 dante while (count) {
775 1.1 dante adv_intr(sc);
776 1.14 thorpej if (xs->xs_status & XS_STS_DONE)
777 1.1 dante return (0);
778 1.1 dante delay(1000); /* only happens in boot so ok */
779 1.1 dante count--;
780 1.1 dante }
781 1.1 dante return (1);
782 1.1 dante }
783 1.1 dante
784 1.1 dante
785 1.1 dante static void
786 1.43 dsl adv_timeout(void *arg)
787 1.1 dante {
788 1.1 dante ADV_CCB *ccb = arg;
789 1.1 dante struct scsipi_xfer *xs = ccb->xs;
790 1.24 bouyer struct scsipi_periph *periph = xs->xs_periph;
791 1.24 bouyer ASC_SOFTC *sc =
792 1.46 chs device_private(periph->periph_channel->chan_adapter->adapt_dev);
793 1.1 dante int s;
794 1.1 dante
795 1.24 bouyer scsipi_printaddr(periph);
796 1.1 dante printf("timed out");
797 1.1 dante
798 1.1 dante s = splbio();
799 1.1 dante
800 1.1 dante /*
801 1.24 bouyer * If it has been through before, then a previous abort has failed,
802 1.24 bouyer * don't try abort again, reset the bus instead.
803 1.24 bouyer */
804 1.1 dante if (ccb->flags & CCB_ABORT) {
805 1.1 dante /* abort timed out */
806 1.1 dante printf(" AGAIN. Resetting Bus\n");
807 1.1 dante /* Lets try resetting the bus! */
808 1.1 dante if (AscResetBus(sc) == ASC_ERROR) {
809 1.1 dante ccb->timeout = sc->scsi_reset_wait;
810 1.1 dante adv_queue_ccb(sc, ccb);
811 1.1 dante }
812 1.1 dante } else {
813 1.1 dante /* abort the operation that has timed out */
814 1.1 dante printf("\n");
815 1.10 dante AscAbortCCB(sc, ccb);
816 1.1 dante ccb->xs->error = XS_TIMEOUT;
817 1.1 dante ccb->timeout = ADV_ABORT_TIMEOUT;
818 1.1 dante ccb->flags |= CCB_ABORT;
819 1.1 dante adv_queue_ccb(sc, ccb);
820 1.1 dante }
821 1.1 dante
822 1.1 dante splx(s);
823 1.1 dante }
824 1.1 dante
825 1.1 dante
826 1.1 dante static void
827 1.43 dsl adv_watchdog(void *arg)
828 1.1 dante {
829 1.1 dante ADV_CCB *ccb = arg;
830 1.1 dante struct scsipi_xfer *xs = ccb->xs;
831 1.24 bouyer struct scsipi_periph *periph = xs->xs_periph;
832 1.24 bouyer ASC_SOFTC *sc =
833 1.46 chs device_private(periph->periph_channel->chan_adapter->adapt_dev);
834 1.1 dante int s;
835 1.1 dante
836 1.1 dante s = splbio();
837 1.1 dante
838 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
839 1.1 dante adv_start_ccbs(sc);
840 1.1 dante
841 1.1 dante splx(s);
842 1.1 dante }
843 1.1 dante
844 1.1 dante
845 1.1 dante /******************************************************************************/
846 1.10 dante /* NARROW boards Interrupt callbacks */
847 1.1 dante /******************************************************************************/
848 1.1 dante
849 1.1 dante
850 1.1 dante /*
851 1.1 dante * adv_narrow_isr_callback() - Second Level Interrupt Handler called by AscISR()
852 1.1 dante *
853 1.1 dante * Interrupt callback function for the Narrow SCSI Asc Library.
854 1.1 dante */
855 1.1 dante static void
856 1.43 dsl adv_narrow_isr_callback(ASC_SOFTC *sc, ASC_QDONE_INFO *qdonep)
857 1.1 dante {
858 1.1 dante bus_dma_tag_t dmat = sc->sc_dmat;
859 1.10 dante ADV_CCB *ccb;
860 1.10 dante struct scsipi_xfer *xs;
861 1.35 thorpej struct scsi_sense_data *s1, *s2;
862 1.1 dante
863 1.10 dante
864 1.10 dante ccb = adv_ccb_phys_kv(sc, qdonep->d2.ccb_ptr);
865 1.10 dante xs = ccb->xs;
866 1.1 dante
867 1.6 dante #ifdef ASC_DEBUG
868 1.6 dante printf(" - ccb=0x%lx, id=%d, lun=%d, cmd=%d, ",
869 1.6 dante (unsigned long)ccb,
870 1.24 bouyer xs->xs_periph->periph_target,
871 1.24 bouyer xs->xs_periph->periph_lun, xs->cmd->opcode);
872 1.6 dante #endif
873 1.16 thorpej callout_stop(&ccb->xs->xs_callout);
874 1.1 dante
875 1.1 dante /*
876 1.24 bouyer * If we were a data transfer, unload the map that described
877 1.24 bouyer * the data buffer.
878 1.24 bouyer */
879 1.1 dante if (xs->datalen) {
880 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
881 1.1 dante ccb->dmamap_xfer->dm_mapsize,
882 1.14 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
883 1.14 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
884 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
885 1.1 dante }
886 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
887 1.46 chs aprint_error_dev(sc->sc_dev, "exiting ccb not allocated!\n");
888 1.1 dante Debugger();
889 1.1 dante return;
890 1.1 dante }
891 1.1 dante /*
892 1.24 bouyer * 'qdonep' contains the command's ending status.
893 1.24 bouyer */
894 1.6 dante #ifdef ASC_DEBUG
895 1.6 dante printf("d_s=%d, h_s=%d", qdonep->d3.done_stat, qdonep->d3.host_stat);
896 1.6 dante #endif
897 1.1 dante switch (qdonep->d3.done_stat) {
898 1.1 dante case ASC_QD_NO_ERROR:
899 1.1 dante switch (qdonep->d3.host_stat) {
900 1.1 dante case ASC_QHSTA_NO_ERROR:
901 1.1 dante xs->error = XS_NOERROR;
902 1.48 rin /*
903 1.48 rin * XXX
904 1.48 rin * According to the original Linux driver, xs->resid
905 1.48 rin * should be qdonep->remain_bytes. However, its value
906 1.48 rin * is bogus, which seems like a H/W bug. The best thing
907 1.48 rin * we can do would be to ignore it, assuming that all
908 1.48 rin * data has been successfully transferred...
909 1.48 rin */
910 1.1 dante xs->resid = 0;
911 1.1 dante break;
912 1.1 dante
913 1.1 dante default:
914 1.1 dante /* QHSTA error occurred */
915 1.1 dante xs->error = XS_DRIVER_STUFFUP;
916 1.1 dante break;
917 1.1 dante }
918 1.1 dante
919 1.1 dante /*
920 1.24 bouyer * If an INQUIRY command completed successfully, then call
921 1.24 bouyer * the AscInquiryHandling() function to patch bugged boards.
922 1.24 bouyer */
923 1.1 dante if ((xs->cmd->opcode == SCSICMD_Inquiry) &&
924 1.24 bouyer (xs->xs_periph->periph_lun == 0) &&
925 1.1 dante (xs->datalen - qdonep->remain_bytes) >= 8) {
926 1.1 dante AscInquiryHandling(sc,
927 1.24 bouyer xs->xs_periph->periph_target & 0x7,
928 1.1 dante (ASC_SCSI_INQUIRY *) xs->data);
929 1.1 dante }
930 1.1 dante break;
931 1.1 dante
932 1.1 dante case ASC_QD_WITH_ERROR:
933 1.1 dante switch (qdonep->d3.host_stat) {
934 1.1 dante case ASC_QHSTA_NO_ERROR:
935 1.1 dante if (qdonep->d3.scsi_stat == SS_CHK_CONDITION) {
936 1.1 dante s1 = &ccb->scsi_sense;
937 1.1 dante s2 = &xs->sense.scsi_sense;
938 1.1 dante *s2 = *s1;
939 1.1 dante xs->error = XS_SENSE;
940 1.4 dante } else {
941 1.1 dante xs->error = XS_DRIVER_STUFFUP;
942 1.4 dante }
943 1.25 briggs break;
944 1.25 briggs
945 1.25 briggs case ASC_QHSTA_M_SEL_TIMEOUT:
946 1.26 briggs xs->error = XS_SELTIMEOUT;
947 1.1 dante break;
948 1.1 dante
949 1.1 dante default:
950 1.1 dante /* QHSTA error occurred */
951 1.1 dante xs->error = XS_DRIVER_STUFFUP;
952 1.1 dante break;
953 1.1 dante }
954 1.1 dante break;
955 1.1 dante
956 1.1 dante case ASC_QD_ABORTED_BY_HOST:
957 1.1 dante default:
958 1.1 dante xs->error = XS_DRIVER_STUFFUP;
959 1.1 dante break;
960 1.1 dante }
961 1.1 dante
962 1.1 dante adv_free_ccb(sc, ccb);
963 1.1 dante scsipi_done(xs);
964 1.1 dante }
965