advlib.c revision 1.28 1 1.28 uwe /* $NetBSD: advlib.c,v 1.28 2019/10/06 00:48:19 uwe Exp $ */
2 1.3 dante
3 1.1 dante /*
4 1.1 dante * Low level routines for the Advanced Systems Inc. SCSI controllers chips
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.4 dante * This product includes software developed by the NetBSD
22 1.4 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante /*
40 1.1 dante * Ported from:
41 1.1 dante */
42 1.1 dante /*
43 1.1 dante * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
44 1.1 dante *
45 1.1 dante * Copyright (c) 1995-1998 Advanced System Products, Inc.
46 1.1 dante * All Rights Reserved.
47 1.1 dante *
48 1.1 dante * Redistribution and use in source and binary forms, with or without
49 1.1 dante * modification, are permitted provided that redistributions of source
50 1.1 dante * code retain the above copyright notice and this comment without
51 1.1 dante * modification.
52 1.1 dante *
53 1.1 dante */
54 1.17 lukem
55 1.17 lukem #include <sys/cdefs.h>
56 1.28 uwe __KERNEL_RCSID(0, "$NetBSD: advlib.c,v 1.28 2019/10/06 00:48:19 uwe Exp $");
57 1.1 dante
58 1.1 dante #include <sys/param.h>
59 1.1 dante #include <sys/systm.h>
60 1.1 dante #include <sys/malloc.h>
61 1.1 dante #include <sys/kernel.h>
62 1.1 dante #include <sys/queue.h>
63 1.1 dante #include <sys/device.h>
64 1.1 dante
65 1.26 ad #include <sys/bus.h>
66 1.26 ad #include <sys/intr.h>
67 1.1 dante
68 1.1 dante #include <dev/scsipi/scsi_all.h>
69 1.1 dante #include <dev/scsipi/scsipi_all.h>
70 1.1 dante #include <dev/scsipi/scsiconf.h>
71 1.1 dante
72 1.8 dante #include <dev/ic/advlib.h>
73 1.1 dante #include <dev/ic/adv.h>
74 1.1 dante #include <dev/ic/advmcode.h>
75 1.1 dante
76 1.1 dante
77 1.7 dante /* #define ASC_DEBUG */
78 1.7 dante
79 1.1 dante /******************************************************************************/
80 1.1 dante /* Static functions */
81 1.1 dante /******************************************************************************/
82 1.1 dante
83 1.19 wiz /* Initialization routines */
84 1.15 lukem static u_int32_t AscLoadMicroCode(bus_space_tag_t, bus_space_handle_t,
85 1.21 christos u_int16_t, const u_int16_t *, u_int16_t);
86 1.15 lukem static void AscInitLram(ASC_SOFTC *);
87 1.15 lukem static void AscInitQLinkVar(ASC_SOFTC *);
88 1.15 lukem static int AscResetChipAndScsiBus(bus_space_tag_t, bus_space_handle_t);
89 1.15 lukem static u_int16_t AscGetChipBusType(bus_space_tag_t, bus_space_handle_t);
90 1.15 lukem #if 0
91 1.15 lukem static u_int16_t AscGetEisaChipCfg(bus_space_tag_t, bus_space_handle_t);
92 1.15 lukem #endif
93 1.15 lukem
94 1.1 dante /* Chip register routines */
95 1.15 lukem static void AscSetBank(bus_space_tag_t, bus_space_handle_t, u_int8_t);
96 1.1 dante
97 1.1 dante /* RISC Chip routines */
98 1.15 lukem static int AscStartChip(bus_space_tag_t, bus_space_handle_t);
99 1.15 lukem static int AscStopChip(bus_space_tag_t, bus_space_handle_t);
100 1.15 lukem static u_int8_t AscSetChipScsiID(bus_space_tag_t, bus_space_handle_t, u_int8_t);
101 1.15 lukem static u_int8_t AscGetChipScsiCtrl(bus_space_tag_t, bus_space_handle_t);
102 1.15 lukem static int AscSetRunChipSynRegAtID(bus_space_tag_t, bus_space_handle_t,
103 1.15 lukem u_int8_t, u_int8_t);
104 1.15 lukem static int AscSetChipSynRegAtID(bus_space_tag_t, bus_space_handle_t,
105 1.15 lukem u_int8_t, u_int8_t);
106 1.15 lukem static int AscHostReqRiscHalt(bus_space_tag_t, bus_space_handle_t);
107 1.15 lukem static int AscIsChipHalted(bus_space_tag_t, bus_space_handle_t);
108 1.15 lukem static void AscSetChipIH(bus_space_tag_t, bus_space_handle_t, u_int16_t);
109 1.1 dante
110 1.1 dante /* Lram routines */
111 1.15 lukem static u_int8_t AscReadLramByte(bus_space_tag_t, bus_space_handle_t, u_int16_t);
112 1.15 lukem static void AscWriteLramByte(bus_space_tag_t, bus_space_handle_t,
113 1.15 lukem u_int16_t, u_int8_t);
114 1.15 lukem static u_int16_t AscReadLramWord(bus_space_tag_t, bus_space_handle_t,
115 1.15 lukem u_int16_t);
116 1.15 lukem static void AscWriteLramWord(bus_space_tag_t, bus_space_handle_t,
117 1.15 lukem u_int16_t, u_int16_t);
118 1.15 lukem static u_int32_t AscReadLramDWord(bus_space_tag_t, bus_space_handle_t,
119 1.15 lukem u_int16_t);
120 1.15 lukem static void AscWriteLramDWord(bus_space_tag_t, bus_space_handle_t,
121 1.15 lukem u_int16_t, u_int32_t);
122 1.15 lukem static void AscMemWordSetLram(bus_space_tag_t, bus_space_handle_t,
123 1.15 lukem u_int16_t, u_int16_t, int);
124 1.15 lukem static void AscMemWordCopyToLram(bus_space_tag_t, bus_space_handle_t,
125 1.21 christos u_int16_t, const u_int16_t *, int);
126 1.15 lukem static void AscMemWordCopyFromLram(bus_space_tag_t, bus_space_handle_t,
127 1.15 lukem u_int16_t, u_int16_t *, int);
128 1.15 lukem static void AscMemDWordCopyToLram(bus_space_tag_t, bus_space_handle_t,
129 1.15 lukem u_int16_t, u_int32_t *, int);
130 1.15 lukem static u_int32_t AscMemSumLramWord(bus_space_tag_t, bus_space_handle_t,
131 1.15 lukem u_int16_t, int);
132 1.15 lukem static int AscTestExternalLram(bus_space_tag_t, bus_space_handle_t);
133 1.1 dante
134 1.1 dante /* MicroCode routines */
135 1.15 lukem static u_int16_t AscInitMicroCodeVar(ASC_SOFTC *);
136 1.1 dante
137 1.1 dante /* EEProm routines */
138 1.15 lukem static int AscWriteEEPCmdReg(bus_space_tag_t, bus_space_handle_t, u_int8_t);
139 1.15 lukem static int AscWriteEEPDataReg(bus_space_tag_t, bus_space_handle_t, u_int16_t);
140 1.15 lukem static void AscWaitEEPRead(void);
141 1.15 lukem static void AscWaitEEPWrite(void);
142 1.15 lukem static u_int16_t AscReadEEPWord(bus_space_tag_t, bus_space_handle_t, u_int8_t);
143 1.15 lukem static u_int16_t AscWriteEEPWord(bus_space_tag_t, bus_space_handle_t,
144 1.15 lukem u_int8_t, u_int16_t);
145 1.15 lukem static u_int16_t AscGetEEPConfig(bus_space_tag_t, bus_space_handle_t,
146 1.15 lukem ASCEEP_CONFIG *, u_int16_t);
147 1.15 lukem static int AscSetEEPConfig(bus_space_tag_t, bus_space_handle_t,
148 1.15 lukem ASCEEP_CONFIG *, u_int16_t);
149 1.15 lukem static int AscSetEEPConfigOnce(bus_space_tag_t, bus_space_handle_t,
150 1.15 lukem ASCEEP_CONFIG *, u_int16_t);
151 1.7 dante #ifdef ASC_DEBUG
152 1.15 lukem static void AscPrintEEPConfig(ASCEEP_CONFIG *, u_int16_t);
153 1.7 dante #endif
154 1.1 dante
155 1.1 dante /* Interrupt routines */
156 1.15 lukem static void AscIsrChipHalted(ASC_SOFTC *);
157 1.15 lukem static int AscIsrQDone(ASC_SOFTC *);
158 1.15 lukem static int AscWaitTixISRDone(ASC_SOFTC *, u_int8_t);
159 1.15 lukem static int AscWaitISRDone(ASC_SOFTC *);
160 1.15 lukem static u_int8_t _AscCopyLramScsiDoneQ(bus_space_tag_t, bus_space_handle_t,
161 1.15 lukem u_int16_t, ASC_QDONE_INFO *, u_int32_t);
162 1.15 lukem static void AscGetQDoneInfo(bus_space_tag_t, bus_space_handle_t, u_int16_t,
163 1.15 lukem ASC_QDONE_INFO *);
164 1.15 lukem static void AscToggleIRQAct(bus_space_tag_t, bus_space_handle_t);
165 1.15 lukem static void AscDisableInterrupt(bus_space_tag_t, bus_space_handle_t);
166 1.15 lukem static void AscEnableInterrupt(bus_space_tag_t, bus_space_handle_t);
167 1.15 lukem static u_int8_t AscSetChipIRQ(bus_space_tag_t, bus_space_handle_t,
168 1.15 lukem u_int8_t, u_int16_t);
169 1.15 lukem static void AscAckInterrupt(bus_space_tag_t, bus_space_handle_t);
170 1.15 lukem static u_int32_t AscGetMaxDmaCount(u_int16_t);
171 1.15 lukem static u_int16_t AscSetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t,
172 1.15 lukem u_int16_t);
173 1.15 lukem static u_int8_t AscGetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t);
174 1.15 lukem static u_int8_t AscSetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t,
175 1.15 lukem u_int8_t);
176 1.20 perry
177 1.1 dante /* Messages routines */
178 1.15 lukem static void AscHandleExtMsgIn(ASC_SOFTC *, u_int16_t, u_int8_t,
179 1.15 lukem ASC_SCSI_BIT_ID_TYPE, int, u_int8_t);
180 1.15 lukem static u_int8_t AscMsgOutSDTR(ASC_SOFTC *, u_int8_t, u_int8_t);
181 1.20 perry
182 1.1 dante /* SDTR routines */
183 1.15 lukem static void AscSetChipSDTR(bus_space_tag_t, bus_space_handle_t,
184 1.15 lukem u_int8_t, u_int8_t);
185 1.15 lukem static u_int8_t AscCalSDTRData(ASC_SOFTC *, u_int8_t, u_int8_t);
186 1.15 lukem static u_int8_t AscGetSynPeriodIndex(ASC_SOFTC *, u_int8_t);
187 1.20 perry
188 1.1 dante /* Queue routines */
189 1.15 lukem static int AscSendScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t);
190 1.15 lukem static int AscSgListToQueue(int);
191 1.15 lukem static u_int AscGetNumOfFreeQueue(ASC_SOFTC *, u_int8_t, u_int8_t);
192 1.15 lukem static int AscPutReadyQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t);
193 1.15 lukem static void AscPutSCSIQ(bus_space_tag_t, bus_space_handle_t,
194 1.15 lukem u_int16_t, ASC_SCSI_Q *);
195 1.15 lukem static int AscPutReadySgListQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t);
196 1.15 lukem static u_int8_t AscAllocFreeQueue(bus_space_tag_t, bus_space_handle_t,
197 1.15 lukem u_int8_t);
198 1.15 lukem static u_int8_t AscAllocMultipleFreeQueue(bus_space_tag_t, bus_space_handle_t,
199 1.15 lukem u_int8_t, u_int8_t);
200 1.15 lukem static int AscStopQueueExe(bus_space_tag_t, bus_space_handle_t);
201 1.15 lukem static void AscStartQueueExe(bus_space_tag_t, bus_space_handle_t);
202 1.15 lukem static void AscCleanUpBusyQueue(bus_space_tag_t, bus_space_handle_t);
203 1.15 lukem static int _AscWaitQDone(bus_space_tag_t, bus_space_handle_t,
204 1.15 lukem ASC_SCSI_Q *);
205 1.15 lukem static int AscCleanUpDiscQueue(bus_space_tag_t, bus_space_handle_t);
206 1.20 perry
207 1.1 dante /* Abort and Reset CCB routines */
208 1.15 lukem static int AscRiscHaltedAbortCCB(ASC_SOFTC *, ADV_CCB *);
209 1.15 lukem static int AscRiscHaltedAbortTIX(ASC_SOFTC *, u_int8_t);
210 1.20 perry
211 1.1 dante /* Error Handling routines */
212 1.15 lukem static int AscSetLibErrorCode(ASC_SOFTC *, u_int16_t);
213 1.20 perry
214 1.1 dante /* Handle bugged borads routines */
215 1.15 lukem static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
216 1.15 lukem static void AscAsyncFix(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *);
217 1.20 perry
218 1.1 dante /* Miscellaneous routines */
219 1.21 christos static int AscCompareString(const u_char *, const u_char *, int);
220 1.20 perry
221 1.1 dante /* Device oriented routines */
222 1.15 lukem static int DvcEnterCritical(void);
223 1.15 lukem static void DvcLeaveCritical(int);
224 1.15 lukem static void DvcSleepMilliSecond(u_int32_t);
225 1.15 lukem #if 0
226 1.15 lukem static void DvcDelayMicroSecond(u_int32_t);
227 1.15 lukem #endif
228 1.15 lukem static void DvcDelayNanoSecond(u_int32_t);
229 1.1 dante
230 1.1 dante
231 1.1 dante /******************************************************************************/
232 1.19 wiz /* Initialization routines */
233 1.1 dante /******************************************************************************/
234 1.1 dante
235 1.1 dante /*
236 1.1 dante * This function perform the following steps:
237 1.1 dante * - initialize ASC_SOFTC structure with defaults values.
238 1.1 dante * - inquire board registers to know what kind of board it is.
239 1.1 dante * - keep track of bugged borads.
240 1.1 dante */
241 1.1 dante void
242 1.15 lukem AscInitASC_SOFTC(ASC_SOFTC *sc)
243 1.1 dante {
244 1.1 dante bus_space_tag_t iot = sc->sc_iot;
245 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
246 1.1 dante int i;
247 1.1 dante
248 1.1 dante
249 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
250 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
251 1.1 dante
252 1.1 dante sc->bug_fix_cntl = 0;
253 1.1 dante sc->pci_fix_asyn_xfer = 0;
254 1.1 dante sc->pci_fix_asyn_xfer_always = 0;
255 1.1 dante sc->sdtr_done = 0;
256 1.1 dante sc->cur_total_qng = 0;
257 1.1 dante sc->last_q_shortage = 0;
258 1.1 dante sc->use_tagged_qng = 0;
259 1.1 dante sc->unit_not_ready = 0;
260 1.1 dante sc->queue_full_or_busy = 0;
261 1.1 dante sc->host_init_sdtr_index = 0;
262 1.1 dante sc->can_tagged_qng = 0;
263 1.1 dante sc->cmd_qng_enabled = 0;
264 1.1 dante sc->dvc_cntl = ASC_DEF_DVC_CNTL;
265 1.1 dante sc->init_sdtr = 0;
266 1.1 dante sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
267 1.1 dante sc->scsi_reset_wait = 3;
268 1.1 dante sc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
269 1.1 dante sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type);
270 1.1 dante sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
271 1.1 dante sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
272 1.1 dante sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
273 1.1 dante sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
274 1.1 dante sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR;
275 1.1 dante if ((sc->bus_type & ASC_IS_PCI) &&
276 1.10 dante (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
277 1.1 dante sc->bus_type = ASC_IS_PCI_ULTRA;
278 1.1 dante sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
279 1.1 dante sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
280 1.1 dante sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
281 1.1 dante sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
282 1.1 dante sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
283 1.1 dante sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
284 1.1 dante sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
285 1.1 dante sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
286 1.1 dante sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
287 1.1 dante sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
288 1.1 dante sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
289 1.1 dante sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
290 1.1 dante sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
291 1.1 dante sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
292 1.1 dante sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
293 1.1 dante sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
294 1.1 dante sc->max_sdtr_index = 15;
295 1.10 dante if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
296 1.1 dante ASC_SET_EXTRA_CONTROL(iot, ioh,
297 1.1 dante (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
298 1.10 dante else if (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050)
299 1.1 dante ASC_SET_EXTRA_CONTROL(iot, ioh,
300 1.1 dante (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
301 1.1 dante } else {
302 1.1 dante sc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
303 1.1 dante sc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
304 1.1 dante sc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
305 1.1 dante sc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
306 1.1 dante sc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
307 1.1 dante sc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
308 1.1 dante sc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
309 1.1 dante sc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
310 1.1 dante sc->max_sdtr_index = 7;
311 1.1 dante }
312 1.1 dante
313 1.1 dante if (sc->bus_type == ASC_IS_PCI)
314 1.1 dante ASC_SET_EXTRA_CONTROL(iot, ioh,
315 1.1 dante (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
316 1.1 dante
317 1.1 dante sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
318 1.1 dante if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) {
319 1.1 dante ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT);
320 1.1 dante sc->bus_type = ASC_IS_ISAPNP;
321 1.1 dante }
322 1.1 dante if ((sc->bus_type & ASC_IS_ISA) != 0)
323 1.1 dante sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh);
324 1.1 dante
325 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++) {
326 1.1 dante sc->cur_dvc_qng[i] = 0;
327 1.1 dante sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
328 1.1 dante sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
329 1.1 dante }
330 1.1 dante }
331 1.1 dante
332 1.1 dante
333 1.1 dante /*
334 1.1 dante * This function initialize some ASC_SOFTC fields with values read from
335 1.1 dante * on-board EEProm.
336 1.1 dante */
337 1.9 dante int16_t
338 1.15 lukem AscInitFromEEP(ASC_SOFTC *sc)
339 1.1 dante {
340 1.1 dante bus_space_tag_t iot = sc->sc_iot;
341 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
342 1.1 dante ASCEEP_CONFIG eep_config_buf;
343 1.1 dante ASCEEP_CONFIG *eep_config;
344 1.1 dante u_int16_t chksum;
345 1.1 dante u_int16_t warn_code;
346 1.1 dante u_int16_t cfg_msw, cfg_lsw;
347 1.1 dante int i;
348 1.1 dante int write_eep = 0;
349 1.1 dante
350 1.1 dante
351 1.1 dante warn_code = 0;
352 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE);
353 1.1 dante AscStopQueueExe(iot, ioh);
354 1.9 dante
355 1.9 dante AscStopChip(iot, ioh);
356 1.9 dante AscResetChipAndScsiBus(iot, ioh);
357 1.9 dante DvcSleepMilliSecond(sc->scsi_reset_wait * 1000);
358 1.9 dante
359 1.1 dante if ((AscStopChip(iot, ioh) == FALSE) ||
360 1.1 dante (AscGetChipScsiCtrl(iot, ioh) != 0)) {
361 1.1 dante AscResetChipAndScsiBus(iot, ioh);
362 1.1 dante DvcSleepMilliSecond(sc->scsi_reset_wait * 1000);
363 1.1 dante }
364 1.1 dante if (AscIsChipHalted(iot, ioh) == FALSE)
365 1.1 dante return (-1);
366 1.1 dante
367 1.1 dante ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
368 1.1 dante if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR)
369 1.1 dante return (-2);
370 1.1 dante
371 1.7 dante eep_config = &eep_config_buf;
372 1.1 dante cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
373 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
374 1.1 dante if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
375 1.1 dante cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
376 1.1 dante warn_code |= ASC_WARN_CFG_MSW_RECOVER;
377 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
378 1.1 dante }
379 1.1 dante chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type);
380 1.7 dante #ifdef ASC_DEBUG
381 1.7 dante AscPrintEEPConfig(eep_config, chksum);
382 1.7 dante #endif
383 1.1 dante if (chksum == 0)
384 1.1 dante chksum = 0xAA55;
385 1.1 dante
386 1.1 dante if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) {
387 1.1 dante warn_code |= ASC_WARN_AUTO_CONFIG;
388 1.1 dante if (sc->chip_version == 3) {
389 1.1 dante if (eep_config->cfg_lsw != cfg_lsw) {
390 1.1 dante warn_code |= ASC_WARN_EEPROM_RECOVER;
391 1.1 dante eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
392 1.1 dante }
393 1.1 dante if (eep_config->cfg_msw != cfg_msw) {
394 1.1 dante warn_code |= ASC_WARN_EEPROM_RECOVER;
395 1.1 dante eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
396 1.1 dante }
397 1.1 dante }
398 1.1 dante }
399 1.1 dante eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
400 1.1 dante eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
401 1.1 dante
402 1.1 dante if (chksum != eep_config->chksum) {
403 1.10 dante if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3050) {
404 1.1 dante eep_config->init_sdtr = 0xFF;
405 1.1 dante eep_config->disc_enable = 0xFF;
406 1.1 dante eep_config->start_motor = 0xFF;
407 1.1 dante eep_config->use_cmd_qng = 0;
408 1.1 dante eep_config->max_total_qng = 0xF0;
409 1.1 dante eep_config->max_tag_qng = 0x20;
410 1.1 dante eep_config->cntl = 0xBFFF;
411 1.1 dante eep_config->chip_scsi_id = 7;
412 1.1 dante eep_config->no_scam = 0;
413 1.1 dante eep_config->adapter_info[0] = 0;
414 1.1 dante eep_config->adapter_info[1] = 0;
415 1.1 dante eep_config->adapter_info[2] = 0;
416 1.1 dante eep_config->adapter_info[3] = 0;
417 1.7 dante #if BYTE_ORDER == BIG_ENDIAN
418 1.7 dante eep_config->adapter_info[5] = 0;
419 1.7 dante /* Indicate EEPROM-less board. */
420 1.7 dante eep_config->adapter_info[4] = 0xBB;
421 1.7 dante #else
422 1.1 dante eep_config->adapter_info[4] = 0;
423 1.1 dante /* Indicate EEPROM-less board. */
424 1.1 dante eep_config->adapter_info[5] = 0xBB;
425 1.7 dante #endif
426 1.1 dante } else {
427 1.1 dante write_eep = 1;
428 1.1 dante warn_code |= ASC_WARN_EEPROM_CHKSUM;
429 1.1 dante }
430 1.1 dante }
431 1.1 dante sc->sdtr_enable = eep_config->init_sdtr;
432 1.1 dante sc->disc_enable = eep_config->disc_enable;
433 1.1 dante sc->cmd_qng_enabled = eep_config->use_cmd_qng;
434 1.1 dante sc->isa_dma_speed = eep_config->isa_dma_speed;
435 1.1 dante sc->start_motor = eep_config->start_motor;
436 1.1 dante sc->dvc_cntl = eep_config->cntl;
437 1.7 dante #if BYTE_ORDER == BIG_ENDIAN
438 1.7 dante sc->adapter_info[0] = eep_config->adapter_info[1];
439 1.7 dante sc->adapter_info[1] = eep_config->adapter_info[0];
440 1.7 dante sc->adapter_info[2] = eep_config->adapter_info[3];
441 1.7 dante sc->adapter_info[3] = eep_config->adapter_info[2];
442 1.7 dante sc->adapter_info[4] = eep_config->adapter_info[5];
443 1.7 dante sc->adapter_info[5] = eep_config->adapter_info[4];
444 1.7 dante #else
445 1.1 dante sc->adapter_info[0] = eep_config->adapter_info[0];
446 1.1 dante sc->adapter_info[1] = eep_config->adapter_info[1];
447 1.1 dante sc->adapter_info[2] = eep_config->adapter_info[2];
448 1.1 dante sc->adapter_info[3] = eep_config->adapter_info[3];
449 1.1 dante sc->adapter_info[4] = eep_config->adapter_info[4];
450 1.1 dante sc->adapter_info[5] = eep_config->adapter_info[5];
451 1.7 dante #endif
452 1.1 dante
453 1.1 dante if (!AscTestExternalLram(iot, ioh)) {
454 1.1 dante if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
455 1.1 dante eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
456 1.1 dante eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
457 1.1 dante } else {
458 1.1 dante eep_config->cfg_msw |= 0x0800;
459 1.1 dante cfg_msw |= 0x0800;
460 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
461 1.1 dante eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
462 1.1 dante eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
463 1.1 dante }
464 1.1 dante }
465 1.1 dante if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG)
466 1.1 dante eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
467 1.1 dante
468 1.1 dante if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG)
469 1.1 dante eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
470 1.1 dante
471 1.1 dante if (eep_config->max_tag_qng > eep_config->max_total_qng)
472 1.1 dante eep_config->max_tag_qng = eep_config->max_total_qng;
473 1.1 dante
474 1.1 dante if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC)
475 1.1 dante eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
476 1.1 dante
477 1.1 dante sc->max_total_qng = eep_config->max_total_qng;
478 1.1 dante if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
479 1.1 dante eep_config->use_cmd_qng) {
480 1.1 dante eep_config->disc_enable = eep_config->use_cmd_qng;
481 1.1 dante warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
482 1.1 dante }
483 1.1 dante if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA))
484 1.1 dante sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type);
485 1.1 dante
486 1.1 dante eep_config->chip_scsi_id &= ASC_MAX_TID;
487 1.1 dante sc->chip_scsi_id = eep_config->chip_scsi_id;
488 1.1 dante if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
489 1.1 dante !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
490 1.1 dante sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
491 1.1 dante }
492 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++) {
493 1.1 dante sc->max_tag_qng[i] = eep_config->max_tag_qng;
494 1.1 dante sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET |
495 1.1 dante (sc->host_init_sdtr_index << 4);
496 1.1 dante }
497 1.1 dante
498 1.1 dante eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
499 1.7 dante if (write_eep) {
500 1.1 dante AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type);
501 1.7 dante #ifdef ASC_DEBUG
502 1.7 dante AscPrintEEPConfig(eep_config, 0);
503 1.7 dante #endif
504 1.7 dante }
505 1.1 dante
506 1.1 dante return (warn_code);
507 1.1 dante }
508 1.1 dante
509 1.1 dante
510 1.1 dante u_int16_t
511 1.15 lukem AscInitFromASC_SOFTC(ASC_SOFTC *sc)
512 1.1 dante {
513 1.1 dante bus_space_tag_t iot = sc->sc_iot;
514 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
515 1.1 dante u_int16_t cfg_msw;
516 1.1 dante u_int16_t warn_code;
517 1.1 dante u_int16_t pci_device_id = sc->pci_device_id;
518 1.1 dante
519 1.1 dante
520 1.1 dante warn_code = 0;
521 1.1 dante cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
522 1.1 dante
523 1.1 dante if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
524 1.1 dante cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
525 1.1 dante warn_code |= ASC_WARN_CFG_MSW_RECOVER;
526 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
527 1.1 dante }
528 1.1 dante if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) {
529 1.1 dante sc->disc_enable = sc->cmd_qng_enabled;
530 1.1 dante warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
531 1.1 dante }
532 1.1 dante if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) {
533 1.1 dante warn_code |= ASC_WARN_AUTO_CONFIG;
534 1.1 dante }
535 1.1 dante if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
536 1.1 dante AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type);
537 1.1 dante }
538 1.1 dante if (sc->bus_type & ASC_IS_PCI) {
539 1.1 dante cfg_msw &= 0xFFC0;
540 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
541 1.1 dante
542 1.1 dante if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) {
543 1.1 dante if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) ||
544 1.1 dante (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) {
545 1.1 dante sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
546 1.1 dante sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
547 1.1 dante }
548 1.1 dante }
549 1.1 dante } else if (sc->bus_type == ASC_IS_ISAPNP) {
550 1.10 dante if (sc->chip_version == ASC_CHIP_VER_ASYN_BUG) {
551 1.1 dante sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
552 1.1 dante }
553 1.1 dante }
554 1.1 dante AscSetChipScsiID(iot, ioh, sc->chip_scsi_id);
555 1.1 dante
556 1.1 dante if (sc->bus_type & ASC_IS_ISA) {
557 1.1 dante AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel);
558 1.1 dante AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed);
559 1.1 dante }
560 1.1 dante return (warn_code);
561 1.1 dante }
562 1.1 dante
563 1.1 dante
564 1.1 dante /*
565 1.1 dante * - Initialize RISC chip
566 1.19 wiz * - Initialize Lram
567 1.1 dante * - Load uCode into Lram
568 1.1 dante * - Enable Interrupts
569 1.1 dante */
570 1.1 dante int
571 1.15 lukem AscInitDriver(ASC_SOFTC *sc)
572 1.1 dante {
573 1.1 dante bus_space_tag_t iot = sc->sc_iot;
574 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
575 1.1 dante u_int32_t chksum;
576 1.1 dante
577 1.1 dante
578 1.1 dante if (!AscFindSignature(iot, ioh))
579 1.1 dante return (1);
580 1.1 dante
581 1.1 dante AscDisableInterrupt(iot, ioh);
582 1.1 dante
583 1.1 dante AscInitLram(sc);
584 1.21 christos chksum = AscLoadMicroCode(iot, ioh, 0, (const u_int16_t *) asc_mcode,
585 1.1 dante asc_mcode_size);
586 1.1 dante if (chksum != asc_mcode_chksum)
587 1.1 dante return (2);
588 1.1 dante
589 1.1 dante if (AscInitMicroCodeVar(sc) == 0)
590 1.1 dante return (3);
591 1.1 dante
592 1.1 dante AscEnableInterrupt(iot, ioh);
593 1.1 dante
594 1.1 dante return (0);
595 1.1 dante }
596 1.1 dante
597 1.1 dante
598 1.1 dante int
599 1.15 lukem AscFindSignature(bus_space_tag_t iot, bus_space_handle_t ioh)
600 1.1 dante {
601 1.1 dante u_int16_t sig_word;
602 1.1 dante
603 1.1 dante if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) {
604 1.1 dante sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh);
605 1.1 dante if (sig_word == ASC_1000_ID0W ||
606 1.1 dante sig_word == ASC_1000_ID0W_FIX)
607 1.1 dante return (1);
608 1.1 dante }
609 1.1 dante return (0);
610 1.1 dante }
611 1.1 dante
612 1.1 dante
613 1.1 dante static void
614 1.15 lukem AscInitLram(ASC_SOFTC *sc)
615 1.1 dante {
616 1.1 dante bus_space_tag_t iot = sc->sc_iot;
617 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
618 1.1 dante u_int8_t i;
619 1.1 dante u_int16_t s_addr;
620 1.1 dante
621 1.1 dante
622 1.1 dante AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0,
623 1.1 dante (((sc->max_total_qng + 2 + 1) * 64) >> 1));
624 1.1 dante
625 1.1 dante i = ASC_MIN_ACTIVE_QNO;
626 1.1 dante s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
627 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1);
628 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng);
629 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
630 1.1 dante i++;
631 1.1 dante s_addr += ASC_QBLK_SIZE;
632 1.1 dante for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
633 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1);
634 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1);
635 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
636 1.1 dante }
637 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END);
638 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1);
639 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng);
640 1.1 dante i++;
641 1.1 dante s_addr += ASC_QBLK_SIZE;
642 1.1 dante for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) {
643 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i);
644 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i);
645 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
646 1.1 dante }
647 1.1 dante }
648 1.1 dante
649 1.1 dante
650 1.1 dante void
651 1.15 lukem AscReInitLram(ASC_SOFTC *sc)
652 1.1 dante {
653 1.1 dante
654 1.1 dante AscInitLram(sc);
655 1.1 dante AscInitQLinkVar(sc);
656 1.1 dante }
657 1.1 dante
658 1.1 dante
659 1.1 dante static void
660 1.15 lukem AscInitQLinkVar(ASC_SOFTC *sc)
661 1.1 dante {
662 1.1 dante bus_space_tag_t iot = sc->sc_iot;
663 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
664 1.1 dante u_int8_t i;
665 1.1 dante u_int16_t lram_addr;
666 1.1 dante
667 1.1 dante
668 1.1 dante ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1);
669 1.1 dante ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng);
670 1.1 dante ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1);
671 1.1 dante ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng);
672 1.1 dante AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1);
673 1.1 dante AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2);
674 1.1 dante AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng);
675 1.1 dante AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0);
676 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
677 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0);
678 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0);
679 1.1 dante AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0);
680 1.1 dante ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0);
681 1.1 dante lram_addr = ASC_QADR_BEG;
682 1.1 dante for (i = 0; i < 32; i++, lram_addr += 2)
683 1.1 dante AscWriteLramWord(iot, ioh, lram_addr, 0);
684 1.1 dante }
685 1.1 dante
686 1.1 dante
687 1.1 dante static int
688 1.15 lukem AscResetChipAndScsiBus(bus_space_tag_t iot, bus_space_handle_t ioh)
689 1.1 dante {
690 1.1 dante while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE);
691 1.1 dante
692 1.1 dante AscStopChip(iot, ioh);
693 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT);
694 1.1 dante
695 1.1 dante DvcDelayNanoSecond(60000);
696 1.1 dante
697 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM);
698 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_HALT);
699 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT);
700 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
701 1.1 dante
702 1.1 dante DvcSleepMilliSecond(200);
703 1.1 dante
704 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
705 1.16 briggs ASC_SET_CHIP_STATUS(iot, ioh, 0);
706 1.1 dante
707 1.1 dante DvcSleepMilliSecond(200);
708 1.1 dante
709 1.1 dante return (AscIsChipHalted(iot, ioh));
710 1.1 dante }
711 1.1 dante
712 1.1 dante
713 1.1 dante static u_int16_t
714 1.15 lukem AscGetChipBusType(bus_space_tag_t iot, bus_space_handle_t ioh)
715 1.1 dante {
716 1.1 dante u_int16_t chip_ver;
717 1.1 dante
718 1.1 dante chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh);
719 1.15 lukem #if 0
720 1.15 lukem if ((chip_ver >= ASC_CHIP_MIN_VER_VL) &&
721 1.1 dante (chip_ver <= ASC_CHIP_MAX_VER_VL)) {
722 1.9 dante if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) {
723 1.9 dante return (ASC_IS_EISA);
724 1.9 dante }
725 1.9 dante else {
726 1.9 dante return (ASC_IS_VL);
727 1.9 dante }
728 1.1 dante }
729 1.15 lukem #endif
730 1.15 lukem if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
731 1.1 dante (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
732 1.1 dante if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP)
733 1.1 dante return (ASC_IS_ISAPNP);
734 1.1 dante
735 1.1 dante return (ASC_IS_ISA);
736 1.1 dante } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
737 1.1 dante (chip_ver <= ASC_CHIP_MAX_VER_PCI))
738 1.1 dante return (ASC_IS_PCI);
739 1.1 dante
740 1.1 dante return (0);
741 1.1 dante }
742 1.1 dante
743 1.10 dante /*
744 1.9 dante static u_int16_t
745 1.15 lukem AscGetEisaChipCfg(bus_space_tag_t iot, bus_space_handle_t ioh)
746 1.9 dante {
747 1.9 dante int eisa_cfg_iop;
748 1.9 dante
749 1.9 dante eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK);
750 1.9 dante return (inw(eisa_cfg_iop));
751 1.9 dante }
752 1.10 dante */
753 1.9 dante
754 1.1 dante /******************************************************************************/
755 1.1 dante /* Chip register routines */
756 1.1 dante /******************************************************************************/
757 1.1 dante
758 1.1 dante
759 1.1 dante static void
760 1.15 lukem AscSetBank(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bank)
761 1.1 dante {
762 1.1 dante u_int8_t val;
763 1.1 dante
764 1.1 dante val = ASC_GET_CHIP_CONTROL(iot, ioh) &
765 1.1 dante (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST |
766 1.1 dante ASC_CC_DIAG | ASC_CC_SCSI_RESET |
767 1.1 dante ASC_CC_CHIP_RESET));
768 1.1 dante
769 1.1 dante switch (bank) {
770 1.1 dante case 1:
771 1.1 dante val |= ASC_CC_BANK_ONE;
772 1.1 dante break;
773 1.1 dante
774 1.1 dante case 2:
775 1.1 dante val |= ASC_CC_DIAG | ASC_CC_BANK_ONE;
776 1.1 dante break;
777 1.1 dante
778 1.1 dante default:
779 1.1 dante val &= ~ASC_CC_BANK_ONE;
780 1.1 dante }
781 1.1 dante
782 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, val);
783 1.1 dante return;
784 1.1 dante }
785 1.1 dante
786 1.1 dante
787 1.1 dante /******************************************************************************/
788 1.1 dante /* Chip routines */
789 1.1 dante /******************************************************************************/
790 1.1 dante
791 1.1 dante
792 1.1 dante static int
793 1.15 lukem AscStartChip(bus_space_tag_t iot, bus_space_handle_t ioh)
794 1.1 dante {
795 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, 0);
796 1.1 dante if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0)
797 1.1 dante return (0);
798 1.1 dante
799 1.1 dante return (1);
800 1.1 dante }
801 1.1 dante
802 1.1 dante
803 1.1 dante static int
804 1.15 lukem AscStopChip(bus_space_tag_t iot, bus_space_handle_t ioh)
805 1.1 dante {
806 1.1 dante u_int8_t cc_val;
807 1.1 dante
808 1.1 dante cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) &
809 1.1 dante (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG));
810 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT);
811 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_HALT);
812 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM);
813 1.1 dante if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0)
814 1.1 dante return (0);
815 1.1 dante
816 1.1 dante return (1);
817 1.1 dante }
818 1.1 dante
819 1.1 dante
820 1.1 dante static u_int8_t
821 1.15 lukem AscSetChipScsiID(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t new_id)
822 1.1 dante {
823 1.1 dante u_int16_t cfg_lsw;
824 1.1 dante
825 1.1 dante if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id)
826 1.1 dante return (new_id);
827 1.1 dante
828 1.1 dante cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh);
829 1.1 dante cfg_lsw &= 0xF8FF;
830 1.1 dante cfg_lsw |= (new_id & ASC_MAX_TID) << 8;
831 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
832 1.1 dante return (ASC_GET_CHIP_SCSI_ID(iot, ioh));
833 1.1 dante }
834 1.1 dante
835 1.1 dante
836 1.1 dante static u_int8_t
837 1.15 lukem AscGetChipScsiCtrl(bus_space_tag_t iot, bus_space_handle_t ioh)
838 1.1 dante {
839 1.1 dante u_int8_t scsi_ctrl;
840 1.1 dante
841 1.1 dante AscSetBank(iot, ioh, 1);
842 1.1 dante scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC);
843 1.1 dante AscSetBank(iot, ioh, 0);
844 1.1 dante return (scsi_ctrl);
845 1.1 dante }
846 1.1 dante
847 1.1 dante
848 1.1 dante static int
849 1.15 lukem AscSetRunChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh,
850 1.15 lukem u_int8_t tid_no, u_int8_t sdtr_data)
851 1.1 dante {
852 1.1 dante int retval = FALSE;
853 1.1 dante
854 1.1 dante if (AscHostReqRiscHalt(iot, ioh)) {
855 1.4 dante retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data);
856 1.1 dante AscStartChip(iot, ioh);
857 1.1 dante }
858 1.1 dante return (retval);
859 1.1 dante }
860 1.1 dante
861 1.1 dante
862 1.1 dante static int
863 1.15 lukem AscSetChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh,
864 1.15 lukem u_int8_t id, u_int8_t sdtr_data)
865 1.1 dante {
866 1.1 dante ASC_SCSI_BIT_ID_TYPE org_id;
867 1.1 dante int i;
868 1.22 christos int stax = TRUE;
869 1.1 dante
870 1.1 dante AscSetBank(iot, ioh, 1);
871 1.1 dante org_id = ASC_READ_CHIP_DVC_ID(iot, ioh);
872 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++)
873 1.1 dante if (org_id == (0x01 << i))
874 1.1 dante break;
875 1.1 dante
876 1.1 dante org_id = i;
877 1.1 dante ASC_WRITE_CHIP_DVC_ID(iot, ioh, id);
878 1.1 dante if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) {
879 1.1 dante AscSetBank(iot, ioh, 0);
880 1.1 dante ASC_SET_CHIP_SYN(iot, ioh, sdtr_data);
881 1.1 dante if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data)
882 1.22 christos stax = FALSE;
883 1.1 dante } else
884 1.22 christos stax = FALSE;
885 1.1 dante
886 1.1 dante AscSetBank(iot, ioh, 1);
887 1.1 dante ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id);
888 1.1 dante AscSetBank(iot, ioh, 0);
889 1.22 christos return (stax);
890 1.1 dante }
891 1.1 dante
892 1.1 dante
893 1.1 dante static int
894 1.15 lukem AscHostReqRiscHalt(bus_space_tag_t iot, bus_space_handle_t ioh)
895 1.1 dante {
896 1.1 dante int count = 0;
897 1.1 dante int retval = 0;
898 1.1 dante u_int8_t saved_stop_code;
899 1.1 dante
900 1.1 dante
901 1.1 dante if (AscIsChipHalted(iot, ioh))
902 1.1 dante return (1);
903 1.1 dante saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
904 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B,
905 1.1 dante ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
906 1.1 dante
907 1.1 dante do {
908 1.1 dante if (AscIsChipHalted(iot, ioh)) {
909 1.1 dante retval = 1;
910 1.1 dante break;
911 1.1 dante }
912 1.1 dante DvcSleepMilliSecond(100);
913 1.1 dante } while (count++ < 20);
914 1.1 dante
915 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code);
916 1.1 dante
917 1.1 dante return (retval);
918 1.1 dante }
919 1.1 dante
920 1.1 dante
921 1.1 dante static int
922 1.15 lukem AscIsChipHalted(bus_space_tag_t iot, bus_space_handle_t ioh)
923 1.1 dante {
924 1.1 dante if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0)
925 1.1 dante if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0)
926 1.1 dante return (1);
927 1.1 dante
928 1.1 dante return (0);
929 1.1 dante }
930 1.1 dante
931 1.1 dante
932 1.1 dante static void
933 1.15 lukem AscSetChipIH(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t ins_code)
934 1.1 dante {
935 1.1 dante AscSetBank(iot, ioh, 1);
936 1.1 dante ASC_WRITE_CHIP_IH(iot, ioh, ins_code);
937 1.1 dante AscSetBank(iot, ioh, 0);
938 1.1 dante
939 1.1 dante return;
940 1.1 dante }
941 1.1 dante
942 1.1 dante
943 1.1 dante /******************************************************************************/
944 1.1 dante /* Lram routines */
945 1.1 dante /******************************************************************************/
946 1.1 dante
947 1.1 dante
948 1.1 dante static u_int8_t
949 1.15 lukem AscReadLramByte(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr)
950 1.1 dante {
951 1.1 dante u_int8_t byte_data;
952 1.1 dante u_int16_t word_data;
953 1.1 dante
954 1.1 dante
955 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE);
956 1.1 dante word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
957 1.7 dante
958 1.7 dante if (addr & 1) {
959 1.7 dante /* odd address */
960 1.1 dante byte_data = (u_int8_t) ((word_data >> 8) & 0xFF);
961 1.7 dante } else {
962 1.7 dante /* even address */
963 1.1 dante byte_data = (u_int8_t) (word_data & 0xFF);
964 1.7 dante }
965 1.7 dante
966 1.1 dante return (byte_data);
967 1.1 dante }
968 1.1 dante
969 1.1 dante
970 1.1 dante static void
971 1.15 lukem AscWriteLramByte(bus_space_tag_t iot, bus_space_handle_t ioh,
972 1.15 lukem u_int16_t addr, u_int8_t data)
973 1.1 dante {
974 1.1 dante u_int16_t word_data;
975 1.1 dante
976 1.1 dante
977 1.1 dante word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE);
978 1.7 dante
979 1.7 dante if (addr & 1) {
980 1.7 dante /* odd address */
981 1.1 dante word_data &= 0x00FF;
982 1.1 dante word_data |= (((u_int16_t) data) << 8) & 0xFF00;
983 1.1 dante } else {
984 1.7 dante /* even address */
985 1.1 dante word_data &= 0xFF00;
986 1.1 dante word_data |= ((u_int16_t) data) & 0x00FF;
987 1.1 dante }
988 1.7 dante
989 1.16 briggs AscWriteLramWord(iot, ioh, addr & 0xFFFE, word_data);
990 1.1 dante }
991 1.1 dante
992 1.1 dante
993 1.1 dante static u_int16_t
994 1.15 lukem AscReadLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr)
995 1.1 dante {
996 1.1 dante
997 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
998 1.1 dante return (ASC_GET_CHIP_LRAM_DATA(iot, ioh));
999 1.1 dante }
1000 1.1 dante
1001 1.1 dante
1002 1.1 dante static void
1003 1.15 lukem AscWriteLramWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1004 1.15 lukem u_int16_t addr, u_int16_t data)
1005 1.1 dante {
1006 1.1 dante
1007 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1008 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, data);
1009 1.1 dante }
1010 1.1 dante
1011 1.1 dante
1012 1.1 dante static u_int32_t
1013 1.15 lukem AscReadLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr)
1014 1.1 dante {
1015 1.1 dante u_int16_t low_word, hi_word;
1016 1.1 dante
1017 1.1 dante
1018 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1019 1.1 dante low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1020 1.1 dante hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1021 1.1 dante
1022 1.1 dante return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word);
1023 1.1 dante }
1024 1.1 dante
1025 1.1 dante
1026 1.1 dante static void
1027 1.15 lukem AscWriteLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1028 1.15 lukem u_int16_t addr, u_int32_t data)
1029 1.1 dante {
1030 1.1 dante
1031 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1032 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF));
1033 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16));
1034 1.1 dante }
1035 1.1 dante
1036 1.1 dante
1037 1.1 dante static void
1038 1.15 lukem AscMemWordSetLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1039 1.15 lukem u_int16_t s_addr, u_int16_t s_words, int count)
1040 1.1 dante {
1041 1.1 dante int i;
1042 1.1 dante
1043 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1044 1.1 dante for (i = 0; i < count; i++)
1045 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words);
1046 1.1 dante }
1047 1.1 dante
1048 1.1 dante
1049 1.1 dante static void
1050 1.15 lukem AscMemWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1051 1.21 christos u_int16_t s_addr, const u_int16_t *s_buffer, int words)
1052 1.1 dante {
1053 1.1 dante int i;
1054 1.1 dante
1055 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1056 1.1 dante for (i = 0; i < words; i++, s_buffer++)
1057 1.7 dante ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer);
1058 1.5 dante }
1059 1.5 dante
1060 1.5 dante
1061 1.5 dante static void
1062 1.15 lukem AscMemWordCopyFromLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1063 1.15 lukem u_int16_t s_addr, u_int16_t *s_buffer, int words)
1064 1.1 dante {
1065 1.1 dante int i;
1066 1.1 dante
1067 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1068 1.1 dante for (i = 0; i < words; i++, s_buffer++)
1069 1.7 dante *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh);
1070 1.1 dante }
1071 1.1 dante
1072 1.1 dante
1073 1.1 dante static void
1074 1.15 lukem AscMemDWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1075 1.15 lukem u_int16_t s_addr, u_int32_t *s_buffer, int dwords)
1076 1.1 dante {
1077 1.1 dante int i;
1078 1.7 dante u_int32_t *pw;
1079 1.1 dante
1080 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1081 1.1 dante
1082 1.7 dante pw = s_buffer;
1083 1.7 dante for (i = 0; i < dwords; i++, pw++) {
1084 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw));
1085 1.7 dante DELAY(1);
1086 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw));
1087 1.7 dante }
1088 1.1 dante }
1089 1.1 dante
1090 1.1 dante
1091 1.1 dante static u_int32_t
1092 1.15 lukem AscMemSumLramWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1093 1.15 lukem u_int16_t s_addr, int words)
1094 1.1 dante {
1095 1.1 dante u_int32_t sum = 0L;
1096 1.1 dante u_int16_t i;
1097 1.1 dante
1098 1.1 dante
1099 1.6 dante for (i = 0; i < words; i++, s_addr += 2)
1100 1.6 dante sum += AscReadLramWord(iot, ioh, s_addr);
1101 1.1 dante
1102 1.1 dante return (sum);
1103 1.1 dante }
1104 1.1 dante
1105 1.1 dante
1106 1.1 dante static int
1107 1.15 lukem AscTestExternalLram(bus_space_tag_t iot, bus_space_handle_t ioh)
1108 1.1 dante {
1109 1.1 dante u_int16_t q_addr;
1110 1.1 dante u_int16_t saved_word;
1111 1.1 dante int retval;
1112 1.1 dante
1113 1.1 dante
1114 1.1 dante retval = 0;
1115 1.1 dante q_addr = ASC_QNO_TO_QADDR(241);
1116 1.1 dante saved_word = AscReadLramWord(iot, ioh, q_addr);
1117 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr);
1118 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA);
1119 1.1 dante DvcSleepMilliSecond(10);
1120 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr);
1121 1.1 dante
1122 1.1 dante if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) {
1123 1.1 dante retval = 1;
1124 1.1 dante AscWriteLramWord(iot, ioh, q_addr, saved_word);
1125 1.1 dante }
1126 1.1 dante return (retval);
1127 1.1 dante }
1128 1.1 dante
1129 1.1 dante
1130 1.1 dante /******************************************************************************/
1131 1.1 dante /* MicroCode routines */
1132 1.1 dante /******************************************************************************/
1133 1.1 dante
1134 1.1 dante
1135 1.1 dante static u_int16_t
1136 1.15 lukem AscInitMicroCodeVar(ASC_SOFTC *sc)
1137 1.1 dante {
1138 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1139 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1140 1.1 dante u_int32_t phy_addr;
1141 1.1 dante int i;
1142 1.1 dante
1143 1.1 dante
1144 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++)
1145 1.1 dante ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i,
1146 1.1 dante sc->sdtr_period_offset[i]);
1147 1.1 dante
1148 1.1 dante AscInitQLinkVar(sc);
1149 1.1 dante AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable);
1150 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B,
1151 1.1 dante ASC_TID_TO_TARGET_ID(sc->chip_scsi_id));
1152 1.1 dante
1153 1.11 thorpej phy_addr = (sc->overrun_buf & 0xfffffff8) + 8;
1154 1.11 thorpej AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr);
1155 1.11 thorpej AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D,
1156 1.11 thorpej ASC_OVERRUN_BSIZE - 8);
1157 1.1 dante
1158 1.1 dante sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W);
1159 1.1 dante sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W);
1160 1.1 dante ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
1161 1.1 dante
1162 1.1 dante if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) {
1163 1.1 dante return (0);
1164 1.1 dante }
1165 1.1 dante if (AscStartChip(iot, ioh) != 1) {
1166 1.1 dante return (0);
1167 1.1 dante }
1168 1.1 dante return (1);
1169 1.1 dante }
1170 1.1 dante
1171 1.1 dante
1172 1.1 dante static u_int32_t
1173 1.15 lukem AscLoadMicroCode(bus_space_tag_t iot, bus_space_handle_t ioh,
1174 1.21 christos u_int16_t s_addr, const u_int16_t *mcode_buf, u_int16_t mcode_size)
1175 1.7 dante {
1176 1.7 dante u_int32_t chksum;
1177 1.7 dante u_int16_t mcode_word_size;
1178 1.7 dante u_int16_t mcode_chksum;
1179 1.7 dante
1180 1.7 dante mcode_word_size = mcode_size >> 1;
1181 1.7 dante /* clear board memory */
1182 1.7 dante AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size);
1183 1.7 dante /* copy uCode to board memory */
1184 1.7 dante AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size);
1185 1.7 dante chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size);
1186 1.7 dante mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG,
1187 1.7 dante ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1));
1188 1.7 dante AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum);
1189 1.7 dante AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size);
1190 1.7 dante
1191 1.7 dante return (chksum);
1192 1.7 dante }
1193 1.7 dante
1194 1.7 dante
1195 1.1 dante /******************************************************************************/
1196 1.1 dante /* EEProm routines */
1197 1.1 dante /******************************************************************************/
1198 1.1 dante
1199 1.1 dante
1200 1.1 dante static int
1201 1.15 lukem AscWriteEEPCmdReg(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t cmd_reg)
1202 1.1 dante {
1203 1.1 dante u_int8_t read_back;
1204 1.1 dante int retry;
1205 1.1 dante
1206 1.1 dante retry = 0;
1207 1.1 dante
1208 1.1 dante while (TRUE) {
1209 1.1 dante ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg);
1210 1.1 dante DvcSleepMilliSecond(1);
1211 1.1 dante read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh);
1212 1.1 dante if (read_back == cmd_reg)
1213 1.1 dante return (1);
1214 1.1 dante
1215 1.1 dante if (retry++ > ASC_EEP_MAX_RETRY)
1216 1.1 dante return (0);
1217 1.1 dante }
1218 1.1 dante }
1219 1.1 dante
1220 1.1 dante
1221 1.1 dante static int
1222 1.15 lukem AscWriteEEPDataReg(bus_space_tag_t iot, bus_space_handle_t ioh,
1223 1.15 lukem u_int16_t data_reg)
1224 1.1 dante {
1225 1.1 dante u_int16_t read_back;
1226 1.1 dante int retry;
1227 1.1 dante
1228 1.1 dante retry = 0;
1229 1.1 dante while (TRUE) {
1230 1.1 dante ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg);
1231 1.1 dante DvcSleepMilliSecond(1);
1232 1.1 dante read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh);
1233 1.1 dante if (read_back == data_reg)
1234 1.1 dante return (1);
1235 1.1 dante
1236 1.1 dante if (retry++ > ASC_EEP_MAX_RETRY)
1237 1.1 dante return (0);
1238 1.1 dante }
1239 1.1 dante }
1240 1.1 dante
1241 1.1 dante
1242 1.1 dante static void
1243 1.1 dante AscWaitEEPRead(void)
1244 1.1 dante {
1245 1.1 dante
1246 1.1 dante DvcSleepMilliSecond(1);
1247 1.1 dante }
1248 1.1 dante
1249 1.1 dante
1250 1.1 dante static void
1251 1.1 dante AscWaitEEPWrite(void)
1252 1.1 dante {
1253 1.1 dante
1254 1.1 dante DvcSleepMilliSecond(1);
1255 1.1 dante }
1256 1.1 dante
1257 1.1 dante
1258 1.1 dante static u_int16_t
1259 1.15 lukem AscReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t addr)
1260 1.1 dante {
1261 1.1 dante u_int16_t read_wval;
1262 1.1 dante u_int8_t cmd_reg;
1263 1.1 dante
1264 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE);
1265 1.1 dante AscWaitEEPRead();
1266 1.1 dante cmd_reg = addr | ASC_EEP_CMD_READ;
1267 1.1 dante AscWriteEEPCmdReg(iot, ioh, cmd_reg);
1268 1.1 dante AscWaitEEPRead();
1269 1.1 dante read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh);
1270 1.1 dante AscWaitEEPRead();
1271 1.1 dante
1272 1.1 dante return (read_wval);
1273 1.1 dante }
1274 1.1 dante
1275 1.1 dante
1276 1.1 dante static u_int16_t
1277 1.15 lukem AscWriteEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1278 1.15 lukem u_int8_t addr, u_int16_t word_val)
1279 1.1 dante {
1280 1.1 dante u_int16_t read_wval;
1281 1.1 dante
1282 1.1 dante read_wval = AscReadEEPWord(iot, ioh, addr);
1283 1.1 dante if (read_wval != word_val) {
1284 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE);
1285 1.1 dante AscWaitEEPRead();
1286 1.1 dante AscWriteEEPDataReg(iot, ioh, word_val);
1287 1.1 dante AscWaitEEPRead();
1288 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr);
1289 1.1 dante AscWaitEEPWrite();
1290 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE);
1291 1.1 dante AscWaitEEPRead();
1292 1.1 dante return (AscReadEEPWord(iot, ioh, addr));
1293 1.1 dante }
1294 1.1 dante return (read_wval);
1295 1.1 dante }
1296 1.1 dante
1297 1.1 dante
1298 1.1 dante static u_int16_t
1299 1.15 lukem AscGetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh,
1300 1.15 lukem ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type)
1301 1.1 dante {
1302 1.1 dante u_int16_t wval;
1303 1.1 dante u_int16_t sum;
1304 1.1 dante u_int16_t *wbuf;
1305 1.1 dante int cfg_beg;
1306 1.1 dante int cfg_end;
1307 1.1 dante int s_addr;
1308 1.1 dante int isa_pnp_wsize;
1309 1.1 dante
1310 1.1 dante
1311 1.1 dante wbuf = (u_int16_t *) cfg_buf;
1312 1.1 dante sum = 0;
1313 1.1 dante isa_pnp_wsize = 0;
1314 1.1 dante
1315 1.1 dante for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) {
1316 1.1 dante wval = AscReadEEPWord(iot, ioh, s_addr);
1317 1.1 dante sum += wval;
1318 1.1 dante *wbuf = wval;
1319 1.1 dante }
1320 1.1 dante
1321 1.1 dante if (bus_type & ASC_IS_VL) {
1322 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
1323 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
1324 1.1 dante } else {
1325 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG;
1326 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR;
1327 1.1 dante }
1328 1.1 dante
1329 1.1 dante for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
1330 1.1 dante wval = AscReadEEPWord(iot, ioh, s_addr);
1331 1.1 dante sum += wval;
1332 1.1 dante *wbuf = wval;
1333 1.1 dante }
1334 1.1 dante
1335 1.1 dante *wbuf = AscReadEEPWord(iot, ioh, s_addr);
1336 1.1 dante
1337 1.1 dante return (sum);
1338 1.1 dante }
1339 1.1 dante
1340 1.1 dante
1341 1.1 dante static int
1342 1.15 lukem AscSetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh,
1343 1.15 lukem ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type)
1344 1.1 dante {
1345 1.1 dante int retry;
1346 1.1 dante int n_error;
1347 1.1 dante
1348 1.1 dante retry = 0;
1349 1.1 dante while (TRUE) {
1350 1.1 dante if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0)
1351 1.1 dante break;
1352 1.1 dante
1353 1.1 dante if (++retry > ASC_EEP_MAX_RETRY)
1354 1.1 dante break;
1355 1.1 dante }
1356 1.1 dante
1357 1.1 dante return (n_error);
1358 1.1 dante }
1359 1.1 dante
1360 1.1 dante
1361 1.1 dante static int
1362 1.15 lukem AscSetEEPConfigOnce(bus_space_tag_t iot, bus_space_handle_t ioh,
1363 1.15 lukem ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type)
1364 1.1 dante {
1365 1.1 dante int n_error;
1366 1.1 dante u_int16_t *wbuf;
1367 1.1 dante u_int16_t sum;
1368 1.1 dante int s_addr;
1369 1.1 dante int cfg_beg;
1370 1.1 dante int cfg_end;
1371 1.1 dante
1372 1.1 dante wbuf = (u_int16_t *) cfg_buf;
1373 1.1 dante n_error = 0;
1374 1.1 dante sum = 0;
1375 1.1 dante
1376 1.1 dante for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
1377 1.1 dante sum += *wbuf;
1378 1.1 dante if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf))
1379 1.1 dante n_error++;
1380 1.1 dante }
1381 1.1 dante
1382 1.1 dante if (bus_type & ASC_IS_VL) {
1383 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
1384 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
1385 1.1 dante } else {
1386 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG;
1387 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR;
1388 1.1 dante }
1389 1.1 dante
1390 1.1 dante for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
1391 1.1 dante sum += *wbuf;
1392 1.1 dante if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf))
1393 1.1 dante n_error++;
1394 1.1 dante }
1395 1.1 dante
1396 1.1 dante *wbuf = sum;
1397 1.1 dante if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum))
1398 1.1 dante n_error++;
1399 1.1 dante
1400 1.1 dante wbuf = (u_int16_t *) cfg_buf;
1401 1.7 dante for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
1402 1.1 dante if (*wbuf != AscReadEEPWord(iot, ioh, s_addr))
1403 1.1 dante n_error++;
1404 1.7 dante }
1405 1.1 dante
1406 1.7 dante for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) {
1407 1.1 dante if (*wbuf != AscReadEEPWord(iot, ioh, s_addr))
1408 1.1 dante n_error++;
1409 1.7 dante }
1410 1.1 dante
1411 1.1 dante return (n_error);
1412 1.1 dante }
1413 1.1 dante
1414 1.1 dante
1415 1.7 dante #ifdef ASC_DEBUG
1416 1.7 dante static void
1417 1.15 lukem AscPrintEEPConfig(ASCEEP_CONFIG *eep_config, u_int16_t chksum)
1418 1.7 dante {
1419 1.7 dante printf("---- ASC EEprom settings ----\n");
1420 1.7 dante printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw);
1421 1.7 dante printf("cfg_msw = 0x%x\n", eep_config->cfg_msw);
1422 1.7 dante printf("init_sdtr = 0x%x\n", eep_config->init_sdtr);
1423 1.7 dante printf("disc_enable = 0x%x\n", eep_config->disc_enable);
1424 1.7 dante printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng);
1425 1.7 dante printf("start_motor = 0x%x\n", eep_config->start_motor);
1426 1.7 dante printf("max_total_qng = 0x%x\n", eep_config->max_total_qng);
1427 1.7 dante printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng);
1428 1.7 dante printf("bios_scan = 0x%x\n", eep_config->bios_scan);
1429 1.7 dante printf("power_up_wait = 0x%x\n", eep_config->power_up_wait);
1430 1.7 dante printf("no_scam = %d\n", eep_config->no_scam);
1431 1.7 dante printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id);
1432 1.7 dante printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed);
1433 1.7 dante printf("cntl = 0x%x\n", eep_config->cntl);
1434 1.7 dante #if BYTE_ORDER == BIG_ENDIAN
1435 1.7 dante printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]);
1436 1.7 dante printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]);
1437 1.7 dante printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]);
1438 1.7 dante printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]);
1439 1.7 dante printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]);
1440 1.7 dante printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]);
1441 1.7 dante #else
1442 1.7 dante printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]);
1443 1.7 dante printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]);
1444 1.7 dante printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]);
1445 1.7 dante printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]);
1446 1.7 dante printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]);
1447 1.7 dante printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]);
1448 1.7 dante #endif
1449 1.7 dante printf("checksum = 0x%x\n", eep_config->chksum);
1450 1.7 dante printf("calculated checksum = 0x%x\n", chksum);
1451 1.7 dante printf("-----------------------------\n");
1452 1.7 dante }
1453 1.7 dante #endif
1454 1.7 dante
1455 1.7 dante
1456 1.1 dante /******************************************************************************/
1457 1.1 dante /* Interrupt routines */
1458 1.1 dante /******************************************************************************/
1459 1.1 dante
1460 1.1 dante
1461 1.1 dante int
1462 1.15 lukem AscISR(ASC_SOFTC *sc)
1463 1.1 dante {
1464 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1465 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1466 1.1 dante u_int16_t chipstat;
1467 1.1 dante u_int16_t saved_ram_addr;
1468 1.1 dante u_int8_t ctrl_reg;
1469 1.1 dante u_int8_t saved_ctrl_reg;
1470 1.1 dante int int_pending;
1471 1.1 dante int status;
1472 1.1 dante u_int8_t host_flag;
1473 1.1 dante
1474 1.1 dante
1475 1.1 dante int_pending = FALSE;
1476 1.1 dante
1477 1.1 dante ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh);
1478 1.1 dante saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET |
1479 1.1 dante ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST));
1480 1.1 dante chipstat = ASC_GET_CHIP_STATUS(iot, ioh);
1481 1.7 dante if (chipstat & ASC_CSW_SCSI_RESET_LATCH) {
1482 1.1 dante if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
1483 1.1 dante int_pending = TRUE;
1484 1.1 dante sc->sdtr_done = 0;
1485 1.1 dante saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT);
1486 1.1 dante
1487 1.1 dante while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE);
1488 1.1 dante
1489 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT));
1490 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
1491 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
1492 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
1493 1.1 dante chipstat = ASC_GET_CHIP_STATUS(iot, ioh);
1494 1.1 dante }
1495 1.7 dante }
1496 1.1 dante saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh);
1497 1.1 dante host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) &
1498 1.1 dante (u_int8_t) (~ASC_HOST_FLAG_IN_ISR);
1499 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B,
1500 1.1 dante (host_flag | ASC_HOST_FLAG_IN_ISR));
1501 1.1 dante
1502 1.1 dante if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) {
1503 1.1 dante AscAckInterrupt(iot, ioh);
1504 1.1 dante int_pending = TRUE;
1505 1.1 dante
1506 1.1 dante if ((chipstat & ASC_CSW_HALTED) &&
1507 1.1 dante (ctrl_reg & ASC_CC_SINGLE_STEP)) {
1508 1.1 dante AscIsrChipHalted(sc);
1509 1.1 dante saved_ctrl_reg &= ~ASC_CC_HALT;
1510 1.1 dante } else {
1511 1.1 dante if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) {
1512 1.1 dante while (((status = AscIsrQDone(sc)) & 0x01) != 0);
1513 1.1 dante } else {
1514 1.1 dante do {
1515 1.1 dante if ((status = AscIsrQDone(sc)) == 1)
1516 1.1 dante break;
1517 1.1 dante } while (status == 0x11);
1518 1.1 dante }
1519 1.1 dante
1520 1.1 dante if (status & 0x80)
1521 1.1 dante int_pending = -1;
1522 1.1 dante }
1523 1.1 dante }
1524 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag);
1525 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr);
1526 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg);
1527 1.1 dante
1528 1.1 dante return (1);
1529 1.1 dante /* return(int_pending); */
1530 1.1 dante }
1531 1.1 dante
1532 1.1 dante
1533 1.1 dante static int
1534 1.15 lukem AscIsrQDone(ASC_SOFTC *sc)
1535 1.1 dante {
1536 1.1 dante u_int8_t next_qp;
1537 1.1 dante u_int8_t n_q_used;
1538 1.1 dante u_int8_t sg_list_qp;
1539 1.1 dante u_int8_t sg_queue_cnt;
1540 1.1 dante u_int8_t q_cnt;
1541 1.1 dante u_int8_t done_q_tail;
1542 1.1 dante u_int8_t tid_no;
1543 1.1 dante ASC_SCSI_BIT_ID_TYPE scsi_busy;
1544 1.1 dante ASC_SCSI_BIT_ID_TYPE target_id;
1545 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1546 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1547 1.1 dante u_int16_t q_addr;
1548 1.1 dante u_int16_t sg_q_addr;
1549 1.1 dante u_int8_t cur_target_qng;
1550 1.1 dante ASC_QDONE_INFO scsiq_buf;
1551 1.1 dante ASC_QDONE_INFO *scsiq;
1552 1.1 dante
1553 1.1 dante n_q_used = 1;
1554 1.1 dante scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
1555 1.1 dante done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh);
1556 1.1 dante q_addr = ASC_QNO_TO_QADDR(done_q_tail);
1557 1.1 dante next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD));
1558 1.1 dante
1559 1.1 dante if (next_qp != ASC_QLINK_END) {
1560 1.1 dante ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp);
1561 1.1 dante q_addr = ASC_QNO_TO_QADDR(next_qp);
1562 1.1 dante sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq,
1563 1.1 dante sc->max_dma_count);
1564 1.1 dante AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS),
1565 1.1 dante (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED)));
1566 1.1 dante tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
1567 1.1 dante target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
1568 1.1 dante if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) {
1569 1.1 dante sg_q_addr = q_addr;
1570 1.1 dante sg_list_qp = next_qp;
1571 1.1 dante for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
1572 1.1 dante sg_list_qp = AscReadLramByte(iot, ioh,
1573 1.1 dante sg_q_addr + ASC_SCSIQ_B_FWD);
1574 1.1 dante sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
1575 1.1 dante if (sg_list_qp == ASC_QLINK_END) {
1576 1.1 dante AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS);
1577 1.1 dante scsiq->d3.done_stat = ASC_QD_WITH_ERROR;
1578 1.1 dante scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED;
1579 1.1 dante panic("AscIsrQDone: Corrupted SG list encountered");
1580 1.1 dante }
1581 1.1 dante AscWriteLramByte(iot, ioh,
1582 1.1 dante sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE);
1583 1.1 dante }
1584 1.1 dante n_q_used = sg_queue_cnt + 1;
1585 1.1 dante ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp);
1586 1.1 dante }
1587 1.1 dante if (sc->queue_full_or_busy & target_id) {
1588 1.1 dante cur_target_qng = AscReadLramByte(iot, ioh,
1589 1.1 dante ASC_QADR_BEG + scsiq->d2.target_ix);
1590 1.1 dante
1591 1.1 dante if (cur_target_qng < sc->max_dvc_qng[tid_no]) {
1592 1.1 dante scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
1593 1.1 dante scsi_busy &= ~target_id;
1594 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
1595 1.1 dante sc->queue_full_or_busy &= ~target_id;
1596 1.1 dante }
1597 1.1 dante }
1598 1.1 dante if (sc->cur_total_qng >= n_q_used) {
1599 1.1 dante sc->cur_total_qng -= n_q_used;
1600 1.7 dante if (sc->cur_dvc_qng[tid_no] != 0) {
1601 1.1 dante sc->cur_dvc_qng[tid_no]--;
1602 1.7 dante }
1603 1.1 dante } else {
1604 1.1 dante AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG);
1605 1.1 dante scsiq->d3.done_stat = ASC_QD_WITH_ERROR;
1606 1.1 dante panic("AscIsrQDone: Attempting to free more queues than are active");
1607 1.1 dante }
1608 1.1 dante
1609 1.8 dante if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) ||
1610 1.8 dante ((scsiq->q_status & ASC_QS_ABORTED) != 0)) {
1611 1.1 dante return (0x11);
1612 1.1 dante } else if (scsiq->q_status == ASC_QS_DONE) {
1613 1.1 dante scsiq->remain_bytes += scsiq->extra_bytes;
1614 1.1 dante
1615 1.1 dante if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) {
1616 1.1 dante if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) {
1617 1.1 dante if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) {
1618 1.1 dante scsiq->d3.done_stat = ASC_QD_NO_ERROR;
1619 1.1 dante scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR;
1620 1.1 dante }
1621 1.1 dante } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
1622 1.1 dante AscStopChip(iot, ioh);
1623 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT));
1624 1.1 dante DvcDelayNanoSecond(60000);
1625 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
1626 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
1627 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
1628 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, 0);
1629 1.1 dante }
1630 1.1 dante }
1631 1.28 uwe (*sc->isr_callback)(sc, scsiq);
1632 1.1 dante
1633 1.1 dante return (1);
1634 1.1 dante } else {
1635 1.1 dante AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS);
1636 1.1 dante panic("AscIsrQDone: completed scsiq with unknown status");
1637 1.1 dante
1638 1.1 dante return (0x80);
1639 1.1 dante }
1640 1.1 dante }
1641 1.1 dante return (0);
1642 1.1 dante }
1643 1.1 dante
1644 1.1 dante
1645 1.1 dante /*
1646 1.1 dante * handle all the conditions that may halt the board
1647 1.1 dante * waiting us to intervene
1648 1.1 dante */
1649 1.1 dante static void
1650 1.15 lukem AscIsrChipHalted(ASC_SOFTC *sc)
1651 1.1 dante {
1652 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1653 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1654 1.1 dante EXT_MSG out_msg;
1655 1.1 dante u_int16_t int_halt_code;
1656 1.1 dante u_int16_t halt_q_addr;
1657 1.1 dante u_int8_t halt_qp;
1658 1.1 dante u_int8_t target_ix;
1659 1.1 dante u_int8_t tag_code;
1660 1.1 dante u_int8_t q_status;
1661 1.1 dante u_int8_t q_cntl;
1662 1.1 dante u_int8_t tid_no;
1663 1.1 dante u_int8_t cur_dvc_qng;
1664 1.1 dante u_int8_t asyn_sdtr;
1665 1.1 dante u_int8_t scsi_status;
1666 1.1 dante u_int8_t sdtr_data;
1667 1.1 dante ASC_SCSI_BIT_ID_TYPE scsi_busy;
1668 1.1 dante ASC_SCSI_BIT_ID_TYPE target_id;
1669 1.1 dante
1670 1.1 dante
1671 1.1 dante int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W);
1672 1.1 dante
1673 1.1 dante halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B);
1674 1.1 dante halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
1675 1.1 dante target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX);
1676 1.1 dante q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL);
1677 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
1678 1.1 dante target_id = ASC_TID_TO_TARGET_ID(tid_no);
1679 1.1 dante
1680 1.7 dante if (sc->pci_fix_asyn_xfer & target_id) {
1681 1.1 dante asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
1682 1.7 dante } else {
1683 1.1 dante asyn_sdtr = 0;
1684 1.7 dante }
1685 1.1 dante
1686 1.1 dante if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
1687 1.1 dante if (sc->pci_fix_asyn_xfer & target_id) {
1688 1.1 dante AscSetChipSDTR(iot, ioh, 0, tid_no);
1689 1.1 dante sc->sdtr_data[tid_no] = 0;
1690 1.1 dante }
1691 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1692 1.1 dante } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
1693 1.1 dante if (sc->pci_fix_asyn_xfer & target_id) {
1694 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
1695 1.1 dante sc->sdtr_data[tid_no] = asyn_sdtr;
1696 1.1 dante }
1697 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1698 1.1 dante } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
1699 1.1 dante AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id,
1700 1.1 dante tid_no, asyn_sdtr);
1701 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1702 1.1 dante } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
1703 1.1 dante q_cntl |= ASC_QC_REQ_SENSE;
1704 1.1 dante
1705 1.1 dante if (sc->init_sdtr & target_id) {
1706 1.1 dante sc->sdtr_done &= ~target_id;
1707 1.1 dante
1708 1.1 dante sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
1709 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
1710 1.1 dante AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) &
1711 1.1 dante (sc->max_sdtr_index - 1)],
1712 1.1 dante (sdtr_data & ASC_SYN_MAX_OFFSET));
1713 1.1 dante }
1714 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
1715 1.1 dante
1716 1.1 dante tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE);
1717 1.1 dante tag_code &= 0xDC;
1718 1.1 dante
1719 1.1 dante if ((sc->pci_fix_asyn_xfer & target_id) &&
1720 1.1 dante !(sc->pci_fix_asyn_xfer_always & target_id)) {
1721 1.1 dante tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT |
1722 1.1 dante ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
1723 1.1 dante }
1724 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code);
1725 1.1 dante
1726 1.1 dante q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS);
1727 1.1 dante q_status |= ASC_QS_READY | ASC_QS_BUSY;
1728 1.1 dante
1729 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status);
1730 1.1 dante
1731 1.1 dante scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
1732 1.1 dante scsi_busy &= ~target_id;
1733 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
1734 1.1 dante
1735 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1736 1.1 dante } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
1737 1.1 dante AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG,
1738 1.1 dante (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1);
1739 1.1 dante
1740 1.1 dante if ((out_msg.msg_type == MS_EXTEND) &&
1741 1.1 dante (out_msg.msg_len == MS_SDTR_LEN) &&
1742 1.1 dante (out_msg.msg_req == MS_SDTR_CODE)) {
1743 1.1 dante sc->init_sdtr &= ~target_id;
1744 1.1 dante sc->sdtr_done &= ~target_id;
1745 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
1746 1.1 dante sc->sdtr_data[tid_no] = asyn_sdtr;
1747 1.1 dante }
1748 1.1 dante q_cntl &= ~ASC_QC_MSG_OUT;
1749 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
1750 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1751 1.1 dante } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
1752 1.1 dante scsi_status = AscReadLramByte(iot, ioh,
1753 1.1 dante halt_q_addr + ASC_SCSIQ_SCSI_STATUS);
1754 1.1 dante cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG);
1755 1.1 dante
1756 1.1 dante if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) {
1757 1.1 dante scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
1758 1.1 dante scsi_busy |= target_id;
1759 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
1760 1.1 dante sc->queue_full_or_busy |= target_id;
1761 1.1 dante
1762 1.1 dante if (scsi_status == SS_QUEUE_FULL) {
1763 1.1 dante if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
1764 1.1 dante cur_dvc_qng -= 1;
1765 1.1 dante sc->max_dvc_qng[tid_no] = cur_dvc_qng;
1766 1.1 dante
1767 1.1 dante AscWriteLramByte(iot, ioh,
1768 1.1 dante tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng);
1769 1.1 dante
1770 1.1 dante #if ASC_QUEUE_FLOW_CONTROL
1771 1.1 dante if ((sc->device[tid_no] != NULL) &&
1772 1.1 dante (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) {
1773 1.1 dante sc->device[tid_no]->queue_curr_depth = cur_dvc_qng;
1774 1.1 dante }
1775 1.1 dante #endif /* ASC_QUEUE_FLOW_CONTROL */
1776 1.1 dante }
1777 1.1 dante }
1778 1.1 dante }
1779 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1780 1.1 dante }
1781 1.1 dante return;
1782 1.1 dante }
1783 1.1 dante
1784 1.1 dante
1785 1.1 dante static int
1786 1.15 lukem AscWaitTixISRDone(ASC_SOFTC *sc, u_int8_t target_ix)
1787 1.1 dante {
1788 1.1 dante u_int8_t cur_req;
1789 1.1 dante u_int8_t tid_no;
1790 1.1 dante int i = 0;
1791 1.1 dante
1792 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
1793 1.1 dante while (i++ < 10) {
1794 1.1 dante if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0)
1795 1.1 dante break;
1796 1.1 dante
1797 1.1 dante DvcSleepMilliSecond(1000L);
1798 1.1 dante if (sc->cur_dvc_qng[tid_no] == cur_req)
1799 1.1 dante break;
1800 1.1 dante }
1801 1.1 dante return (1);
1802 1.1 dante }
1803 1.1 dante
1804 1.1 dante static int
1805 1.15 lukem AscWaitISRDone(ASC_SOFTC *sc)
1806 1.1 dante {
1807 1.1 dante int tid;
1808 1.1 dante
1809 1.1 dante for (tid = 0; tid <= ASC_MAX_TID; tid++)
1810 1.1 dante AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid));
1811 1.1 dante
1812 1.1 dante return (1);
1813 1.1 dante }
1814 1.1 dante
1815 1.1 dante
1816 1.1 dante static u_int8_t
1817 1.15 lukem _AscCopyLramScsiDoneQ(bus_space_tag_t iot, bus_space_handle_t ioh,
1818 1.15 lukem u_int16_t q_addr, ASC_QDONE_INFO *scsiq, u_int32_t max_dma_count)
1819 1.1 dante {
1820 1.1 dante u_int16_t _val;
1821 1.1 dante u_int8_t sg_queue_cnt;
1822 1.1 dante
1823 1.7 dante AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq);
1824 1.7 dante
1825 1.1 dante _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
1826 1.7 dante scsiq->q_status = LO_BYTE(_val);
1827 1.7 dante scsiq->q_no = HI_BYTE(_val);
1828 1.1 dante _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL);
1829 1.7 dante scsiq->cntl = LO_BYTE(_val);
1830 1.7 dante sg_queue_cnt = HI_BYTE(_val);
1831 1.1 dante _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN);
1832 1.7 dante scsiq->sense_len = LO_BYTE(_val);
1833 1.7 dante scsiq->extra_bytes = HI_BYTE(_val);
1834 1.1 dante scsiq->remain_bytes = AscReadLramWord(iot, ioh,
1835 1.1 dante q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT);
1836 1.1 dante scsiq->remain_bytes &= max_dma_count;
1837 1.1 dante
1838 1.1 dante return (sg_queue_cnt);
1839 1.1 dante }
1840 1.1 dante
1841 1.1 dante
1842 1.1 dante static void
1843 1.15 lukem AscGetQDoneInfo(bus_space_tag_t iot, bus_space_handle_t ioh,
1844 1.15 lukem u_int16_t addr, ASC_QDONE_INFO *scsiq)
1845 1.7 dante {
1846 1.7 dante u_int16_t val;
1847 1.7 dante
1848 1.7 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1849 1.7 dante
1850 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1851 1.7 dante scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh));
1852 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1853 1.7 dante scsiq->d2.target_ix = LO_BYTE(val);
1854 1.7 dante scsiq->d2.flag = HI_BYTE(val);
1855 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1856 1.7 dante scsiq->d2.cdb_len = LO_BYTE(val);
1857 1.7 dante scsiq->d2.tag_code = HI_BYTE(val);
1858 1.7 dante scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1859 1.7 dante
1860 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1861 1.7 dante scsiq->d3.done_stat = LO_BYTE(val);
1862 1.7 dante scsiq->d3.host_stat = HI_BYTE(val);
1863 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1864 1.7 dante scsiq->d3.scsi_stat = LO_BYTE(val);
1865 1.7 dante scsiq->d3.scsi_msg = HI_BYTE(val);
1866 1.7 dante }
1867 1.7 dante
1868 1.7 dante
1869 1.7 dante static void
1870 1.15 lukem AscToggleIRQAct(bus_space_tag_t iot, bus_space_handle_t ioh)
1871 1.1 dante {
1872 1.1 dante
1873 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT);
1874 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
1875 1.1 dante }
1876 1.1 dante
1877 1.1 dante
1878 1.1 dante static void
1879 1.15 lukem AscDisableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh)
1880 1.1 dante {
1881 1.1 dante u_int16_t cfg;
1882 1.1 dante
1883 1.1 dante cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1884 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON));
1885 1.1 dante }
1886 1.1 dante
1887 1.1 dante
1888 1.1 dante static void
1889 1.15 lukem AscEnableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh)
1890 1.1 dante {
1891 1.1 dante u_int16_t cfg;
1892 1.1 dante
1893 1.1 dante cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1894 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON);
1895 1.1 dante }
1896 1.1 dante
1897 1.1 dante
1898 1.9 dante u_int8_t
1899 1.15 lukem AscGetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t bus_type)
1900 1.1 dante {
1901 1.1 dante u_int16_t cfg_lsw;
1902 1.1 dante u_int8_t chip_irq;
1903 1.1 dante
1904 1.1 dante
1905 1.15 lukem #if 0
1906 1.15 lukem if (bus_type & ASC_IS_EISA) {
1907 1.9 dante cfg_lsw = AscGetEisaChipCfg(iot, ioh);
1908 1.9 dante chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
1909 1.9 dante if((chip_irq == 13) || (chip_irq > 15))
1910 1.9 dante return (0);
1911 1.9 dante return(chip_irq);
1912 1.1 dante }
1913 1.15 lukem #endif
1914 1.15 lukem if ((bus_type & ASC_IS_VL) != 0) {
1915 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1916 1.1 dante chip_irq = (cfg_lsw >> 2) & 0x07;
1917 1.1 dante if ((chip_irq == 0) ||
1918 1.1 dante (chip_irq == 4) ||
1919 1.1 dante (chip_irq == 7)) {
1920 1.1 dante return (0);
1921 1.1 dante }
1922 1.1 dante return (chip_irq + (ASC_MIN_IRQ_NO - 1));
1923 1.1 dante }
1924 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1925 1.1 dante chip_irq = (cfg_lsw >> 2) & 0x03;
1926 1.1 dante if (chip_irq == 3)
1927 1.1 dante chip_irq += 2;
1928 1.1 dante return (chip_irq + ASC_MIN_IRQ_NO);
1929 1.1 dante }
1930 1.1 dante
1931 1.1 dante
1932 1.1 dante static u_int8_t
1933 1.15 lukem AscSetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh,
1934 1.15 lukem u_int8_t irq_no, u_int16_t bus_type)
1935 1.1 dante {
1936 1.1 dante u_int16_t cfg_lsw;
1937 1.1 dante
1938 1.1 dante
1939 1.1 dante if (bus_type & ASC_IS_VL) {
1940 1.2 thorpej if (irq_no) {
1941 1.1 dante if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO))
1942 1.1 dante irq_no = 0;
1943 1.1 dante else
1944 1.1 dante irq_no -= ASC_MIN_IRQ_NO - 1;
1945 1.2 thorpej }
1946 1.1 dante
1947 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3;
1948 1.1 dante cfg_lsw |= 0x0010;
1949 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
1950 1.1 dante AscToggleIRQAct(iot, ioh);
1951 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0;
1952 1.1 dante cfg_lsw |= (irq_no & 0x07) << 2;
1953 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
1954 1.1 dante AscToggleIRQAct(iot, ioh);
1955 1.1 dante
1956 1.1 dante return (AscGetChipIRQ(iot, ioh, bus_type));
1957 1.1 dante }
1958 1.1 dante if (bus_type & ASC_IS_ISA) {
1959 1.1 dante if (irq_no == 15)
1960 1.1 dante irq_no -= 2;
1961 1.1 dante irq_no -= ASC_MIN_IRQ_NO;
1962 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3;
1963 1.1 dante cfg_lsw |= (irq_no & 0x03) << 2;
1964 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
1965 1.1 dante
1966 1.1 dante return (AscGetChipIRQ(iot, ioh, bus_type));
1967 1.1 dante }
1968 1.1 dante return (0);
1969 1.1 dante }
1970 1.1 dante
1971 1.1 dante
1972 1.1 dante static void
1973 1.15 lukem AscAckInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh)
1974 1.1 dante {
1975 1.1 dante u_int8_t host_flag;
1976 1.1 dante u_int8_t risc_flag;
1977 1.1 dante u_int16_t loop;
1978 1.1 dante
1979 1.1 dante
1980 1.1 dante loop = 0;
1981 1.1 dante do {
1982 1.1 dante risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B);
1983 1.1 dante if (loop++ > 0x7FFF)
1984 1.1 dante break;
1985 1.1 dante } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
1986 1.1 dante
1987 1.1 dante host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) &
1988 1.1 dante (~ASC_HOST_FLAG_ACK_INT);
1989 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B,
1990 1.1 dante host_flag | ASC_HOST_FLAG_ACK_INT);
1991 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK);
1992 1.1 dante
1993 1.1 dante loop = 0;
1994 1.1 dante while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) {
1995 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK);
1996 1.1 dante if (loop++ > 3)
1997 1.1 dante break;
1998 1.1 dante }
1999 1.1 dante
2000 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag);
2001 1.1 dante }
2002 1.1 dante
2003 1.1 dante
2004 1.1 dante static u_int32_t
2005 1.15 lukem AscGetMaxDmaCount(u_int16_t bus_type)
2006 1.1 dante {
2007 1.1 dante if (bus_type & ASC_IS_ISA)
2008 1.1 dante return (ASC_MAX_ISA_DMA_COUNT);
2009 1.1 dante else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
2010 1.1 dante return (ASC_MAX_VL_DMA_COUNT);
2011 1.1 dante return (ASC_MAX_PCI_DMA_COUNT);
2012 1.1 dante }
2013 1.1 dante
2014 1.1 dante
2015 1.9 dante u_int16_t
2016 1.15 lukem AscGetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh)
2017 1.1 dante {
2018 1.1 dante u_int16_t channel;
2019 1.1 dante
2020 1.1 dante channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003;
2021 1.1 dante if (channel == 0x03)
2022 1.1 dante return (0);
2023 1.1 dante else if (channel == 0x00)
2024 1.1 dante return (7);
2025 1.1 dante return (channel + 4);
2026 1.1 dante }
2027 1.1 dante
2028 1.1 dante
2029 1.1 dante static u_int16_t
2030 1.15 lukem AscSetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh,
2031 1.15 lukem u_int16_t dma_channel)
2032 1.1 dante {
2033 1.1 dante u_int16_t cfg_lsw;
2034 1.1 dante u_int8_t value;
2035 1.1 dante
2036 1.1 dante if ((dma_channel >= 5) && (dma_channel <= 7)) {
2037 1.1 dante if (dma_channel == 7)
2038 1.1 dante value = 0x00;
2039 1.1 dante else
2040 1.1 dante value = dma_channel - 4;
2041 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC;
2042 1.1 dante cfg_lsw |= value;
2043 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
2044 1.1 dante return (AscGetIsaDmaChannel(iot, ioh));
2045 1.1 dante }
2046 1.1 dante return (0);
2047 1.1 dante }
2048 1.1 dante
2049 1.1 dante
2050 1.1 dante static u_int8_t
2051 1.15 lukem AscGetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh)
2052 1.1 dante {
2053 1.1 dante u_int8_t speed_value;
2054 1.1 dante
2055 1.1 dante AscSetBank(iot, ioh, 1);
2056 1.1 dante speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh);
2057 1.1 dante speed_value &= 0x07;
2058 1.1 dante AscSetBank(iot, ioh, 0);
2059 1.1 dante return (speed_value);
2060 1.1 dante }
2061 1.1 dante
2062 1.1 dante
2063 1.1 dante static u_int8_t
2064 1.15 lukem AscSetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh,
2065 1.15 lukem u_int8_t speed_value)
2066 1.1 dante {
2067 1.1 dante speed_value &= 0x07;
2068 1.1 dante AscSetBank(iot, ioh, 1);
2069 1.1 dante ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value);
2070 1.1 dante AscSetBank(iot, ioh, 0);
2071 1.1 dante return (AscGetIsaDmaSpeed(iot, ioh));
2072 1.1 dante }
2073 1.1 dante
2074 1.1 dante
2075 1.1 dante /******************************************************************************/
2076 1.1 dante /* Messages routines */
2077 1.1 dante /******************************************************************************/
2078 1.1 dante
2079 1.1 dante
2080 1.1 dante static void
2081 1.15 lukem AscHandleExtMsgIn(ASC_SOFTC *sc, u_int16_t halt_q_addr, u_int8_t q_cntl,
2082 1.15 lukem ASC_SCSI_BIT_ID_TYPE target_id, int tid_no, u_int8_t asyn_sdtr)
2083 1.1 dante {
2084 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2085 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2086 1.1 dante EXT_MSG ext_msg;
2087 1.1 dante u_int8_t sdtr_data;
2088 1.1 dante int sdtr_accept;
2089 1.1 dante
2090 1.1 dante
2091 1.1 dante AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG,
2092 1.1 dante (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
2093 1.1 dante
2094 1.1 dante if (ext_msg.msg_type == MS_EXTEND &&
2095 1.1 dante ext_msg.msg_req == MS_SDTR_CODE &&
2096 1.1 dante ext_msg.msg_len == MS_SDTR_LEN) {
2097 1.1 dante sdtr_accept = TRUE;
2098 1.1 dante
2099 1.1 dante if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) {
2100 1.1 dante sdtr_accept = FALSE;
2101 1.1 dante ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
2102 1.1 dante }
2103 1.1 dante if ((ext_msg.xfer_period <
2104 1.1 dante sc->sdtr_period_tbl[sc->host_init_sdtr_index]) ||
2105 1.1 dante (ext_msg.xfer_period >
2106 1.1 dante sc->sdtr_period_tbl[sc->max_sdtr_index])) {
2107 1.1 dante sdtr_accept = FALSE;
2108 1.1 dante ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index];
2109 1.1 dante }
2110 1.1 dante if (sdtr_accept) {
2111 1.1 dante sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
2112 1.1 dante ext_msg.req_ack_offset);
2113 1.1 dante if (sdtr_data == 0xFF) {
2114 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2115 1.1 dante sc->init_sdtr &= ~target_id;
2116 1.1 dante sc->sdtr_done &= ~target_id;
2117 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
2118 1.1 dante sc->sdtr_data[tid_no] = asyn_sdtr;
2119 1.1 dante }
2120 1.1 dante }
2121 1.1 dante if (ext_msg.req_ack_offset == 0) {
2122 1.1 dante q_cntl &= ~ASC_QC_MSG_OUT;
2123 1.1 dante sc->init_sdtr &= ~target_id;
2124 1.1 dante sc->sdtr_done &= ~target_id;
2125 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
2126 1.1 dante } else {
2127 1.1 dante if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) {
2128 1.1 dante q_cntl &= ~ASC_QC_MSG_OUT;
2129 1.1 dante sc->sdtr_done |= target_id;
2130 1.1 dante sc->init_sdtr |= target_id;
2131 1.1 dante sc->pci_fix_asyn_xfer &= ~target_id;
2132 1.1 dante sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
2133 1.1 dante ext_msg.req_ack_offset);
2134 1.1 dante AscSetChipSDTR(iot, ioh, sdtr_data, tid_no);
2135 1.1 dante sc->sdtr_data[tid_no] = sdtr_data;
2136 1.1 dante } else {
2137 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2138 1.1 dante AscMsgOutSDTR(sc, ext_msg.xfer_period,
2139 1.1 dante ext_msg.req_ack_offset);
2140 1.1 dante sc->pci_fix_asyn_xfer &= ~target_id;
2141 1.1 dante sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
2142 1.1 dante ext_msg.req_ack_offset);
2143 1.1 dante AscSetChipSDTR(iot, ioh, sdtr_data, tid_no);
2144 1.1 dante sc->sdtr_data[tid_no] = sdtr_data;
2145 1.1 dante sc->sdtr_done |= target_id;
2146 1.1 dante sc->init_sdtr |= target_id;
2147 1.1 dante }
2148 1.1 dante }
2149 1.1 dante } else if (ext_msg.msg_type == MS_EXTEND &&
2150 1.1 dante ext_msg.msg_req == MS_WDTR_CODE &&
2151 1.1 dante ext_msg.msg_len == MS_WDTR_LEN) {
2152 1.1 dante ext_msg.wdtr_width = 0;
2153 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2154 1.21 christos (const u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
2155 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2156 1.1 dante } else {
2157 1.1 dante ext_msg.msg_type = M1_MSG_REJECT;
2158 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2159 1.21 christos (const u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
2160 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2161 1.1 dante }
2162 1.1 dante
2163 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
2164 1.1 dante }
2165 1.1 dante
2166 1.1 dante
2167 1.1 dante static u_int8_t
2168 1.15 lukem AscMsgOutSDTR(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t sdtr_offset)
2169 1.1 dante {
2170 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2171 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2172 1.1 dante EXT_MSG sdtr_buf;
2173 1.1 dante u_int8_t sdtr_period_index;
2174 1.1 dante
2175 1.1 dante
2176 1.1 dante sdtr_buf.msg_type = MS_EXTEND;
2177 1.1 dante sdtr_buf.msg_len = MS_SDTR_LEN;
2178 1.1 dante sdtr_buf.msg_req = MS_SDTR_CODE;
2179 1.1 dante sdtr_buf.xfer_period = sdtr_period;
2180 1.1 dante sdtr_offset &= ASC_SYN_MAX_OFFSET;
2181 1.1 dante sdtr_buf.req_ack_offset = sdtr_offset;
2182 1.1 dante if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <=
2183 1.1 dante sc->max_sdtr_index) {
2184 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2185 1.21 christos (const u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1);
2186 1.1 dante return ((sdtr_period_index << 4) | sdtr_offset);
2187 1.1 dante } else {
2188 1.1 dante sdtr_buf.req_ack_offset = 0;
2189 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2190 1.21 christos (const u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1);
2191 1.1 dante return (0);
2192 1.1 dante }
2193 1.1 dante }
2194 1.1 dante
2195 1.1 dante
2196 1.1 dante /******************************************************************************/
2197 1.1 dante /* SDTR routines */
2198 1.1 dante /******************************************************************************/
2199 1.1 dante
2200 1.1 dante
2201 1.1 dante static void
2202 1.15 lukem AscSetChipSDTR(bus_space_tag_t iot, bus_space_handle_t ioh,
2203 1.15 lukem u_int8_t sdtr_data, u_int8_t tid_no)
2204 1.1 dante {
2205 1.4 dante AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data);
2206 1.1 dante AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data);
2207 1.1 dante }
2208 1.1 dante
2209 1.1 dante
2210 1.1 dante static u_int8_t
2211 1.15 lukem AscCalSDTRData(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t syn_offset)
2212 1.1 dante {
2213 1.1 dante u_int8_t byte;
2214 1.1 dante u_int8_t sdtr_period_ix;
2215 1.1 dante
2216 1.1 dante sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period);
2217 1.1 dante if (sdtr_period_ix > sc->max_sdtr_index)
2218 1.1 dante return (0xFF);
2219 1.1 dante
2220 1.1 dante byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
2221 1.1 dante return (byte);
2222 1.1 dante }
2223 1.1 dante
2224 1.1 dante
2225 1.1 dante static u_int8_t
2226 1.15 lukem AscGetSynPeriodIndex(ASC_SOFTC *sc, u_int8_t syn_time)
2227 1.1 dante {
2228 1.1 dante u_int8_t *period_table;
2229 1.1 dante int max_index;
2230 1.1 dante int min_index;
2231 1.1 dante int i;
2232 1.1 dante
2233 1.1 dante period_table = sc->sdtr_period_tbl;
2234 1.1 dante max_index = sc->max_sdtr_index;
2235 1.1 dante min_index = sc->host_init_sdtr_index;
2236 1.1 dante if ((syn_time <= period_table[max_index])) {
2237 1.1 dante for (i = min_index; i < (max_index - 1); i++) {
2238 1.1 dante if (syn_time <= period_table[i])
2239 1.1 dante return (i);
2240 1.1 dante }
2241 1.1 dante
2242 1.1 dante return (max_index);
2243 1.1 dante } else
2244 1.1 dante return (max_index + 1);
2245 1.1 dante }
2246 1.1 dante
2247 1.1 dante
2248 1.1 dante /******************************************************************************/
2249 1.1 dante /* Queue routines */
2250 1.1 dante /******************************************************************************/
2251 1.1 dante
2252 1.1 dante /*
2253 1.1 dante * Send a command to the board
2254 1.1 dante */
2255 1.1 dante int
2256 1.15 lukem AscExeScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq)
2257 1.1 dante {
2258 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2259 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2260 1.1 dante ASC_SG_HEAD *sg_head = scsiq->sg_head;
2261 1.1 dante int retval;
2262 1.1 dante int n_q_required;
2263 1.1 dante int disable_syn_offset_one_fix;
2264 1.1 dante int i;
2265 1.1 dante u_int32_t addr;
2266 1.1 dante u_int16_t sg_entry_cnt = 0;
2267 1.1 dante u_int16_t sg_entry_cnt_minus_one = 0;
2268 1.1 dante u_int8_t target_ix;
2269 1.1 dante u_int8_t tid_no;
2270 1.1 dante u_int8_t sdtr_data;
2271 1.1 dante u_int8_t extra_bytes;
2272 1.1 dante u_int8_t scsi_cmd;
2273 1.1 dante u_int32_t data_cnt;
2274 1.1 dante
2275 1.1 dante
2276 1.1 dante scsiq->q1.q_no = 0;
2277 1.1 dante if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)
2278 1.1 dante scsiq->q1.extra_bytes = 0;
2279 1.1 dante
2280 1.1 dante retval = ASC_BUSY;
2281 1.1 dante target_ix = scsiq->q2.target_ix;
2282 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
2283 1.1 dante n_q_required = 1;
2284 1.1 dante
2285 1.1 dante if (scsiq->cdbptr[0] == SCSICMD_RequestSense)
2286 1.1 dante if ((sc->init_sdtr & scsiq->q1.target_id) != 0) {
2287 1.1 dante sc->sdtr_done &= ~scsiq->q1.target_id;
2288 1.1 dante sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
2289 1.1 dante AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) &
2290 1.1 dante (sc->max_sdtr_index - 1)],
2291 1.1 dante sdtr_data & ASC_SYN_MAX_OFFSET);
2292 1.1 dante scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT);
2293 1.1 dante }
2294 1.1 dante /*
2295 1.1 dante * if there is just one segment into S/G list then
2296 1.1 dante * map it as it was a single request, filling
2297 1.1 dante * data_addr and data_cnt of ASC_SCSIQ structure.
2298 1.1 dante */
2299 1.1 dante if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
2300 1.1 dante sg_entry_cnt = sg_head->entry_cnt;
2301 1.1 dante
2302 1.1 dante if (sg_entry_cnt < 1)
2303 1.1 dante panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.",
2304 1.1 dante sg_entry_cnt);
2305 1.1 dante
2306 1.1 dante if (sg_entry_cnt > ASC_MAX_SG_LIST)
2307 1.1 dante panic("AscExeScsiQueue: Queue with too many segs.");
2308 1.1 dante
2309 1.1 dante if (sg_entry_cnt == 1) {
2310 1.1 dante scsiq->q1.data_addr = sg_head->sg_list[0].addr;
2311 1.1 dante scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
2312 1.1 dante scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE);
2313 1.1 dante }
2314 1.1 dante sg_entry_cnt_minus_one = sg_entry_cnt - 1;
2315 1.1 dante }
2316 1.1 dante scsi_cmd = scsiq->cdbptr[0];
2317 1.1 dante disable_syn_offset_one_fix = FALSE;
2318 1.1 dante if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
2319 1.1 dante !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
2320 1.1 dante if (scsiq->q1.cntl & ASC_QC_SG_HEAD) {
2321 1.1 dante data_cnt = 0;
2322 1.1 dante for (i = 0; i < sg_entry_cnt; i++)
2323 1.1 dante data_cnt += sg_head->sg_list[i].bytes;
2324 1.1 dante } else {
2325 1.1 dante data_cnt = scsiq->q1.data_cnt;
2326 1.1 dante }
2327 1.1 dante
2328 1.1 dante if (data_cnt != 0ul) {
2329 1.1 dante if (data_cnt < 512ul) {
2330 1.1 dante disable_syn_offset_one_fix = TRUE;
2331 1.1 dante } else {
2332 1.1 dante if (scsi_cmd == SCSICMD_Inquiry ||
2333 1.1 dante scsi_cmd == SCSICMD_RequestSense ||
2334 1.1 dante scsi_cmd == SCSICMD_ReadCapacity ||
2335 1.1 dante scsi_cmd == SCSICMD_ReadTOC ||
2336 1.1 dante scsi_cmd == SCSICMD_ModeSelect6 ||
2337 1.1 dante scsi_cmd == SCSICMD_ModeSense6 ||
2338 1.1 dante scsi_cmd == SCSICMD_ModeSelect10 ||
2339 1.1 dante scsi_cmd == SCSICMD_ModeSense10) {
2340 1.1 dante disable_syn_offset_one_fix = TRUE;
2341 1.1 dante }
2342 1.1 dante }
2343 1.1 dante }
2344 1.1 dante }
2345 1.1 dante if (disable_syn_offset_one_fix) {
2346 1.1 dante scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE;
2347 1.1 dante scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
2348 1.1 dante ASC_TAG_FLAG_DISABLE_DISCONNECT);
2349 1.1 dante } else {
2350 1.1 dante scsiq->q2.tag_code &= 0x23;
2351 1.1 dante }
2352 1.1 dante
2353 1.1 dante if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
2354 1.1 dante if (sc->bug_fix_cntl) {
2355 1.1 dante if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
2356 1.1 dante if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) {
2357 1.1 dante addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr +
2358 1.1 dante sg_head->sg_list[sg_entry_cnt_minus_one].bytes;
2359 1.1 dante extra_bytes = addr & 0x0003;
2360 1.1 dante if ((extra_bytes != 0) &&
2361 1.1 dante ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) {
2362 1.1 dante scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
2363 1.1 dante scsiq->q1.extra_bytes = extra_bytes;
2364 1.1 dante sg_head->sg_list[sg_entry_cnt_minus_one].bytes -=
2365 1.1 dante extra_bytes;
2366 1.1 dante }
2367 1.1 dante }
2368 1.1 dante }
2369 1.1 dante }
2370 1.1 dante sg_head->entry_to_copy = sg_head->entry_cnt;
2371 1.1 dante n_q_required = AscSgListToQueue(sg_entry_cnt);
2372 1.1 dante if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required)
2373 1.1 dante || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) {
2374 1.1 dante retval = AscSendScsiQueue(sc, scsiq, n_q_required);
2375 1.1 dante }
2376 1.1 dante } else {
2377 1.1 dante if (sc->bug_fix_cntl) {
2378 1.1 dante if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
2379 1.1 dante if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) {
2380 1.1 dante addr = scsiq->q1.data_addr + scsiq->q1.data_cnt;
2381 1.1 dante extra_bytes = addr & 0x0003;
2382 1.1 dante if ((extra_bytes != 0) &&
2383 1.1 dante ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) {
2384 1.1 dante if ((scsiq->q1.data_cnt & 0x01FF) == 0) {
2385 1.1 dante scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
2386 1.1 dante scsiq->q1.data_cnt -= extra_bytes;
2387 1.1 dante scsiq->q1.extra_bytes = extra_bytes;
2388 1.1 dante }
2389 1.1 dante }
2390 1.1 dante }
2391 1.1 dante }
2392 1.1 dante }
2393 1.1 dante n_q_required = 1;
2394 1.1 dante if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) ||
2395 1.1 dante ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) {
2396 1.1 dante retval = AscSendScsiQueue(sc, scsiq, n_q_required);
2397 1.1 dante }
2398 1.1 dante }
2399 1.1 dante
2400 1.1 dante return (retval);
2401 1.1 dante }
2402 1.1 dante
2403 1.1 dante
2404 1.1 dante static int
2405 1.15 lukem AscSendScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t n_q_required)
2406 1.1 dante {
2407 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2408 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2409 1.1 dante u_int8_t free_q_head;
2410 1.1 dante u_int8_t next_qp;
2411 1.1 dante u_int8_t tid_no;
2412 1.1 dante u_int8_t target_ix;
2413 1.1 dante int retval;
2414 1.1 dante
2415 1.1 dante
2416 1.1 dante target_ix = scsiq->q2.target_ix;
2417 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
2418 1.1 dante retval = ASC_BUSY;
2419 1.1 dante free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh);
2420 1.1 dante
2421 1.1 dante if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required))
2422 1.1 dante != ASC_QLINK_END) {
2423 1.1 dante if (n_q_required > 1) {
2424 1.1 dante sc->last_q_shortage = 0;
2425 1.1 dante scsiq->sg_head->queue_cnt = n_q_required - 1;
2426 1.1 dante }
2427 1.1 dante scsiq->q1.q_no = free_q_head;
2428 1.1 dante
2429 1.1 dante if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) {
2430 1.1 dante ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp);
2431 1.1 dante sc->cur_total_qng += n_q_required;
2432 1.1 dante sc->cur_dvc_qng[tid_no]++;
2433 1.1 dante }
2434 1.1 dante }
2435 1.1 dante return (retval);
2436 1.1 dante }
2437 1.1 dante
2438 1.1 dante
2439 1.1 dante static int
2440 1.15 lukem AscPutReadySgListQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no)
2441 1.1 dante {
2442 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2443 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2444 1.1 dante int retval;
2445 1.1 dante int i;
2446 1.1 dante ASC_SG_HEAD *sg_head;
2447 1.1 dante ASC_SG_LIST_Q scsi_sg_q;
2448 1.1 dante u_int32_t saved_data_addr;
2449 1.1 dante u_int32_t saved_data_cnt;
2450 1.1 dante u_int16_t sg_list_dwords;
2451 1.1 dante u_int16_t sg_index;
2452 1.1 dante u_int16_t sg_entry_cnt;
2453 1.1 dante u_int16_t q_addr;
2454 1.1 dante u_int8_t next_qp;
2455 1.1 dante
2456 1.1 dante
2457 1.1 dante saved_data_addr = scsiq->q1.data_addr;
2458 1.1 dante saved_data_cnt = scsiq->q1.data_cnt;
2459 1.1 dante
2460 1.1 dante if ((sg_head = scsiq->sg_head) != 0) {
2461 1.1 dante scsiq->q1.data_addr = sg_head->sg_list[0].addr;
2462 1.1 dante scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
2463 1.1 dante sg_entry_cnt = sg_head->entry_cnt - 1;
2464 1.1 dante if (sg_entry_cnt != 0) {
2465 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2466 1.1 dante sg_index = 1;
2467 1.1 dante scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
2468 1.1 dante scsi_sg_q.sg_head_qp = q_no;
2469 1.1 dante scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST;
2470 1.1 dante
2471 1.1 dante for (i = 0; i < sg_head->queue_cnt; i++) {
2472 1.1 dante scsi_sg_q.seq_no = i + 1;
2473 1.1 dante if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
2474 1.1 dante sg_list_dwords = ASC_SG_LIST_PER_Q * 2;
2475 1.1 dante sg_entry_cnt -= ASC_SG_LIST_PER_Q;
2476 1.1 dante if (i == 0) {
2477 1.1 dante scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
2478 1.1 dante scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
2479 1.1 dante } else {
2480 1.1 dante scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
2481 1.1 dante scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
2482 1.1 dante }
2483 1.1 dante } else {
2484 1.1 dante scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END;
2485 1.1 dante sg_list_dwords = sg_entry_cnt << 1;
2486 1.1 dante if (i == 0) {
2487 1.1 dante scsi_sg_q.sg_list_cnt = sg_entry_cnt;
2488 1.1 dante scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
2489 1.1 dante } else {
2490 1.1 dante scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
2491 1.1 dante scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
2492 1.1 dante }
2493 1.1 dante
2494 1.1 dante sg_entry_cnt = 0;
2495 1.1 dante }
2496 1.1 dante
2497 1.1 dante next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD);
2498 1.1 dante scsi_sg_q.q_no = next_qp;
2499 1.1 dante q_addr = ASC_QNO_TO_QADDR(next_qp);
2500 1.1 dante
2501 1.1 dante /*
2502 1.1 dante * Tell the board how many entries are in the S/G list
2503 1.1 dante */
2504 1.1 dante AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
2505 1.21 christos (const u_int16_t *) & scsi_sg_q,
2506 1.7 dante sizeof(ASC_SG_LIST_Q) >> 1);
2507 1.1 dante /*
2508 1.1 dante * Tell the board the addresses of the S/G list segments
2509 1.1 dante */
2510 1.1 dante AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG,
2511 1.7 dante (u_int32_t *) & sg_head->sg_list[sg_index],
2512 1.7 dante sg_list_dwords);
2513 1.1 dante sg_index += ASC_SG_LIST_PER_Q;
2514 1.1 dante }
2515 1.1 dante }
2516 1.1 dante }
2517 1.1 dante retval = AscPutReadyQueue(sc, scsiq, q_no);
2518 1.1 dante scsiq->q1.data_addr = saved_data_addr;
2519 1.1 dante scsiq->q1.data_cnt = saved_data_cnt;
2520 1.1 dante return (retval);
2521 1.1 dante }
2522 1.1 dante
2523 1.1 dante
2524 1.1 dante static int
2525 1.15 lukem AscPutReadyQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no)
2526 1.1 dante {
2527 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2528 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2529 1.1 dante u_int16_t q_addr;
2530 1.1 dante u_int8_t tid_no;
2531 1.1 dante u_int8_t sdtr_data;
2532 1.1 dante u_int8_t syn_period_ix;
2533 1.1 dante u_int8_t syn_offset;
2534 1.1 dante
2535 1.1 dante
2536 1.1 dante if (((sc->init_sdtr & scsiq->q1.target_id) != 0) &&
2537 1.1 dante ((sc->sdtr_done & scsiq->q1.target_id) == 0)) {
2538 1.1 dante tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
2539 1.1 dante sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
2540 1.1 dante syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1);
2541 1.1 dante syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
2542 1.1 dante AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset);
2543 1.1 dante scsiq->q1.cntl |= ASC_QC_MSG_OUT;
2544 1.1 dante }
2545 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2546 1.1 dante
2547 1.1 dante if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) {
2548 1.1 dante scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE;
2549 1.1 dante }
2550 1.1 dante scsiq->q1.status = ASC_QS_FREE;
2551 1.1 dante AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG,
2552 1.21 christos (const u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
2553 1.1 dante
2554 1.7 dante AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq);
2555 1.1 dante
2556 1.1 dante /*
2557 1.1 dante * Let's start the command
2558 1.1 dante */
2559 1.1 dante AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
2560 1.1 dante (scsiq->q1.q_no << 8) | ASC_QS_READY);
2561 1.1 dante
2562 1.1 dante return (ASC_NOERROR);
2563 1.1 dante }
2564 1.1 dante
2565 1.1 dante
2566 1.7 dante static void
2567 1.15 lukem AscPutSCSIQ(bus_space_tag_t iot, bus_space_handle_t ioh,
2568 1.15 lukem u_int16_t addr, ASC_SCSI_Q *scsiq)
2569 1.7 dante {
2570 1.7 dante u_int16_t val;
2571 1.7 dante
2572 1.7 dante
2573 1.7 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
2574 1.7 dante
2575 1.7 dante /* ASC_SCSIQ_1 */
2576 1.7 dante val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt);
2577 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2578 1.7 dante val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun);
2579 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2580 1.7 dante val = LO_WORD(scsiq->q1.data_addr);
2581 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2582 1.7 dante val = HI_WORD(scsiq->q1.data_addr);
2583 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2584 1.7 dante val = LO_WORD(scsiq->q1.data_cnt);
2585 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2586 1.7 dante val = HI_WORD(scsiq->q1.data_cnt);
2587 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2588 1.7 dante val = LO_WORD(scsiq->q1.sense_addr);
2589 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2590 1.7 dante val = HI_WORD(scsiq->q1.sense_addr);
2591 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2592 1.7 dante val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes);
2593 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2594 1.7 dante
2595 1.7 dante /* ASC_SCSIQ_2 */
2596 1.7 dante val = LO_WORD(scsiq->q2.ccb_ptr);
2597 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2598 1.7 dante val = HI_WORD(scsiq->q2.ccb_ptr);
2599 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2600 1.7 dante val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag);
2601 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2602 1.7 dante val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code);
2603 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2604 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id);
2605 1.7 dante }
2606 1.7 dante
2607 1.7 dante
2608 1.1 dante static int
2609 1.15 lukem AscSgListToQueue(int sg_list)
2610 1.1 dante {
2611 1.1 dante int n_sg_list_qs;
2612 1.1 dante
2613 1.1 dante n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
2614 1.1 dante if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
2615 1.1 dante n_sg_list_qs++;
2616 1.1 dante
2617 1.1 dante return (n_sg_list_qs + 1);
2618 1.1 dante }
2619 1.1 dante
2620 1.1 dante
2621 1.1 dante static u_int
2622 1.25 christos AscGetNumOfFreeQueue(ASC_SOFTC *sc, u_int8_t target_ix, u_int8_t n_qs)
2623 1.1 dante {
2624 1.1 dante u_int cur_used_qs;
2625 1.1 dante u_int cur_free_qs;
2626 1.1 dante
2627 1.1 dante
2628 1.1 dante if (n_qs == 1) {
2629 1.1 dante cur_used_qs = sc->cur_total_qng +
2630 1.1 dante sc->last_q_shortage +
2631 1.1 dante ASC_MIN_FREE_Q;
2632 1.1 dante } else {
2633 1.1 dante cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q;
2634 1.1 dante }
2635 1.1 dante
2636 1.1 dante if ((cur_used_qs + n_qs) <= sc->max_total_qng) {
2637 1.1 dante cur_free_qs = sc->max_total_qng - cur_used_qs;
2638 1.1 dante return (cur_free_qs);
2639 1.1 dante }
2640 1.1 dante if (n_qs > 1)
2641 1.1 dante if ((n_qs > sc->last_q_shortage) &&
2642 1.1 dante (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) {
2643 1.1 dante sc->last_q_shortage = n_qs;
2644 1.1 dante }
2645 1.1 dante return (0);
2646 1.1 dante }
2647 1.1 dante
2648 1.1 dante
2649 1.1 dante static u_int8_t
2650 1.15 lukem AscAllocFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh,
2651 1.15 lukem u_int8_t free_q_head)
2652 1.1 dante {
2653 1.1 dante u_int16_t q_addr;
2654 1.1 dante u_int8_t next_qp;
2655 1.1 dante u_int8_t q_status;
2656 1.1 dante
2657 1.1 dante
2658 1.1 dante q_addr = ASC_QNO_TO_QADDR(free_q_head);
2659 1.1 dante q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
2660 1.1 dante next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD);
2661 1.1 dante if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END))
2662 1.1 dante return (next_qp);
2663 1.1 dante
2664 1.1 dante return (ASC_QLINK_END);
2665 1.1 dante }
2666 1.1 dante
2667 1.1 dante
2668 1.1 dante static u_int8_t
2669 1.15 lukem AscAllocMultipleFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh,
2670 1.15 lukem u_int8_t free_q_head, u_int8_t n_free_q)
2671 1.1 dante {
2672 1.1 dante u_int8_t i;
2673 1.1 dante
2674 1.1 dante for (i = 0; i < n_free_q; i++) {
2675 1.1 dante free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head);
2676 1.1 dante if (free_q_head == ASC_QLINK_END)
2677 1.1 dante break;
2678 1.1 dante }
2679 1.1 dante
2680 1.1 dante return (free_q_head);
2681 1.1 dante }
2682 1.1 dante
2683 1.1 dante
2684 1.1 dante static int
2685 1.15 lukem AscStopQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh)
2686 1.1 dante {
2687 1.1 dante int count = 0;
2688 1.1 dante
2689 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) {
2690 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP);
2691 1.1 dante do {
2692 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) &
2693 1.1 dante ASC_STOP_ACK_RISC_STOP)
2694 1.1 dante return (1);
2695 1.1 dante
2696 1.1 dante DvcSleepMilliSecond(100);
2697 1.1 dante } while (count++ < 20);
2698 1.1 dante }
2699 1.1 dante return (0);
2700 1.1 dante }
2701 1.1 dante
2702 1.1 dante
2703 1.1 dante static void
2704 1.15 lukem AscStartQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh)
2705 1.1 dante {
2706 1.1 dante
2707 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0)
2708 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0);
2709 1.1 dante }
2710 1.1 dante
2711 1.1 dante
2712 1.1 dante static void
2713 1.15 lukem AscCleanUpBusyQueue(bus_space_tag_t iot, bus_space_handle_t ioh)
2714 1.1 dante {
2715 1.1 dante int count = 0;
2716 1.1 dante u_int8_t stop_code;
2717 1.1 dante
2718 1.1 dante
2719 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) {
2720 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q);
2721 1.1 dante do {
2722 1.1 dante stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
2723 1.1 dante if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0)
2724 1.1 dante break;
2725 1.1 dante
2726 1.1 dante DvcSleepMilliSecond(100);
2727 1.1 dante } while (count++ < 20);
2728 1.1 dante }
2729 1.1 dante }
2730 1.1 dante
2731 1.1 dante
2732 1.1 dante static int
2733 1.15 lukem _AscWaitQDone(bus_space_tag_t iot, bus_space_handle_t ioh, ASC_SCSI_Q *scsiq)
2734 1.1 dante {
2735 1.1 dante u_int16_t q_addr;
2736 1.1 dante u_int8_t q_status;
2737 1.1 dante int count = 0;
2738 1.1 dante
2739 1.1 dante while (scsiq->q1.q_no == 0);
2740 1.1 dante
2741 1.1 dante q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no);
2742 1.1 dante do {
2743 1.1 dante q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
2744 1.1 dante DvcSleepMilliSecond(100L);
2745 1.1 dante if (count++ > 30)
2746 1.1 dante return (0);
2747 1.1 dante
2748 1.1 dante } while ((q_status & ASC_QS_READY) != 0);
2749 1.1 dante
2750 1.1 dante return (1);
2751 1.1 dante }
2752 1.1 dante
2753 1.1 dante
2754 1.1 dante static int
2755 1.15 lukem AscCleanUpDiscQueue(bus_space_tag_t iot, bus_space_handle_t ioh)
2756 1.1 dante {
2757 1.1 dante int count;
2758 1.1 dante u_int8_t stop_code;
2759 1.1 dante
2760 1.1 dante count = 0;
2761 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) {
2762 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q);
2763 1.1 dante do {
2764 1.1 dante stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
2765 1.1 dante if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0)
2766 1.1 dante break;
2767 1.1 dante
2768 1.1 dante DvcSleepMilliSecond(100);
2769 1.1 dante } while (count++ < 20);
2770 1.1 dante }
2771 1.1 dante return (1);
2772 1.1 dante }
2773 1.1 dante
2774 1.1 dante
2775 1.1 dante /******************************************************************************/
2776 1.1 dante /* Abort and Reset CCB routines */
2777 1.1 dante /******************************************************************************/
2778 1.1 dante
2779 1.1 dante
2780 1.1 dante int
2781 1.15 lukem AscAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb)
2782 1.1 dante {
2783 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2784 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2785 1.1 dante int retval;
2786 1.1 dante ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready;
2787 1.1 dante
2788 1.1 dante
2789 1.1 dante retval = -1;
2790 1.1 dante saved_unit_not_ready = sc->unit_not_ready;
2791 1.1 dante sc->unit_not_ready = 0xFF;
2792 1.1 dante AscWaitISRDone(sc);
2793 1.1 dante if (AscStopQueueExe(iot, ioh) == 1) {
2794 1.1 dante if (AscRiscHaltedAbortCCB(sc, ccb) == 1) {
2795 1.1 dante retval = 1;
2796 1.1 dante AscCleanUpBusyQueue(iot, ioh);
2797 1.1 dante AscStartQueueExe(iot, ioh);
2798 1.1 dante } else {
2799 1.1 dante retval = 0;
2800 1.1 dante AscStartQueueExe(iot, ioh);
2801 1.1 dante }
2802 1.1 dante }
2803 1.1 dante sc->unit_not_ready = saved_unit_not_ready;
2804 1.1 dante
2805 1.1 dante return (retval);
2806 1.1 dante }
2807 1.1 dante
2808 1.1 dante
2809 1.1 dante static int
2810 1.15 lukem AscRiscHaltedAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb)
2811 1.1 dante {
2812 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2813 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2814 1.1 dante u_int16_t q_addr;
2815 1.1 dante u_int8_t q_no;
2816 1.1 dante ASC_QDONE_INFO scsiq_buf;
2817 1.1 dante ASC_QDONE_INFO *scsiq;
2818 1.1 dante int last_int_level;
2819 1.1 dante
2820 1.1 dante last_int_level = DvcEnterCritical();
2821 1.1 dante scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
2822 1.1 dante
2823 1.1 dante for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) {
2824 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2825 1.1 dante scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh,
2826 1.1 dante q_addr + ASC_SCSIQ_D_CCBPTR);
2827 1.8 dante if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) {
2828 1.1 dante _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count);
2829 1.1 dante if (((scsiq->q_status & ASC_QS_READY) != 0)
2830 1.1 dante && ((scsiq->q_status & ASC_QS_ABORTED) == 0)
2831 1.1 dante && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) {
2832 1.1 dante scsiq->q_status |= ASC_QS_ABORTED;
2833 1.1 dante scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST;
2834 1.1 dante AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L);
2835 1.1 dante AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
2836 1.1 dante scsiq->q_status);
2837 1.28 uwe (*sc->isr_callback)(sc, scsiq);
2838 1.1 dante return (1);
2839 1.1 dante }
2840 1.1 dante }
2841 1.1 dante }
2842 1.1 dante
2843 1.1 dante DvcLeaveCritical(last_int_level);
2844 1.1 dante return (0);
2845 1.1 dante }
2846 1.1 dante
2847 1.1 dante
2848 1.1 dante static int
2849 1.15 lukem AscRiscHaltedAbortTIX(ASC_SOFTC *sc, u_int8_t target_ix)
2850 1.1 dante {
2851 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2852 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2853 1.1 dante u_int16_t q_addr;
2854 1.1 dante u_int8_t q_no;
2855 1.1 dante ASC_QDONE_INFO scsiq_buf;
2856 1.1 dante ASC_QDONE_INFO *scsiq;
2857 1.1 dante int last_int_level;
2858 1.1 dante
2859 1.1 dante last_int_level = DvcEnterCritical();
2860 1.1 dante scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
2861 1.1 dante for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) {
2862 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2863 1.1 dante _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count);
2864 1.1 dante if (((scsiq->q_status & ASC_QS_READY) != 0) &&
2865 1.1 dante ((scsiq->q_status & ASC_QS_ABORTED) == 0) &&
2866 1.1 dante ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) {
2867 1.1 dante if (scsiq->d2.target_ix == target_ix) {
2868 1.1 dante scsiq->q_status |= ASC_QS_ABORTED;
2869 1.1 dante scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST;
2870 1.1 dante AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L);
2871 1.1 dante AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
2872 1.1 dante scsiq->q_status);
2873 1.28 uwe (*sc->isr_callback)(sc, scsiq);
2874 1.1 dante }
2875 1.1 dante }
2876 1.1 dante }
2877 1.1 dante DvcLeaveCritical(last_int_level);
2878 1.1 dante return (1);
2879 1.1 dante }
2880 1.1 dante
2881 1.1 dante
2882 1.1 dante /*
2883 1.1 dante * AscResetDevice calls _AscWaitQDone which requires interrupt enabled,
2884 1.1 dante * so we cannot use this function with the actual NetBSD SCSI layer
2885 1.1 dante * because at boot time interrupts are disabled.
2886 1.1 dante */
2887 1.1 dante int
2888 1.15 lukem AscResetDevice(ASC_SOFTC *sc, u_char target_ix)
2889 1.1 dante {
2890 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2891 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2892 1.1 dante int retval;
2893 1.1 dante u_int8_t tid_no;
2894 1.1 dante ASC_SCSI_BIT_ID_TYPE target_id;
2895 1.1 dante int i;
2896 1.1 dante ASC_SCSI_REQ_Q scsiq_buf;
2897 1.1 dante ASC_SCSI_REQ_Q *scsiq;
2898 1.1 dante u_int8_t *buf;
2899 1.1 dante ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready;
2900 1.1 dante
2901 1.1 dante
2902 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
2903 1.1 dante target_id = ASC_TID_TO_TARGET_ID(tid_no);
2904 1.1 dante saved_unit_not_ready = sc->unit_not_ready;
2905 1.1 dante sc->unit_not_ready = target_id;
2906 1.1 dante retval = ASC_ERROR;
2907 1.1 dante
2908 1.1 dante AscWaitTixISRDone(sc, target_ix);
2909 1.1 dante
2910 1.1 dante if (AscStopQueueExe(iot, ioh) == 1) {
2911 1.1 dante if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) {
2912 1.1 dante AscCleanUpBusyQueue(iot, ioh);
2913 1.1 dante AscStartQueueExe(iot, ioh);
2914 1.1 dante AscWaitTixISRDone(sc, target_ix);
2915 1.1 dante retval = ASC_NOERROR;
2916 1.1 dante scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf;
2917 1.1 dante buf = (u_char *) & scsiq_buf;
2918 1.1 dante for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++)
2919 1.1 dante *buf++ = 0x00;
2920 1.1 dante scsiq->q1.status = (u_char) ASC_QS_READY;
2921 1.1 dante scsiq->q2.cdb_len = 6;
2922 1.1 dante scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE;
2923 1.1 dante scsiq->q1.target_id = target_id;
2924 1.1 dante scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0);
2925 1.8 dante scsiq->cdbptr = scsiq->cdb;
2926 1.1 dante scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT;
2927 1.1 dante AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET);
2928 1.1 dante sc->unit_not_ready &= ~target_id;
2929 1.1 dante sc->sdtr_done |= target_id;
2930 1.1 dante if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) {
2931 1.1 dante sc->unit_not_ready = target_id;
2932 1.1 dante DvcSleepMilliSecond(1000);
2933 1.1 dante _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq);
2934 1.1 dante if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) {
2935 1.1 dante AscCleanUpDiscQueue(iot, ioh);
2936 1.1 dante AscStartQueueExe(iot, ioh);
2937 1.1 dante if (sc->pci_fix_asyn_xfer & target_id)
2938 1.1 dante AscSetRunChipSynRegAtID(iot, ioh, tid_no,
2939 1.7 dante ASYN_SDTR_DATA_FIX_PCI_REV_AB);
2940 1.1 dante AscWaitTixISRDone(sc, target_ix);
2941 1.1 dante }
2942 1.1 dante } else
2943 1.1 dante retval = ASC_BUSY;
2944 1.1 dante sc->sdtr_done &= ~target_id;
2945 1.1 dante } else {
2946 1.1 dante retval = ASC_ERROR;
2947 1.1 dante AscStartQueueExe(iot, ioh);
2948 1.1 dante }
2949 1.1 dante }
2950 1.1 dante sc->unit_not_ready = saved_unit_not_ready;
2951 1.1 dante return (retval);
2952 1.1 dante }
2953 1.1 dante
2954 1.1 dante
2955 1.1 dante int
2956 1.15 lukem AscResetBus(ASC_SOFTC *sc)
2957 1.1 dante {
2958 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2959 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2960 1.1 dante int retval;
2961 1.1 dante int i;
2962 1.1 dante
2963 1.1 dante
2964 1.1 dante sc->unit_not_ready = 0xFF;
2965 1.1 dante retval = ASC_NOERROR;
2966 1.1 dante
2967 1.1 dante AscWaitISRDone(sc);
2968 1.1 dante AscStopQueueExe(iot, ioh);
2969 1.1 dante sc->sdtr_done = 0;
2970 1.1 dante AscResetChipAndScsiBus(iot, ioh);
2971 1.1 dante DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000));
2972 1.1 dante AscReInitLram(sc);
2973 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++) {
2974 1.1 dante sc->cur_dvc_qng[i] = 0;
2975 1.1 dante if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i))
2976 1.4 dante AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB);
2977 1.1 dante }
2978 1.1 dante
2979 1.1 dante ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
2980 1.1 dante if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR)
2981 1.1 dante retval = ASC_ERROR;
2982 1.1 dante
2983 1.1 dante if (AscStartChip(iot, ioh) == 0)
2984 1.1 dante retval = ASC_ERROR;
2985 1.1 dante
2986 1.1 dante AscStartQueueExe(iot, ioh);
2987 1.1 dante sc->unit_not_ready = 0;
2988 1.1 dante sc->queue_full_or_busy = 0;
2989 1.1 dante return (retval);
2990 1.1 dante }
2991 1.1 dante
2992 1.1 dante
2993 1.1 dante /******************************************************************************/
2994 1.1 dante /* Error Handling routines */
2995 1.1 dante /******************************************************************************/
2996 1.1 dante
2997 1.1 dante
2998 1.1 dante static int
2999 1.15 lukem AscSetLibErrorCode(ASC_SOFTC *sc, u_int16_t err_code)
3000 1.1 dante {
3001 1.1 dante /*
3002 1.1 dante * if(sc->err_code == 0) { sc->err_code = err_code;
3003 1.7 dante */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W,
3004 1.1 dante err_code);
3005 1.1 dante /*
3006 1.1 dante * }
3007 1.1 dante */
3008 1.1 dante return (err_code);
3009 1.1 dante }
3010 1.1 dante
3011 1.1 dante
3012 1.1 dante /******************************************************************************/
3013 1.1 dante /* Handle bugged borads routines */
3014 1.1 dante /******************************************************************************/
3015 1.1 dante
3016 1.1 dante
3017 1.1 dante void
3018 1.15 lukem AscInquiryHandling(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq)
3019 1.1 dante {
3020 1.1 dante bus_space_tag_t iot = sc->sc_iot;
3021 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
3022 1.1 dante ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
3023 1.1 dante ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
3024 1.1 dante
3025 1.1 dante orig_init_sdtr = sc->init_sdtr;
3026 1.1 dante orig_use_tagged_qng = sc->use_tagged_qng;
3027 1.1 dante
3028 1.1 dante sc->init_sdtr &= ~tid_bit;
3029 1.1 dante sc->can_tagged_qng &= ~tid_bit;
3030 1.1 dante sc->use_tagged_qng &= ~tid_bit;
3031 1.1 dante
3032 1.1 dante if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) {
3033 1.1 dante if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync)
3034 1.1 dante sc->init_sdtr |= tid_bit;
3035 1.1 dante
3036 1.1 dante if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue)
3037 1.1 dante if (AscTagQueuingSafe(inq)) {
3038 1.1 dante sc->use_tagged_qng |= tid_bit;
3039 1.1 dante sc->can_tagged_qng |= tid_bit;
3040 1.1 dante }
3041 1.1 dante }
3042 1.1 dante if (orig_use_tagged_qng != sc->use_tagged_qng) {
3043 1.1 dante AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B,
3044 1.1 dante sc->disc_enable);
3045 1.1 dante AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B,
3046 1.1 dante sc->use_tagged_qng);
3047 1.1 dante AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B,
3048 1.1 dante sc->can_tagged_qng);
3049 1.1 dante
3050 1.1 dante sc->max_dvc_qng[tid_no] =
3051 1.1 dante sc->max_tag_qng[tid_no];
3052 1.1 dante AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no,
3053 1.1 dante sc->max_dvc_qng[tid_no]);
3054 1.1 dante }
3055 1.1 dante if (orig_init_sdtr != sc->init_sdtr)
3056 1.1 dante AscAsyncFix(sc, tid_no, inq);
3057 1.1 dante }
3058 1.1 dante
3059 1.1 dante
3060 1.1 dante static int
3061 1.15 lukem AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
3062 1.1 dante {
3063 1.1 dante if ((inq->add_len >= 32) &&
3064 1.1 dante (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) &&
3065 1.1 dante (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) {
3066 1.1 dante return 0;
3067 1.1 dante }
3068 1.1 dante return 1;
3069 1.1 dante }
3070 1.1 dante
3071 1.1 dante
3072 1.1 dante static void
3073 1.15 lukem AscAsyncFix(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq)
3074 1.1 dante {
3075 1.1 dante u_int8_t dvc_type;
3076 1.1 dante ASC_SCSI_BIT_ID_TYPE tid_bits;
3077 1.1 dante
3078 1.1 dante
3079 1.1 dante dvc_type = inq->byte0.peri_dvc_type;
3080 1.1 dante tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
3081 1.1 dante
3082 1.1 dante if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) {
3083 1.1 dante if (!(sc->init_sdtr & tid_bits)) {
3084 1.1 dante if ((dvc_type == SCSI_TYPE_CDROM) &&
3085 1.1 dante (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) {
3086 1.1 dante sc->pci_fix_asyn_xfer_always |= tid_bits;
3087 1.1 dante }
3088 1.1 dante sc->pci_fix_asyn_xfer |= tid_bits;
3089 1.1 dante if ((dvc_type == SCSI_TYPE_PROC) ||
3090 1.1 dante (dvc_type == SCSI_TYPE_SCANNER)) {
3091 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3092 1.1 dante }
3093 1.1 dante if ((dvc_type == SCSI_TYPE_SASD) &&
3094 1.1 dante (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) &&
3095 1.1 dante (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) {
3096 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3097 1.1 dante }
3098 1.1 dante if ((dvc_type == SCSI_TYPE_SASD) &&
3099 1.1 dante (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) {
3100 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3101 1.1 dante }
3102 1.1 dante if ((dvc_type == SCSI_TYPE_CDROM) &&
3103 1.1 dante (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) &&
3104 1.1 dante (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) {
3105 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3106 1.1 dante }
3107 1.1 dante if ((dvc_type == SCSI_TYPE_CDROM) &&
3108 1.1 dante (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) &&
3109 1.1 dante (AscCompareString(inq->product_id, "CDR400", 6) == 0)) {
3110 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3111 1.1 dante }
3112 1.1 dante if (sc->pci_fix_asyn_xfer & tid_bits) {
3113 1.1 dante AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no,
3114 1.1 dante ASYN_SDTR_DATA_FIX_PCI_REV_AB);
3115 1.1 dante }
3116 1.1 dante }
3117 1.1 dante }
3118 1.1 dante }
3119 1.1 dante
3120 1.1 dante
3121 1.1 dante /******************************************************************************/
3122 1.1 dante /* Miscellaneous routines */
3123 1.1 dante /******************************************************************************/
3124 1.1 dante
3125 1.1 dante
3126 1.1 dante static int
3127 1.21 christos AscCompareString(const u_char *str1, const u_char *str2, int len)
3128 1.1 dante {
3129 1.1 dante int i;
3130 1.1 dante int diff;
3131 1.1 dante
3132 1.1 dante for (i = 0; i < len; i++) {
3133 1.1 dante diff = (int) (str1[i] - str2[i]);
3134 1.1 dante if (diff != 0)
3135 1.1 dante return (diff);
3136 1.1 dante }
3137 1.1 dante
3138 1.1 dante return (0);
3139 1.1 dante }
3140 1.1 dante
3141 1.1 dante
3142 1.1 dante /******************************************************************************/
3143 1.1 dante /* Device oriented routines */
3144 1.1 dante /******************************************************************************/
3145 1.1 dante
3146 1.1 dante
3147 1.1 dante static int
3148 1.1 dante DvcEnterCritical(void)
3149 1.1 dante {
3150 1.1 dante int s;
3151 1.1 dante
3152 1.1 dante s = splbio();
3153 1.1 dante return (s);
3154 1.1 dante }
3155 1.1 dante
3156 1.1 dante
3157 1.1 dante static void
3158 1.15 lukem DvcLeaveCritical(int s)
3159 1.1 dante {
3160 1.1 dante
3161 1.1 dante splx(s);
3162 1.1 dante }
3163 1.1 dante
3164 1.1 dante
3165 1.1 dante static void
3166 1.15 lukem DvcSleepMilliSecond(u_int32_t n)
3167 1.1 dante {
3168 1.1 dante
3169 1.1 dante DELAY(n * 1000);
3170 1.1 dante }
3171 1.1 dante
3172 1.1 dante #ifdef UNUSED
3173 1.1 dante static void
3174 1.15 lukem DvcDelayMicroSecond(u_int32_t n)
3175 1.1 dante {
3176 1.1 dante
3177 1.1 dante DELAY(n);
3178 1.1 dante }
3179 1.1 dante #endif
3180 1.1 dante
3181 1.1 dante static void
3182 1.15 lukem DvcDelayNanoSecond(u_int32_t n)
3183 1.1 dante {
3184 1.1 dante
3185 1.1 dante DELAY((n + 999) / 1000);
3186 1.1 dante }
3187