advlib.c revision 1.31 1 1.31 andvar /* $NetBSD: advlib.c,v 1.31 2024/05/24 20:06:55 andvar Exp $ */
2 1.3 dante
3 1.1 dante /*
4 1.1 dante * Low level routines for the Advanced Systems Inc. SCSI controllers chips
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante *
20 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
31 1.1 dante */
32 1.1 dante /*
33 1.1 dante * Ported from:
34 1.1 dante */
35 1.1 dante /*
36 1.1 dante * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
37 1.1 dante *
38 1.1 dante * Copyright (c) 1995-1998 Advanced System Products, Inc.
39 1.1 dante * All Rights Reserved.
40 1.1 dante *
41 1.1 dante * Redistribution and use in source and binary forms, with or without
42 1.1 dante * modification, are permitted provided that redistributions of source
43 1.1 dante * code retain the above copyright notice and this comment without
44 1.1 dante * modification.
45 1.1 dante *
46 1.1 dante */
47 1.17 lukem
48 1.17 lukem #include <sys/cdefs.h>
49 1.31 andvar __KERNEL_RCSID(0, "$NetBSD: advlib.c,v 1.31 2024/05/24 20:06:55 andvar Exp $");
50 1.1 dante
51 1.1 dante #include <sys/param.h>
52 1.1 dante #include <sys/systm.h>
53 1.1 dante #include <sys/kernel.h>
54 1.1 dante #include <sys/queue.h>
55 1.1 dante #include <sys/device.h>
56 1.1 dante
57 1.26 ad #include <sys/bus.h>
58 1.26 ad #include <sys/intr.h>
59 1.1 dante
60 1.1 dante #include <dev/scsipi/scsi_all.h>
61 1.1 dante #include <dev/scsipi/scsipi_all.h>
62 1.1 dante #include <dev/scsipi/scsiconf.h>
63 1.1 dante
64 1.8 dante #include <dev/ic/advlib.h>
65 1.1 dante #include <dev/ic/adv.h>
66 1.1 dante #include <dev/ic/advmcode.h>
67 1.1 dante
68 1.1 dante
69 1.7 dante /* #define ASC_DEBUG */
70 1.7 dante
71 1.1 dante /******************************************************************************/
72 1.1 dante /* Static functions */
73 1.1 dante /******************************************************************************/
74 1.1 dante
75 1.19 wiz /* Initialization routines */
76 1.15 lukem static u_int32_t AscLoadMicroCode(bus_space_tag_t, bus_space_handle_t,
77 1.21 christos u_int16_t, const u_int16_t *, u_int16_t);
78 1.15 lukem static void AscInitLram(ASC_SOFTC *);
79 1.15 lukem static void AscInitQLinkVar(ASC_SOFTC *);
80 1.15 lukem static int AscResetChipAndScsiBus(bus_space_tag_t, bus_space_handle_t);
81 1.15 lukem static u_int16_t AscGetChipBusType(bus_space_tag_t, bus_space_handle_t);
82 1.15 lukem #if 0
83 1.15 lukem static u_int16_t AscGetEisaChipCfg(bus_space_tag_t, bus_space_handle_t);
84 1.15 lukem #endif
85 1.15 lukem
86 1.1 dante /* Chip register routines */
87 1.15 lukem static void AscSetBank(bus_space_tag_t, bus_space_handle_t, u_int8_t);
88 1.1 dante
89 1.1 dante /* RISC Chip routines */
90 1.15 lukem static int AscStartChip(bus_space_tag_t, bus_space_handle_t);
91 1.15 lukem static int AscStopChip(bus_space_tag_t, bus_space_handle_t);
92 1.15 lukem static u_int8_t AscSetChipScsiID(bus_space_tag_t, bus_space_handle_t, u_int8_t);
93 1.15 lukem static u_int8_t AscGetChipScsiCtrl(bus_space_tag_t, bus_space_handle_t);
94 1.15 lukem static int AscSetRunChipSynRegAtID(bus_space_tag_t, bus_space_handle_t,
95 1.15 lukem u_int8_t, u_int8_t);
96 1.15 lukem static int AscSetChipSynRegAtID(bus_space_tag_t, bus_space_handle_t,
97 1.15 lukem u_int8_t, u_int8_t);
98 1.15 lukem static int AscHostReqRiscHalt(bus_space_tag_t, bus_space_handle_t);
99 1.15 lukem static int AscIsChipHalted(bus_space_tag_t, bus_space_handle_t);
100 1.15 lukem static void AscSetChipIH(bus_space_tag_t, bus_space_handle_t, u_int16_t);
101 1.1 dante
102 1.1 dante /* Lram routines */
103 1.15 lukem static u_int8_t AscReadLramByte(bus_space_tag_t, bus_space_handle_t, u_int16_t);
104 1.15 lukem static void AscWriteLramByte(bus_space_tag_t, bus_space_handle_t,
105 1.15 lukem u_int16_t, u_int8_t);
106 1.15 lukem static u_int16_t AscReadLramWord(bus_space_tag_t, bus_space_handle_t,
107 1.15 lukem u_int16_t);
108 1.15 lukem static void AscWriteLramWord(bus_space_tag_t, bus_space_handle_t,
109 1.15 lukem u_int16_t, u_int16_t);
110 1.15 lukem static u_int32_t AscReadLramDWord(bus_space_tag_t, bus_space_handle_t,
111 1.15 lukem u_int16_t);
112 1.15 lukem static void AscWriteLramDWord(bus_space_tag_t, bus_space_handle_t,
113 1.15 lukem u_int16_t, u_int32_t);
114 1.15 lukem static void AscMemWordSetLram(bus_space_tag_t, bus_space_handle_t,
115 1.15 lukem u_int16_t, u_int16_t, int);
116 1.15 lukem static void AscMemWordCopyToLram(bus_space_tag_t, bus_space_handle_t,
117 1.21 christos u_int16_t, const u_int16_t *, int);
118 1.15 lukem static void AscMemWordCopyFromLram(bus_space_tag_t, bus_space_handle_t,
119 1.15 lukem u_int16_t, u_int16_t *, int);
120 1.15 lukem static void AscMemDWordCopyToLram(bus_space_tag_t, bus_space_handle_t,
121 1.15 lukem u_int16_t, u_int32_t *, int);
122 1.15 lukem static u_int32_t AscMemSumLramWord(bus_space_tag_t, bus_space_handle_t,
123 1.15 lukem u_int16_t, int);
124 1.15 lukem static int AscTestExternalLram(bus_space_tag_t, bus_space_handle_t);
125 1.1 dante
126 1.1 dante /* MicroCode routines */
127 1.15 lukem static u_int16_t AscInitMicroCodeVar(ASC_SOFTC *);
128 1.1 dante
129 1.1 dante /* EEProm routines */
130 1.15 lukem static int AscWriteEEPCmdReg(bus_space_tag_t, bus_space_handle_t, u_int8_t);
131 1.15 lukem static int AscWriteEEPDataReg(bus_space_tag_t, bus_space_handle_t, u_int16_t);
132 1.15 lukem static void AscWaitEEPRead(void);
133 1.15 lukem static void AscWaitEEPWrite(void);
134 1.15 lukem static u_int16_t AscReadEEPWord(bus_space_tag_t, bus_space_handle_t, u_int8_t);
135 1.15 lukem static u_int16_t AscWriteEEPWord(bus_space_tag_t, bus_space_handle_t,
136 1.15 lukem u_int8_t, u_int16_t);
137 1.15 lukem static u_int16_t AscGetEEPConfig(bus_space_tag_t, bus_space_handle_t,
138 1.15 lukem ASCEEP_CONFIG *, u_int16_t);
139 1.15 lukem static int AscSetEEPConfig(bus_space_tag_t, bus_space_handle_t,
140 1.15 lukem ASCEEP_CONFIG *, u_int16_t);
141 1.15 lukem static int AscSetEEPConfigOnce(bus_space_tag_t, bus_space_handle_t,
142 1.15 lukem ASCEEP_CONFIG *, u_int16_t);
143 1.7 dante #ifdef ASC_DEBUG
144 1.15 lukem static void AscPrintEEPConfig(ASCEEP_CONFIG *, u_int16_t);
145 1.7 dante #endif
146 1.1 dante
147 1.1 dante /* Interrupt routines */
148 1.15 lukem static void AscIsrChipHalted(ASC_SOFTC *);
149 1.15 lukem static int AscIsrQDone(ASC_SOFTC *);
150 1.15 lukem static int AscWaitTixISRDone(ASC_SOFTC *, u_int8_t);
151 1.15 lukem static int AscWaitISRDone(ASC_SOFTC *);
152 1.15 lukem static u_int8_t _AscCopyLramScsiDoneQ(bus_space_tag_t, bus_space_handle_t,
153 1.15 lukem u_int16_t, ASC_QDONE_INFO *, u_int32_t);
154 1.15 lukem static void AscGetQDoneInfo(bus_space_tag_t, bus_space_handle_t, u_int16_t,
155 1.15 lukem ASC_QDONE_INFO *);
156 1.15 lukem static void AscToggleIRQAct(bus_space_tag_t, bus_space_handle_t);
157 1.15 lukem static void AscDisableInterrupt(bus_space_tag_t, bus_space_handle_t);
158 1.15 lukem static void AscEnableInterrupt(bus_space_tag_t, bus_space_handle_t);
159 1.15 lukem static u_int8_t AscSetChipIRQ(bus_space_tag_t, bus_space_handle_t,
160 1.15 lukem u_int8_t, u_int16_t);
161 1.15 lukem static void AscAckInterrupt(bus_space_tag_t, bus_space_handle_t);
162 1.15 lukem static u_int32_t AscGetMaxDmaCount(u_int16_t);
163 1.15 lukem static u_int16_t AscSetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t,
164 1.15 lukem u_int16_t);
165 1.15 lukem static u_int8_t AscGetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t);
166 1.15 lukem static u_int8_t AscSetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t,
167 1.15 lukem u_int8_t);
168 1.20 perry
169 1.1 dante /* Messages routines */
170 1.15 lukem static void AscHandleExtMsgIn(ASC_SOFTC *, u_int16_t, u_int8_t,
171 1.15 lukem ASC_SCSI_BIT_ID_TYPE, int, u_int8_t);
172 1.15 lukem static u_int8_t AscMsgOutSDTR(ASC_SOFTC *, u_int8_t, u_int8_t);
173 1.20 perry
174 1.1 dante /* SDTR routines */
175 1.15 lukem static void AscSetChipSDTR(bus_space_tag_t, bus_space_handle_t,
176 1.15 lukem u_int8_t, u_int8_t);
177 1.15 lukem static u_int8_t AscCalSDTRData(ASC_SOFTC *, u_int8_t, u_int8_t);
178 1.15 lukem static u_int8_t AscGetSynPeriodIndex(ASC_SOFTC *, u_int8_t);
179 1.20 perry
180 1.1 dante /* Queue routines */
181 1.15 lukem static int AscSendScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t);
182 1.15 lukem static int AscSgListToQueue(int);
183 1.15 lukem static u_int AscGetNumOfFreeQueue(ASC_SOFTC *, u_int8_t, u_int8_t);
184 1.15 lukem static int AscPutReadyQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t);
185 1.15 lukem static void AscPutSCSIQ(bus_space_tag_t, bus_space_handle_t,
186 1.15 lukem u_int16_t, ASC_SCSI_Q *);
187 1.15 lukem static int AscPutReadySgListQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t);
188 1.15 lukem static u_int8_t AscAllocFreeQueue(bus_space_tag_t, bus_space_handle_t,
189 1.15 lukem u_int8_t);
190 1.15 lukem static u_int8_t AscAllocMultipleFreeQueue(bus_space_tag_t, bus_space_handle_t,
191 1.15 lukem u_int8_t, u_int8_t);
192 1.15 lukem static int AscStopQueueExe(bus_space_tag_t, bus_space_handle_t);
193 1.15 lukem static void AscStartQueueExe(bus_space_tag_t, bus_space_handle_t);
194 1.15 lukem static void AscCleanUpBusyQueue(bus_space_tag_t, bus_space_handle_t);
195 1.15 lukem static int _AscWaitQDone(bus_space_tag_t, bus_space_handle_t,
196 1.15 lukem ASC_SCSI_Q *);
197 1.15 lukem static int AscCleanUpDiscQueue(bus_space_tag_t, bus_space_handle_t);
198 1.20 perry
199 1.1 dante /* Abort and Reset CCB routines */
200 1.15 lukem static int AscRiscHaltedAbortCCB(ASC_SOFTC *, ADV_CCB *);
201 1.15 lukem static int AscRiscHaltedAbortTIX(ASC_SOFTC *, u_int8_t);
202 1.20 perry
203 1.1 dante /* Error Handling routines */
204 1.15 lukem static int AscSetLibErrorCode(ASC_SOFTC *, u_int16_t);
205 1.20 perry
206 1.31 andvar /* Handle bugged boards routines */
207 1.15 lukem static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
208 1.15 lukem static void AscAsyncFix(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *);
209 1.20 perry
210 1.1 dante /* Miscellaneous routines */
211 1.21 christos static int AscCompareString(const u_char *, const u_char *, int);
212 1.20 perry
213 1.1 dante /* Device oriented routines */
214 1.15 lukem static int DvcEnterCritical(void);
215 1.15 lukem static void DvcLeaveCritical(int);
216 1.15 lukem static void DvcSleepMilliSecond(u_int32_t);
217 1.15 lukem #if 0
218 1.15 lukem static void DvcDelayMicroSecond(u_int32_t);
219 1.15 lukem #endif
220 1.15 lukem static void DvcDelayNanoSecond(u_int32_t);
221 1.1 dante
222 1.1 dante
223 1.1 dante /******************************************************************************/
224 1.19 wiz /* Initialization routines */
225 1.1 dante /******************************************************************************/
226 1.1 dante
227 1.1 dante /*
228 1.1 dante * This function perform the following steps:
229 1.1 dante * - initialize ASC_SOFTC structure with defaults values.
230 1.1 dante * - inquire board registers to know what kind of board it is.
231 1.31 andvar * - keep track of bugged boards.
232 1.1 dante */
233 1.1 dante void
234 1.15 lukem AscInitASC_SOFTC(ASC_SOFTC *sc)
235 1.1 dante {
236 1.1 dante bus_space_tag_t iot = sc->sc_iot;
237 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
238 1.1 dante int i;
239 1.1 dante
240 1.1 dante
241 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
242 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
243 1.1 dante
244 1.1 dante sc->bug_fix_cntl = 0;
245 1.1 dante sc->pci_fix_asyn_xfer = 0;
246 1.1 dante sc->pci_fix_asyn_xfer_always = 0;
247 1.1 dante sc->sdtr_done = 0;
248 1.1 dante sc->cur_total_qng = 0;
249 1.1 dante sc->last_q_shortage = 0;
250 1.1 dante sc->use_tagged_qng = 0;
251 1.1 dante sc->unit_not_ready = 0;
252 1.1 dante sc->queue_full_or_busy = 0;
253 1.1 dante sc->host_init_sdtr_index = 0;
254 1.1 dante sc->can_tagged_qng = 0;
255 1.1 dante sc->cmd_qng_enabled = 0;
256 1.1 dante sc->dvc_cntl = ASC_DEF_DVC_CNTL;
257 1.1 dante sc->init_sdtr = 0;
258 1.1 dante sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
259 1.1 dante sc->scsi_reset_wait = 3;
260 1.1 dante sc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
261 1.1 dante sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type);
262 1.1 dante sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
263 1.1 dante sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
264 1.1 dante sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
265 1.1 dante sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
266 1.1 dante sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR;
267 1.1 dante if ((sc->bus_type & ASC_IS_PCI) &&
268 1.10 dante (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
269 1.1 dante sc->bus_type = ASC_IS_PCI_ULTRA;
270 1.1 dante sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
271 1.1 dante sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
272 1.1 dante sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
273 1.1 dante sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
274 1.1 dante sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
275 1.1 dante sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
276 1.1 dante sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
277 1.1 dante sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
278 1.1 dante sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
279 1.1 dante sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
280 1.1 dante sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
281 1.1 dante sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
282 1.1 dante sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
283 1.1 dante sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
284 1.1 dante sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
285 1.1 dante sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
286 1.1 dante sc->max_sdtr_index = 15;
287 1.10 dante if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
288 1.1 dante ASC_SET_EXTRA_CONTROL(iot, ioh,
289 1.1 dante (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
290 1.10 dante else if (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050)
291 1.1 dante ASC_SET_EXTRA_CONTROL(iot, ioh,
292 1.1 dante (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
293 1.1 dante } else {
294 1.1 dante sc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
295 1.1 dante sc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
296 1.1 dante sc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
297 1.1 dante sc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
298 1.1 dante sc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
299 1.1 dante sc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
300 1.1 dante sc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
301 1.1 dante sc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
302 1.1 dante sc->max_sdtr_index = 7;
303 1.1 dante }
304 1.1 dante
305 1.1 dante if (sc->bus_type == ASC_IS_PCI)
306 1.1 dante ASC_SET_EXTRA_CONTROL(iot, ioh,
307 1.1 dante (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
308 1.1 dante
309 1.1 dante sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
310 1.1 dante if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) {
311 1.1 dante ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT);
312 1.1 dante sc->bus_type = ASC_IS_ISAPNP;
313 1.1 dante }
314 1.1 dante if ((sc->bus_type & ASC_IS_ISA) != 0)
315 1.1 dante sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh);
316 1.1 dante
317 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++) {
318 1.1 dante sc->cur_dvc_qng[i] = 0;
319 1.1 dante sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
320 1.1 dante sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
321 1.1 dante }
322 1.1 dante }
323 1.1 dante
324 1.1 dante
325 1.1 dante /*
326 1.1 dante * This function initialize some ASC_SOFTC fields with values read from
327 1.1 dante * on-board EEProm.
328 1.1 dante */
329 1.9 dante int16_t
330 1.15 lukem AscInitFromEEP(ASC_SOFTC *sc)
331 1.1 dante {
332 1.1 dante bus_space_tag_t iot = sc->sc_iot;
333 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
334 1.1 dante ASCEEP_CONFIG eep_config_buf;
335 1.1 dante ASCEEP_CONFIG *eep_config;
336 1.1 dante u_int16_t chksum;
337 1.1 dante u_int16_t warn_code;
338 1.1 dante u_int16_t cfg_msw, cfg_lsw;
339 1.1 dante int i;
340 1.1 dante int write_eep = 0;
341 1.1 dante
342 1.1 dante
343 1.1 dante warn_code = 0;
344 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE);
345 1.1 dante AscStopQueueExe(iot, ioh);
346 1.9 dante
347 1.9 dante AscStopChip(iot, ioh);
348 1.9 dante AscResetChipAndScsiBus(iot, ioh);
349 1.9 dante DvcSleepMilliSecond(sc->scsi_reset_wait * 1000);
350 1.9 dante
351 1.1 dante if ((AscStopChip(iot, ioh) == FALSE) ||
352 1.1 dante (AscGetChipScsiCtrl(iot, ioh) != 0)) {
353 1.1 dante AscResetChipAndScsiBus(iot, ioh);
354 1.1 dante DvcSleepMilliSecond(sc->scsi_reset_wait * 1000);
355 1.1 dante }
356 1.1 dante if (AscIsChipHalted(iot, ioh) == FALSE)
357 1.1 dante return (-1);
358 1.1 dante
359 1.1 dante ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
360 1.1 dante if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR)
361 1.1 dante return (-2);
362 1.1 dante
363 1.7 dante eep_config = &eep_config_buf;
364 1.1 dante cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
365 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
366 1.1 dante if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
367 1.1 dante cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
368 1.1 dante warn_code |= ASC_WARN_CFG_MSW_RECOVER;
369 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
370 1.1 dante }
371 1.1 dante chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type);
372 1.7 dante #ifdef ASC_DEBUG
373 1.7 dante AscPrintEEPConfig(eep_config, chksum);
374 1.7 dante #endif
375 1.1 dante if (chksum == 0)
376 1.1 dante chksum = 0xAA55;
377 1.1 dante
378 1.1 dante if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) {
379 1.1 dante warn_code |= ASC_WARN_AUTO_CONFIG;
380 1.1 dante if (sc->chip_version == 3) {
381 1.1 dante if (eep_config->cfg_lsw != cfg_lsw) {
382 1.1 dante warn_code |= ASC_WARN_EEPROM_RECOVER;
383 1.1 dante eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
384 1.1 dante }
385 1.1 dante if (eep_config->cfg_msw != cfg_msw) {
386 1.1 dante warn_code |= ASC_WARN_EEPROM_RECOVER;
387 1.1 dante eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
388 1.1 dante }
389 1.1 dante }
390 1.1 dante }
391 1.1 dante eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
392 1.1 dante eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
393 1.1 dante
394 1.1 dante if (chksum != eep_config->chksum) {
395 1.10 dante if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3050) {
396 1.1 dante eep_config->init_sdtr = 0xFF;
397 1.1 dante eep_config->disc_enable = 0xFF;
398 1.1 dante eep_config->start_motor = 0xFF;
399 1.1 dante eep_config->use_cmd_qng = 0;
400 1.1 dante eep_config->max_total_qng = 0xF0;
401 1.1 dante eep_config->max_tag_qng = 0x20;
402 1.1 dante eep_config->cntl = 0xBFFF;
403 1.1 dante eep_config->chip_scsi_id = 7;
404 1.1 dante eep_config->no_scam = 0;
405 1.1 dante eep_config->adapter_info[0] = 0;
406 1.1 dante eep_config->adapter_info[1] = 0;
407 1.1 dante eep_config->adapter_info[2] = 0;
408 1.1 dante eep_config->adapter_info[3] = 0;
409 1.7 dante #if BYTE_ORDER == BIG_ENDIAN
410 1.7 dante eep_config->adapter_info[5] = 0;
411 1.7 dante /* Indicate EEPROM-less board. */
412 1.7 dante eep_config->adapter_info[4] = 0xBB;
413 1.7 dante #else
414 1.1 dante eep_config->adapter_info[4] = 0;
415 1.1 dante /* Indicate EEPROM-less board. */
416 1.1 dante eep_config->adapter_info[5] = 0xBB;
417 1.7 dante #endif
418 1.1 dante } else {
419 1.1 dante write_eep = 1;
420 1.1 dante warn_code |= ASC_WARN_EEPROM_CHKSUM;
421 1.1 dante }
422 1.1 dante }
423 1.1 dante sc->sdtr_enable = eep_config->init_sdtr;
424 1.1 dante sc->disc_enable = eep_config->disc_enable;
425 1.1 dante sc->cmd_qng_enabled = eep_config->use_cmd_qng;
426 1.1 dante sc->isa_dma_speed = eep_config->isa_dma_speed;
427 1.1 dante sc->start_motor = eep_config->start_motor;
428 1.1 dante sc->dvc_cntl = eep_config->cntl;
429 1.7 dante #if BYTE_ORDER == BIG_ENDIAN
430 1.7 dante sc->adapter_info[0] = eep_config->adapter_info[1];
431 1.7 dante sc->adapter_info[1] = eep_config->adapter_info[0];
432 1.7 dante sc->adapter_info[2] = eep_config->adapter_info[3];
433 1.7 dante sc->adapter_info[3] = eep_config->adapter_info[2];
434 1.7 dante sc->adapter_info[4] = eep_config->adapter_info[5];
435 1.7 dante sc->adapter_info[5] = eep_config->adapter_info[4];
436 1.7 dante #else
437 1.1 dante sc->adapter_info[0] = eep_config->adapter_info[0];
438 1.1 dante sc->adapter_info[1] = eep_config->adapter_info[1];
439 1.1 dante sc->adapter_info[2] = eep_config->adapter_info[2];
440 1.1 dante sc->adapter_info[3] = eep_config->adapter_info[3];
441 1.1 dante sc->adapter_info[4] = eep_config->adapter_info[4];
442 1.1 dante sc->adapter_info[5] = eep_config->adapter_info[5];
443 1.7 dante #endif
444 1.1 dante
445 1.1 dante if (!AscTestExternalLram(iot, ioh)) {
446 1.1 dante if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
447 1.1 dante eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
448 1.1 dante eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
449 1.1 dante } else {
450 1.1 dante eep_config->cfg_msw |= 0x0800;
451 1.1 dante cfg_msw |= 0x0800;
452 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
453 1.1 dante eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
454 1.1 dante eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
455 1.1 dante }
456 1.1 dante }
457 1.1 dante if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG)
458 1.1 dante eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
459 1.1 dante
460 1.1 dante if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG)
461 1.1 dante eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
462 1.1 dante
463 1.1 dante if (eep_config->max_tag_qng > eep_config->max_total_qng)
464 1.1 dante eep_config->max_tag_qng = eep_config->max_total_qng;
465 1.1 dante
466 1.1 dante if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC)
467 1.1 dante eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
468 1.1 dante
469 1.1 dante sc->max_total_qng = eep_config->max_total_qng;
470 1.1 dante if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
471 1.1 dante eep_config->use_cmd_qng) {
472 1.1 dante eep_config->disc_enable = eep_config->use_cmd_qng;
473 1.1 dante warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
474 1.1 dante }
475 1.1 dante if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA))
476 1.1 dante sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type);
477 1.1 dante
478 1.1 dante eep_config->chip_scsi_id &= ASC_MAX_TID;
479 1.1 dante sc->chip_scsi_id = eep_config->chip_scsi_id;
480 1.1 dante if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
481 1.1 dante !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
482 1.1 dante sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
483 1.1 dante }
484 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++) {
485 1.1 dante sc->max_tag_qng[i] = eep_config->max_tag_qng;
486 1.1 dante sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET |
487 1.1 dante (sc->host_init_sdtr_index << 4);
488 1.1 dante }
489 1.1 dante
490 1.1 dante eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
491 1.7 dante if (write_eep) {
492 1.1 dante AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type);
493 1.7 dante #ifdef ASC_DEBUG
494 1.7 dante AscPrintEEPConfig(eep_config, 0);
495 1.7 dante #endif
496 1.7 dante }
497 1.1 dante
498 1.1 dante return (warn_code);
499 1.1 dante }
500 1.1 dante
501 1.1 dante
502 1.1 dante u_int16_t
503 1.15 lukem AscInitFromASC_SOFTC(ASC_SOFTC *sc)
504 1.1 dante {
505 1.1 dante bus_space_tag_t iot = sc->sc_iot;
506 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
507 1.1 dante u_int16_t cfg_msw;
508 1.1 dante u_int16_t warn_code;
509 1.1 dante u_int16_t pci_device_id = sc->pci_device_id;
510 1.1 dante
511 1.1 dante
512 1.1 dante warn_code = 0;
513 1.1 dante cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh);
514 1.1 dante
515 1.1 dante if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
516 1.1 dante cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
517 1.1 dante warn_code |= ASC_WARN_CFG_MSW_RECOVER;
518 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
519 1.1 dante }
520 1.1 dante if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) {
521 1.1 dante sc->disc_enable = sc->cmd_qng_enabled;
522 1.1 dante warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
523 1.1 dante }
524 1.1 dante if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) {
525 1.1 dante warn_code |= ASC_WARN_AUTO_CONFIG;
526 1.1 dante }
527 1.1 dante if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
528 1.1 dante AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type);
529 1.1 dante }
530 1.1 dante if (sc->bus_type & ASC_IS_PCI) {
531 1.1 dante cfg_msw &= 0xFFC0;
532 1.1 dante ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw);
533 1.1 dante
534 1.1 dante if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) {
535 1.1 dante if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) ||
536 1.1 dante (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) {
537 1.1 dante sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
538 1.1 dante sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
539 1.1 dante }
540 1.1 dante }
541 1.1 dante } else if (sc->bus_type == ASC_IS_ISAPNP) {
542 1.10 dante if (sc->chip_version == ASC_CHIP_VER_ASYN_BUG) {
543 1.1 dante sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
544 1.1 dante }
545 1.1 dante }
546 1.1 dante AscSetChipScsiID(iot, ioh, sc->chip_scsi_id);
547 1.1 dante
548 1.1 dante if (sc->bus_type & ASC_IS_ISA) {
549 1.1 dante AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel);
550 1.1 dante AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed);
551 1.1 dante }
552 1.1 dante return (warn_code);
553 1.1 dante }
554 1.1 dante
555 1.1 dante
556 1.1 dante /*
557 1.1 dante * - Initialize RISC chip
558 1.19 wiz * - Initialize Lram
559 1.1 dante * - Load uCode into Lram
560 1.1 dante * - Enable Interrupts
561 1.1 dante */
562 1.1 dante int
563 1.15 lukem AscInitDriver(ASC_SOFTC *sc)
564 1.1 dante {
565 1.1 dante bus_space_tag_t iot = sc->sc_iot;
566 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
567 1.1 dante u_int32_t chksum;
568 1.1 dante
569 1.1 dante
570 1.1 dante if (!AscFindSignature(iot, ioh))
571 1.1 dante return (1);
572 1.1 dante
573 1.1 dante AscDisableInterrupt(iot, ioh);
574 1.1 dante
575 1.1 dante AscInitLram(sc);
576 1.21 christos chksum = AscLoadMicroCode(iot, ioh, 0, (const u_int16_t *) asc_mcode,
577 1.1 dante asc_mcode_size);
578 1.1 dante if (chksum != asc_mcode_chksum)
579 1.1 dante return (2);
580 1.1 dante
581 1.1 dante if (AscInitMicroCodeVar(sc) == 0)
582 1.1 dante return (3);
583 1.1 dante
584 1.1 dante AscEnableInterrupt(iot, ioh);
585 1.1 dante
586 1.1 dante return (0);
587 1.1 dante }
588 1.1 dante
589 1.1 dante
590 1.1 dante int
591 1.15 lukem AscFindSignature(bus_space_tag_t iot, bus_space_handle_t ioh)
592 1.1 dante {
593 1.1 dante u_int16_t sig_word;
594 1.1 dante
595 1.1 dante if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) {
596 1.1 dante sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh);
597 1.1 dante if (sig_word == ASC_1000_ID0W ||
598 1.1 dante sig_word == ASC_1000_ID0W_FIX)
599 1.1 dante return (1);
600 1.1 dante }
601 1.1 dante return (0);
602 1.1 dante }
603 1.1 dante
604 1.1 dante
605 1.1 dante static void
606 1.15 lukem AscInitLram(ASC_SOFTC *sc)
607 1.1 dante {
608 1.1 dante bus_space_tag_t iot = sc->sc_iot;
609 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
610 1.1 dante u_int8_t i;
611 1.1 dante u_int16_t s_addr;
612 1.1 dante
613 1.1 dante
614 1.1 dante AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0,
615 1.1 dante (((sc->max_total_qng + 2 + 1) * 64) >> 1));
616 1.1 dante
617 1.1 dante i = ASC_MIN_ACTIVE_QNO;
618 1.1 dante s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
619 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1);
620 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng);
621 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
622 1.1 dante i++;
623 1.1 dante s_addr += ASC_QBLK_SIZE;
624 1.1 dante for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
625 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1);
626 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1);
627 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
628 1.1 dante }
629 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END);
630 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1);
631 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng);
632 1.1 dante i++;
633 1.1 dante s_addr += ASC_QBLK_SIZE;
634 1.1 dante for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) {
635 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i);
636 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i);
637 1.1 dante AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i);
638 1.1 dante }
639 1.1 dante }
640 1.1 dante
641 1.1 dante
642 1.1 dante void
643 1.15 lukem AscReInitLram(ASC_SOFTC *sc)
644 1.1 dante {
645 1.1 dante
646 1.1 dante AscInitLram(sc);
647 1.1 dante AscInitQLinkVar(sc);
648 1.1 dante }
649 1.1 dante
650 1.1 dante
651 1.1 dante static void
652 1.15 lukem AscInitQLinkVar(ASC_SOFTC *sc)
653 1.1 dante {
654 1.1 dante bus_space_tag_t iot = sc->sc_iot;
655 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
656 1.1 dante u_int8_t i;
657 1.1 dante u_int16_t lram_addr;
658 1.1 dante
659 1.1 dante
660 1.1 dante ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1);
661 1.1 dante ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng);
662 1.1 dante ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1);
663 1.1 dante ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng);
664 1.1 dante AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1);
665 1.1 dante AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2);
666 1.1 dante AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng);
667 1.1 dante AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0);
668 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
669 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0);
670 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0);
671 1.1 dante AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0);
672 1.1 dante ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0);
673 1.1 dante lram_addr = ASC_QADR_BEG;
674 1.1 dante for (i = 0; i < 32; i++, lram_addr += 2)
675 1.1 dante AscWriteLramWord(iot, ioh, lram_addr, 0);
676 1.1 dante }
677 1.1 dante
678 1.1 dante
679 1.1 dante static int
680 1.15 lukem AscResetChipAndScsiBus(bus_space_tag_t iot, bus_space_handle_t ioh)
681 1.1 dante {
682 1.1 dante while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE);
683 1.1 dante
684 1.1 dante AscStopChip(iot, ioh);
685 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT);
686 1.1 dante
687 1.1 dante DvcDelayNanoSecond(60000);
688 1.1 dante
689 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM);
690 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_HALT);
691 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT);
692 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
693 1.1 dante
694 1.1 dante DvcSleepMilliSecond(200);
695 1.1 dante
696 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
697 1.16 briggs ASC_SET_CHIP_STATUS(iot, ioh, 0);
698 1.1 dante
699 1.1 dante DvcSleepMilliSecond(200);
700 1.1 dante
701 1.1 dante return (AscIsChipHalted(iot, ioh));
702 1.1 dante }
703 1.1 dante
704 1.1 dante
705 1.1 dante static u_int16_t
706 1.15 lukem AscGetChipBusType(bus_space_tag_t iot, bus_space_handle_t ioh)
707 1.1 dante {
708 1.1 dante u_int16_t chip_ver;
709 1.1 dante
710 1.1 dante chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh);
711 1.15 lukem #if 0
712 1.15 lukem if ((chip_ver >= ASC_CHIP_MIN_VER_VL) &&
713 1.1 dante (chip_ver <= ASC_CHIP_MAX_VER_VL)) {
714 1.9 dante if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) {
715 1.9 dante return (ASC_IS_EISA);
716 1.9 dante }
717 1.9 dante else {
718 1.9 dante return (ASC_IS_VL);
719 1.9 dante }
720 1.1 dante }
721 1.15 lukem #endif
722 1.15 lukem if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
723 1.1 dante (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
724 1.1 dante if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP)
725 1.1 dante return (ASC_IS_ISAPNP);
726 1.1 dante
727 1.1 dante return (ASC_IS_ISA);
728 1.1 dante } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
729 1.1 dante (chip_ver <= ASC_CHIP_MAX_VER_PCI))
730 1.1 dante return (ASC_IS_PCI);
731 1.1 dante
732 1.1 dante return (0);
733 1.1 dante }
734 1.1 dante
735 1.10 dante /*
736 1.9 dante static u_int16_t
737 1.15 lukem AscGetEisaChipCfg(bus_space_tag_t iot, bus_space_handle_t ioh)
738 1.9 dante {
739 1.9 dante int eisa_cfg_iop;
740 1.9 dante
741 1.9 dante eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK);
742 1.9 dante return (inw(eisa_cfg_iop));
743 1.9 dante }
744 1.10 dante */
745 1.9 dante
746 1.1 dante /******************************************************************************/
747 1.1 dante /* Chip register routines */
748 1.1 dante /******************************************************************************/
749 1.1 dante
750 1.1 dante
751 1.1 dante static void
752 1.15 lukem AscSetBank(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bank)
753 1.1 dante {
754 1.1 dante u_int8_t val;
755 1.1 dante
756 1.1 dante val = ASC_GET_CHIP_CONTROL(iot, ioh) &
757 1.1 dante (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST |
758 1.1 dante ASC_CC_DIAG | ASC_CC_SCSI_RESET |
759 1.1 dante ASC_CC_CHIP_RESET));
760 1.1 dante
761 1.1 dante switch (bank) {
762 1.1 dante case 1:
763 1.1 dante val |= ASC_CC_BANK_ONE;
764 1.1 dante break;
765 1.1 dante
766 1.1 dante case 2:
767 1.1 dante val |= ASC_CC_DIAG | ASC_CC_BANK_ONE;
768 1.1 dante break;
769 1.1 dante
770 1.1 dante default:
771 1.1 dante val &= ~ASC_CC_BANK_ONE;
772 1.1 dante }
773 1.1 dante
774 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, val);
775 1.1 dante return;
776 1.1 dante }
777 1.1 dante
778 1.1 dante
779 1.1 dante /******************************************************************************/
780 1.1 dante /* Chip routines */
781 1.1 dante /******************************************************************************/
782 1.1 dante
783 1.1 dante
784 1.1 dante static int
785 1.15 lukem AscStartChip(bus_space_tag_t iot, bus_space_handle_t ioh)
786 1.1 dante {
787 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, 0);
788 1.1 dante if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0)
789 1.1 dante return (0);
790 1.1 dante
791 1.1 dante return (1);
792 1.1 dante }
793 1.1 dante
794 1.1 dante
795 1.1 dante static int
796 1.15 lukem AscStopChip(bus_space_tag_t iot, bus_space_handle_t ioh)
797 1.1 dante {
798 1.1 dante u_int8_t cc_val;
799 1.1 dante
800 1.1 dante cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) &
801 1.1 dante (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG));
802 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT);
803 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_HALT);
804 1.1 dante AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM);
805 1.1 dante if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0)
806 1.1 dante return (0);
807 1.1 dante
808 1.1 dante return (1);
809 1.1 dante }
810 1.1 dante
811 1.1 dante
812 1.1 dante static u_int8_t
813 1.15 lukem AscSetChipScsiID(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t new_id)
814 1.1 dante {
815 1.1 dante u_int16_t cfg_lsw;
816 1.1 dante
817 1.1 dante if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id)
818 1.1 dante return (new_id);
819 1.1 dante
820 1.1 dante cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh);
821 1.1 dante cfg_lsw &= 0xF8FF;
822 1.1 dante cfg_lsw |= (new_id & ASC_MAX_TID) << 8;
823 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
824 1.1 dante return (ASC_GET_CHIP_SCSI_ID(iot, ioh));
825 1.1 dante }
826 1.1 dante
827 1.1 dante
828 1.1 dante static u_int8_t
829 1.15 lukem AscGetChipScsiCtrl(bus_space_tag_t iot, bus_space_handle_t ioh)
830 1.1 dante {
831 1.1 dante u_int8_t scsi_ctrl;
832 1.1 dante
833 1.1 dante AscSetBank(iot, ioh, 1);
834 1.1 dante scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC);
835 1.1 dante AscSetBank(iot, ioh, 0);
836 1.1 dante return (scsi_ctrl);
837 1.1 dante }
838 1.1 dante
839 1.1 dante
840 1.1 dante static int
841 1.15 lukem AscSetRunChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh,
842 1.15 lukem u_int8_t tid_no, u_int8_t sdtr_data)
843 1.1 dante {
844 1.1 dante int retval = FALSE;
845 1.1 dante
846 1.1 dante if (AscHostReqRiscHalt(iot, ioh)) {
847 1.4 dante retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data);
848 1.1 dante AscStartChip(iot, ioh);
849 1.1 dante }
850 1.1 dante return (retval);
851 1.1 dante }
852 1.1 dante
853 1.1 dante
854 1.1 dante static int
855 1.15 lukem AscSetChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh,
856 1.15 lukem u_int8_t id, u_int8_t sdtr_data)
857 1.1 dante {
858 1.1 dante ASC_SCSI_BIT_ID_TYPE org_id;
859 1.1 dante int i;
860 1.22 christos int stax = TRUE;
861 1.1 dante
862 1.1 dante AscSetBank(iot, ioh, 1);
863 1.1 dante org_id = ASC_READ_CHIP_DVC_ID(iot, ioh);
864 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++)
865 1.1 dante if (org_id == (0x01 << i))
866 1.1 dante break;
867 1.1 dante
868 1.1 dante org_id = i;
869 1.1 dante ASC_WRITE_CHIP_DVC_ID(iot, ioh, id);
870 1.1 dante if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) {
871 1.1 dante AscSetBank(iot, ioh, 0);
872 1.1 dante ASC_SET_CHIP_SYN(iot, ioh, sdtr_data);
873 1.1 dante if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data)
874 1.22 christos stax = FALSE;
875 1.1 dante } else
876 1.22 christos stax = FALSE;
877 1.1 dante
878 1.1 dante AscSetBank(iot, ioh, 1);
879 1.1 dante ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id);
880 1.1 dante AscSetBank(iot, ioh, 0);
881 1.22 christos return (stax);
882 1.1 dante }
883 1.1 dante
884 1.1 dante
885 1.1 dante static int
886 1.15 lukem AscHostReqRiscHalt(bus_space_tag_t iot, bus_space_handle_t ioh)
887 1.1 dante {
888 1.1 dante int count = 0;
889 1.1 dante int retval = 0;
890 1.1 dante u_int8_t saved_stop_code;
891 1.1 dante
892 1.1 dante
893 1.1 dante if (AscIsChipHalted(iot, ioh))
894 1.1 dante return (1);
895 1.1 dante saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
896 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B,
897 1.1 dante ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
898 1.1 dante
899 1.1 dante do {
900 1.1 dante if (AscIsChipHalted(iot, ioh)) {
901 1.1 dante retval = 1;
902 1.1 dante break;
903 1.1 dante }
904 1.1 dante DvcSleepMilliSecond(100);
905 1.1 dante } while (count++ < 20);
906 1.1 dante
907 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code);
908 1.1 dante
909 1.1 dante return (retval);
910 1.1 dante }
911 1.1 dante
912 1.1 dante
913 1.1 dante static int
914 1.15 lukem AscIsChipHalted(bus_space_tag_t iot, bus_space_handle_t ioh)
915 1.1 dante {
916 1.1 dante if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0)
917 1.1 dante if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0)
918 1.1 dante return (1);
919 1.1 dante
920 1.1 dante return (0);
921 1.1 dante }
922 1.1 dante
923 1.1 dante
924 1.1 dante static void
925 1.15 lukem AscSetChipIH(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t ins_code)
926 1.1 dante {
927 1.1 dante AscSetBank(iot, ioh, 1);
928 1.1 dante ASC_WRITE_CHIP_IH(iot, ioh, ins_code);
929 1.1 dante AscSetBank(iot, ioh, 0);
930 1.1 dante
931 1.1 dante return;
932 1.1 dante }
933 1.1 dante
934 1.1 dante
935 1.1 dante /******************************************************************************/
936 1.1 dante /* Lram routines */
937 1.1 dante /******************************************************************************/
938 1.1 dante
939 1.1 dante
940 1.1 dante static u_int8_t
941 1.15 lukem AscReadLramByte(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr)
942 1.1 dante {
943 1.1 dante u_int8_t byte_data;
944 1.1 dante u_int16_t word_data;
945 1.1 dante
946 1.1 dante
947 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE);
948 1.1 dante word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
949 1.7 dante
950 1.7 dante if (addr & 1) {
951 1.7 dante /* odd address */
952 1.1 dante byte_data = (u_int8_t) ((word_data >> 8) & 0xFF);
953 1.7 dante } else {
954 1.7 dante /* even address */
955 1.1 dante byte_data = (u_int8_t) (word_data & 0xFF);
956 1.7 dante }
957 1.7 dante
958 1.1 dante return (byte_data);
959 1.1 dante }
960 1.1 dante
961 1.1 dante
962 1.1 dante static void
963 1.15 lukem AscWriteLramByte(bus_space_tag_t iot, bus_space_handle_t ioh,
964 1.15 lukem u_int16_t addr, u_int8_t data)
965 1.1 dante {
966 1.1 dante u_int16_t word_data;
967 1.1 dante
968 1.1 dante
969 1.1 dante word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE);
970 1.7 dante
971 1.7 dante if (addr & 1) {
972 1.7 dante /* odd address */
973 1.1 dante word_data &= 0x00FF;
974 1.1 dante word_data |= (((u_int16_t) data) << 8) & 0xFF00;
975 1.1 dante } else {
976 1.7 dante /* even address */
977 1.1 dante word_data &= 0xFF00;
978 1.1 dante word_data |= ((u_int16_t) data) & 0x00FF;
979 1.1 dante }
980 1.7 dante
981 1.16 briggs AscWriteLramWord(iot, ioh, addr & 0xFFFE, word_data);
982 1.1 dante }
983 1.1 dante
984 1.1 dante
985 1.1 dante static u_int16_t
986 1.15 lukem AscReadLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr)
987 1.1 dante {
988 1.1 dante
989 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
990 1.1 dante return (ASC_GET_CHIP_LRAM_DATA(iot, ioh));
991 1.1 dante }
992 1.1 dante
993 1.1 dante
994 1.1 dante static void
995 1.15 lukem AscWriteLramWord(bus_space_tag_t iot, bus_space_handle_t ioh,
996 1.15 lukem u_int16_t addr, u_int16_t data)
997 1.1 dante {
998 1.1 dante
999 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1000 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, data);
1001 1.1 dante }
1002 1.1 dante
1003 1.1 dante
1004 1.1 dante static u_int32_t
1005 1.15 lukem AscReadLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr)
1006 1.1 dante {
1007 1.1 dante u_int16_t low_word, hi_word;
1008 1.1 dante
1009 1.1 dante
1010 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1011 1.1 dante low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1012 1.1 dante hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1013 1.1 dante
1014 1.1 dante return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word);
1015 1.1 dante }
1016 1.1 dante
1017 1.1 dante
1018 1.1 dante static void
1019 1.15 lukem AscWriteLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1020 1.15 lukem u_int16_t addr, u_int32_t data)
1021 1.1 dante {
1022 1.1 dante
1023 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1024 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF));
1025 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16));
1026 1.1 dante }
1027 1.1 dante
1028 1.1 dante
1029 1.1 dante static void
1030 1.15 lukem AscMemWordSetLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1031 1.15 lukem u_int16_t s_addr, u_int16_t s_words, int count)
1032 1.1 dante {
1033 1.1 dante int i;
1034 1.1 dante
1035 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1036 1.1 dante for (i = 0; i < count; i++)
1037 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words);
1038 1.1 dante }
1039 1.1 dante
1040 1.1 dante
1041 1.1 dante static void
1042 1.15 lukem AscMemWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1043 1.21 christos u_int16_t s_addr, const u_int16_t *s_buffer, int words)
1044 1.1 dante {
1045 1.1 dante int i;
1046 1.1 dante
1047 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1048 1.1 dante for (i = 0; i < words; i++, s_buffer++)
1049 1.7 dante ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer);
1050 1.5 dante }
1051 1.5 dante
1052 1.5 dante
1053 1.5 dante static void
1054 1.15 lukem AscMemWordCopyFromLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1055 1.15 lukem u_int16_t s_addr, u_int16_t *s_buffer, int words)
1056 1.1 dante {
1057 1.1 dante int i;
1058 1.1 dante
1059 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1060 1.1 dante for (i = 0; i < words; i++, s_buffer++)
1061 1.7 dante *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh);
1062 1.1 dante }
1063 1.1 dante
1064 1.1 dante
1065 1.1 dante static void
1066 1.15 lukem AscMemDWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh,
1067 1.15 lukem u_int16_t s_addr, u_int32_t *s_buffer, int dwords)
1068 1.1 dante {
1069 1.1 dante int i;
1070 1.7 dante u_int32_t *pw;
1071 1.1 dante
1072 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr);
1073 1.1 dante
1074 1.7 dante pw = s_buffer;
1075 1.7 dante for (i = 0; i < dwords; i++, pw++) {
1076 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw));
1077 1.7 dante DELAY(1);
1078 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw));
1079 1.7 dante }
1080 1.1 dante }
1081 1.1 dante
1082 1.1 dante
1083 1.1 dante static u_int32_t
1084 1.15 lukem AscMemSumLramWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1085 1.15 lukem u_int16_t s_addr, int words)
1086 1.1 dante {
1087 1.1 dante u_int32_t sum = 0L;
1088 1.1 dante u_int16_t i;
1089 1.1 dante
1090 1.1 dante
1091 1.6 dante for (i = 0; i < words; i++, s_addr += 2)
1092 1.6 dante sum += AscReadLramWord(iot, ioh, s_addr);
1093 1.1 dante
1094 1.1 dante return (sum);
1095 1.1 dante }
1096 1.1 dante
1097 1.1 dante
1098 1.1 dante static int
1099 1.15 lukem AscTestExternalLram(bus_space_tag_t iot, bus_space_handle_t ioh)
1100 1.1 dante {
1101 1.1 dante u_int16_t q_addr;
1102 1.1 dante u_int16_t saved_word;
1103 1.1 dante int retval;
1104 1.1 dante
1105 1.1 dante
1106 1.1 dante retval = 0;
1107 1.1 dante q_addr = ASC_QNO_TO_QADDR(241);
1108 1.1 dante saved_word = AscReadLramWord(iot, ioh, q_addr);
1109 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr);
1110 1.1 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA);
1111 1.1 dante DvcSleepMilliSecond(10);
1112 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr);
1113 1.1 dante
1114 1.1 dante if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) {
1115 1.1 dante retval = 1;
1116 1.1 dante AscWriteLramWord(iot, ioh, q_addr, saved_word);
1117 1.1 dante }
1118 1.1 dante return (retval);
1119 1.1 dante }
1120 1.1 dante
1121 1.1 dante
1122 1.1 dante /******************************************************************************/
1123 1.1 dante /* MicroCode routines */
1124 1.1 dante /******************************************************************************/
1125 1.1 dante
1126 1.1 dante
1127 1.1 dante static u_int16_t
1128 1.15 lukem AscInitMicroCodeVar(ASC_SOFTC *sc)
1129 1.1 dante {
1130 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1131 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1132 1.1 dante u_int32_t phy_addr;
1133 1.1 dante int i;
1134 1.1 dante
1135 1.1 dante
1136 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++)
1137 1.1 dante ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i,
1138 1.1 dante sc->sdtr_period_offset[i]);
1139 1.1 dante
1140 1.1 dante AscInitQLinkVar(sc);
1141 1.1 dante AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable);
1142 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B,
1143 1.1 dante ASC_TID_TO_TARGET_ID(sc->chip_scsi_id));
1144 1.1 dante
1145 1.11 thorpej phy_addr = (sc->overrun_buf & 0xfffffff8) + 8;
1146 1.11 thorpej AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr);
1147 1.11 thorpej AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D,
1148 1.11 thorpej ASC_OVERRUN_BSIZE - 8);
1149 1.1 dante
1150 1.1 dante sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W);
1151 1.1 dante sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W);
1152 1.1 dante ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
1153 1.1 dante
1154 1.1 dante if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) {
1155 1.1 dante return (0);
1156 1.1 dante }
1157 1.1 dante if (AscStartChip(iot, ioh) != 1) {
1158 1.1 dante return (0);
1159 1.1 dante }
1160 1.1 dante return (1);
1161 1.1 dante }
1162 1.1 dante
1163 1.1 dante
1164 1.1 dante static u_int32_t
1165 1.15 lukem AscLoadMicroCode(bus_space_tag_t iot, bus_space_handle_t ioh,
1166 1.21 christos u_int16_t s_addr, const u_int16_t *mcode_buf, u_int16_t mcode_size)
1167 1.7 dante {
1168 1.7 dante u_int32_t chksum;
1169 1.7 dante u_int16_t mcode_word_size;
1170 1.7 dante u_int16_t mcode_chksum;
1171 1.7 dante
1172 1.7 dante mcode_word_size = mcode_size >> 1;
1173 1.7 dante /* clear board memory */
1174 1.7 dante AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size);
1175 1.7 dante /* copy uCode to board memory */
1176 1.7 dante AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size);
1177 1.7 dante chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size);
1178 1.7 dante mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG,
1179 1.7 dante ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1));
1180 1.7 dante AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum);
1181 1.7 dante AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size);
1182 1.7 dante
1183 1.7 dante return (chksum);
1184 1.7 dante }
1185 1.7 dante
1186 1.7 dante
1187 1.1 dante /******************************************************************************/
1188 1.1 dante /* EEProm routines */
1189 1.1 dante /******************************************************************************/
1190 1.1 dante
1191 1.1 dante
1192 1.1 dante static int
1193 1.15 lukem AscWriteEEPCmdReg(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t cmd_reg)
1194 1.1 dante {
1195 1.1 dante u_int8_t read_back;
1196 1.1 dante int retry;
1197 1.1 dante
1198 1.1 dante retry = 0;
1199 1.1 dante
1200 1.1 dante while (TRUE) {
1201 1.1 dante ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg);
1202 1.1 dante DvcSleepMilliSecond(1);
1203 1.1 dante read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh);
1204 1.1 dante if (read_back == cmd_reg)
1205 1.1 dante return (1);
1206 1.1 dante
1207 1.1 dante if (retry++ > ASC_EEP_MAX_RETRY)
1208 1.1 dante return (0);
1209 1.1 dante }
1210 1.1 dante }
1211 1.1 dante
1212 1.1 dante
1213 1.1 dante static int
1214 1.15 lukem AscWriteEEPDataReg(bus_space_tag_t iot, bus_space_handle_t ioh,
1215 1.15 lukem u_int16_t data_reg)
1216 1.1 dante {
1217 1.1 dante u_int16_t read_back;
1218 1.1 dante int retry;
1219 1.1 dante
1220 1.1 dante retry = 0;
1221 1.1 dante while (TRUE) {
1222 1.1 dante ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg);
1223 1.1 dante DvcSleepMilliSecond(1);
1224 1.1 dante read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh);
1225 1.1 dante if (read_back == data_reg)
1226 1.1 dante return (1);
1227 1.1 dante
1228 1.1 dante if (retry++ > ASC_EEP_MAX_RETRY)
1229 1.1 dante return (0);
1230 1.1 dante }
1231 1.1 dante }
1232 1.1 dante
1233 1.1 dante
1234 1.1 dante static void
1235 1.1 dante AscWaitEEPRead(void)
1236 1.1 dante {
1237 1.1 dante
1238 1.1 dante DvcSleepMilliSecond(1);
1239 1.1 dante }
1240 1.1 dante
1241 1.1 dante
1242 1.1 dante static void
1243 1.1 dante AscWaitEEPWrite(void)
1244 1.1 dante {
1245 1.1 dante
1246 1.1 dante DvcSleepMilliSecond(1);
1247 1.1 dante }
1248 1.1 dante
1249 1.1 dante
1250 1.1 dante static u_int16_t
1251 1.15 lukem AscReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t addr)
1252 1.1 dante {
1253 1.1 dante u_int16_t read_wval;
1254 1.1 dante u_int8_t cmd_reg;
1255 1.1 dante
1256 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE);
1257 1.1 dante AscWaitEEPRead();
1258 1.1 dante cmd_reg = addr | ASC_EEP_CMD_READ;
1259 1.1 dante AscWriteEEPCmdReg(iot, ioh, cmd_reg);
1260 1.1 dante AscWaitEEPRead();
1261 1.1 dante read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh);
1262 1.1 dante AscWaitEEPRead();
1263 1.1 dante
1264 1.1 dante return (read_wval);
1265 1.1 dante }
1266 1.1 dante
1267 1.1 dante
1268 1.1 dante static u_int16_t
1269 1.15 lukem AscWriteEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh,
1270 1.15 lukem u_int8_t addr, u_int16_t word_val)
1271 1.1 dante {
1272 1.1 dante u_int16_t read_wval;
1273 1.1 dante
1274 1.1 dante read_wval = AscReadEEPWord(iot, ioh, addr);
1275 1.1 dante if (read_wval != word_val) {
1276 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE);
1277 1.1 dante AscWaitEEPRead();
1278 1.1 dante AscWriteEEPDataReg(iot, ioh, word_val);
1279 1.1 dante AscWaitEEPRead();
1280 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr);
1281 1.1 dante AscWaitEEPWrite();
1282 1.1 dante AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE);
1283 1.1 dante AscWaitEEPRead();
1284 1.1 dante return (AscReadEEPWord(iot, ioh, addr));
1285 1.1 dante }
1286 1.1 dante return (read_wval);
1287 1.1 dante }
1288 1.1 dante
1289 1.1 dante
1290 1.1 dante static u_int16_t
1291 1.15 lukem AscGetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh,
1292 1.15 lukem ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type)
1293 1.1 dante {
1294 1.1 dante u_int16_t wval;
1295 1.1 dante u_int16_t sum;
1296 1.1 dante u_int16_t *wbuf;
1297 1.1 dante int cfg_beg;
1298 1.1 dante int cfg_end;
1299 1.1 dante int s_addr;
1300 1.1 dante int isa_pnp_wsize;
1301 1.1 dante
1302 1.1 dante
1303 1.1 dante wbuf = (u_int16_t *) cfg_buf;
1304 1.1 dante sum = 0;
1305 1.1 dante isa_pnp_wsize = 0;
1306 1.1 dante
1307 1.1 dante for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) {
1308 1.1 dante wval = AscReadEEPWord(iot, ioh, s_addr);
1309 1.1 dante sum += wval;
1310 1.1 dante *wbuf = wval;
1311 1.1 dante }
1312 1.1 dante
1313 1.1 dante if (bus_type & ASC_IS_VL) {
1314 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
1315 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
1316 1.1 dante } else {
1317 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG;
1318 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR;
1319 1.1 dante }
1320 1.1 dante
1321 1.1 dante for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
1322 1.1 dante wval = AscReadEEPWord(iot, ioh, s_addr);
1323 1.1 dante sum += wval;
1324 1.1 dante *wbuf = wval;
1325 1.1 dante }
1326 1.1 dante
1327 1.1 dante *wbuf = AscReadEEPWord(iot, ioh, s_addr);
1328 1.1 dante
1329 1.1 dante return (sum);
1330 1.1 dante }
1331 1.1 dante
1332 1.1 dante
1333 1.1 dante static int
1334 1.15 lukem AscSetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh,
1335 1.15 lukem ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type)
1336 1.1 dante {
1337 1.1 dante int retry;
1338 1.1 dante int n_error;
1339 1.1 dante
1340 1.1 dante retry = 0;
1341 1.1 dante while (TRUE) {
1342 1.1 dante if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0)
1343 1.1 dante break;
1344 1.1 dante
1345 1.1 dante if (++retry > ASC_EEP_MAX_RETRY)
1346 1.1 dante break;
1347 1.1 dante }
1348 1.1 dante
1349 1.1 dante return (n_error);
1350 1.1 dante }
1351 1.1 dante
1352 1.1 dante
1353 1.1 dante static int
1354 1.15 lukem AscSetEEPConfigOnce(bus_space_tag_t iot, bus_space_handle_t ioh,
1355 1.15 lukem ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type)
1356 1.1 dante {
1357 1.1 dante int n_error;
1358 1.1 dante u_int16_t *wbuf;
1359 1.1 dante u_int16_t sum;
1360 1.1 dante int s_addr;
1361 1.1 dante int cfg_beg;
1362 1.1 dante int cfg_end;
1363 1.1 dante
1364 1.1 dante wbuf = (u_int16_t *) cfg_buf;
1365 1.1 dante n_error = 0;
1366 1.1 dante sum = 0;
1367 1.1 dante
1368 1.1 dante for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
1369 1.1 dante sum += *wbuf;
1370 1.1 dante if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf))
1371 1.1 dante n_error++;
1372 1.1 dante }
1373 1.1 dante
1374 1.1 dante if (bus_type & ASC_IS_VL) {
1375 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
1376 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
1377 1.1 dante } else {
1378 1.1 dante cfg_beg = ASC_EEP_DVC_CFG_BEG;
1379 1.1 dante cfg_end = ASC_EEP_MAX_DVC_ADDR;
1380 1.1 dante }
1381 1.1 dante
1382 1.1 dante for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
1383 1.1 dante sum += *wbuf;
1384 1.1 dante if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf))
1385 1.1 dante n_error++;
1386 1.1 dante }
1387 1.1 dante
1388 1.1 dante *wbuf = sum;
1389 1.1 dante if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum))
1390 1.1 dante n_error++;
1391 1.1 dante
1392 1.1 dante wbuf = (u_int16_t *) cfg_buf;
1393 1.7 dante for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
1394 1.1 dante if (*wbuf != AscReadEEPWord(iot, ioh, s_addr))
1395 1.1 dante n_error++;
1396 1.7 dante }
1397 1.1 dante
1398 1.7 dante for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) {
1399 1.1 dante if (*wbuf != AscReadEEPWord(iot, ioh, s_addr))
1400 1.1 dante n_error++;
1401 1.7 dante }
1402 1.1 dante
1403 1.1 dante return (n_error);
1404 1.1 dante }
1405 1.1 dante
1406 1.1 dante
1407 1.7 dante #ifdef ASC_DEBUG
1408 1.7 dante static void
1409 1.15 lukem AscPrintEEPConfig(ASCEEP_CONFIG *eep_config, u_int16_t chksum)
1410 1.7 dante {
1411 1.7 dante printf("---- ASC EEprom settings ----\n");
1412 1.7 dante printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw);
1413 1.7 dante printf("cfg_msw = 0x%x\n", eep_config->cfg_msw);
1414 1.7 dante printf("init_sdtr = 0x%x\n", eep_config->init_sdtr);
1415 1.7 dante printf("disc_enable = 0x%x\n", eep_config->disc_enable);
1416 1.7 dante printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng);
1417 1.7 dante printf("start_motor = 0x%x\n", eep_config->start_motor);
1418 1.7 dante printf("max_total_qng = 0x%x\n", eep_config->max_total_qng);
1419 1.7 dante printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng);
1420 1.7 dante printf("bios_scan = 0x%x\n", eep_config->bios_scan);
1421 1.7 dante printf("power_up_wait = 0x%x\n", eep_config->power_up_wait);
1422 1.7 dante printf("no_scam = %d\n", eep_config->no_scam);
1423 1.7 dante printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id);
1424 1.7 dante printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed);
1425 1.7 dante printf("cntl = 0x%x\n", eep_config->cntl);
1426 1.7 dante #if BYTE_ORDER == BIG_ENDIAN
1427 1.7 dante printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]);
1428 1.7 dante printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]);
1429 1.7 dante printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]);
1430 1.7 dante printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]);
1431 1.7 dante printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]);
1432 1.7 dante printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]);
1433 1.7 dante #else
1434 1.7 dante printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]);
1435 1.7 dante printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]);
1436 1.7 dante printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]);
1437 1.7 dante printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]);
1438 1.7 dante printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]);
1439 1.7 dante printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]);
1440 1.7 dante #endif
1441 1.7 dante printf("checksum = 0x%x\n", eep_config->chksum);
1442 1.7 dante printf("calculated checksum = 0x%x\n", chksum);
1443 1.7 dante printf("-----------------------------\n");
1444 1.7 dante }
1445 1.7 dante #endif
1446 1.7 dante
1447 1.7 dante
1448 1.1 dante /******************************************************************************/
1449 1.1 dante /* Interrupt routines */
1450 1.1 dante /******************************************************************************/
1451 1.1 dante
1452 1.1 dante
1453 1.1 dante int
1454 1.15 lukem AscISR(ASC_SOFTC *sc)
1455 1.1 dante {
1456 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1457 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1458 1.1 dante u_int16_t chipstat;
1459 1.1 dante u_int16_t saved_ram_addr;
1460 1.1 dante u_int8_t ctrl_reg;
1461 1.1 dante u_int8_t saved_ctrl_reg;
1462 1.1 dante int int_pending;
1463 1.1 dante int status;
1464 1.1 dante u_int8_t host_flag;
1465 1.1 dante
1466 1.1 dante
1467 1.1 dante int_pending = FALSE;
1468 1.1 dante
1469 1.1 dante ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh);
1470 1.1 dante saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET |
1471 1.1 dante ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST));
1472 1.1 dante chipstat = ASC_GET_CHIP_STATUS(iot, ioh);
1473 1.7 dante if (chipstat & ASC_CSW_SCSI_RESET_LATCH) {
1474 1.1 dante if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
1475 1.1 dante int_pending = TRUE;
1476 1.1 dante sc->sdtr_done = 0;
1477 1.1 dante saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT);
1478 1.1 dante
1479 1.1 dante while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE);
1480 1.1 dante
1481 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT));
1482 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
1483 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
1484 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
1485 1.1 dante chipstat = ASC_GET_CHIP_STATUS(iot, ioh);
1486 1.1 dante }
1487 1.7 dante }
1488 1.1 dante saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh);
1489 1.1 dante host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) &
1490 1.1 dante (u_int8_t) (~ASC_HOST_FLAG_IN_ISR);
1491 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B,
1492 1.1 dante (host_flag | ASC_HOST_FLAG_IN_ISR));
1493 1.1 dante
1494 1.1 dante if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) {
1495 1.1 dante AscAckInterrupt(iot, ioh);
1496 1.1 dante int_pending = TRUE;
1497 1.1 dante
1498 1.1 dante if ((chipstat & ASC_CSW_HALTED) &&
1499 1.1 dante (ctrl_reg & ASC_CC_SINGLE_STEP)) {
1500 1.1 dante AscIsrChipHalted(sc);
1501 1.1 dante saved_ctrl_reg &= ~ASC_CC_HALT;
1502 1.1 dante } else {
1503 1.1 dante if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) {
1504 1.1 dante while (((status = AscIsrQDone(sc)) & 0x01) != 0);
1505 1.1 dante } else {
1506 1.1 dante do {
1507 1.1 dante if ((status = AscIsrQDone(sc)) == 1)
1508 1.1 dante break;
1509 1.1 dante } while (status == 0x11);
1510 1.1 dante }
1511 1.1 dante
1512 1.1 dante if (status & 0x80)
1513 1.1 dante int_pending = -1;
1514 1.1 dante }
1515 1.1 dante }
1516 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag);
1517 1.1 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr);
1518 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg);
1519 1.1 dante
1520 1.1 dante return (1);
1521 1.1 dante /* return(int_pending); */
1522 1.1 dante }
1523 1.1 dante
1524 1.1 dante
1525 1.1 dante static int
1526 1.15 lukem AscIsrQDone(ASC_SOFTC *sc)
1527 1.1 dante {
1528 1.1 dante u_int8_t next_qp;
1529 1.1 dante u_int8_t n_q_used;
1530 1.1 dante u_int8_t sg_list_qp;
1531 1.1 dante u_int8_t sg_queue_cnt;
1532 1.1 dante u_int8_t q_cnt;
1533 1.1 dante u_int8_t done_q_tail;
1534 1.1 dante u_int8_t tid_no;
1535 1.1 dante ASC_SCSI_BIT_ID_TYPE scsi_busy;
1536 1.1 dante ASC_SCSI_BIT_ID_TYPE target_id;
1537 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1538 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1539 1.1 dante u_int16_t q_addr;
1540 1.1 dante u_int16_t sg_q_addr;
1541 1.1 dante u_int8_t cur_target_qng;
1542 1.1 dante ASC_QDONE_INFO scsiq_buf;
1543 1.1 dante ASC_QDONE_INFO *scsiq;
1544 1.1 dante
1545 1.1 dante n_q_used = 1;
1546 1.1 dante scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
1547 1.1 dante done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh);
1548 1.1 dante q_addr = ASC_QNO_TO_QADDR(done_q_tail);
1549 1.1 dante next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD));
1550 1.1 dante
1551 1.1 dante if (next_qp != ASC_QLINK_END) {
1552 1.1 dante ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp);
1553 1.1 dante q_addr = ASC_QNO_TO_QADDR(next_qp);
1554 1.1 dante sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq,
1555 1.1 dante sc->max_dma_count);
1556 1.1 dante AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS),
1557 1.1 dante (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED)));
1558 1.1 dante tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
1559 1.1 dante target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
1560 1.1 dante if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) {
1561 1.1 dante sg_q_addr = q_addr;
1562 1.1 dante sg_list_qp = next_qp;
1563 1.1 dante for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
1564 1.1 dante sg_list_qp = AscReadLramByte(iot, ioh,
1565 1.1 dante sg_q_addr + ASC_SCSIQ_B_FWD);
1566 1.1 dante sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
1567 1.1 dante if (sg_list_qp == ASC_QLINK_END) {
1568 1.1 dante AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS);
1569 1.1 dante scsiq->d3.done_stat = ASC_QD_WITH_ERROR;
1570 1.1 dante scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED;
1571 1.1 dante panic("AscIsrQDone: Corrupted SG list encountered");
1572 1.1 dante }
1573 1.1 dante AscWriteLramByte(iot, ioh,
1574 1.1 dante sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE);
1575 1.1 dante }
1576 1.1 dante n_q_used = sg_queue_cnt + 1;
1577 1.1 dante ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp);
1578 1.1 dante }
1579 1.1 dante if (sc->queue_full_or_busy & target_id) {
1580 1.1 dante cur_target_qng = AscReadLramByte(iot, ioh,
1581 1.1 dante ASC_QADR_BEG + scsiq->d2.target_ix);
1582 1.1 dante
1583 1.1 dante if (cur_target_qng < sc->max_dvc_qng[tid_no]) {
1584 1.1 dante scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
1585 1.1 dante scsi_busy &= ~target_id;
1586 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
1587 1.1 dante sc->queue_full_or_busy &= ~target_id;
1588 1.1 dante }
1589 1.1 dante }
1590 1.1 dante if (sc->cur_total_qng >= n_q_used) {
1591 1.1 dante sc->cur_total_qng -= n_q_used;
1592 1.7 dante if (sc->cur_dvc_qng[tid_no] != 0) {
1593 1.1 dante sc->cur_dvc_qng[tid_no]--;
1594 1.7 dante }
1595 1.1 dante } else {
1596 1.1 dante AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG);
1597 1.1 dante scsiq->d3.done_stat = ASC_QD_WITH_ERROR;
1598 1.1 dante panic("AscIsrQDone: Attempting to free more queues than are active");
1599 1.1 dante }
1600 1.1 dante
1601 1.8 dante if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) ||
1602 1.8 dante ((scsiq->q_status & ASC_QS_ABORTED) != 0)) {
1603 1.1 dante return (0x11);
1604 1.1 dante } else if (scsiq->q_status == ASC_QS_DONE) {
1605 1.1 dante scsiq->remain_bytes += scsiq->extra_bytes;
1606 1.1 dante
1607 1.1 dante if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) {
1608 1.1 dante if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) {
1609 1.1 dante if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) {
1610 1.1 dante scsiq->d3.done_stat = ASC_QD_NO_ERROR;
1611 1.1 dante scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR;
1612 1.1 dante }
1613 1.1 dante } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
1614 1.1 dante AscStopChip(iot, ioh);
1615 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT));
1616 1.1 dante DvcDelayNanoSecond(60000);
1617 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
1618 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT);
1619 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
1620 1.1 dante ASC_SET_CHIP_CONTROL(iot, ioh, 0);
1621 1.1 dante }
1622 1.1 dante }
1623 1.28 uwe (*sc->isr_callback)(sc, scsiq);
1624 1.1 dante
1625 1.1 dante return (1);
1626 1.1 dante } else {
1627 1.1 dante AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS);
1628 1.1 dante panic("AscIsrQDone: completed scsiq with unknown status");
1629 1.1 dante
1630 1.1 dante return (0x80);
1631 1.1 dante }
1632 1.1 dante }
1633 1.1 dante return (0);
1634 1.1 dante }
1635 1.1 dante
1636 1.1 dante
1637 1.1 dante /*
1638 1.1 dante * handle all the conditions that may halt the board
1639 1.1 dante * waiting us to intervene
1640 1.1 dante */
1641 1.1 dante static void
1642 1.15 lukem AscIsrChipHalted(ASC_SOFTC *sc)
1643 1.1 dante {
1644 1.1 dante bus_space_tag_t iot = sc->sc_iot;
1645 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
1646 1.1 dante EXT_MSG out_msg;
1647 1.1 dante u_int16_t int_halt_code;
1648 1.1 dante u_int16_t halt_q_addr;
1649 1.1 dante u_int8_t halt_qp;
1650 1.1 dante u_int8_t target_ix;
1651 1.1 dante u_int8_t tag_code;
1652 1.1 dante u_int8_t q_status;
1653 1.1 dante u_int8_t q_cntl;
1654 1.1 dante u_int8_t tid_no;
1655 1.1 dante u_int8_t cur_dvc_qng;
1656 1.1 dante u_int8_t asyn_sdtr;
1657 1.1 dante u_int8_t scsi_status;
1658 1.1 dante u_int8_t sdtr_data;
1659 1.1 dante ASC_SCSI_BIT_ID_TYPE scsi_busy;
1660 1.1 dante ASC_SCSI_BIT_ID_TYPE target_id;
1661 1.1 dante
1662 1.1 dante
1663 1.1 dante int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W);
1664 1.1 dante
1665 1.1 dante halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B);
1666 1.1 dante halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
1667 1.1 dante target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX);
1668 1.1 dante q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL);
1669 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
1670 1.1 dante target_id = ASC_TID_TO_TARGET_ID(tid_no);
1671 1.1 dante
1672 1.7 dante if (sc->pci_fix_asyn_xfer & target_id) {
1673 1.1 dante asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
1674 1.7 dante } else {
1675 1.1 dante asyn_sdtr = 0;
1676 1.7 dante }
1677 1.1 dante
1678 1.1 dante if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
1679 1.1 dante if (sc->pci_fix_asyn_xfer & target_id) {
1680 1.1 dante AscSetChipSDTR(iot, ioh, 0, tid_no);
1681 1.1 dante sc->sdtr_data[tid_no] = 0;
1682 1.1 dante }
1683 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1684 1.1 dante } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
1685 1.1 dante if (sc->pci_fix_asyn_xfer & target_id) {
1686 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
1687 1.1 dante sc->sdtr_data[tid_no] = asyn_sdtr;
1688 1.1 dante }
1689 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1690 1.1 dante } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
1691 1.1 dante AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id,
1692 1.1 dante tid_no, asyn_sdtr);
1693 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1694 1.1 dante } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
1695 1.1 dante q_cntl |= ASC_QC_REQ_SENSE;
1696 1.1 dante
1697 1.1 dante if (sc->init_sdtr & target_id) {
1698 1.1 dante sc->sdtr_done &= ~target_id;
1699 1.1 dante
1700 1.1 dante sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
1701 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
1702 1.1 dante AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) &
1703 1.1 dante (sc->max_sdtr_index - 1)],
1704 1.1 dante (sdtr_data & ASC_SYN_MAX_OFFSET));
1705 1.1 dante }
1706 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
1707 1.1 dante
1708 1.1 dante tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE);
1709 1.1 dante tag_code &= 0xDC;
1710 1.1 dante
1711 1.1 dante if ((sc->pci_fix_asyn_xfer & target_id) &&
1712 1.1 dante !(sc->pci_fix_asyn_xfer_always & target_id)) {
1713 1.1 dante tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT |
1714 1.1 dante ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
1715 1.1 dante }
1716 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code);
1717 1.1 dante
1718 1.1 dante q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS);
1719 1.1 dante q_status |= ASC_QS_READY | ASC_QS_BUSY;
1720 1.1 dante
1721 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status);
1722 1.1 dante
1723 1.1 dante scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
1724 1.1 dante scsi_busy &= ~target_id;
1725 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
1726 1.1 dante
1727 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1728 1.1 dante } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
1729 1.1 dante AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG,
1730 1.1 dante (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1);
1731 1.1 dante
1732 1.1 dante if ((out_msg.msg_type == MS_EXTEND) &&
1733 1.1 dante (out_msg.msg_len == MS_SDTR_LEN) &&
1734 1.1 dante (out_msg.msg_req == MS_SDTR_CODE)) {
1735 1.1 dante sc->init_sdtr &= ~target_id;
1736 1.1 dante sc->sdtr_done &= ~target_id;
1737 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
1738 1.1 dante sc->sdtr_data[tid_no] = asyn_sdtr;
1739 1.1 dante }
1740 1.1 dante q_cntl &= ~ASC_QC_MSG_OUT;
1741 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
1742 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1743 1.1 dante } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
1744 1.1 dante scsi_status = AscReadLramByte(iot, ioh,
1745 1.1 dante halt_q_addr + ASC_SCSIQ_SCSI_STATUS);
1746 1.1 dante cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG);
1747 1.1 dante
1748 1.1 dante if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) {
1749 1.1 dante scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B);
1750 1.1 dante scsi_busy |= target_id;
1751 1.1 dante AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy);
1752 1.1 dante sc->queue_full_or_busy |= target_id;
1753 1.1 dante
1754 1.1 dante if (scsi_status == SS_QUEUE_FULL) {
1755 1.1 dante if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
1756 1.1 dante cur_dvc_qng -= 1;
1757 1.1 dante sc->max_dvc_qng[tid_no] = cur_dvc_qng;
1758 1.1 dante
1759 1.1 dante AscWriteLramByte(iot, ioh,
1760 1.1 dante tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng);
1761 1.1 dante
1762 1.1 dante #if ASC_QUEUE_FLOW_CONTROL
1763 1.1 dante if ((sc->device[tid_no] != NULL) &&
1764 1.1 dante (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) {
1765 1.1 dante sc->device[tid_no]->queue_curr_depth = cur_dvc_qng;
1766 1.1 dante }
1767 1.1 dante #endif /* ASC_QUEUE_FLOW_CONTROL */
1768 1.1 dante }
1769 1.1 dante }
1770 1.1 dante }
1771 1.1 dante AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0);
1772 1.1 dante }
1773 1.1 dante return;
1774 1.1 dante }
1775 1.1 dante
1776 1.1 dante
1777 1.1 dante static int
1778 1.15 lukem AscWaitTixISRDone(ASC_SOFTC *sc, u_int8_t target_ix)
1779 1.1 dante {
1780 1.1 dante u_int8_t cur_req;
1781 1.1 dante u_int8_t tid_no;
1782 1.1 dante int i = 0;
1783 1.1 dante
1784 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
1785 1.1 dante while (i++ < 10) {
1786 1.1 dante if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0)
1787 1.1 dante break;
1788 1.1 dante
1789 1.1 dante DvcSleepMilliSecond(1000L);
1790 1.1 dante if (sc->cur_dvc_qng[tid_no] == cur_req)
1791 1.1 dante break;
1792 1.1 dante }
1793 1.1 dante return (1);
1794 1.1 dante }
1795 1.1 dante
1796 1.1 dante static int
1797 1.15 lukem AscWaitISRDone(ASC_SOFTC *sc)
1798 1.1 dante {
1799 1.1 dante int tid;
1800 1.1 dante
1801 1.1 dante for (tid = 0; tid <= ASC_MAX_TID; tid++)
1802 1.1 dante AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid));
1803 1.1 dante
1804 1.1 dante return (1);
1805 1.1 dante }
1806 1.1 dante
1807 1.1 dante
1808 1.1 dante static u_int8_t
1809 1.15 lukem _AscCopyLramScsiDoneQ(bus_space_tag_t iot, bus_space_handle_t ioh,
1810 1.15 lukem u_int16_t q_addr, ASC_QDONE_INFO *scsiq, u_int32_t max_dma_count)
1811 1.1 dante {
1812 1.1 dante u_int16_t _val;
1813 1.1 dante u_int8_t sg_queue_cnt;
1814 1.1 dante
1815 1.7 dante AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq);
1816 1.7 dante
1817 1.1 dante _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
1818 1.7 dante scsiq->q_status = LO_BYTE(_val);
1819 1.7 dante scsiq->q_no = HI_BYTE(_val);
1820 1.1 dante _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL);
1821 1.7 dante scsiq->cntl = LO_BYTE(_val);
1822 1.7 dante sg_queue_cnt = HI_BYTE(_val);
1823 1.1 dante _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN);
1824 1.7 dante scsiq->sense_len = LO_BYTE(_val);
1825 1.7 dante scsiq->extra_bytes = HI_BYTE(_val);
1826 1.1 dante scsiq->remain_bytes = AscReadLramWord(iot, ioh,
1827 1.1 dante q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT);
1828 1.1 dante scsiq->remain_bytes &= max_dma_count;
1829 1.1 dante
1830 1.1 dante return (sg_queue_cnt);
1831 1.1 dante }
1832 1.1 dante
1833 1.1 dante
1834 1.1 dante static void
1835 1.15 lukem AscGetQDoneInfo(bus_space_tag_t iot, bus_space_handle_t ioh,
1836 1.15 lukem u_int16_t addr, ASC_QDONE_INFO *scsiq)
1837 1.7 dante {
1838 1.7 dante u_int16_t val;
1839 1.7 dante
1840 1.7 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
1841 1.7 dante
1842 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1843 1.7 dante scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh));
1844 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1845 1.7 dante scsiq->d2.target_ix = LO_BYTE(val);
1846 1.7 dante scsiq->d2.flag = HI_BYTE(val);
1847 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1848 1.7 dante scsiq->d2.cdb_len = LO_BYTE(val);
1849 1.7 dante scsiq->d2.tag_code = HI_BYTE(val);
1850 1.7 dante scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1851 1.7 dante
1852 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1853 1.7 dante scsiq->d3.done_stat = LO_BYTE(val);
1854 1.7 dante scsiq->d3.host_stat = HI_BYTE(val);
1855 1.7 dante val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
1856 1.7 dante scsiq->d3.scsi_stat = LO_BYTE(val);
1857 1.7 dante scsiq->d3.scsi_msg = HI_BYTE(val);
1858 1.7 dante }
1859 1.7 dante
1860 1.7 dante
1861 1.7 dante static void
1862 1.15 lukem AscToggleIRQAct(bus_space_tag_t iot, bus_space_handle_t ioh)
1863 1.1 dante {
1864 1.1 dante
1865 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT);
1866 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
1867 1.1 dante }
1868 1.1 dante
1869 1.1 dante
1870 1.1 dante static void
1871 1.15 lukem AscDisableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh)
1872 1.1 dante {
1873 1.1 dante u_int16_t cfg;
1874 1.1 dante
1875 1.1 dante cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1876 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON));
1877 1.1 dante }
1878 1.1 dante
1879 1.1 dante
1880 1.1 dante static void
1881 1.15 lukem AscEnableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh)
1882 1.1 dante {
1883 1.1 dante u_int16_t cfg;
1884 1.1 dante
1885 1.1 dante cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1886 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON);
1887 1.1 dante }
1888 1.1 dante
1889 1.1 dante
1890 1.9 dante u_int8_t
1891 1.15 lukem AscGetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t bus_type)
1892 1.1 dante {
1893 1.1 dante u_int16_t cfg_lsw;
1894 1.1 dante u_int8_t chip_irq;
1895 1.1 dante
1896 1.1 dante
1897 1.15 lukem #if 0
1898 1.15 lukem if (bus_type & ASC_IS_EISA) {
1899 1.9 dante cfg_lsw = AscGetEisaChipCfg(iot, ioh);
1900 1.9 dante chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
1901 1.9 dante if((chip_irq == 13) || (chip_irq > 15))
1902 1.9 dante return (0);
1903 1.9 dante return(chip_irq);
1904 1.1 dante }
1905 1.15 lukem #endif
1906 1.15 lukem if ((bus_type & ASC_IS_VL) != 0) {
1907 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1908 1.1 dante chip_irq = (cfg_lsw >> 2) & 0x07;
1909 1.1 dante if ((chip_irq == 0) ||
1910 1.1 dante (chip_irq == 4) ||
1911 1.1 dante (chip_irq == 7)) {
1912 1.1 dante return (0);
1913 1.1 dante }
1914 1.1 dante return (chip_irq + (ASC_MIN_IRQ_NO - 1));
1915 1.1 dante }
1916 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh);
1917 1.1 dante chip_irq = (cfg_lsw >> 2) & 0x03;
1918 1.1 dante if (chip_irq == 3)
1919 1.1 dante chip_irq += 2;
1920 1.1 dante return (chip_irq + ASC_MIN_IRQ_NO);
1921 1.1 dante }
1922 1.1 dante
1923 1.1 dante
1924 1.1 dante static u_int8_t
1925 1.15 lukem AscSetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh,
1926 1.15 lukem u_int8_t irq_no, u_int16_t bus_type)
1927 1.1 dante {
1928 1.1 dante u_int16_t cfg_lsw;
1929 1.1 dante
1930 1.1 dante
1931 1.1 dante if (bus_type & ASC_IS_VL) {
1932 1.2 thorpej if (irq_no) {
1933 1.1 dante if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO))
1934 1.1 dante irq_no = 0;
1935 1.1 dante else
1936 1.1 dante irq_no -= ASC_MIN_IRQ_NO - 1;
1937 1.2 thorpej }
1938 1.1 dante
1939 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3;
1940 1.1 dante cfg_lsw |= 0x0010;
1941 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
1942 1.1 dante AscToggleIRQAct(iot, ioh);
1943 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0;
1944 1.1 dante cfg_lsw |= (irq_no & 0x07) << 2;
1945 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
1946 1.1 dante AscToggleIRQAct(iot, ioh);
1947 1.1 dante
1948 1.1 dante return (AscGetChipIRQ(iot, ioh, bus_type));
1949 1.1 dante }
1950 1.1 dante if (bus_type & ASC_IS_ISA) {
1951 1.1 dante if (irq_no == 15)
1952 1.1 dante irq_no -= 2;
1953 1.1 dante irq_no -= ASC_MIN_IRQ_NO;
1954 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3;
1955 1.1 dante cfg_lsw |= (irq_no & 0x03) << 2;
1956 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
1957 1.1 dante
1958 1.1 dante return (AscGetChipIRQ(iot, ioh, bus_type));
1959 1.1 dante }
1960 1.1 dante return (0);
1961 1.1 dante }
1962 1.1 dante
1963 1.1 dante
1964 1.1 dante static void
1965 1.15 lukem AscAckInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh)
1966 1.1 dante {
1967 1.1 dante u_int8_t host_flag;
1968 1.1 dante u_int8_t risc_flag;
1969 1.1 dante u_int16_t loop;
1970 1.1 dante
1971 1.1 dante
1972 1.1 dante loop = 0;
1973 1.1 dante do {
1974 1.1 dante risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B);
1975 1.1 dante if (loop++ > 0x7FFF)
1976 1.1 dante break;
1977 1.1 dante } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
1978 1.1 dante
1979 1.1 dante host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) &
1980 1.1 dante (~ASC_HOST_FLAG_ACK_INT);
1981 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B,
1982 1.1 dante host_flag | ASC_HOST_FLAG_ACK_INT);
1983 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK);
1984 1.1 dante
1985 1.1 dante loop = 0;
1986 1.1 dante while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) {
1987 1.1 dante ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK);
1988 1.1 dante if (loop++ > 3)
1989 1.1 dante break;
1990 1.1 dante }
1991 1.1 dante
1992 1.1 dante AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag);
1993 1.1 dante }
1994 1.1 dante
1995 1.1 dante
1996 1.1 dante static u_int32_t
1997 1.15 lukem AscGetMaxDmaCount(u_int16_t bus_type)
1998 1.1 dante {
1999 1.1 dante if (bus_type & ASC_IS_ISA)
2000 1.1 dante return (ASC_MAX_ISA_DMA_COUNT);
2001 1.1 dante else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
2002 1.1 dante return (ASC_MAX_VL_DMA_COUNT);
2003 1.1 dante return (ASC_MAX_PCI_DMA_COUNT);
2004 1.1 dante }
2005 1.1 dante
2006 1.1 dante
2007 1.9 dante u_int16_t
2008 1.15 lukem AscGetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh)
2009 1.1 dante {
2010 1.1 dante u_int16_t channel;
2011 1.1 dante
2012 1.1 dante channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003;
2013 1.1 dante if (channel == 0x03)
2014 1.1 dante return (0);
2015 1.1 dante else if (channel == 0x00)
2016 1.1 dante return (7);
2017 1.1 dante return (channel + 4);
2018 1.1 dante }
2019 1.1 dante
2020 1.1 dante
2021 1.1 dante static u_int16_t
2022 1.15 lukem AscSetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh,
2023 1.15 lukem u_int16_t dma_channel)
2024 1.1 dante {
2025 1.1 dante u_int16_t cfg_lsw;
2026 1.1 dante u_int8_t value;
2027 1.1 dante
2028 1.1 dante if ((dma_channel >= 5) && (dma_channel <= 7)) {
2029 1.1 dante if (dma_channel == 7)
2030 1.1 dante value = 0x00;
2031 1.1 dante else
2032 1.1 dante value = dma_channel - 4;
2033 1.1 dante cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC;
2034 1.1 dante cfg_lsw |= value;
2035 1.1 dante ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw);
2036 1.1 dante return (AscGetIsaDmaChannel(iot, ioh));
2037 1.1 dante }
2038 1.1 dante return (0);
2039 1.1 dante }
2040 1.1 dante
2041 1.1 dante
2042 1.1 dante static u_int8_t
2043 1.15 lukem AscGetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh)
2044 1.1 dante {
2045 1.1 dante u_int8_t speed_value;
2046 1.1 dante
2047 1.1 dante AscSetBank(iot, ioh, 1);
2048 1.1 dante speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh);
2049 1.1 dante speed_value &= 0x07;
2050 1.1 dante AscSetBank(iot, ioh, 0);
2051 1.1 dante return (speed_value);
2052 1.1 dante }
2053 1.1 dante
2054 1.1 dante
2055 1.1 dante static u_int8_t
2056 1.15 lukem AscSetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh,
2057 1.15 lukem u_int8_t speed_value)
2058 1.1 dante {
2059 1.1 dante speed_value &= 0x07;
2060 1.1 dante AscSetBank(iot, ioh, 1);
2061 1.1 dante ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value);
2062 1.1 dante AscSetBank(iot, ioh, 0);
2063 1.1 dante return (AscGetIsaDmaSpeed(iot, ioh));
2064 1.1 dante }
2065 1.1 dante
2066 1.1 dante
2067 1.1 dante /******************************************************************************/
2068 1.1 dante /* Messages routines */
2069 1.1 dante /******************************************************************************/
2070 1.1 dante
2071 1.1 dante
2072 1.1 dante static void
2073 1.15 lukem AscHandleExtMsgIn(ASC_SOFTC *sc, u_int16_t halt_q_addr, u_int8_t q_cntl,
2074 1.15 lukem ASC_SCSI_BIT_ID_TYPE target_id, int tid_no, u_int8_t asyn_sdtr)
2075 1.1 dante {
2076 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2077 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2078 1.1 dante EXT_MSG ext_msg;
2079 1.1 dante u_int8_t sdtr_data;
2080 1.1 dante int sdtr_accept;
2081 1.1 dante
2082 1.1 dante
2083 1.1 dante AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG,
2084 1.1 dante (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
2085 1.1 dante
2086 1.1 dante if (ext_msg.msg_type == MS_EXTEND &&
2087 1.1 dante ext_msg.msg_req == MS_SDTR_CODE &&
2088 1.1 dante ext_msg.msg_len == MS_SDTR_LEN) {
2089 1.1 dante sdtr_accept = TRUE;
2090 1.1 dante
2091 1.1 dante if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) {
2092 1.1 dante sdtr_accept = FALSE;
2093 1.1 dante ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
2094 1.1 dante }
2095 1.1 dante if ((ext_msg.xfer_period <
2096 1.1 dante sc->sdtr_period_tbl[sc->host_init_sdtr_index]) ||
2097 1.1 dante (ext_msg.xfer_period >
2098 1.1 dante sc->sdtr_period_tbl[sc->max_sdtr_index])) {
2099 1.1 dante sdtr_accept = FALSE;
2100 1.1 dante ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index];
2101 1.1 dante }
2102 1.1 dante if (sdtr_accept) {
2103 1.1 dante sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
2104 1.1 dante ext_msg.req_ack_offset);
2105 1.1 dante if (sdtr_data == 0xFF) {
2106 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2107 1.1 dante sc->init_sdtr &= ~target_id;
2108 1.1 dante sc->sdtr_done &= ~target_id;
2109 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
2110 1.1 dante sc->sdtr_data[tid_no] = asyn_sdtr;
2111 1.1 dante }
2112 1.1 dante }
2113 1.1 dante if (ext_msg.req_ack_offset == 0) {
2114 1.1 dante q_cntl &= ~ASC_QC_MSG_OUT;
2115 1.1 dante sc->init_sdtr &= ~target_id;
2116 1.1 dante sc->sdtr_done &= ~target_id;
2117 1.1 dante AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no);
2118 1.1 dante } else {
2119 1.1 dante if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) {
2120 1.1 dante q_cntl &= ~ASC_QC_MSG_OUT;
2121 1.1 dante sc->sdtr_done |= target_id;
2122 1.1 dante sc->init_sdtr |= target_id;
2123 1.1 dante sc->pci_fix_asyn_xfer &= ~target_id;
2124 1.1 dante sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
2125 1.1 dante ext_msg.req_ack_offset);
2126 1.1 dante AscSetChipSDTR(iot, ioh, sdtr_data, tid_no);
2127 1.1 dante sc->sdtr_data[tid_no] = sdtr_data;
2128 1.1 dante } else {
2129 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2130 1.1 dante AscMsgOutSDTR(sc, ext_msg.xfer_period,
2131 1.1 dante ext_msg.req_ack_offset);
2132 1.1 dante sc->pci_fix_asyn_xfer &= ~target_id;
2133 1.1 dante sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period,
2134 1.1 dante ext_msg.req_ack_offset);
2135 1.1 dante AscSetChipSDTR(iot, ioh, sdtr_data, tid_no);
2136 1.1 dante sc->sdtr_data[tid_no] = sdtr_data;
2137 1.1 dante sc->sdtr_done |= target_id;
2138 1.1 dante sc->init_sdtr |= target_id;
2139 1.1 dante }
2140 1.1 dante }
2141 1.1 dante } else if (ext_msg.msg_type == MS_EXTEND &&
2142 1.1 dante ext_msg.msg_req == MS_WDTR_CODE &&
2143 1.1 dante ext_msg.msg_len == MS_WDTR_LEN) {
2144 1.1 dante ext_msg.wdtr_width = 0;
2145 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2146 1.21 christos (const u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
2147 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2148 1.1 dante } else {
2149 1.1 dante ext_msg.msg_type = M1_MSG_REJECT;
2150 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2151 1.21 christos (const u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1);
2152 1.1 dante q_cntl |= ASC_QC_MSG_OUT;
2153 1.1 dante }
2154 1.1 dante
2155 1.1 dante AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl);
2156 1.1 dante }
2157 1.1 dante
2158 1.1 dante
2159 1.1 dante static u_int8_t
2160 1.15 lukem AscMsgOutSDTR(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t sdtr_offset)
2161 1.1 dante {
2162 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2163 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2164 1.1 dante EXT_MSG sdtr_buf;
2165 1.1 dante u_int8_t sdtr_period_index;
2166 1.1 dante
2167 1.1 dante
2168 1.1 dante sdtr_buf.msg_type = MS_EXTEND;
2169 1.1 dante sdtr_buf.msg_len = MS_SDTR_LEN;
2170 1.1 dante sdtr_buf.msg_req = MS_SDTR_CODE;
2171 1.1 dante sdtr_buf.xfer_period = sdtr_period;
2172 1.1 dante sdtr_offset &= ASC_SYN_MAX_OFFSET;
2173 1.1 dante sdtr_buf.req_ack_offset = sdtr_offset;
2174 1.1 dante if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <=
2175 1.1 dante sc->max_sdtr_index) {
2176 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2177 1.21 christos (const u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1);
2178 1.1 dante return ((sdtr_period_index << 4) | sdtr_offset);
2179 1.1 dante } else {
2180 1.1 dante sdtr_buf.req_ack_offset = 0;
2181 1.1 dante AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG,
2182 1.21 christos (const u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1);
2183 1.1 dante return (0);
2184 1.1 dante }
2185 1.1 dante }
2186 1.1 dante
2187 1.1 dante
2188 1.1 dante /******************************************************************************/
2189 1.1 dante /* SDTR routines */
2190 1.1 dante /******************************************************************************/
2191 1.1 dante
2192 1.1 dante
2193 1.1 dante static void
2194 1.15 lukem AscSetChipSDTR(bus_space_tag_t iot, bus_space_handle_t ioh,
2195 1.15 lukem u_int8_t sdtr_data, u_int8_t tid_no)
2196 1.1 dante {
2197 1.4 dante AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data);
2198 1.1 dante AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data);
2199 1.1 dante }
2200 1.1 dante
2201 1.1 dante
2202 1.1 dante static u_int8_t
2203 1.15 lukem AscCalSDTRData(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t syn_offset)
2204 1.1 dante {
2205 1.1 dante u_int8_t byte;
2206 1.1 dante u_int8_t sdtr_period_ix;
2207 1.1 dante
2208 1.1 dante sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period);
2209 1.1 dante if (sdtr_period_ix > sc->max_sdtr_index)
2210 1.1 dante return (0xFF);
2211 1.1 dante
2212 1.1 dante byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
2213 1.1 dante return (byte);
2214 1.1 dante }
2215 1.1 dante
2216 1.1 dante
2217 1.1 dante static u_int8_t
2218 1.15 lukem AscGetSynPeriodIndex(ASC_SOFTC *sc, u_int8_t syn_time)
2219 1.1 dante {
2220 1.1 dante u_int8_t *period_table;
2221 1.1 dante int max_index;
2222 1.1 dante int min_index;
2223 1.1 dante int i;
2224 1.1 dante
2225 1.1 dante period_table = sc->sdtr_period_tbl;
2226 1.1 dante max_index = sc->max_sdtr_index;
2227 1.1 dante min_index = sc->host_init_sdtr_index;
2228 1.1 dante if ((syn_time <= period_table[max_index])) {
2229 1.1 dante for (i = min_index; i < (max_index - 1); i++) {
2230 1.1 dante if (syn_time <= period_table[i])
2231 1.1 dante return (i);
2232 1.1 dante }
2233 1.1 dante
2234 1.1 dante return (max_index);
2235 1.1 dante } else
2236 1.1 dante return (max_index + 1);
2237 1.1 dante }
2238 1.1 dante
2239 1.1 dante
2240 1.1 dante /******************************************************************************/
2241 1.1 dante /* Queue routines */
2242 1.1 dante /******************************************************************************/
2243 1.1 dante
2244 1.1 dante /*
2245 1.1 dante * Send a command to the board
2246 1.1 dante */
2247 1.1 dante int
2248 1.15 lukem AscExeScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq)
2249 1.1 dante {
2250 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2251 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2252 1.1 dante ASC_SG_HEAD *sg_head = scsiq->sg_head;
2253 1.1 dante int retval;
2254 1.1 dante int n_q_required;
2255 1.1 dante int disable_syn_offset_one_fix;
2256 1.1 dante int i;
2257 1.1 dante u_int32_t addr;
2258 1.1 dante u_int16_t sg_entry_cnt = 0;
2259 1.1 dante u_int16_t sg_entry_cnt_minus_one = 0;
2260 1.1 dante u_int8_t target_ix;
2261 1.1 dante u_int8_t tid_no;
2262 1.1 dante u_int8_t sdtr_data;
2263 1.1 dante u_int8_t extra_bytes;
2264 1.1 dante u_int8_t scsi_cmd;
2265 1.1 dante u_int32_t data_cnt;
2266 1.1 dante
2267 1.1 dante
2268 1.1 dante scsiq->q1.q_no = 0;
2269 1.1 dante if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)
2270 1.1 dante scsiq->q1.extra_bytes = 0;
2271 1.1 dante
2272 1.1 dante retval = ASC_BUSY;
2273 1.1 dante target_ix = scsiq->q2.target_ix;
2274 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
2275 1.1 dante n_q_required = 1;
2276 1.1 dante
2277 1.1 dante if (scsiq->cdbptr[0] == SCSICMD_RequestSense)
2278 1.1 dante if ((sc->init_sdtr & scsiq->q1.target_id) != 0) {
2279 1.1 dante sc->sdtr_done &= ~scsiq->q1.target_id;
2280 1.1 dante sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
2281 1.1 dante AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) &
2282 1.1 dante (sc->max_sdtr_index - 1)],
2283 1.1 dante sdtr_data & ASC_SYN_MAX_OFFSET);
2284 1.1 dante scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT);
2285 1.1 dante }
2286 1.1 dante /*
2287 1.1 dante * if there is just one segment into S/G list then
2288 1.1 dante * map it as it was a single request, filling
2289 1.1 dante * data_addr and data_cnt of ASC_SCSIQ structure.
2290 1.1 dante */
2291 1.1 dante if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
2292 1.1 dante sg_entry_cnt = sg_head->entry_cnt;
2293 1.1 dante
2294 1.1 dante if (sg_entry_cnt < 1)
2295 1.1 dante panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.",
2296 1.1 dante sg_entry_cnt);
2297 1.1 dante
2298 1.1 dante if (sg_entry_cnt > ASC_MAX_SG_LIST)
2299 1.1 dante panic("AscExeScsiQueue: Queue with too many segs.");
2300 1.1 dante
2301 1.1 dante if (sg_entry_cnt == 1) {
2302 1.1 dante scsiq->q1.data_addr = sg_head->sg_list[0].addr;
2303 1.1 dante scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
2304 1.1 dante scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE);
2305 1.1 dante }
2306 1.1 dante sg_entry_cnt_minus_one = sg_entry_cnt - 1;
2307 1.1 dante }
2308 1.1 dante scsi_cmd = scsiq->cdbptr[0];
2309 1.1 dante disable_syn_offset_one_fix = FALSE;
2310 1.1 dante if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
2311 1.1 dante !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
2312 1.1 dante if (scsiq->q1.cntl & ASC_QC_SG_HEAD) {
2313 1.1 dante data_cnt = 0;
2314 1.1 dante for (i = 0; i < sg_entry_cnt; i++)
2315 1.1 dante data_cnt += sg_head->sg_list[i].bytes;
2316 1.1 dante } else {
2317 1.1 dante data_cnt = scsiq->q1.data_cnt;
2318 1.1 dante }
2319 1.1 dante
2320 1.1 dante if (data_cnt != 0ul) {
2321 1.1 dante if (data_cnt < 512ul) {
2322 1.1 dante disable_syn_offset_one_fix = TRUE;
2323 1.1 dante } else {
2324 1.1 dante if (scsi_cmd == SCSICMD_Inquiry ||
2325 1.1 dante scsi_cmd == SCSICMD_RequestSense ||
2326 1.1 dante scsi_cmd == SCSICMD_ReadCapacity ||
2327 1.1 dante scsi_cmd == SCSICMD_ReadTOC ||
2328 1.1 dante scsi_cmd == SCSICMD_ModeSelect6 ||
2329 1.1 dante scsi_cmd == SCSICMD_ModeSense6 ||
2330 1.1 dante scsi_cmd == SCSICMD_ModeSelect10 ||
2331 1.1 dante scsi_cmd == SCSICMD_ModeSense10) {
2332 1.1 dante disable_syn_offset_one_fix = TRUE;
2333 1.1 dante }
2334 1.1 dante }
2335 1.1 dante }
2336 1.1 dante }
2337 1.1 dante if (disable_syn_offset_one_fix) {
2338 1.1 dante scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE;
2339 1.1 dante scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
2340 1.1 dante ASC_TAG_FLAG_DISABLE_DISCONNECT);
2341 1.1 dante } else {
2342 1.1 dante scsiq->q2.tag_code &= 0x23;
2343 1.1 dante }
2344 1.1 dante
2345 1.1 dante if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
2346 1.1 dante if (sc->bug_fix_cntl) {
2347 1.1 dante if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
2348 1.1 dante if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) {
2349 1.1 dante addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr +
2350 1.1 dante sg_head->sg_list[sg_entry_cnt_minus_one].bytes;
2351 1.1 dante extra_bytes = addr & 0x0003;
2352 1.1 dante if ((extra_bytes != 0) &&
2353 1.1 dante ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) {
2354 1.1 dante scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
2355 1.1 dante scsiq->q1.extra_bytes = extra_bytes;
2356 1.1 dante sg_head->sg_list[sg_entry_cnt_minus_one].bytes -=
2357 1.1 dante extra_bytes;
2358 1.1 dante }
2359 1.1 dante }
2360 1.1 dante }
2361 1.1 dante }
2362 1.1 dante sg_head->entry_to_copy = sg_head->entry_cnt;
2363 1.1 dante n_q_required = AscSgListToQueue(sg_entry_cnt);
2364 1.1 dante if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required)
2365 1.1 dante || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) {
2366 1.1 dante retval = AscSendScsiQueue(sc, scsiq, n_q_required);
2367 1.1 dante }
2368 1.1 dante } else {
2369 1.1 dante if (sc->bug_fix_cntl) {
2370 1.1 dante if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
2371 1.1 dante if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) {
2372 1.1 dante addr = scsiq->q1.data_addr + scsiq->q1.data_cnt;
2373 1.1 dante extra_bytes = addr & 0x0003;
2374 1.1 dante if ((extra_bytes != 0) &&
2375 1.1 dante ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) {
2376 1.1 dante if ((scsiq->q1.data_cnt & 0x01FF) == 0) {
2377 1.1 dante scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
2378 1.1 dante scsiq->q1.data_cnt -= extra_bytes;
2379 1.1 dante scsiq->q1.extra_bytes = extra_bytes;
2380 1.1 dante }
2381 1.1 dante }
2382 1.1 dante }
2383 1.1 dante }
2384 1.1 dante }
2385 1.1 dante n_q_required = 1;
2386 1.1 dante if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) ||
2387 1.1 dante ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) {
2388 1.1 dante retval = AscSendScsiQueue(sc, scsiq, n_q_required);
2389 1.1 dante }
2390 1.1 dante }
2391 1.1 dante
2392 1.1 dante return (retval);
2393 1.1 dante }
2394 1.1 dante
2395 1.1 dante
2396 1.1 dante static int
2397 1.15 lukem AscSendScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t n_q_required)
2398 1.1 dante {
2399 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2400 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2401 1.1 dante u_int8_t free_q_head;
2402 1.1 dante u_int8_t next_qp;
2403 1.1 dante u_int8_t tid_no;
2404 1.1 dante u_int8_t target_ix;
2405 1.1 dante int retval;
2406 1.1 dante
2407 1.1 dante
2408 1.1 dante target_ix = scsiq->q2.target_ix;
2409 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
2410 1.1 dante retval = ASC_BUSY;
2411 1.1 dante free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh);
2412 1.1 dante
2413 1.1 dante if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required))
2414 1.1 dante != ASC_QLINK_END) {
2415 1.1 dante if (n_q_required > 1) {
2416 1.1 dante sc->last_q_shortage = 0;
2417 1.1 dante scsiq->sg_head->queue_cnt = n_q_required - 1;
2418 1.1 dante }
2419 1.1 dante scsiq->q1.q_no = free_q_head;
2420 1.1 dante
2421 1.1 dante if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) {
2422 1.1 dante ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp);
2423 1.1 dante sc->cur_total_qng += n_q_required;
2424 1.1 dante sc->cur_dvc_qng[tid_no]++;
2425 1.1 dante }
2426 1.1 dante }
2427 1.1 dante return (retval);
2428 1.1 dante }
2429 1.1 dante
2430 1.1 dante
2431 1.1 dante static int
2432 1.15 lukem AscPutReadySgListQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no)
2433 1.1 dante {
2434 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2435 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2436 1.1 dante int retval;
2437 1.1 dante int i;
2438 1.1 dante ASC_SG_HEAD *sg_head;
2439 1.1 dante ASC_SG_LIST_Q scsi_sg_q;
2440 1.1 dante u_int32_t saved_data_addr;
2441 1.1 dante u_int32_t saved_data_cnt;
2442 1.1 dante u_int16_t sg_list_dwords;
2443 1.1 dante u_int16_t sg_index;
2444 1.1 dante u_int16_t sg_entry_cnt;
2445 1.1 dante u_int16_t q_addr;
2446 1.1 dante u_int8_t next_qp;
2447 1.1 dante
2448 1.1 dante
2449 1.1 dante saved_data_addr = scsiq->q1.data_addr;
2450 1.1 dante saved_data_cnt = scsiq->q1.data_cnt;
2451 1.1 dante
2452 1.1 dante if ((sg_head = scsiq->sg_head) != 0) {
2453 1.1 dante scsiq->q1.data_addr = sg_head->sg_list[0].addr;
2454 1.1 dante scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
2455 1.1 dante sg_entry_cnt = sg_head->entry_cnt - 1;
2456 1.1 dante if (sg_entry_cnt != 0) {
2457 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2458 1.1 dante sg_index = 1;
2459 1.1 dante scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
2460 1.1 dante scsi_sg_q.sg_head_qp = q_no;
2461 1.1 dante scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST;
2462 1.1 dante
2463 1.1 dante for (i = 0; i < sg_head->queue_cnt; i++) {
2464 1.1 dante scsi_sg_q.seq_no = i + 1;
2465 1.1 dante if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
2466 1.1 dante sg_list_dwords = ASC_SG_LIST_PER_Q * 2;
2467 1.1 dante sg_entry_cnt -= ASC_SG_LIST_PER_Q;
2468 1.1 dante if (i == 0) {
2469 1.1 dante scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
2470 1.1 dante scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
2471 1.1 dante } else {
2472 1.1 dante scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
2473 1.1 dante scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
2474 1.1 dante }
2475 1.1 dante } else {
2476 1.1 dante scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END;
2477 1.1 dante sg_list_dwords = sg_entry_cnt << 1;
2478 1.1 dante if (i == 0) {
2479 1.1 dante scsi_sg_q.sg_list_cnt = sg_entry_cnt;
2480 1.1 dante scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
2481 1.1 dante } else {
2482 1.1 dante scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
2483 1.1 dante scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
2484 1.1 dante }
2485 1.1 dante
2486 1.1 dante sg_entry_cnt = 0;
2487 1.1 dante }
2488 1.1 dante
2489 1.1 dante next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD);
2490 1.1 dante scsi_sg_q.q_no = next_qp;
2491 1.1 dante q_addr = ASC_QNO_TO_QADDR(next_qp);
2492 1.1 dante
2493 1.1 dante /*
2494 1.1 dante * Tell the board how many entries are in the S/G list
2495 1.1 dante */
2496 1.1 dante AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
2497 1.21 christos (const u_int16_t *) & scsi_sg_q,
2498 1.7 dante sizeof(ASC_SG_LIST_Q) >> 1);
2499 1.1 dante /*
2500 1.1 dante * Tell the board the addresses of the S/G list segments
2501 1.1 dante */
2502 1.1 dante AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG,
2503 1.7 dante (u_int32_t *) & sg_head->sg_list[sg_index],
2504 1.7 dante sg_list_dwords);
2505 1.1 dante sg_index += ASC_SG_LIST_PER_Q;
2506 1.1 dante }
2507 1.1 dante }
2508 1.1 dante }
2509 1.1 dante retval = AscPutReadyQueue(sc, scsiq, q_no);
2510 1.1 dante scsiq->q1.data_addr = saved_data_addr;
2511 1.1 dante scsiq->q1.data_cnt = saved_data_cnt;
2512 1.1 dante return (retval);
2513 1.1 dante }
2514 1.1 dante
2515 1.1 dante
2516 1.1 dante static int
2517 1.15 lukem AscPutReadyQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no)
2518 1.1 dante {
2519 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2520 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2521 1.1 dante u_int16_t q_addr;
2522 1.1 dante u_int8_t tid_no;
2523 1.1 dante u_int8_t sdtr_data;
2524 1.1 dante u_int8_t syn_period_ix;
2525 1.1 dante u_int8_t syn_offset;
2526 1.1 dante
2527 1.1 dante
2528 1.1 dante if (((sc->init_sdtr & scsiq->q1.target_id) != 0) &&
2529 1.1 dante ((sc->sdtr_done & scsiq->q1.target_id) == 0)) {
2530 1.1 dante tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
2531 1.1 dante sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no);
2532 1.1 dante syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1);
2533 1.1 dante syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
2534 1.1 dante AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset);
2535 1.1 dante scsiq->q1.cntl |= ASC_QC_MSG_OUT;
2536 1.1 dante }
2537 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2538 1.1 dante
2539 1.1 dante if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) {
2540 1.1 dante scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE;
2541 1.1 dante }
2542 1.1 dante scsiq->q1.status = ASC_QS_FREE;
2543 1.1 dante AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG,
2544 1.21 christos (const u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
2545 1.1 dante
2546 1.7 dante AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq);
2547 1.1 dante
2548 1.1 dante /*
2549 1.1 dante * Let's start the command
2550 1.1 dante */
2551 1.1 dante AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
2552 1.1 dante (scsiq->q1.q_no << 8) | ASC_QS_READY);
2553 1.1 dante
2554 1.1 dante return (ASC_NOERROR);
2555 1.1 dante }
2556 1.1 dante
2557 1.1 dante
2558 1.7 dante static void
2559 1.15 lukem AscPutSCSIQ(bus_space_tag_t iot, bus_space_handle_t ioh,
2560 1.15 lukem u_int16_t addr, ASC_SCSI_Q *scsiq)
2561 1.7 dante {
2562 1.7 dante u_int16_t val;
2563 1.7 dante
2564 1.7 dante
2565 1.7 dante ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr);
2566 1.7 dante
2567 1.7 dante /* ASC_SCSIQ_1 */
2568 1.7 dante val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt);
2569 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2570 1.7 dante val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun);
2571 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2572 1.7 dante val = LO_WORD(scsiq->q1.data_addr);
2573 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2574 1.7 dante val = HI_WORD(scsiq->q1.data_addr);
2575 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2576 1.7 dante val = LO_WORD(scsiq->q1.data_cnt);
2577 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2578 1.7 dante val = HI_WORD(scsiq->q1.data_cnt);
2579 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2580 1.7 dante val = LO_WORD(scsiq->q1.sense_addr);
2581 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2582 1.7 dante val = HI_WORD(scsiq->q1.sense_addr);
2583 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2584 1.7 dante val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes);
2585 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2586 1.7 dante
2587 1.7 dante /* ASC_SCSIQ_2 */
2588 1.7 dante val = LO_WORD(scsiq->q2.ccb_ptr);
2589 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2590 1.7 dante val = HI_WORD(scsiq->q2.ccb_ptr);
2591 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2592 1.7 dante val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag);
2593 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2594 1.7 dante val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code);
2595 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
2596 1.7 dante ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id);
2597 1.7 dante }
2598 1.7 dante
2599 1.7 dante
2600 1.1 dante static int
2601 1.15 lukem AscSgListToQueue(int sg_list)
2602 1.1 dante {
2603 1.1 dante int n_sg_list_qs;
2604 1.1 dante
2605 1.1 dante n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
2606 1.1 dante if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
2607 1.1 dante n_sg_list_qs++;
2608 1.1 dante
2609 1.1 dante return (n_sg_list_qs + 1);
2610 1.1 dante }
2611 1.1 dante
2612 1.1 dante
2613 1.1 dante static u_int
2614 1.25 christos AscGetNumOfFreeQueue(ASC_SOFTC *sc, u_int8_t target_ix, u_int8_t n_qs)
2615 1.1 dante {
2616 1.1 dante u_int cur_used_qs;
2617 1.1 dante u_int cur_free_qs;
2618 1.1 dante
2619 1.1 dante
2620 1.1 dante if (n_qs == 1) {
2621 1.1 dante cur_used_qs = sc->cur_total_qng +
2622 1.1 dante sc->last_q_shortage +
2623 1.1 dante ASC_MIN_FREE_Q;
2624 1.1 dante } else {
2625 1.1 dante cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q;
2626 1.1 dante }
2627 1.1 dante
2628 1.1 dante if ((cur_used_qs + n_qs) <= sc->max_total_qng) {
2629 1.1 dante cur_free_qs = sc->max_total_qng - cur_used_qs;
2630 1.1 dante return (cur_free_qs);
2631 1.1 dante }
2632 1.1 dante if (n_qs > 1)
2633 1.1 dante if ((n_qs > sc->last_q_shortage) &&
2634 1.1 dante (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) {
2635 1.1 dante sc->last_q_shortage = n_qs;
2636 1.1 dante }
2637 1.1 dante return (0);
2638 1.1 dante }
2639 1.1 dante
2640 1.1 dante
2641 1.1 dante static u_int8_t
2642 1.15 lukem AscAllocFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh,
2643 1.15 lukem u_int8_t free_q_head)
2644 1.1 dante {
2645 1.1 dante u_int16_t q_addr;
2646 1.1 dante u_int8_t next_qp;
2647 1.1 dante u_int8_t q_status;
2648 1.1 dante
2649 1.1 dante
2650 1.1 dante q_addr = ASC_QNO_TO_QADDR(free_q_head);
2651 1.1 dante q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
2652 1.1 dante next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD);
2653 1.1 dante if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END))
2654 1.1 dante return (next_qp);
2655 1.1 dante
2656 1.1 dante return (ASC_QLINK_END);
2657 1.1 dante }
2658 1.1 dante
2659 1.1 dante
2660 1.1 dante static u_int8_t
2661 1.15 lukem AscAllocMultipleFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh,
2662 1.15 lukem u_int8_t free_q_head, u_int8_t n_free_q)
2663 1.1 dante {
2664 1.1 dante u_int8_t i;
2665 1.1 dante
2666 1.1 dante for (i = 0; i < n_free_q; i++) {
2667 1.1 dante free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head);
2668 1.1 dante if (free_q_head == ASC_QLINK_END)
2669 1.1 dante break;
2670 1.1 dante }
2671 1.1 dante
2672 1.1 dante return (free_q_head);
2673 1.1 dante }
2674 1.1 dante
2675 1.1 dante
2676 1.1 dante static int
2677 1.15 lukem AscStopQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh)
2678 1.1 dante {
2679 1.1 dante int count = 0;
2680 1.1 dante
2681 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) {
2682 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP);
2683 1.1 dante do {
2684 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) &
2685 1.1 dante ASC_STOP_ACK_RISC_STOP)
2686 1.1 dante return (1);
2687 1.1 dante
2688 1.1 dante DvcSleepMilliSecond(100);
2689 1.1 dante } while (count++ < 20);
2690 1.1 dante }
2691 1.1 dante return (0);
2692 1.1 dante }
2693 1.1 dante
2694 1.1 dante
2695 1.1 dante static void
2696 1.15 lukem AscStartQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh)
2697 1.1 dante {
2698 1.1 dante
2699 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0)
2700 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0);
2701 1.1 dante }
2702 1.1 dante
2703 1.1 dante
2704 1.1 dante static void
2705 1.15 lukem AscCleanUpBusyQueue(bus_space_tag_t iot, bus_space_handle_t ioh)
2706 1.1 dante {
2707 1.1 dante int count = 0;
2708 1.1 dante u_int8_t stop_code;
2709 1.1 dante
2710 1.1 dante
2711 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) {
2712 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q);
2713 1.1 dante do {
2714 1.1 dante stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
2715 1.1 dante if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0)
2716 1.1 dante break;
2717 1.1 dante
2718 1.1 dante DvcSleepMilliSecond(100);
2719 1.1 dante } while (count++ < 20);
2720 1.1 dante }
2721 1.1 dante }
2722 1.1 dante
2723 1.1 dante
2724 1.1 dante static int
2725 1.15 lukem _AscWaitQDone(bus_space_tag_t iot, bus_space_handle_t ioh, ASC_SCSI_Q *scsiq)
2726 1.1 dante {
2727 1.1 dante u_int16_t q_addr;
2728 1.1 dante u_int8_t q_status;
2729 1.1 dante int count = 0;
2730 1.1 dante
2731 1.1 dante while (scsiq->q1.q_no == 0);
2732 1.1 dante
2733 1.1 dante q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no);
2734 1.1 dante do {
2735 1.1 dante q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
2736 1.1 dante DvcSleepMilliSecond(100L);
2737 1.1 dante if (count++ > 30)
2738 1.1 dante return (0);
2739 1.1 dante
2740 1.1 dante } while ((q_status & ASC_QS_READY) != 0);
2741 1.1 dante
2742 1.1 dante return (1);
2743 1.1 dante }
2744 1.1 dante
2745 1.1 dante
2746 1.1 dante static int
2747 1.15 lukem AscCleanUpDiscQueue(bus_space_tag_t iot, bus_space_handle_t ioh)
2748 1.1 dante {
2749 1.1 dante int count;
2750 1.1 dante u_int8_t stop_code;
2751 1.1 dante
2752 1.1 dante count = 0;
2753 1.1 dante if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) {
2754 1.1 dante AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q);
2755 1.1 dante do {
2756 1.1 dante stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B);
2757 1.1 dante if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0)
2758 1.1 dante break;
2759 1.1 dante
2760 1.1 dante DvcSleepMilliSecond(100);
2761 1.1 dante } while (count++ < 20);
2762 1.1 dante }
2763 1.1 dante return (1);
2764 1.1 dante }
2765 1.1 dante
2766 1.1 dante
2767 1.1 dante /******************************************************************************/
2768 1.1 dante /* Abort and Reset CCB routines */
2769 1.1 dante /******************************************************************************/
2770 1.1 dante
2771 1.1 dante
2772 1.1 dante int
2773 1.15 lukem AscAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb)
2774 1.1 dante {
2775 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2776 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2777 1.1 dante int retval;
2778 1.1 dante ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready;
2779 1.1 dante
2780 1.1 dante
2781 1.1 dante retval = -1;
2782 1.1 dante saved_unit_not_ready = sc->unit_not_ready;
2783 1.1 dante sc->unit_not_ready = 0xFF;
2784 1.1 dante AscWaitISRDone(sc);
2785 1.1 dante if (AscStopQueueExe(iot, ioh) == 1) {
2786 1.1 dante if (AscRiscHaltedAbortCCB(sc, ccb) == 1) {
2787 1.1 dante retval = 1;
2788 1.1 dante AscCleanUpBusyQueue(iot, ioh);
2789 1.1 dante AscStartQueueExe(iot, ioh);
2790 1.1 dante } else {
2791 1.1 dante retval = 0;
2792 1.1 dante AscStartQueueExe(iot, ioh);
2793 1.1 dante }
2794 1.1 dante }
2795 1.1 dante sc->unit_not_ready = saved_unit_not_ready;
2796 1.1 dante
2797 1.1 dante return (retval);
2798 1.1 dante }
2799 1.1 dante
2800 1.1 dante
2801 1.1 dante static int
2802 1.15 lukem AscRiscHaltedAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb)
2803 1.1 dante {
2804 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2805 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2806 1.1 dante u_int16_t q_addr;
2807 1.1 dante u_int8_t q_no;
2808 1.1 dante ASC_QDONE_INFO scsiq_buf;
2809 1.1 dante ASC_QDONE_INFO *scsiq;
2810 1.1 dante int last_int_level;
2811 1.1 dante
2812 1.1 dante last_int_level = DvcEnterCritical();
2813 1.1 dante scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
2814 1.1 dante
2815 1.1 dante for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) {
2816 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2817 1.1 dante scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh,
2818 1.1 dante q_addr + ASC_SCSIQ_D_CCBPTR);
2819 1.8 dante if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) {
2820 1.1 dante _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count);
2821 1.1 dante if (((scsiq->q_status & ASC_QS_READY) != 0)
2822 1.1 dante && ((scsiq->q_status & ASC_QS_ABORTED) == 0)
2823 1.1 dante && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) {
2824 1.1 dante scsiq->q_status |= ASC_QS_ABORTED;
2825 1.1 dante scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST;
2826 1.1 dante AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L);
2827 1.1 dante AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
2828 1.1 dante scsiq->q_status);
2829 1.28 uwe (*sc->isr_callback)(sc, scsiq);
2830 1.1 dante return (1);
2831 1.1 dante }
2832 1.1 dante }
2833 1.1 dante }
2834 1.1 dante
2835 1.1 dante DvcLeaveCritical(last_int_level);
2836 1.1 dante return (0);
2837 1.1 dante }
2838 1.1 dante
2839 1.1 dante
2840 1.1 dante static int
2841 1.15 lukem AscRiscHaltedAbortTIX(ASC_SOFTC *sc, u_int8_t target_ix)
2842 1.1 dante {
2843 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2844 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2845 1.1 dante u_int16_t q_addr;
2846 1.1 dante u_int8_t q_no;
2847 1.1 dante ASC_QDONE_INFO scsiq_buf;
2848 1.1 dante ASC_QDONE_INFO *scsiq;
2849 1.1 dante int last_int_level;
2850 1.1 dante
2851 1.1 dante last_int_level = DvcEnterCritical();
2852 1.1 dante scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
2853 1.1 dante for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) {
2854 1.1 dante q_addr = ASC_QNO_TO_QADDR(q_no);
2855 1.1 dante _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count);
2856 1.1 dante if (((scsiq->q_status & ASC_QS_READY) != 0) &&
2857 1.1 dante ((scsiq->q_status & ASC_QS_ABORTED) == 0) &&
2858 1.1 dante ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) {
2859 1.1 dante if (scsiq->d2.target_ix == target_ix) {
2860 1.1 dante scsiq->q_status |= ASC_QS_ABORTED;
2861 1.1 dante scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST;
2862 1.1 dante AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L);
2863 1.1 dante AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS,
2864 1.1 dante scsiq->q_status);
2865 1.28 uwe (*sc->isr_callback)(sc, scsiq);
2866 1.1 dante }
2867 1.1 dante }
2868 1.1 dante }
2869 1.1 dante DvcLeaveCritical(last_int_level);
2870 1.1 dante return (1);
2871 1.1 dante }
2872 1.1 dante
2873 1.1 dante
2874 1.1 dante /*
2875 1.1 dante * AscResetDevice calls _AscWaitQDone which requires interrupt enabled,
2876 1.1 dante * so we cannot use this function with the actual NetBSD SCSI layer
2877 1.1 dante * because at boot time interrupts are disabled.
2878 1.1 dante */
2879 1.1 dante int
2880 1.15 lukem AscResetDevice(ASC_SOFTC *sc, u_char target_ix)
2881 1.1 dante {
2882 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2883 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2884 1.1 dante int retval;
2885 1.1 dante u_int8_t tid_no;
2886 1.1 dante ASC_SCSI_BIT_ID_TYPE target_id;
2887 1.1 dante int i;
2888 1.1 dante ASC_SCSI_REQ_Q scsiq_buf;
2889 1.1 dante ASC_SCSI_REQ_Q *scsiq;
2890 1.1 dante u_int8_t *buf;
2891 1.1 dante ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready;
2892 1.1 dante
2893 1.1 dante
2894 1.1 dante tid_no = ASC_TIX_TO_TID(target_ix);
2895 1.1 dante target_id = ASC_TID_TO_TARGET_ID(tid_no);
2896 1.1 dante saved_unit_not_ready = sc->unit_not_ready;
2897 1.1 dante sc->unit_not_ready = target_id;
2898 1.1 dante retval = ASC_ERROR;
2899 1.1 dante
2900 1.1 dante AscWaitTixISRDone(sc, target_ix);
2901 1.1 dante
2902 1.1 dante if (AscStopQueueExe(iot, ioh) == 1) {
2903 1.1 dante if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) {
2904 1.1 dante AscCleanUpBusyQueue(iot, ioh);
2905 1.1 dante AscStartQueueExe(iot, ioh);
2906 1.1 dante AscWaitTixISRDone(sc, target_ix);
2907 1.1 dante retval = ASC_NOERROR;
2908 1.1 dante scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf;
2909 1.1 dante buf = (u_char *) & scsiq_buf;
2910 1.1 dante for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++)
2911 1.1 dante *buf++ = 0x00;
2912 1.1 dante scsiq->q1.status = (u_char) ASC_QS_READY;
2913 1.1 dante scsiq->q2.cdb_len = 6;
2914 1.1 dante scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE;
2915 1.1 dante scsiq->q1.target_id = target_id;
2916 1.1 dante scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0);
2917 1.8 dante scsiq->cdbptr = scsiq->cdb;
2918 1.1 dante scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT;
2919 1.1 dante AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET);
2920 1.1 dante sc->unit_not_ready &= ~target_id;
2921 1.1 dante sc->sdtr_done |= target_id;
2922 1.1 dante if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) {
2923 1.1 dante sc->unit_not_ready = target_id;
2924 1.1 dante DvcSleepMilliSecond(1000);
2925 1.1 dante _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq);
2926 1.1 dante if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) {
2927 1.1 dante AscCleanUpDiscQueue(iot, ioh);
2928 1.1 dante AscStartQueueExe(iot, ioh);
2929 1.1 dante if (sc->pci_fix_asyn_xfer & target_id)
2930 1.1 dante AscSetRunChipSynRegAtID(iot, ioh, tid_no,
2931 1.7 dante ASYN_SDTR_DATA_FIX_PCI_REV_AB);
2932 1.1 dante AscWaitTixISRDone(sc, target_ix);
2933 1.1 dante }
2934 1.1 dante } else
2935 1.1 dante retval = ASC_BUSY;
2936 1.1 dante sc->sdtr_done &= ~target_id;
2937 1.1 dante } else {
2938 1.1 dante retval = ASC_ERROR;
2939 1.1 dante AscStartQueueExe(iot, ioh);
2940 1.1 dante }
2941 1.1 dante }
2942 1.1 dante sc->unit_not_ready = saved_unit_not_ready;
2943 1.1 dante return (retval);
2944 1.1 dante }
2945 1.1 dante
2946 1.1 dante
2947 1.1 dante int
2948 1.15 lukem AscResetBus(ASC_SOFTC *sc)
2949 1.1 dante {
2950 1.1 dante bus_space_tag_t iot = sc->sc_iot;
2951 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
2952 1.1 dante int retval;
2953 1.1 dante int i;
2954 1.1 dante
2955 1.1 dante
2956 1.1 dante sc->unit_not_ready = 0xFF;
2957 1.1 dante retval = ASC_NOERROR;
2958 1.1 dante
2959 1.1 dante AscWaitISRDone(sc);
2960 1.1 dante AscStopQueueExe(iot, ioh);
2961 1.1 dante sc->sdtr_done = 0;
2962 1.1 dante AscResetChipAndScsiBus(iot, ioh);
2963 1.1 dante DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000));
2964 1.1 dante AscReInitLram(sc);
2965 1.1 dante for (i = 0; i <= ASC_MAX_TID; i++) {
2966 1.1 dante sc->cur_dvc_qng[i] = 0;
2967 1.1 dante if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i))
2968 1.4 dante AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB);
2969 1.1 dante }
2970 1.1 dante
2971 1.1 dante ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR);
2972 1.1 dante if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR)
2973 1.1 dante retval = ASC_ERROR;
2974 1.1 dante
2975 1.1 dante if (AscStartChip(iot, ioh) == 0)
2976 1.1 dante retval = ASC_ERROR;
2977 1.1 dante
2978 1.1 dante AscStartQueueExe(iot, ioh);
2979 1.1 dante sc->unit_not_ready = 0;
2980 1.1 dante sc->queue_full_or_busy = 0;
2981 1.1 dante return (retval);
2982 1.1 dante }
2983 1.1 dante
2984 1.1 dante
2985 1.1 dante /******************************************************************************/
2986 1.1 dante /* Error Handling routines */
2987 1.1 dante /******************************************************************************/
2988 1.1 dante
2989 1.1 dante
2990 1.1 dante static int
2991 1.15 lukem AscSetLibErrorCode(ASC_SOFTC *sc, u_int16_t err_code)
2992 1.1 dante {
2993 1.1 dante /*
2994 1.1 dante * if(sc->err_code == 0) { sc->err_code = err_code;
2995 1.7 dante */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W,
2996 1.1 dante err_code);
2997 1.1 dante /*
2998 1.1 dante * }
2999 1.1 dante */
3000 1.1 dante return (err_code);
3001 1.1 dante }
3002 1.1 dante
3003 1.1 dante
3004 1.1 dante /******************************************************************************/
3005 1.31 andvar /* Handle bugged boards routines */
3006 1.1 dante /******************************************************************************/
3007 1.1 dante
3008 1.1 dante
3009 1.1 dante void
3010 1.15 lukem AscInquiryHandling(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq)
3011 1.1 dante {
3012 1.1 dante bus_space_tag_t iot = sc->sc_iot;
3013 1.1 dante bus_space_handle_t ioh = sc->sc_ioh;
3014 1.1 dante ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
3015 1.1 dante ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
3016 1.1 dante
3017 1.1 dante orig_init_sdtr = sc->init_sdtr;
3018 1.1 dante orig_use_tagged_qng = sc->use_tagged_qng;
3019 1.1 dante
3020 1.1 dante sc->init_sdtr &= ~tid_bit;
3021 1.1 dante sc->can_tagged_qng &= ~tid_bit;
3022 1.1 dante sc->use_tagged_qng &= ~tid_bit;
3023 1.1 dante
3024 1.1 dante if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) {
3025 1.1 dante if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync)
3026 1.1 dante sc->init_sdtr |= tid_bit;
3027 1.1 dante
3028 1.1 dante if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue)
3029 1.1 dante if (AscTagQueuingSafe(inq)) {
3030 1.1 dante sc->use_tagged_qng |= tid_bit;
3031 1.1 dante sc->can_tagged_qng |= tid_bit;
3032 1.1 dante }
3033 1.1 dante }
3034 1.1 dante if (orig_use_tagged_qng != sc->use_tagged_qng) {
3035 1.1 dante AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B,
3036 1.1 dante sc->disc_enable);
3037 1.1 dante AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B,
3038 1.1 dante sc->use_tagged_qng);
3039 1.1 dante AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B,
3040 1.1 dante sc->can_tagged_qng);
3041 1.1 dante
3042 1.1 dante sc->max_dvc_qng[tid_no] =
3043 1.1 dante sc->max_tag_qng[tid_no];
3044 1.1 dante AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no,
3045 1.1 dante sc->max_dvc_qng[tid_no]);
3046 1.1 dante }
3047 1.1 dante if (orig_init_sdtr != sc->init_sdtr)
3048 1.1 dante AscAsyncFix(sc, tid_no, inq);
3049 1.1 dante }
3050 1.1 dante
3051 1.1 dante
3052 1.1 dante static int
3053 1.15 lukem AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
3054 1.1 dante {
3055 1.1 dante if ((inq->add_len >= 32) &&
3056 1.1 dante (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) &&
3057 1.1 dante (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) {
3058 1.1 dante return 0;
3059 1.1 dante }
3060 1.1 dante return 1;
3061 1.1 dante }
3062 1.1 dante
3063 1.1 dante
3064 1.1 dante static void
3065 1.15 lukem AscAsyncFix(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq)
3066 1.1 dante {
3067 1.1 dante u_int8_t dvc_type;
3068 1.1 dante ASC_SCSI_BIT_ID_TYPE tid_bits;
3069 1.1 dante
3070 1.1 dante
3071 1.1 dante dvc_type = inq->byte0.peri_dvc_type;
3072 1.1 dante tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
3073 1.1 dante
3074 1.1 dante if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) {
3075 1.1 dante if (!(sc->init_sdtr & tid_bits)) {
3076 1.1 dante if ((dvc_type == SCSI_TYPE_CDROM) &&
3077 1.1 dante (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) {
3078 1.1 dante sc->pci_fix_asyn_xfer_always |= tid_bits;
3079 1.1 dante }
3080 1.1 dante sc->pci_fix_asyn_xfer |= tid_bits;
3081 1.1 dante if ((dvc_type == SCSI_TYPE_PROC) ||
3082 1.1 dante (dvc_type == SCSI_TYPE_SCANNER)) {
3083 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3084 1.1 dante }
3085 1.1 dante if ((dvc_type == SCSI_TYPE_SASD) &&
3086 1.1 dante (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) &&
3087 1.1 dante (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) {
3088 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3089 1.1 dante }
3090 1.1 dante if ((dvc_type == SCSI_TYPE_SASD) &&
3091 1.1 dante (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) {
3092 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3093 1.1 dante }
3094 1.1 dante if ((dvc_type == SCSI_TYPE_CDROM) &&
3095 1.1 dante (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) &&
3096 1.1 dante (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) {
3097 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3098 1.1 dante }
3099 1.1 dante if ((dvc_type == SCSI_TYPE_CDROM) &&
3100 1.1 dante (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) &&
3101 1.1 dante (AscCompareString(inq->product_id, "CDR400", 6) == 0)) {
3102 1.1 dante sc->pci_fix_asyn_xfer &= ~tid_bits;
3103 1.1 dante }
3104 1.1 dante if (sc->pci_fix_asyn_xfer & tid_bits) {
3105 1.1 dante AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no,
3106 1.1 dante ASYN_SDTR_DATA_FIX_PCI_REV_AB);
3107 1.1 dante }
3108 1.1 dante }
3109 1.1 dante }
3110 1.1 dante }
3111 1.1 dante
3112 1.1 dante
3113 1.1 dante /******************************************************************************/
3114 1.1 dante /* Miscellaneous routines */
3115 1.1 dante /******************************************************************************/
3116 1.1 dante
3117 1.1 dante
3118 1.1 dante static int
3119 1.21 christos AscCompareString(const u_char *str1, const u_char *str2, int len)
3120 1.1 dante {
3121 1.1 dante int i;
3122 1.1 dante int diff;
3123 1.1 dante
3124 1.1 dante for (i = 0; i < len; i++) {
3125 1.1 dante diff = (int) (str1[i] - str2[i]);
3126 1.1 dante if (diff != 0)
3127 1.1 dante return (diff);
3128 1.1 dante }
3129 1.1 dante
3130 1.1 dante return (0);
3131 1.1 dante }
3132 1.1 dante
3133 1.1 dante
3134 1.1 dante /******************************************************************************/
3135 1.1 dante /* Device oriented routines */
3136 1.1 dante /******************************************************************************/
3137 1.1 dante
3138 1.1 dante
3139 1.1 dante static int
3140 1.1 dante DvcEnterCritical(void)
3141 1.1 dante {
3142 1.1 dante int s;
3143 1.1 dante
3144 1.1 dante s = splbio();
3145 1.1 dante return (s);
3146 1.1 dante }
3147 1.1 dante
3148 1.1 dante
3149 1.1 dante static void
3150 1.15 lukem DvcLeaveCritical(int s)
3151 1.1 dante {
3152 1.1 dante
3153 1.1 dante splx(s);
3154 1.1 dante }
3155 1.1 dante
3156 1.1 dante
3157 1.1 dante static void
3158 1.15 lukem DvcSleepMilliSecond(u_int32_t n)
3159 1.1 dante {
3160 1.1 dante
3161 1.1 dante DELAY(n * 1000);
3162 1.1 dante }
3163 1.1 dante
3164 1.1 dante #ifdef UNUSED
3165 1.1 dante static void
3166 1.15 lukem DvcDelayMicroSecond(u_int32_t n)
3167 1.1 dante {
3168 1.1 dante
3169 1.1 dante DELAY(n);
3170 1.1 dante }
3171 1.1 dante #endif
3172 1.1 dante
3173 1.1 dante static void
3174 1.15 lukem DvcDelayNanoSecond(u_int32_t n)
3175 1.1 dante {
3176 1.1 dante
3177 1.1 dante DELAY((n + 999) / 1000);
3178 1.1 dante }
3179