advlib.c revision 1.11
1 /* $NetBSD: advlib.c,v 1.11 1999/08/07 07:20:16 thorpej Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/scsipi/scsi_all.h> 67 #include <dev/scsipi/scsipi_all.h> 68 #include <dev/scsipi/scsiconf.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_param.h> 72 #include <vm/pmap.h> 73 74 #include <dev/ic/advlib.h> 75 #include <dev/ic/adv.h> 76 #include <dev/ic/advmcode.h> 77 78 79 /* #define ASC_DEBUG */ 80 81 /******************************************************************************/ 82 /* Static functions */ 83 /******************************************************************************/ 84 85 /* Initializzation routines */ 86 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 87 u_int16_t, u_int16_t *, u_int16_t)); 88 static void AscInitLram __P((ASC_SOFTC *)); 89 static void AscInitQLinkVar __P((ASC_SOFTC *)); 90 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 91 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 92 /* 93 static u_int16_t AscGetEisaChipCfg __P((bus_space_tag_t, bus_space_handle_t)); 94 */ 95 /* Chip register routines */ 96 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 97 98 /* RISC Chip routines */ 99 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 100 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 101 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 102 u_int8_t)); 103 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 104 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 105 u_int8_t, u_int8_t)); 106 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 107 u_int8_t, u_int8_t)); 108 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 109 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 110 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 111 112 /* Lram routines */ 113 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t)); 115 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int8_t)); 117 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t)); 119 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int16_t)); 121 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t)); 123 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int32_t)); 125 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t, int)); 127 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int)); 129 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int16_t *, int)); 131 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, u_int32_t *, int)); 133 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 134 u_int16_t, int)); 135 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 136 137 /* MicroCode routines */ 138 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 139 140 /* EEProm routines */ 141 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 142 u_int8_t)); 143 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 144 u_int16_t)); 145 static void AscWaitEEPRead __P((void)); 146 static void AscWaitEEPWrite __P((void)); 147 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 148 u_int8_t)); 149 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 150 u_int8_t, u_int16_t)); 151 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 152 ASCEEP_CONFIG *, u_int16_t)); 153 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 154 ASCEEP_CONFIG *, u_int16_t)); 155 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 156 ASCEEP_CONFIG *, u_int16_t)); 157 #ifdef ASC_DEBUG 158 static void AscPrintEEPConfig __P((ASCEEP_CONFIG *, u_int16_t)); 159 #endif 160 161 /* Interrupt routines */ 162 static void AscIsrChipHalted __P((ASC_SOFTC *)); 163 static int AscIsrQDone __P((ASC_SOFTC *)); 164 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 165 static int AscWaitISRDone __P((ASC_SOFTC *)); 166 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 167 u_int16_t, ASC_QDONE_INFO *, 168 u_int32_t)); 169 static void AscGetQDoneInfo __P((bus_space_tag_t, bus_space_handle_t, u_int16_t, 170 ASC_QDONE_INFO *)); 171 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 172 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 173 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 174 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 175 u_int8_t, u_int16_t)); 176 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 177 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 178 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 179 u_int16_t)); 180 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 181 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 182 u_int8_t)); 183 184 /* Messages routines */ 185 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 186 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 187 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 188 189 /* SDTR routines */ 190 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 191 u_int8_t, u_int8_t)); 192 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 193 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 194 195 /* Queue routines */ 196 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 197 static int AscSgListToQueue __P((int)); 198 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 199 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 200 static void AscPutSCSIQ __P((bus_space_tag_t, bus_space_handle_t, 201 u_int16_t, ASC_SCSI_Q *)); 202 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 203 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 204 u_int8_t)); 205 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 206 bus_space_handle_t, 207 u_int8_t, u_int8_t)); 208 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 209 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 210 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 211 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 212 ASC_SCSI_Q *)); 213 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 214 215 /* Abort and Reset CCB routines */ 216 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, ADV_CCB *)); 217 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 218 219 /* Error Handling routines */ 220 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 221 222 /* Handle bugged borads routines */ 223 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 224 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 225 226 /* Miscellaneous routines */ 227 static int AscCompareString __P((u_char *, u_char *, int)); 228 229 /* Device oriented routines */ 230 static int DvcEnterCritical __P((void)); 231 static void DvcLeaveCritical __P((int)); 232 static void DvcSleepMilliSecond __P((u_int32_t)); 233 //static void DvcDelayMicroSecond __P((u_int32_t)); 234 static void DvcDelayNanoSecond __P((u_int32_t)); 235 236 237 /******************************************************************************/ 238 /* Initializzation routines */ 239 /******************************************************************************/ 240 241 /* 242 * This function perform the following steps: 243 * - initialize ASC_SOFTC structure with defaults values. 244 * - inquire board registers to know what kind of board it is. 245 * - keep track of bugged borads. 246 */ 247 void 248 AscInitASC_SOFTC(sc) 249 ASC_SOFTC *sc; 250 { 251 bus_space_tag_t iot = sc->sc_iot; 252 bus_space_handle_t ioh = sc->sc_ioh; 253 int i; 254 255 256 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 257 ASC_SET_CHIP_STATUS(iot, ioh, 0); 258 259 sc->bug_fix_cntl = 0; 260 sc->pci_fix_asyn_xfer = 0; 261 sc->pci_fix_asyn_xfer_always = 0; 262 sc->sdtr_done = 0; 263 sc->cur_total_qng = 0; 264 sc->last_q_shortage = 0; 265 sc->use_tagged_qng = 0; 266 sc->unit_not_ready = 0; 267 sc->queue_full_or_busy = 0; 268 sc->host_init_sdtr_index = 0; 269 sc->can_tagged_qng = 0; 270 sc->cmd_qng_enabled = 0; 271 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 272 sc->init_sdtr = 0; 273 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 274 sc->scsi_reset_wait = 3; 275 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 276 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 277 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 278 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 279 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 280 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 281 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 282 if ((sc->bus_type & ASC_IS_PCI) && 283 (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 284 sc->bus_type = ASC_IS_PCI_ULTRA; 285 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 286 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 287 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 288 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 289 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 290 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 291 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 292 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 293 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 294 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 295 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 296 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 297 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 298 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 299 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 300 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 301 sc->max_sdtr_index = 15; 302 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 303 ASC_SET_EXTRA_CONTROL(iot, ioh, 304 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 305 else if (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 306 ASC_SET_EXTRA_CONTROL(iot, ioh, 307 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 308 } else { 309 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 310 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 311 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 312 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 313 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 314 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 315 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 316 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 317 sc->max_sdtr_index = 7; 318 } 319 320 if (sc->bus_type == ASC_IS_PCI) 321 ASC_SET_EXTRA_CONTROL(iot, ioh, 322 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 323 324 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 325 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 326 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 327 sc->bus_type = ASC_IS_ISAPNP; 328 } 329 if ((sc->bus_type & ASC_IS_ISA) != 0) 330 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 331 332 for (i = 0; i <= ASC_MAX_TID; i++) { 333 sc->cur_dvc_qng[i] = 0; 334 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 335 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 336 } 337 } 338 339 340 /* 341 * This function initialize some ASC_SOFTC fields with values read from 342 * on-board EEProm. 343 */ 344 int16_t 345 AscInitFromEEP(sc) 346 ASC_SOFTC *sc; 347 { 348 bus_space_tag_t iot = sc->sc_iot; 349 bus_space_handle_t ioh = sc->sc_ioh; 350 ASCEEP_CONFIG eep_config_buf; 351 ASCEEP_CONFIG *eep_config; 352 u_int16_t chksum; 353 u_int16_t warn_code; 354 u_int16_t cfg_msw, cfg_lsw; 355 int i; 356 int write_eep = 0; 357 358 359 warn_code = 0; 360 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 361 AscStopQueueExe(iot, ioh); 362 363 AscStopChip(iot, ioh); 364 AscResetChipAndScsiBus(iot, ioh); 365 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 366 367 if ((AscStopChip(iot, ioh) == FALSE) || 368 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 369 AscResetChipAndScsiBus(iot, ioh); 370 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 371 } 372 if (AscIsChipHalted(iot, ioh) == FALSE) 373 return (-1); 374 375 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 376 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 377 return (-2); 378 379 eep_config = &eep_config_buf; 380 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 381 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 382 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 383 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 384 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 385 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 386 } 387 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 388 #ifdef ASC_DEBUG 389 AscPrintEEPConfig(eep_config, chksum); 390 #endif 391 if (chksum == 0) 392 chksum = 0xAA55; 393 394 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 395 warn_code |= ASC_WARN_AUTO_CONFIG; 396 if (sc->chip_version == 3) { 397 if (eep_config->cfg_lsw != cfg_lsw) { 398 warn_code |= ASC_WARN_EEPROM_RECOVER; 399 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 400 } 401 if (eep_config->cfg_msw != cfg_msw) { 402 warn_code |= ASC_WARN_EEPROM_RECOVER; 403 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 404 } 405 } 406 } 407 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 408 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 409 410 if (chksum != eep_config->chksum) { 411 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3050) { 412 eep_config->init_sdtr = 0xFF; 413 eep_config->disc_enable = 0xFF; 414 eep_config->start_motor = 0xFF; 415 eep_config->use_cmd_qng = 0; 416 eep_config->max_total_qng = 0xF0; 417 eep_config->max_tag_qng = 0x20; 418 eep_config->cntl = 0xBFFF; 419 eep_config->chip_scsi_id = 7; 420 eep_config->no_scam = 0; 421 eep_config->adapter_info[0] = 0; 422 eep_config->adapter_info[1] = 0; 423 eep_config->adapter_info[2] = 0; 424 eep_config->adapter_info[3] = 0; 425 #if BYTE_ORDER == BIG_ENDIAN 426 eep_config->adapter_info[5] = 0; 427 /* Indicate EEPROM-less board. */ 428 eep_config->adapter_info[4] = 0xBB; 429 #else 430 eep_config->adapter_info[4] = 0; 431 /* Indicate EEPROM-less board. */ 432 eep_config->adapter_info[5] = 0xBB; 433 #endif 434 } else { 435 write_eep = 1; 436 warn_code |= ASC_WARN_EEPROM_CHKSUM; 437 } 438 } 439 sc->sdtr_enable = eep_config->init_sdtr; 440 sc->disc_enable = eep_config->disc_enable; 441 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 442 sc->isa_dma_speed = eep_config->isa_dma_speed; 443 sc->start_motor = eep_config->start_motor; 444 sc->dvc_cntl = eep_config->cntl; 445 #if BYTE_ORDER == BIG_ENDIAN 446 sc->adapter_info[0] = eep_config->adapter_info[1]; 447 sc->adapter_info[1] = eep_config->adapter_info[0]; 448 sc->adapter_info[2] = eep_config->adapter_info[3]; 449 sc->adapter_info[3] = eep_config->adapter_info[2]; 450 sc->adapter_info[4] = eep_config->adapter_info[5]; 451 sc->adapter_info[5] = eep_config->adapter_info[4]; 452 #else 453 sc->adapter_info[0] = eep_config->adapter_info[0]; 454 sc->adapter_info[1] = eep_config->adapter_info[1]; 455 sc->adapter_info[2] = eep_config->adapter_info[2]; 456 sc->adapter_info[3] = eep_config->adapter_info[3]; 457 sc->adapter_info[4] = eep_config->adapter_info[4]; 458 sc->adapter_info[5] = eep_config->adapter_info[5]; 459 #endif 460 461 if (!AscTestExternalLram(iot, ioh)) { 462 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 463 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 464 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 465 } else { 466 eep_config->cfg_msw |= 0x0800; 467 cfg_msw |= 0x0800; 468 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 469 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 470 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 471 } 472 } 473 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 474 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 475 476 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 477 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 478 479 if (eep_config->max_tag_qng > eep_config->max_total_qng) 480 eep_config->max_tag_qng = eep_config->max_total_qng; 481 482 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 483 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 484 485 sc->max_total_qng = eep_config->max_total_qng; 486 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 487 eep_config->use_cmd_qng) { 488 eep_config->disc_enable = eep_config->use_cmd_qng; 489 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 490 } 491 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 492 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 493 494 eep_config->chip_scsi_id &= ASC_MAX_TID; 495 sc->chip_scsi_id = eep_config->chip_scsi_id; 496 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 497 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 498 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 499 } 500 for (i = 0; i <= ASC_MAX_TID; i++) { 501 sc->max_tag_qng[i] = eep_config->max_tag_qng; 502 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 503 (sc->host_init_sdtr_index << 4); 504 } 505 506 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 507 if (write_eep) { 508 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 509 #ifdef ASC_DEBUG 510 AscPrintEEPConfig(eep_config, 0); 511 #endif 512 } 513 514 return (warn_code); 515 } 516 517 518 u_int16_t 519 AscInitFromASC_SOFTC(sc) 520 ASC_SOFTC *sc; 521 { 522 bus_space_tag_t iot = sc->sc_iot; 523 bus_space_handle_t ioh = sc->sc_ioh; 524 u_int16_t cfg_msw; 525 u_int16_t warn_code; 526 u_int16_t pci_device_id = sc->pci_device_id; 527 528 529 warn_code = 0; 530 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 531 532 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 533 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 534 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 535 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 536 } 537 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 538 sc->disc_enable = sc->cmd_qng_enabled; 539 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 540 } 541 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 542 warn_code |= ASC_WARN_AUTO_CONFIG; 543 } 544 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 545 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 546 } 547 if (sc->bus_type & ASC_IS_PCI) { 548 cfg_msw &= 0xFFC0; 549 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 550 551 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 552 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 553 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 554 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 555 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 556 } 557 } 558 } else if (sc->bus_type == ASC_IS_ISAPNP) { 559 if (sc->chip_version == ASC_CHIP_VER_ASYN_BUG) { 560 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 561 } 562 } 563 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 564 565 if (sc->bus_type & ASC_IS_ISA) { 566 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 567 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 568 } 569 return (warn_code); 570 } 571 572 573 /* 574 * - Initialize RISC chip 575 * - Intialize Lram 576 * - Load uCode into Lram 577 * - Enable Interrupts 578 */ 579 int 580 AscInitDriver(sc) 581 ASC_SOFTC *sc; 582 { 583 bus_space_tag_t iot = sc->sc_iot; 584 bus_space_handle_t ioh = sc->sc_ioh; 585 u_int32_t chksum; 586 587 588 if (!AscFindSignature(iot, ioh)) 589 return (1); 590 591 AscDisableInterrupt(iot, ioh); 592 593 AscInitLram(sc); 594 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 595 asc_mcode_size); 596 if (chksum != asc_mcode_chksum) 597 return (2); 598 599 if (AscInitMicroCodeVar(sc) == 0) 600 return (3); 601 602 AscEnableInterrupt(iot, ioh); 603 604 return (0); 605 } 606 607 608 int 609 AscFindSignature(iot, ioh) 610 bus_space_tag_t iot; 611 bus_space_handle_t ioh; 612 { 613 u_int16_t sig_word; 614 615 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 616 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 617 if (sig_word == ASC_1000_ID0W || 618 sig_word == ASC_1000_ID0W_FIX) 619 return (1); 620 } 621 return (0); 622 } 623 624 625 static void 626 AscInitLram(sc) 627 ASC_SOFTC *sc; 628 { 629 bus_space_tag_t iot = sc->sc_iot; 630 bus_space_handle_t ioh = sc->sc_ioh; 631 u_int8_t i; 632 u_int16_t s_addr; 633 634 635 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 636 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 637 638 i = ASC_MIN_ACTIVE_QNO; 639 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 640 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 641 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 642 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 643 i++; 644 s_addr += ASC_QBLK_SIZE; 645 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 647 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 648 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 649 } 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 651 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 652 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 653 i++; 654 s_addr += ASC_QBLK_SIZE; 655 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 657 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 658 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 659 } 660 } 661 662 663 void 664 AscReInitLram(sc) 665 ASC_SOFTC *sc; 666 { 667 668 AscInitLram(sc); 669 AscInitQLinkVar(sc); 670 } 671 672 673 static void 674 AscInitQLinkVar(sc) 675 ASC_SOFTC *sc; 676 { 677 bus_space_tag_t iot = sc->sc_iot; 678 bus_space_handle_t ioh = sc->sc_ioh; 679 u_int8_t i; 680 u_int16_t lram_addr; 681 682 683 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 684 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 685 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 686 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 687 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 688 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 689 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 690 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 691 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 692 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 693 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 694 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 695 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 696 lram_addr = ASC_QADR_BEG; 697 for (i = 0; i < 32; i++, lram_addr += 2) 698 AscWriteLramWord(iot, ioh, lram_addr, 0); 699 } 700 701 702 static int 703 AscResetChipAndScsiBus(bus_space_tag_t iot, 704 bus_space_handle_t ioh) 705 { 706 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 707 708 AscStopChip(iot, ioh); 709 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 710 711 DvcDelayNanoSecond(60000); 712 713 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 714 AscSetChipIH(iot, ioh, ASC_INS_HALT); 715 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 716 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 717 718 DvcSleepMilliSecond(200); 719 720 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 721 AscStartChip(iot, ioh); 722 723 DvcSleepMilliSecond(200); 724 725 return (AscIsChipHalted(iot, ioh)); 726 } 727 728 729 static u_int16_t 730 AscGetChipBusType(iot, ioh) 731 bus_space_tag_t iot; 732 bus_space_handle_t ioh; 733 { 734 u_int16_t chip_ver; 735 736 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 737 /* if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 738 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 739 if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) { 740 return (ASC_IS_EISA); 741 } 742 else { 743 return (ASC_IS_VL); 744 } 745 } 746 */ if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 747 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 748 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 749 return (ASC_IS_ISAPNP); 750 751 return (ASC_IS_ISA); 752 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 753 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 754 return (ASC_IS_PCI); 755 756 return (0); 757 } 758 759 /* 760 static u_int16_t 761 AscGetEisaChipCfg(iot, ioh) 762 bus_space_tag_t iot; 763 bus_space_handle_t ioh; 764 { 765 int eisa_cfg_iop; 766 767 eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK); 768 return (inw(eisa_cfg_iop)); 769 } 770 */ 771 772 /******************************************************************************/ 773 /* Chip register routines */ 774 /******************************************************************************/ 775 776 777 static void 778 AscSetBank(iot, ioh, bank) 779 bus_space_tag_t iot; 780 bus_space_handle_t ioh; 781 u_int8_t bank; 782 { 783 u_int8_t val; 784 785 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 786 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 787 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 788 ASC_CC_CHIP_RESET)); 789 790 switch (bank) { 791 case 1: 792 val |= ASC_CC_BANK_ONE; 793 break; 794 795 case 2: 796 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 797 break; 798 799 default: 800 val &= ~ASC_CC_BANK_ONE; 801 } 802 803 ASC_SET_CHIP_CONTROL(iot, ioh, val); 804 return; 805 } 806 807 808 /******************************************************************************/ 809 /* Chip routines */ 810 /******************************************************************************/ 811 812 813 static int 814 AscStartChip(iot, ioh) 815 bus_space_tag_t iot; 816 bus_space_handle_t ioh; 817 { 818 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 819 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 820 return (0); 821 822 return (1); 823 } 824 825 826 static int 827 AscStopChip(iot, ioh) 828 bus_space_tag_t iot; 829 bus_space_handle_t ioh; 830 { 831 u_int8_t cc_val; 832 833 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 834 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 835 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 836 AscSetChipIH(iot, ioh, ASC_INS_HALT); 837 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 838 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 839 return (0); 840 841 return (1); 842 } 843 844 845 static u_int8_t 846 AscSetChipScsiID(iot, ioh, new_id) 847 bus_space_tag_t iot; 848 bus_space_handle_t ioh; 849 u_int8_t new_id; 850 { 851 u_int16_t cfg_lsw; 852 853 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 854 return (new_id); 855 856 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 857 cfg_lsw &= 0xF8FF; 858 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 859 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 860 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 861 } 862 863 864 static u_int8_t 865 AscGetChipScsiCtrl(iot, ioh) 866 bus_space_tag_t iot; 867 bus_space_handle_t ioh; 868 { 869 u_int8_t scsi_ctrl; 870 871 AscSetBank(iot, ioh, 1); 872 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 873 AscSetBank(iot, ioh, 0); 874 return (scsi_ctrl); 875 } 876 877 878 static int 879 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 880 bus_space_tag_t iot; 881 bus_space_handle_t ioh; 882 u_int8_t tid_no; 883 u_int8_t sdtr_data; 884 { 885 int retval = FALSE; 886 887 if (AscHostReqRiscHalt(iot, ioh)) { 888 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 889 AscStartChip(iot, ioh); 890 } 891 return (retval); 892 } 893 894 895 static int 896 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 897 bus_space_tag_t iot; 898 bus_space_handle_t ioh; 899 u_int8_t id; 900 u_int8_t sdtr_data; 901 { 902 ASC_SCSI_BIT_ID_TYPE org_id; 903 int i; 904 int sta = TRUE; 905 906 AscSetBank(iot, ioh, 1); 907 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 908 for (i = 0; i <= ASC_MAX_TID; i++) 909 if (org_id == (0x01 << i)) 910 break; 911 912 org_id = i; 913 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 914 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 915 AscSetBank(iot, ioh, 0); 916 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 917 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 918 sta = FALSE; 919 } else 920 sta = FALSE; 921 922 AscSetBank(iot, ioh, 1); 923 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 924 AscSetBank(iot, ioh, 0); 925 return (sta); 926 } 927 928 929 static int 930 AscHostReqRiscHalt(iot, ioh) 931 bus_space_tag_t iot; 932 bus_space_handle_t ioh; 933 { 934 int count = 0; 935 int retval = 0; 936 u_int8_t saved_stop_code; 937 938 939 if (AscIsChipHalted(iot, ioh)) 940 return (1); 941 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 942 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 943 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 944 945 do { 946 if (AscIsChipHalted(iot, ioh)) { 947 retval = 1; 948 break; 949 } 950 DvcSleepMilliSecond(100); 951 } while (count++ < 20); 952 953 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 954 955 return (retval); 956 } 957 958 959 static int 960 AscIsChipHalted(iot, ioh) 961 bus_space_tag_t iot; 962 bus_space_handle_t ioh; 963 { 964 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 965 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 966 return (1); 967 968 return (0); 969 } 970 971 972 static void 973 AscSetChipIH(iot, ioh, ins_code) 974 bus_space_tag_t iot; 975 bus_space_handle_t ioh; 976 u_int16_t ins_code; 977 { 978 AscSetBank(iot, ioh, 1); 979 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 980 AscSetBank(iot, ioh, 0); 981 982 return; 983 } 984 985 986 /******************************************************************************/ 987 /* Lram routines */ 988 /******************************************************************************/ 989 990 991 static u_int8_t 992 AscReadLramByte(iot, ioh, addr) 993 bus_space_tag_t iot; 994 bus_space_handle_t ioh; 995 u_int16_t addr; 996 { 997 u_int8_t byte_data; 998 u_int16_t word_data; 999 1000 1001 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1002 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1003 1004 if (addr & 1) { 1005 /* odd address */ 1006 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1007 } else { 1008 /* even address */ 1009 byte_data = (u_int8_t) (word_data & 0xFF); 1010 } 1011 1012 return (byte_data); 1013 } 1014 1015 1016 static void 1017 AscWriteLramByte(iot, ioh, addr, data) 1018 bus_space_tag_t iot; 1019 bus_space_handle_t ioh; 1020 u_int16_t addr; 1021 u_int8_t data; 1022 { 1023 u_int16_t word_data; 1024 1025 1026 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1027 1028 if (addr & 1) { 1029 /* odd address */ 1030 word_data &= 0x00FF; 1031 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1032 } else { 1033 /* even address */ 1034 word_data &= 0xFF00; 1035 word_data |= ((u_int16_t) data) & 0x00FF; 1036 } 1037 1038 AscWriteLramWord(iot, ioh, addr, word_data); 1039 } 1040 1041 1042 static u_int16_t 1043 AscReadLramWord(iot, ioh, addr) 1044 bus_space_tag_t iot; 1045 bus_space_handle_t ioh; 1046 u_int16_t addr; 1047 { 1048 1049 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1050 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1051 } 1052 1053 1054 static void 1055 AscWriteLramWord(iot, ioh, addr, data) 1056 bus_space_tag_t iot; 1057 bus_space_handle_t ioh; 1058 u_int16_t addr; 1059 u_int16_t data; 1060 { 1061 1062 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1063 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1064 } 1065 1066 1067 static u_int32_t 1068 AscReadLramDWord(iot, ioh, addr) 1069 bus_space_tag_t iot; 1070 bus_space_handle_t ioh; 1071 u_int16_t addr; 1072 { 1073 u_int16_t low_word, hi_word; 1074 1075 1076 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1077 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1078 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1079 1080 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1081 } 1082 1083 1084 static void 1085 AscWriteLramDWord(iot, ioh, addr, data) 1086 bus_space_tag_t iot; 1087 bus_space_handle_t ioh; 1088 u_int16_t addr; 1089 u_int32_t data; 1090 { 1091 1092 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1093 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1094 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1095 } 1096 1097 1098 static void 1099 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1100 bus_space_tag_t iot; 1101 bus_space_handle_t ioh; 1102 u_int16_t s_addr; 1103 u_int16_t s_words; 1104 int count; 1105 { 1106 int i; 1107 1108 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1109 for (i = 0; i < count; i++) 1110 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1111 } 1112 1113 1114 static void 1115 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1116 bus_space_tag_t iot; 1117 bus_space_handle_t ioh; 1118 u_int16_t s_addr; 1119 u_int16_t *s_buffer; 1120 int words; 1121 { 1122 int i; 1123 1124 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1125 for (i = 0; i < words; i++, s_buffer++) 1126 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1127 } 1128 1129 1130 static void 1131 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1132 bus_space_tag_t iot; 1133 bus_space_handle_t ioh; 1134 u_int16_t s_addr; 1135 u_int16_t *s_buffer; 1136 int words; 1137 { 1138 int i; 1139 1140 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1141 for (i = 0; i < words; i++, s_buffer++) 1142 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1143 } 1144 1145 1146 static void 1147 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1148 bus_space_tag_t iot; 1149 bus_space_handle_t ioh; 1150 u_int16_t s_addr; 1151 u_int32_t *s_buffer; 1152 int dwords; 1153 { 1154 int i; 1155 u_int32_t *pw; 1156 1157 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1158 1159 pw = s_buffer; 1160 for (i = 0; i < dwords; i++, pw++) { 1161 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1162 DELAY(1); 1163 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1164 } 1165 } 1166 1167 1168 static u_int32_t 1169 AscMemSumLramWord(iot, ioh, s_addr, words) 1170 bus_space_tag_t iot; 1171 bus_space_handle_t ioh; 1172 u_int16_t s_addr; 1173 int words; 1174 { 1175 u_int32_t sum = 0L; 1176 u_int16_t i; 1177 1178 1179 for (i = 0; i < words; i++, s_addr += 2) 1180 sum += AscReadLramWord(iot, ioh, s_addr); 1181 1182 return (sum); 1183 } 1184 1185 1186 static int 1187 AscTestExternalLram(iot, ioh) 1188 bus_space_tag_t iot; 1189 bus_space_handle_t ioh; 1190 { 1191 u_int16_t q_addr; 1192 u_int16_t saved_word; 1193 int retval; 1194 1195 1196 retval = 0; 1197 q_addr = ASC_QNO_TO_QADDR(241); 1198 saved_word = AscReadLramWord(iot, ioh, q_addr); 1199 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1200 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1201 DvcSleepMilliSecond(10); 1202 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1203 1204 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1205 retval = 1; 1206 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1207 } 1208 return (retval); 1209 } 1210 1211 1212 /******************************************************************************/ 1213 /* MicroCode routines */ 1214 /******************************************************************************/ 1215 1216 1217 static u_int16_t 1218 AscInitMicroCodeVar(sc) 1219 ASC_SOFTC *sc; 1220 { 1221 bus_space_tag_t iot = sc->sc_iot; 1222 bus_space_handle_t ioh = sc->sc_ioh; 1223 u_int32_t phy_addr; 1224 int i; 1225 1226 1227 for (i = 0; i <= ASC_MAX_TID; i++) 1228 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1229 sc->sdtr_period_offset[i]); 1230 1231 AscInitQLinkVar(sc); 1232 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1233 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1234 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1235 1236 phy_addr = (sc->overrun_buf & 0xfffffff8) + 8; 1237 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1238 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1239 ASC_OVERRUN_BSIZE - 8); 1240 1241 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1242 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1243 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1244 1245 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1246 return (0); 1247 } 1248 if (AscStartChip(iot, ioh) != 1) { 1249 return (0); 1250 } 1251 return (1); 1252 } 1253 1254 1255 static u_int32_t 1256 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 1257 bus_space_tag_t iot; 1258 bus_space_handle_t ioh; 1259 u_int16_t s_addr; 1260 u_int16_t *mcode_buf; 1261 u_int16_t mcode_size; 1262 { 1263 u_int32_t chksum; 1264 u_int16_t mcode_word_size; 1265 u_int16_t mcode_chksum; 1266 1267 mcode_word_size = mcode_size >> 1; 1268 /* clear board memory */ 1269 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1270 /* copy uCode to board memory */ 1271 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1272 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1273 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1274 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1275 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1276 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1277 1278 return (chksum); 1279 } 1280 1281 1282 /******************************************************************************/ 1283 /* EEProm routines */ 1284 /******************************************************************************/ 1285 1286 1287 static int 1288 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1289 bus_space_tag_t iot; 1290 bus_space_handle_t ioh; 1291 u_int8_t cmd_reg; 1292 { 1293 u_int8_t read_back; 1294 int retry; 1295 1296 retry = 0; 1297 1298 while (TRUE) { 1299 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1300 DvcSleepMilliSecond(1); 1301 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1302 if (read_back == cmd_reg) 1303 return (1); 1304 1305 if (retry++ > ASC_EEP_MAX_RETRY) 1306 return (0); 1307 } 1308 } 1309 1310 1311 static int 1312 AscWriteEEPDataReg(iot, ioh, data_reg) 1313 bus_space_tag_t iot; 1314 bus_space_handle_t ioh; 1315 u_int16_t data_reg; 1316 { 1317 u_int16_t read_back; 1318 int retry; 1319 1320 retry = 0; 1321 while (TRUE) { 1322 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1323 DvcSleepMilliSecond(1); 1324 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1325 if (read_back == data_reg) 1326 return (1); 1327 1328 if (retry++ > ASC_EEP_MAX_RETRY) 1329 return (0); 1330 } 1331 } 1332 1333 1334 static void 1335 AscWaitEEPRead(void) 1336 { 1337 1338 DvcSleepMilliSecond(1); 1339 } 1340 1341 1342 static void 1343 AscWaitEEPWrite(void) 1344 { 1345 1346 DvcSleepMilliSecond(1); 1347 } 1348 1349 1350 static u_int16_t 1351 AscReadEEPWord(iot, ioh, addr) 1352 bus_space_tag_t iot; 1353 bus_space_handle_t ioh; 1354 u_int8_t addr; 1355 { 1356 u_int16_t read_wval; 1357 u_int8_t cmd_reg; 1358 1359 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1360 AscWaitEEPRead(); 1361 cmd_reg = addr | ASC_EEP_CMD_READ; 1362 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1363 AscWaitEEPRead(); 1364 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1365 AscWaitEEPRead(); 1366 1367 return (read_wval); 1368 } 1369 1370 1371 static u_int16_t 1372 AscWriteEEPWord(iot, ioh, addr, word_val) 1373 bus_space_tag_t iot; 1374 bus_space_handle_t ioh; 1375 u_int8_t addr; 1376 u_int16_t word_val; 1377 { 1378 u_int16_t read_wval; 1379 1380 read_wval = AscReadEEPWord(iot, ioh, addr); 1381 if (read_wval != word_val) { 1382 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1383 AscWaitEEPRead(); 1384 AscWriteEEPDataReg(iot, ioh, word_val); 1385 AscWaitEEPRead(); 1386 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1387 AscWaitEEPWrite(); 1388 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1389 AscWaitEEPRead(); 1390 return (AscReadEEPWord(iot, ioh, addr)); 1391 } 1392 return (read_wval); 1393 } 1394 1395 1396 static u_int16_t 1397 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1398 bus_space_tag_t iot; 1399 bus_space_handle_t ioh; 1400 ASCEEP_CONFIG *cfg_buf; 1401 u_int16_t bus_type; 1402 { 1403 u_int16_t wval; 1404 u_int16_t sum; 1405 u_int16_t *wbuf; 1406 int cfg_beg; 1407 int cfg_end; 1408 int s_addr; 1409 int isa_pnp_wsize; 1410 1411 1412 wbuf = (u_int16_t *) cfg_buf; 1413 sum = 0; 1414 isa_pnp_wsize = 0; 1415 1416 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1417 wval = AscReadEEPWord(iot, ioh, s_addr); 1418 sum += wval; 1419 *wbuf = wval; 1420 } 1421 1422 if (bus_type & ASC_IS_VL) { 1423 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1424 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1425 } else { 1426 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1427 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1428 } 1429 1430 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1431 wval = AscReadEEPWord(iot, ioh, s_addr); 1432 sum += wval; 1433 *wbuf = wval; 1434 } 1435 1436 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1437 1438 return (sum); 1439 } 1440 1441 1442 static int 1443 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1444 bus_space_tag_t iot; 1445 bus_space_handle_t ioh; 1446 ASCEEP_CONFIG *cfg_buf; 1447 u_int16_t bus_type; 1448 { 1449 int retry; 1450 int n_error; 1451 1452 retry = 0; 1453 while (TRUE) { 1454 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1455 break; 1456 1457 if (++retry > ASC_EEP_MAX_RETRY) 1458 break; 1459 } 1460 1461 return (n_error); 1462 } 1463 1464 1465 static int 1466 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1467 bus_space_tag_t iot; 1468 bus_space_handle_t ioh; 1469 ASCEEP_CONFIG *cfg_buf; 1470 u_int16_t bus_type; 1471 { 1472 int n_error; 1473 u_int16_t *wbuf; 1474 u_int16_t sum; 1475 int s_addr; 1476 int cfg_beg; 1477 int cfg_end; 1478 1479 wbuf = (u_int16_t *) cfg_buf; 1480 n_error = 0; 1481 sum = 0; 1482 1483 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1484 sum += *wbuf; 1485 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1486 n_error++; 1487 } 1488 1489 if (bus_type & ASC_IS_VL) { 1490 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1491 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1492 } else { 1493 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1494 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1495 } 1496 1497 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1498 sum += *wbuf; 1499 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1500 n_error++; 1501 } 1502 1503 *wbuf = sum; 1504 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1505 n_error++; 1506 1507 wbuf = (u_int16_t *) cfg_buf; 1508 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1509 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1510 n_error++; 1511 } 1512 1513 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1514 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1515 n_error++; 1516 } 1517 1518 return (n_error); 1519 } 1520 1521 1522 #ifdef ASC_DEBUG 1523 static void 1524 AscPrintEEPConfig(eep_config, chksum) 1525 ASCEEP_CONFIG *eep_config; 1526 u_int16_t chksum; 1527 { 1528 printf("---- ASC EEprom settings ----\n"); 1529 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1530 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1531 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1532 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1533 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1534 printf("start_motor = 0x%x\n", eep_config->start_motor); 1535 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1536 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1537 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1538 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1539 printf("no_scam = %d\n", eep_config->no_scam); 1540 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1541 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1542 printf("cntl = 0x%x\n", eep_config->cntl); 1543 #if BYTE_ORDER == BIG_ENDIAN 1544 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1545 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1546 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1547 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1548 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1549 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1550 #else 1551 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1552 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1553 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1554 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1555 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1556 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1557 #endif 1558 printf("checksum = 0x%x\n", eep_config->chksum); 1559 printf("calculated checksum = 0x%x\n", chksum); 1560 printf("-----------------------------\n"); 1561 } 1562 #endif 1563 1564 1565 /******************************************************************************/ 1566 /* Interrupt routines */ 1567 /******************************************************************************/ 1568 1569 1570 int 1571 AscISR(sc) 1572 ASC_SOFTC *sc; 1573 { 1574 bus_space_tag_t iot = sc->sc_iot; 1575 bus_space_handle_t ioh = sc->sc_ioh; 1576 u_int16_t chipstat; 1577 u_int16_t saved_ram_addr; 1578 u_int8_t ctrl_reg; 1579 u_int8_t saved_ctrl_reg; 1580 int int_pending; 1581 int status; 1582 u_int8_t host_flag; 1583 1584 1585 int_pending = FALSE; 1586 1587 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1588 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1589 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1590 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1591 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1592 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1593 int_pending = TRUE; 1594 sc->sdtr_done = 0; 1595 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1596 1597 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1598 1599 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1600 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1601 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1602 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1603 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1604 } 1605 } 1606 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1607 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1608 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1609 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1610 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1611 1612 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1613 AscAckInterrupt(iot, ioh); 1614 int_pending = TRUE; 1615 1616 if ((chipstat & ASC_CSW_HALTED) && 1617 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1618 AscIsrChipHalted(sc); 1619 saved_ctrl_reg &= ~ASC_CC_HALT; 1620 } else { 1621 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1622 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1623 } else { 1624 do { 1625 if ((status = AscIsrQDone(sc)) == 1) 1626 break; 1627 } while (status == 0x11); 1628 } 1629 1630 if (status & 0x80) 1631 int_pending = -1; 1632 } 1633 } 1634 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1635 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1636 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1637 1638 return (1); 1639 /* return(int_pending); */ 1640 } 1641 1642 1643 static int 1644 AscIsrQDone(sc) 1645 ASC_SOFTC *sc; 1646 { 1647 u_int8_t next_qp; 1648 u_int8_t n_q_used; 1649 u_int8_t sg_list_qp; 1650 u_int8_t sg_queue_cnt; 1651 u_int8_t q_cnt; 1652 u_int8_t done_q_tail; 1653 u_int8_t tid_no; 1654 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1655 ASC_SCSI_BIT_ID_TYPE target_id; 1656 bus_space_tag_t iot = sc->sc_iot; 1657 bus_space_handle_t ioh = sc->sc_ioh; 1658 u_int16_t q_addr; 1659 u_int16_t sg_q_addr; 1660 u_int8_t cur_target_qng; 1661 ASC_QDONE_INFO scsiq_buf; 1662 ASC_QDONE_INFO *scsiq; 1663 ASC_ISR_CALLBACK asc_isr_callback; 1664 1665 1666 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1667 n_q_used = 1; 1668 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1669 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1670 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1671 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1672 1673 if (next_qp != ASC_QLINK_END) { 1674 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1675 q_addr = ASC_QNO_TO_QADDR(next_qp); 1676 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1677 sc->max_dma_count); 1678 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1679 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1680 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1681 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1682 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1683 sg_q_addr = q_addr; 1684 sg_list_qp = next_qp; 1685 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1686 sg_list_qp = AscReadLramByte(iot, ioh, 1687 sg_q_addr + ASC_SCSIQ_B_FWD); 1688 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1689 if (sg_list_qp == ASC_QLINK_END) { 1690 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1691 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1692 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1693 panic("AscIsrQDone: Corrupted SG list encountered"); 1694 } 1695 AscWriteLramByte(iot, ioh, 1696 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1697 } 1698 n_q_used = sg_queue_cnt + 1; 1699 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1700 } 1701 if (sc->queue_full_or_busy & target_id) { 1702 cur_target_qng = AscReadLramByte(iot, ioh, 1703 ASC_QADR_BEG + scsiq->d2.target_ix); 1704 1705 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1706 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1707 scsi_busy &= ~target_id; 1708 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1709 sc->queue_full_or_busy &= ~target_id; 1710 } 1711 } 1712 if (sc->cur_total_qng >= n_q_used) { 1713 sc->cur_total_qng -= n_q_used; 1714 if (sc->cur_dvc_qng[tid_no] != 0) { 1715 sc->cur_dvc_qng[tid_no]--; 1716 } 1717 } else { 1718 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1719 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1720 panic("AscIsrQDone: Attempting to free more queues than are active"); 1721 } 1722 1723 if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) || 1724 ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1725 return (0x11); 1726 } else if (scsiq->q_status == ASC_QS_DONE) { 1727 scsiq->remain_bytes += scsiq->extra_bytes; 1728 1729 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1730 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1731 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1732 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1733 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1734 } 1735 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1736 AscStopChip(iot, ioh); 1737 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1738 DvcDelayNanoSecond(60000); 1739 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1740 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1741 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1742 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1743 } 1744 } 1745 (*asc_isr_callback) (sc, scsiq); 1746 1747 return (1); 1748 } else { 1749 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1750 panic("AscIsrQDone: completed scsiq with unknown status"); 1751 1752 return (0x80); 1753 } 1754 } 1755 return (0); 1756 } 1757 1758 1759 /* 1760 * handle all the conditions that may halt the board 1761 * waiting us to intervene 1762 */ 1763 static void 1764 AscIsrChipHalted(sc) 1765 ASC_SOFTC *sc; 1766 { 1767 bus_space_tag_t iot = sc->sc_iot; 1768 bus_space_handle_t ioh = sc->sc_ioh; 1769 EXT_MSG out_msg; 1770 u_int16_t int_halt_code; 1771 u_int16_t halt_q_addr; 1772 u_int8_t halt_qp; 1773 u_int8_t target_ix; 1774 u_int8_t tag_code; 1775 u_int8_t q_status; 1776 u_int8_t q_cntl; 1777 u_int8_t tid_no; 1778 u_int8_t cur_dvc_qng; 1779 u_int8_t asyn_sdtr; 1780 u_int8_t scsi_status; 1781 u_int8_t sdtr_data; 1782 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1783 ASC_SCSI_BIT_ID_TYPE target_id; 1784 1785 1786 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1787 1788 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1789 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1790 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1791 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1792 tid_no = ASC_TIX_TO_TID(target_ix); 1793 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1794 1795 if (sc->pci_fix_asyn_xfer & target_id) { 1796 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1797 } else { 1798 asyn_sdtr = 0; 1799 } 1800 1801 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1802 if (sc->pci_fix_asyn_xfer & target_id) { 1803 AscSetChipSDTR(iot, ioh, 0, tid_no); 1804 sc->sdtr_data[tid_no] = 0; 1805 } 1806 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1807 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1808 if (sc->pci_fix_asyn_xfer & target_id) { 1809 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1810 sc->sdtr_data[tid_no] = asyn_sdtr; 1811 } 1812 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1813 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1814 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1815 tid_no, asyn_sdtr); 1816 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1817 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1818 q_cntl |= ASC_QC_REQ_SENSE; 1819 1820 if (sc->init_sdtr & target_id) { 1821 sc->sdtr_done &= ~target_id; 1822 1823 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1824 q_cntl |= ASC_QC_MSG_OUT; 1825 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1826 (sc->max_sdtr_index - 1)], 1827 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1828 } 1829 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1830 1831 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1832 tag_code &= 0xDC; 1833 1834 if ((sc->pci_fix_asyn_xfer & target_id) && 1835 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1836 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1837 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1838 } 1839 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1840 1841 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1842 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1843 1844 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1845 1846 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1847 scsi_busy &= ~target_id; 1848 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1849 1850 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1851 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1852 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1853 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1854 1855 if ((out_msg.msg_type == MS_EXTEND) && 1856 (out_msg.msg_len == MS_SDTR_LEN) && 1857 (out_msg.msg_req == MS_SDTR_CODE)) { 1858 sc->init_sdtr &= ~target_id; 1859 sc->sdtr_done &= ~target_id; 1860 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1861 sc->sdtr_data[tid_no] = asyn_sdtr; 1862 } 1863 q_cntl &= ~ASC_QC_MSG_OUT; 1864 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1865 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1866 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1867 scsi_status = AscReadLramByte(iot, ioh, 1868 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1869 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1870 1871 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1872 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1873 scsi_busy |= target_id; 1874 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1875 sc->queue_full_or_busy |= target_id; 1876 1877 if (scsi_status == SS_QUEUE_FULL) { 1878 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1879 cur_dvc_qng -= 1; 1880 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1881 1882 AscWriteLramByte(iot, ioh, 1883 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1884 1885 #if ASC_QUEUE_FLOW_CONTROL 1886 if ((sc->device[tid_no] != NULL) && 1887 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1888 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1889 } 1890 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1891 } 1892 } 1893 } 1894 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1895 } 1896 return; 1897 } 1898 1899 1900 static int 1901 AscWaitTixISRDone(sc, target_ix) 1902 ASC_SOFTC *sc; 1903 u_int8_t target_ix; 1904 { 1905 u_int8_t cur_req; 1906 u_int8_t tid_no; 1907 int i = 0; 1908 1909 tid_no = ASC_TIX_TO_TID(target_ix); 1910 while (i++ < 10) { 1911 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1912 break; 1913 1914 DvcSleepMilliSecond(1000L); 1915 if (sc->cur_dvc_qng[tid_no] == cur_req) 1916 break; 1917 } 1918 return (1); 1919 } 1920 1921 static int 1922 AscWaitISRDone(sc) 1923 ASC_SOFTC *sc; 1924 { 1925 int tid; 1926 1927 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1928 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1929 1930 return (1); 1931 } 1932 1933 1934 static u_int8_t 1935 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1936 bus_space_tag_t iot; 1937 bus_space_handle_t ioh; 1938 u_int16_t q_addr; 1939 ASC_QDONE_INFO *scsiq; 1940 u_int32_t max_dma_count; 1941 { 1942 u_int16_t _val; 1943 u_int8_t sg_queue_cnt; 1944 1945 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 1946 1947 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1948 scsiq->q_status = LO_BYTE(_val); 1949 scsiq->q_no = HI_BYTE(_val); 1950 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1951 scsiq->cntl = LO_BYTE(_val); 1952 sg_queue_cnt = HI_BYTE(_val); 1953 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 1954 scsiq->sense_len = LO_BYTE(_val); 1955 scsiq->extra_bytes = HI_BYTE(_val); 1956 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 1957 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 1958 scsiq->remain_bytes &= max_dma_count; 1959 1960 return (sg_queue_cnt); 1961 } 1962 1963 1964 static void 1965 AscGetQDoneInfo(iot, ioh, addr, scsiq) 1966 bus_space_tag_t iot; 1967 bus_space_handle_t ioh; 1968 u_int16_t addr; 1969 ASC_QDONE_INFO *scsiq; 1970 { 1971 u_int16_t val; 1972 1973 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1974 1975 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1976 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1977 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1978 scsiq->d2.target_ix = LO_BYTE(val); 1979 scsiq->d2.flag = HI_BYTE(val); 1980 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1981 scsiq->d2.cdb_len = LO_BYTE(val); 1982 scsiq->d2.tag_code = HI_BYTE(val); 1983 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1984 1985 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1986 scsiq->d3.done_stat = LO_BYTE(val); 1987 scsiq->d3.host_stat = HI_BYTE(val); 1988 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1989 scsiq->d3.scsi_stat = LO_BYTE(val); 1990 scsiq->d3.scsi_msg = HI_BYTE(val); 1991 } 1992 1993 1994 static void 1995 AscToggleIRQAct(iot, ioh) 1996 bus_space_tag_t iot; 1997 bus_space_handle_t ioh; 1998 { 1999 2000 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 2001 ASC_SET_CHIP_STATUS(iot, ioh, 0); 2002 } 2003 2004 2005 static void 2006 AscDisableInterrupt(iot, ioh) 2007 bus_space_tag_t iot; 2008 bus_space_handle_t ioh; 2009 { 2010 u_int16_t cfg; 2011 2012 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2013 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 2014 } 2015 2016 2017 static void 2018 AscEnableInterrupt(iot, ioh) 2019 bus_space_tag_t iot; 2020 bus_space_handle_t ioh; 2021 { 2022 u_int16_t cfg; 2023 2024 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2025 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2026 } 2027 2028 2029 u_int8_t 2030 AscGetChipIRQ(iot, ioh, bus_type) 2031 bus_space_tag_t iot; 2032 bus_space_handle_t ioh; 2033 u_int16_t bus_type; 2034 { 2035 u_int16_t cfg_lsw; 2036 u_int8_t chip_irq; 2037 2038 2039 /* if (bus_type & ASC_IS_EISA) { 2040 cfg_lsw = AscGetEisaChipCfg(iot, ioh); 2041 chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 2042 if((chip_irq == 13) || (chip_irq > 15)) 2043 return (0); 2044 return(chip_irq); 2045 } 2046 */ if ((bus_type & ASC_IS_VL) != 0) { 2047 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2048 chip_irq = (cfg_lsw >> 2) & 0x07; 2049 if ((chip_irq == 0) || 2050 (chip_irq == 4) || 2051 (chip_irq == 7)) { 2052 return (0); 2053 } 2054 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2055 } 2056 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2057 chip_irq = (cfg_lsw >> 2) & 0x03; 2058 if (chip_irq == 3) 2059 chip_irq += 2; 2060 return (chip_irq + ASC_MIN_IRQ_NO); 2061 } 2062 2063 2064 static u_int8_t 2065 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2066 bus_space_tag_t iot; 2067 bus_space_handle_t ioh; 2068 u_int8_t irq_no; 2069 u_int16_t bus_type; 2070 { 2071 u_int16_t cfg_lsw; 2072 2073 2074 if (bus_type & ASC_IS_VL) { 2075 if (irq_no) { 2076 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2077 irq_no = 0; 2078 else 2079 irq_no -= ASC_MIN_IRQ_NO - 1; 2080 } 2081 2082 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2083 cfg_lsw |= 0x0010; 2084 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2085 AscToggleIRQAct(iot, ioh); 2086 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2087 cfg_lsw |= (irq_no & 0x07) << 2; 2088 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2089 AscToggleIRQAct(iot, ioh); 2090 2091 return (AscGetChipIRQ(iot, ioh, bus_type)); 2092 } 2093 if (bus_type & ASC_IS_ISA) { 2094 if (irq_no == 15) 2095 irq_no -= 2; 2096 irq_no -= ASC_MIN_IRQ_NO; 2097 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2098 cfg_lsw |= (irq_no & 0x03) << 2; 2099 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2100 2101 return (AscGetChipIRQ(iot, ioh, bus_type)); 2102 } 2103 return (0); 2104 } 2105 2106 2107 static void 2108 AscAckInterrupt(iot, ioh) 2109 bus_space_tag_t iot; 2110 bus_space_handle_t ioh; 2111 { 2112 u_int8_t host_flag; 2113 u_int8_t risc_flag; 2114 u_int16_t loop; 2115 2116 2117 loop = 0; 2118 do { 2119 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2120 if (loop++ > 0x7FFF) 2121 break; 2122 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2123 2124 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2125 (~ASC_HOST_FLAG_ACK_INT); 2126 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2127 host_flag | ASC_HOST_FLAG_ACK_INT); 2128 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2129 2130 loop = 0; 2131 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2132 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2133 if (loop++ > 3) 2134 break; 2135 } 2136 2137 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2138 } 2139 2140 2141 static u_int32_t 2142 AscGetMaxDmaCount(bus_type) 2143 u_int16_t bus_type; 2144 { 2145 if (bus_type & ASC_IS_ISA) 2146 return (ASC_MAX_ISA_DMA_COUNT); 2147 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2148 return (ASC_MAX_VL_DMA_COUNT); 2149 return (ASC_MAX_PCI_DMA_COUNT); 2150 } 2151 2152 2153 u_int16_t 2154 AscGetIsaDmaChannel(iot, ioh) 2155 bus_space_tag_t iot; 2156 bus_space_handle_t ioh; 2157 { 2158 u_int16_t channel; 2159 2160 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2161 if (channel == 0x03) 2162 return (0); 2163 else if (channel == 0x00) 2164 return (7); 2165 return (channel + 4); 2166 } 2167 2168 2169 static u_int16_t 2170 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2171 bus_space_tag_t iot; 2172 bus_space_handle_t ioh; 2173 u_int16_t dma_channel; 2174 { 2175 u_int16_t cfg_lsw; 2176 u_int8_t value; 2177 2178 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2179 if (dma_channel == 7) 2180 value = 0x00; 2181 else 2182 value = dma_channel - 4; 2183 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2184 cfg_lsw |= value; 2185 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2186 return (AscGetIsaDmaChannel(iot, ioh)); 2187 } 2188 return (0); 2189 } 2190 2191 2192 static u_int8_t 2193 AscGetIsaDmaSpeed(iot, ioh) 2194 bus_space_tag_t iot; 2195 bus_space_handle_t ioh; 2196 { 2197 u_int8_t speed_value; 2198 2199 AscSetBank(iot, ioh, 1); 2200 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2201 speed_value &= 0x07; 2202 AscSetBank(iot, ioh, 0); 2203 return (speed_value); 2204 } 2205 2206 2207 static u_int8_t 2208 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2209 bus_space_tag_t iot; 2210 bus_space_handle_t ioh; 2211 u_int8_t speed_value; 2212 { 2213 speed_value &= 0x07; 2214 AscSetBank(iot, ioh, 1); 2215 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2216 AscSetBank(iot, ioh, 0); 2217 return (AscGetIsaDmaSpeed(iot, ioh)); 2218 } 2219 2220 2221 /******************************************************************************/ 2222 /* Messages routines */ 2223 /******************************************************************************/ 2224 2225 2226 static void 2227 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2228 ASC_SOFTC *sc; 2229 u_int16_t halt_q_addr; 2230 u_int8_t q_cntl; 2231 ASC_SCSI_BIT_ID_TYPE target_id; 2232 int tid_no; 2233 u_int8_t asyn_sdtr; 2234 { 2235 bus_space_tag_t iot = sc->sc_iot; 2236 bus_space_handle_t ioh = sc->sc_ioh; 2237 EXT_MSG ext_msg; 2238 u_int8_t sdtr_data; 2239 int sdtr_accept; 2240 2241 2242 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2243 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2244 2245 if (ext_msg.msg_type == MS_EXTEND && 2246 ext_msg.msg_req == MS_SDTR_CODE && 2247 ext_msg.msg_len == MS_SDTR_LEN) { 2248 sdtr_accept = TRUE; 2249 2250 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2251 sdtr_accept = FALSE; 2252 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2253 } 2254 if ((ext_msg.xfer_period < 2255 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2256 (ext_msg.xfer_period > 2257 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2258 sdtr_accept = FALSE; 2259 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2260 } 2261 if (sdtr_accept) { 2262 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2263 ext_msg.req_ack_offset); 2264 if (sdtr_data == 0xFF) { 2265 q_cntl |= ASC_QC_MSG_OUT; 2266 sc->init_sdtr &= ~target_id; 2267 sc->sdtr_done &= ~target_id; 2268 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2269 sc->sdtr_data[tid_no] = asyn_sdtr; 2270 } 2271 } 2272 if (ext_msg.req_ack_offset == 0) { 2273 q_cntl &= ~ASC_QC_MSG_OUT; 2274 sc->init_sdtr &= ~target_id; 2275 sc->sdtr_done &= ~target_id; 2276 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2277 } else { 2278 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2279 q_cntl &= ~ASC_QC_MSG_OUT; 2280 sc->sdtr_done |= target_id; 2281 sc->init_sdtr |= target_id; 2282 sc->pci_fix_asyn_xfer &= ~target_id; 2283 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2284 ext_msg.req_ack_offset); 2285 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2286 sc->sdtr_data[tid_no] = sdtr_data; 2287 } else { 2288 q_cntl |= ASC_QC_MSG_OUT; 2289 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2290 ext_msg.req_ack_offset); 2291 sc->pci_fix_asyn_xfer &= ~target_id; 2292 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2293 ext_msg.req_ack_offset); 2294 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2295 sc->sdtr_data[tid_no] = sdtr_data; 2296 sc->sdtr_done |= target_id; 2297 sc->init_sdtr |= target_id; 2298 } 2299 } 2300 } else if (ext_msg.msg_type == MS_EXTEND && 2301 ext_msg.msg_req == MS_WDTR_CODE && 2302 ext_msg.msg_len == MS_WDTR_LEN) { 2303 ext_msg.wdtr_width = 0; 2304 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2305 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2306 q_cntl |= ASC_QC_MSG_OUT; 2307 } else { 2308 ext_msg.msg_type = M1_MSG_REJECT; 2309 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2310 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2311 q_cntl |= ASC_QC_MSG_OUT; 2312 } 2313 2314 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2315 } 2316 2317 2318 static u_int8_t 2319 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2320 ASC_SOFTC *sc; 2321 u_int8_t sdtr_period; 2322 u_int8_t sdtr_offset; 2323 { 2324 bus_space_tag_t iot = sc->sc_iot; 2325 bus_space_handle_t ioh = sc->sc_ioh; 2326 EXT_MSG sdtr_buf; 2327 u_int8_t sdtr_period_index; 2328 2329 2330 sdtr_buf.msg_type = MS_EXTEND; 2331 sdtr_buf.msg_len = MS_SDTR_LEN; 2332 sdtr_buf.msg_req = MS_SDTR_CODE; 2333 sdtr_buf.xfer_period = sdtr_period; 2334 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2335 sdtr_buf.req_ack_offset = sdtr_offset; 2336 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2337 sc->max_sdtr_index) { 2338 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2339 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2340 return ((sdtr_period_index << 4) | sdtr_offset); 2341 } else { 2342 sdtr_buf.req_ack_offset = 0; 2343 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2344 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2345 return (0); 2346 } 2347 } 2348 2349 2350 /******************************************************************************/ 2351 /* SDTR routines */ 2352 /******************************************************************************/ 2353 2354 2355 static void 2356 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2357 bus_space_tag_t iot; 2358 bus_space_handle_t ioh; 2359 u_int8_t sdtr_data; 2360 u_int8_t tid_no; 2361 { 2362 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2363 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2364 } 2365 2366 2367 static u_int8_t 2368 AscCalSDTRData(sc, sdtr_period, syn_offset) 2369 ASC_SOFTC *sc; 2370 u_int8_t sdtr_period; 2371 u_int8_t syn_offset; 2372 { 2373 u_int8_t byte; 2374 u_int8_t sdtr_period_ix; 2375 2376 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2377 if (sdtr_period_ix > sc->max_sdtr_index) 2378 return (0xFF); 2379 2380 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2381 return (byte); 2382 } 2383 2384 2385 static u_int8_t 2386 AscGetSynPeriodIndex(sc, syn_time) 2387 ASC_SOFTC *sc; 2388 u_int8_t syn_time; 2389 { 2390 u_int8_t *period_table; 2391 int max_index; 2392 int min_index; 2393 int i; 2394 2395 period_table = sc->sdtr_period_tbl; 2396 max_index = sc->max_sdtr_index; 2397 min_index = sc->host_init_sdtr_index; 2398 if ((syn_time <= period_table[max_index])) { 2399 for (i = min_index; i < (max_index - 1); i++) { 2400 if (syn_time <= period_table[i]) 2401 return (i); 2402 } 2403 2404 return (max_index); 2405 } else 2406 return (max_index + 1); 2407 } 2408 2409 2410 /******************************************************************************/ 2411 /* Queue routines */ 2412 /******************************************************************************/ 2413 2414 /* 2415 * Send a command to the board 2416 */ 2417 int 2418 AscExeScsiQueue(sc, scsiq) 2419 ASC_SOFTC *sc; 2420 ASC_SCSI_Q *scsiq; 2421 { 2422 bus_space_tag_t iot = sc->sc_iot; 2423 bus_space_handle_t ioh = sc->sc_ioh; 2424 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2425 int retval; 2426 int n_q_required; 2427 int disable_syn_offset_one_fix; 2428 int i; 2429 u_int32_t addr; 2430 u_int16_t sg_entry_cnt = 0; 2431 u_int16_t sg_entry_cnt_minus_one = 0; 2432 u_int8_t target_ix; 2433 u_int8_t tid_no; 2434 u_int8_t sdtr_data; 2435 u_int8_t extra_bytes; 2436 u_int8_t scsi_cmd; 2437 u_int32_t data_cnt; 2438 2439 2440 scsiq->q1.q_no = 0; 2441 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2442 scsiq->q1.extra_bytes = 0; 2443 2444 retval = ASC_BUSY; 2445 target_ix = scsiq->q2.target_ix; 2446 tid_no = ASC_TIX_TO_TID(target_ix); 2447 n_q_required = 1; 2448 2449 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2450 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2451 sc->sdtr_done &= ~scsiq->q1.target_id; 2452 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2453 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2454 (sc->max_sdtr_index - 1)], 2455 sdtr_data & ASC_SYN_MAX_OFFSET); 2456 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2457 } 2458 /* 2459 * if there is just one segment into S/G list then 2460 * map it as it was a single request, filling 2461 * data_addr and data_cnt of ASC_SCSIQ structure. 2462 */ 2463 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2464 sg_entry_cnt = sg_head->entry_cnt; 2465 2466 if (sg_entry_cnt < 1) 2467 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2468 sg_entry_cnt); 2469 2470 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2471 panic("AscExeScsiQueue: Queue with too many segs."); 2472 2473 if (sg_entry_cnt == 1) { 2474 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2475 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2476 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2477 } 2478 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2479 } 2480 scsi_cmd = scsiq->cdbptr[0]; 2481 disable_syn_offset_one_fix = FALSE; 2482 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2483 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2484 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2485 data_cnt = 0; 2486 for (i = 0; i < sg_entry_cnt; i++) 2487 data_cnt += sg_head->sg_list[i].bytes; 2488 } else { 2489 data_cnt = scsiq->q1.data_cnt; 2490 } 2491 2492 if (data_cnt != 0ul) { 2493 if (data_cnt < 512ul) { 2494 disable_syn_offset_one_fix = TRUE; 2495 } else { 2496 if (scsi_cmd == SCSICMD_Inquiry || 2497 scsi_cmd == SCSICMD_RequestSense || 2498 scsi_cmd == SCSICMD_ReadCapacity || 2499 scsi_cmd == SCSICMD_ReadTOC || 2500 scsi_cmd == SCSICMD_ModeSelect6 || 2501 scsi_cmd == SCSICMD_ModeSense6 || 2502 scsi_cmd == SCSICMD_ModeSelect10 || 2503 scsi_cmd == SCSICMD_ModeSense10) { 2504 disable_syn_offset_one_fix = TRUE; 2505 } 2506 } 2507 } 2508 } 2509 if (disable_syn_offset_one_fix) { 2510 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2511 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2512 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2513 } else { 2514 scsiq->q2.tag_code &= 0x23; 2515 } 2516 2517 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2518 if (sc->bug_fix_cntl) { 2519 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2520 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2521 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2522 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2523 extra_bytes = addr & 0x0003; 2524 if ((extra_bytes != 0) && 2525 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2526 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2527 scsiq->q1.extra_bytes = extra_bytes; 2528 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2529 extra_bytes; 2530 } 2531 } 2532 } 2533 } 2534 sg_head->entry_to_copy = sg_head->entry_cnt; 2535 n_q_required = AscSgListToQueue(sg_entry_cnt); 2536 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2537 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2538 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2539 } 2540 } else { 2541 if (sc->bug_fix_cntl) { 2542 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2543 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2544 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2545 extra_bytes = addr & 0x0003; 2546 if ((extra_bytes != 0) && 2547 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2548 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2549 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2550 scsiq->q1.data_cnt -= extra_bytes; 2551 scsiq->q1.extra_bytes = extra_bytes; 2552 } 2553 } 2554 } 2555 } 2556 } 2557 n_q_required = 1; 2558 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2559 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2560 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2561 } 2562 } 2563 2564 return (retval); 2565 } 2566 2567 2568 static int 2569 AscSendScsiQueue(sc, scsiq, n_q_required) 2570 ASC_SOFTC *sc; 2571 ASC_SCSI_Q *scsiq; 2572 u_int8_t n_q_required; 2573 { 2574 bus_space_tag_t iot = sc->sc_iot; 2575 bus_space_handle_t ioh = sc->sc_ioh; 2576 u_int8_t free_q_head; 2577 u_int8_t next_qp; 2578 u_int8_t tid_no; 2579 u_int8_t target_ix; 2580 int retval; 2581 2582 2583 target_ix = scsiq->q2.target_ix; 2584 tid_no = ASC_TIX_TO_TID(target_ix); 2585 retval = ASC_BUSY; 2586 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2587 2588 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2589 != ASC_QLINK_END) { 2590 if (n_q_required > 1) { 2591 sc->last_q_shortage = 0; 2592 scsiq->sg_head->queue_cnt = n_q_required - 1; 2593 } 2594 scsiq->q1.q_no = free_q_head; 2595 2596 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2597 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2598 sc->cur_total_qng += n_q_required; 2599 sc->cur_dvc_qng[tid_no]++; 2600 } 2601 } 2602 return (retval); 2603 } 2604 2605 2606 static int 2607 AscPutReadySgListQueue(sc, scsiq, q_no) 2608 ASC_SOFTC *sc; 2609 ASC_SCSI_Q *scsiq; 2610 u_int8_t q_no; 2611 { 2612 bus_space_tag_t iot = sc->sc_iot; 2613 bus_space_handle_t ioh = sc->sc_ioh; 2614 int retval; 2615 int i; 2616 ASC_SG_HEAD *sg_head; 2617 ASC_SG_LIST_Q scsi_sg_q; 2618 u_int32_t saved_data_addr; 2619 u_int32_t saved_data_cnt; 2620 u_int16_t sg_list_dwords; 2621 u_int16_t sg_index; 2622 u_int16_t sg_entry_cnt; 2623 u_int16_t q_addr; 2624 u_int8_t next_qp; 2625 2626 2627 saved_data_addr = scsiq->q1.data_addr; 2628 saved_data_cnt = scsiq->q1.data_cnt; 2629 2630 if ((sg_head = scsiq->sg_head) != 0) { 2631 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2632 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2633 sg_entry_cnt = sg_head->entry_cnt - 1; 2634 if (sg_entry_cnt != 0) { 2635 q_addr = ASC_QNO_TO_QADDR(q_no); 2636 sg_index = 1; 2637 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2638 scsi_sg_q.sg_head_qp = q_no; 2639 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2640 2641 for (i = 0; i < sg_head->queue_cnt; i++) { 2642 scsi_sg_q.seq_no = i + 1; 2643 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2644 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2645 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2646 if (i == 0) { 2647 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2648 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2649 } else { 2650 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2651 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2652 } 2653 } else { 2654 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2655 sg_list_dwords = sg_entry_cnt << 1; 2656 if (i == 0) { 2657 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2658 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2659 } else { 2660 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2661 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2662 } 2663 2664 sg_entry_cnt = 0; 2665 } 2666 2667 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2668 scsi_sg_q.q_no = next_qp; 2669 q_addr = ASC_QNO_TO_QADDR(next_qp); 2670 2671 /* 2672 * Tell the board how many entries are in the S/G list 2673 */ 2674 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2675 (u_int16_t *) & scsi_sg_q, 2676 sizeof(ASC_SG_LIST_Q) >> 1); 2677 /* 2678 * Tell the board the addresses of the S/G list segments 2679 */ 2680 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2681 (u_int32_t *) & sg_head->sg_list[sg_index], 2682 sg_list_dwords); 2683 sg_index += ASC_SG_LIST_PER_Q; 2684 } 2685 } 2686 } 2687 retval = AscPutReadyQueue(sc, scsiq, q_no); 2688 scsiq->q1.data_addr = saved_data_addr; 2689 scsiq->q1.data_cnt = saved_data_cnt; 2690 return (retval); 2691 } 2692 2693 2694 static int 2695 AscPutReadyQueue(sc, scsiq, q_no) 2696 ASC_SOFTC *sc; 2697 ASC_SCSI_Q *scsiq; 2698 u_int8_t q_no; 2699 { 2700 bus_space_tag_t iot = sc->sc_iot; 2701 bus_space_handle_t ioh = sc->sc_ioh; 2702 u_int16_t q_addr; 2703 u_int8_t tid_no; 2704 u_int8_t sdtr_data; 2705 u_int8_t syn_period_ix; 2706 u_int8_t syn_offset; 2707 2708 2709 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2710 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2711 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2712 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2713 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2714 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2715 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2716 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2717 } 2718 q_addr = ASC_QNO_TO_QADDR(q_no); 2719 2720 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2721 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2722 } 2723 scsiq->q1.status = ASC_QS_FREE; 2724 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2725 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2726 2727 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2728 2729 /* 2730 * Let's start the command 2731 */ 2732 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2733 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2734 2735 return (ASC_NOERROR); 2736 } 2737 2738 2739 static void 2740 AscPutSCSIQ(iot, ioh, addr, scsiq) 2741 bus_space_tag_t iot; 2742 bus_space_handle_t ioh; 2743 u_int16_t addr; 2744 ASC_SCSI_Q *scsiq; 2745 { 2746 u_int16_t val; 2747 2748 2749 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2750 2751 /* ASC_SCSIQ_1 */ 2752 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2753 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2754 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2755 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2756 val = LO_WORD(scsiq->q1.data_addr); 2757 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2758 val = HI_WORD(scsiq->q1.data_addr); 2759 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2760 val = LO_WORD(scsiq->q1.data_cnt); 2761 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2762 val = HI_WORD(scsiq->q1.data_cnt); 2763 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2764 val = LO_WORD(scsiq->q1.sense_addr); 2765 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2766 val = HI_WORD(scsiq->q1.sense_addr); 2767 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2768 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2769 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2770 2771 /* ASC_SCSIQ_2 */ 2772 val = LO_WORD(scsiq->q2.ccb_ptr); 2773 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2774 val = HI_WORD(scsiq->q2.ccb_ptr); 2775 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2776 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2777 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2778 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2779 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2780 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2781 } 2782 2783 2784 static int 2785 AscSgListToQueue(sg_list) 2786 int sg_list; 2787 { 2788 int n_sg_list_qs; 2789 2790 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2791 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2792 n_sg_list_qs++; 2793 2794 return (n_sg_list_qs + 1); 2795 } 2796 2797 2798 static u_int 2799 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2800 ASC_SOFTC *sc; 2801 u_int8_t target_ix; 2802 u_int8_t n_qs; 2803 { 2804 u_int cur_used_qs; 2805 u_int cur_free_qs; 2806 2807 2808 if (n_qs == 1) { 2809 cur_used_qs = sc->cur_total_qng + 2810 sc->last_q_shortage + 2811 ASC_MIN_FREE_Q; 2812 } else { 2813 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2814 } 2815 2816 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2817 cur_free_qs = sc->max_total_qng - cur_used_qs; 2818 return (cur_free_qs); 2819 } 2820 if (n_qs > 1) 2821 if ((n_qs > sc->last_q_shortage) && 2822 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2823 sc->last_q_shortage = n_qs; 2824 } 2825 return (0); 2826 } 2827 2828 2829 static u_int8_t 2830 AscAllocFreeQueue(iot, ioh, free_q_head) 2831 bus_space_tag_t iot; 2832 bus_space_handle_t ioh; 2833 u_int8_t free_q_head; 2834 { 2835 u_int16_t q_addr; 2836 u_int8_t next_qp; 2837 u_int8_t q_status; 2838 2839 2840 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2841 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2842 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2843 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2844 return (next_qp); 2845 2846 return (ASC_QLINK_END); 2847 } 2848 2849 2850 static u_int8_t 2851 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2852 bus_space_tag_t iot; 2853 bus_space_handle_t ioh; 2854 u_int8_t free_q_head; 2855 u_int8_t n_free_q; 2856 { 2857 u_int8_t i; 2858 2859 for (i = 0; i < n_free_q; i++) { 2860 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2861 if (free_q_head == ASC_QLINK_END) 2862 break; 2863 } 2864 2865 return (free_q_head); 2866 } 2867 2868 2869 static int 2870 AscStopQueueExe(iot, ioh) 2871 bus_space_tag_t iot; 2872 bus_space_handle_t ioh; 2873 { 2874 int count = 0; 2875 2876 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2877 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2878 do { 2879 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2880 ASC_STOP_ACK_RISC_STOP) 2881 return (1); 2882 2883 DvcSleepMilliSecond(100); 2884 } while (count++ < 20); 2885 } 2886 return (0); 2887 } 2888 2889 2890 static void 2891 AscStartQueueExe(iot, ioh) 2892 bus_space_tag_t iot; 2893 bus_space_handle_t ioh; 2894 { 2895 2896 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2897 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2898 } 2899 2900 2901 static void 2902 AscCleanUpBusyQueue(iot, ioh) 2903 bus_space_tag_t iot; 2904 bus_space_handle_t ioh; 2905 { 2906 int count = 0; 2907 u_int8_t stop_code; 2908 2909 2910 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2911 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2912 do { 2913 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2914 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2915 break; 2916 2917 DvcSleepMilliSecond(100); 2918 } while (count++ < 20); 2919 } 2920 } 2921 2922 2923 static int 2924 _AscWaitQDone(iot, ioh, scsiq) 2925 bus_space_tag_t iot; 2926 bus_space_handle_t ioh; 2927 ASC_SCSI_Q *scsiq; 2928 { 2929 u_int16_t q_addr; 2930 u_int8_t q_status; 2931 int count = 0; 2932 2933 while (scsiq->q1.q_no == 0); 2934 2935 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2936 do { 2937 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2938 DvcSleepMilliSecond(100L); 2939 if (count++ > 30) 2940 return (0); 2941 2942 } while ((q_status & ASC_QS_READY) != 0); 2943 2944 return (1); 2945 } 2946 2947 2948 static int 2949 AscCleanUpDiscQueue(iot, ioh) 2950 bus_space_tag_t iot; 2951 bus_space_handle_t ioh; 2952 { 2953 int count; 2954 u_int8_t stop_code; 2955 2956 count = 0; 2957 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2958 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 2959 do { 2960 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2961 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 2962 break; 2963 2964 DvcSleepMilliSecond(100); 2965 } while (count++ < 20); 2966 } 2967 return (1); 2968 } 2969 2970 2971 /******************************************************************************/ 2972 /* Abort and Reset CCB routines */ 2973 /******************************************************************************/ 2974 2975 2976 int 2977 AscAbortCCB(sc, ccb) 2978 ASC_SOFTC *sc; 2979 ADV_CCB *ccb; 2980 { 2981 bus_space_tag_t iot = sc->sc_iot; 2982 bus_space_handle_t ioh = sc->sc_ioh; 2983 int retval; 2984 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2985 2986 2987 retval = -1; 2988 saved_unit_not_ready = sc->unit_not_ready; 2989 sc->unit_not_ready = 0xFF; 2990 AscWaitISRDone(sc); 2991 if (AscStopQueueExe(iot, ioh) == 1) { 2992 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 2993 retval = 1; 2994 AscCleanUpBusyQueue(iot, ioh); 2995 AscStartQueueExe(iot, ioh); 2996 } else { 2997 retval = 0; 2998 AscStartQueueExe(iot, ioh); 2999 } 3000 } 3001 sc->unit_not_ready = saved_unit_not_ready; 3002 3003 return (retval); 3004 } 3005 3006 3007 static int 3008 AscRiscHaltedAbortCCB(sc, ccb) 3009 ASC_SOFTC *sc; 3010 ADV_CCB *ccb; 3011 { 3012 bus_space_tag_t iot = sc->sc_iot; 3013 bus_space_handle_t ioh = sc->sc_ioh; 3014 u_int16_t q_addr; 3015 u_int8_t q_no; 3016 ASC_QDONE_INFO scsiq_buf; 3017 ASC_QDONE_INFO *scsiq; 3018 ASC_ISR_CALLBACK asc_isr_callback; 3019 int last_int_level; 3020 3021 3022 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3023 last_int_level = DvcEnterCritical(); 3024 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3025 3026 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3027 q_addr = ASC_QNO_TO_QADDR(q_no); 3028 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 3029 q_addr + ASC_SCSIQ_D_CCBPTR); 3030 if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) { 3031 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3032 if (((scsiq->q_status & ASC_QS_READY) != 0) 3033 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 3034 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3035 scsiq->q_status |= ASC_QS_ABORTED; 3036 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3037 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3038 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3039 scsiq->q_status); 3040 (*asc_isr_callback) (sc, scsiq); 3041 return (1); 3042 } 3043 } 3044 } 3045 3046 DvcLeaveCritical(last_int_level); 3047 return (0); 3048 } 3049 3050 3051 static int 3052 AscRiscHaltedAbortTIX(sc, target_ix) 3053 ASC_SOFTC *sc; 3054 u_int8_t target_ix; 3055 { 3056 bus_space_tag_t iot = sc->sc_iot; 3057 bus_space_handle_t ioh = sc->sc_ioh; 3058 u_int16_t q_addr; 3059 u_int8_t q_no; 3060 ASC_QDONE_INFO scsiq_buf; 3061 ASC_QDONE_INFO *scsiq; 3062 ASC_ISR_CALLBACK asc_isr_callback; 3063 int last_int_level; 3064 3065 3066 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3067 last_int_level = DvcEnterCritical(); 3068 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3069 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3070 q_addr = ASC_QNO_TO_QADDR(q_no); 3071 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3072 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3073 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3074 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3075 if (scsiq->d2.target_ix == target_ix) { 3076 scsiq->q_status |= ASC_QS_ABORTED; 3077 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3078 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3079 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3080 scsiq->q_status); 3081 (*asc_isr_callback) (sc, scsiq); 3082 } 3083 } 3084 } 3085 DvcLeaveCritical(last_int_level); 3086 return (1); 3087 } 3088 3089 3090 /* 3091 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3092 * so we cannot use this function with the actual NetBSD SCSI layer 3093 * because at boot time interrupts are disabled. 3094 */ 3095 int 3096 AscResetDevice(sc, target_ix) 3097 ASC_SOFTC *sc; 3098 u_char target_ix; 3099 { 3100 bus_space_tag_t iot = sc->sc_iot; 3101 bus_space_handle_t ioh = sc->sc_ioh; 3102 int retval; 3103 u_int8_t tid_no; 3104 ASC_SCSI_BIT_ID_TYPE target_id; 3105 int i; 3106 ASC_SCSI_REQ_Q scsiq_buf; 3107 ASC_SCSI_REQ_Q *scsiq; 3108 u_int8_t *buf; 3109 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3110 3111 3112 tid_no = ASC_TIX_TO_TID(target_ix); 3113 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3114 saved_unit_not_ready = sc->unit_not_ready; 3115 sc->unit_not_ready = target_id; 3116 retval = ASC_ERROR; 3117 3118 AscWaitTixISRDone(sc, target_ix); 3119 3120 if (AscStopQueueExe(iot, ioh) == 1) { 3121 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3122 AscCleanUpBusyQueue(iot, ioh); 3123 AscStartQueueExe(iot, ioh); 3124 AscWaitTixISRDone(sc, target_ix); 3125 retval = ASC_NOERROR; 3126 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3127 buf = (u_char *) & scsiq_buf; 3128 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3129 *buf++ = 0x00; 3130 scsiq->q1.status = (u_char) ASC_QS_READY; 3131 scsiq->q2.cdb_len = 6; 3132 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3133 scsiq->q1.target_id = target_id; 3134 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3135 scsiq->cdbptr = scsiq->cdb; 3136 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3137 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3138 sc->unit_not_ready &= ~target_id; 3139 sc->sdtr_done |= target_id; 3140 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3141 sc->unit_not_ready = target_id; 3142 DvcSleepMilliSecond(1000); 3143 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3144 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3145 AscCleanUpDiscQueue(iot, ioh); 3146 AscStartQueueExe(iot, ioh); 3147 if (sc->pci_fix_asyn_xfer & target_id) 3148 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3149 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3150 AscWaitTixISRDone(sc, target_ix); 3151 } 3152 } else 3153 retval = ASC_BUSY; 3154 sc->sdtr_done &= ~target_id; 3155 } else { 3156 retval = ASC_ERROR; 3157 AscStartQueueExe(iot, ioh); 3158 } 3159 } 3160 sc->unit_not_ready = saved_unit_not_ready; 3161 return (retval); 3162 } 3163 3164 3165 int 3166 AscResetBus(sc) 3167 ASC_SOFTC *sc; 3168 { 3169 bus_space_tag_t iot = sc->sc_iot; 3170 bus_space_handle_t ioh = sc->sc_ioh; 3171 int retval; 3172 int i; 3173 3174 3175 sc->unit_not_ready = 0xFF; 3176 retval = ASC_NOERROR; 3177 3178 AscWaitISRDone(sc); 3179 AscStopQueueExe(iot, ioh); 3180 sc->sdtr_done = 0; 3181 AscResetChipAndScsiBus(iot, ioh); 3182 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3183 AscReInitLram(sc); 3184 for (i = 0; i <= ASC_MAX_TID; i++) { 3185 sc->cur_dvc_qng[i] = 0; 3186 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3187 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3188 } 3189 3190 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3191 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3192 retval = ASC_ERROR; 3193 3194 if (AscStartChip(iot, ioh) == 0) 3195 retval = ASC_ERROR; 3196 3197 AscStartQueueExe(iot, ioh); 3198 sc->unit_not_ready = 0; 3199 sc->queue_full_or_busy = 0; 3200 return (retval); 3201 } 3202 3203 3204 /******************************************************************************/ 3205 /* Error Handling routines */ 3206 /******************************************************************************/ 3207 3208 3209 static int 3210 AscSetLibErrorCode(sc, err_code) 3211 ASC_SOFTC *sc; 3212 u_int16_t err_code; 3213 { 3214 /* 3215 * if(sc->err_code == 0) { sc->err_code = err_code; 3216 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3217 err_code); 3218 /* 3219 * } 3220 */ 3221 return (err_code); 3222 } 3223 3224 3225 /******************************************************************************/ 3226 /* Handle bugged borads routines */ 3227 /******************************************************************************/ 3228 3229 3230 void 3231 AscInquiryHandling(sc, tid_no, inq) 3232 ASC_SOFTC *sc; 3233 u_int8_t tid_no; 3234 ASC_SCSI_INQUIRY *inq; 3235 { 3236 bus_space_tag_t iot = sc->sc_iot; 3237 bus_space_handle_t ioh = sc->sc_ioh; 3238 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3239 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3240 3241 3242 orig_init_sdtr = sc->init_sdtr; 3243 orig_use_tagged_qng = sc->use_tagged_qng; 3244 3245 sc->init_sdtr &= ~tid_bit; 3246 sc->can_tagged_qng &= ~tid_bit; 3247 sc->use_tagged_qng &= ~tid_bit; 3248 3249 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3250 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3251 sc->init_sdtr |= tid_bit; 3252 3253 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3254 if (AscTagQueuingSafe(inq)) { 3255 sc->use_tagged_qng |= tid_bit; 3256 sc->can_tagged_qng |= tid_bit; 3257 } 3258 } 3259 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3260 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3261 sc->disc_enable); 3262 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3263 sc->use_tagged_qng); 3264 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3265 sc->can_tagged_qng); 3266 3267 sc->max_dvc_qng[tid_no] = 3268 sc->max_tag_qng[tid_no]; 3269 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3270 sc->max_dvc_qng[tid_no]); 3271 } 3272 if (orig_init_sdtr != sc->init_sdtr) 3273 AscAsyncFix(sc, tid_no, inq); 3274 } 3275 3276 3277 static int 3278 AscTagQueuingSafe(inq) 3279 ASC_SCSI_INQUIRY *inq; 3280 { 3281 if ((inq->add_len >= 32) && 3282 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3283 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3284 return 0; 3285 } 3286 return 1; 3287 } 3288 3289 3290 static void 3291 AscAsyncFix(sc, tid_no, inq) 3292 ASC_SOFTC *sc; 3293 u_int8_t tid_no; 3294 ASC_SCSI_INQUIRY *inq; 3295 { 3296 u_int8_t dvc_type; 3297 ASC_SCSI_BIT_ID_TYPE tid_bits; 3298 3299 3300 dvc_type = inq->byte0.peri_dvc_type; 3301 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3302 3303 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3304 if (!(sc->init_sdtr & tid_bits)) { 3305 if ((dvc_type == SCSI_TYPE_CDROM) && 3306 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3307 sc->pci_fix_asyn_xfer_always |= tid_bits; 3308 } 3309 sc->pci_fix_asyn_xfer |= tid_bits; 3310 if ((dvc_type == SCSI_TYPE_PROC) || 3311 (dvc_type == SCSI_TYPE_SCANNER)) { 3312 sc->pci_fix_asyn_xfer &= ~tid_bits; 3313 } 3314 if ((dvc_type == SCSI_TYPE_SASD) && 3315 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3316 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3317 sc->pci_fix_asyn_xfer &= ~tid_bits; 3318 } 3319 if ((dvc_type == SCSI_TYPE_SASD) && 3320 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3321 sc->pci_fix_asyn_xfer &= ~tid_bits; 3322 } 3323 if ((dvc_type == SCSI_TYPE_CDROM) && 3324 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3325 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3326 sc->pci_fix_asyn_xfer &= ~tid_bits; 3327 } 3328 if ((dvc_type == SCSI_TYPE_CDROM) && 3329 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3330 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3331 sc->pci_fix_asyn_xfer &= ~tid_bits; 3332 } 3333 if (sc->pci_fix_asyn_xfer & tid_bits) { 3334 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3335 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3336 } 3337 } 3338 } 3339 } 3340 3341 3342 /******************************************************************************/ 3343 /* Miscellaneous routines */ 3344 /******************************************************************************/ 3345 3346 3347 static int 3348 AscCompareString(str1, str2, len) 3349 u_char *str1; 3350 u_char *str2; 3351 int len; 3352 { 3353 int i; 3354 int diff; 3355 3356 for (i = 0; i < len; i++) { 3357 diff = (int) (str1[i] - str2[i]); 3358 if (diff != 0) 3359 return (diff); 3360 } 3361 3362 return (0); 3363 } 3364 3365 3366 /******************************************************************************/ 3367 /* Device oriented routines */ 3368 /******************************************************************************/ 3369 3370 3371 static int 3372 DvcEnterCritical(void) 3373 { 3374 int s; 3375 3376 s = splbio(); 3377 return (s); 3378 } 3379 3380 3381 static void 3382 DvcLeaveCritical(s) 3383 int s; 3384 { 3385 3386 splx(s); 3387 } 3388 3389 3390 static void 3391 DvcSleepMilliSecond(n) 3392 u_int32_t n; 3393 { 3394 3395 DELAY(n * 1000); 3396 } 3397 3398 #ifdef UNUSED 3399 static void 3400 DvcDelayMicroSecond(n) 3401 u_int32_t n; 3402 { 3403 3404 DELAY(n); 3405 } 3406 #endif 3407 3408 static void 3409 DvcDelayNanoSecond(n) 3410 u_int32_t n; 3411 { 3412 3413 DELAY((n + 999) / 1000); 3414 } 3415
Indexes created Thu Oct 02 10:09:58 GMT 2025