advlib.c revision 1.17
1 /* $NetBSD: advlib.c,v 1.17 2001/11/13 13:14:32 lukem Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: advlib.c,v 1.17 2001/11/13 13:14:32 lukem Exp $"); 57 58 #include <sys/types.h> 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/malloc.h> 62 #include <sys/kernel.h> 63 #include <sys/queue.h> 64 #include <sys/device.h> 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <uvm/uvm_extern.h> 74 75 #include <dev/ic/advlib.h> 76 #include <dev/ic/adv.h> 77 #include <dev/ic/advmcode.h> 78 79 80 /* #define ASC_DEBUG */ 81 82 /******************************************************************************/ 83 /* Static functions */ 84 /******************************************************************************/ 85 86 /* Initializzation routines */ 87 static u_int32_t AscLoadMicroCode(bus_space_tag_t, bus_space_handle_t, 88 u_int16_t, u_int16_t *, u_int16_t); 89 static void AscInitLram(ASC_SOFTC *); 90 static void AscInitQLinkVar(ASC_SOFTC *); 91 static int AscResetChipAndScsiBus(bus_space_tag_t, bus_space_handle_t); 92 static u_int16_t AscGetChipBusType(bus_space_tag_t, bus_space_handle_t); 93 #if 0 94 static u_int16_t AscGetEisaChipCfg(bus_space_tag_t, bus_space_handle_t); 95 #endif 96 97 /* Chip register routines */ 98 static void AscSetBank(bus_space_tag_t, bus_space_handle_t, u_int8_t); 99 100 /* RISC Chip routines */ 101 static int AscStartChip(bus_space_tag_t, bus_space_handle_t); 102 static int AscStopChip(bus_space_tag_t, bus_space_handle_t); 103 static u_int8_t AscSetChipScsiID(bus_space_tag_t, bus_space_handle_t, u_int8_t); 104 static u_int8_t AscGetChipScsiCtrl(bus_space_tag_t, bus_space_handle_t); 105 static int AscSetRunChipSynRegAtID(bus_space_tag_t, bus_space_handle_t, 106 u_int8_t, u_int8_t); 107 static int AscSetChipSynRegAtID(bus_space_tag_t, bus_space_handle_t, 108 u_int8_t, u_int8_t); 109 static int AscHostReqRiscHalt(bus_space_tag_t, bus_space_handle_t); 110 static int AscIsChipHalted(bus_space_tag_t, bus_space_handle_t); 111 static void AscSetChipIH(bus_space_tag_t, bus_space_handle_t, u_int16_t); 112 113 /* Lram routines */ 114 static u_int8_t AscReadLramByte(bus_space_tag_t, bus_space_handle_t, u_int16_t); 115 static void AscWriteLramByte(bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int8_t); 117 static u_int16_t AscReadLramWord(bus_space_tag_t, bus_space_handle_t, 118 u_int16_t); 119 static void AscWriteLramWord(bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int16_t); 121 static u_int32_t AscReadLramDWord(bus_space_tag_t, bus_space_handle_t, 122 u_int16_t); 123 static void AscWriteLramDWord(bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int32_t); 125 static void AscMemWordSetLram(bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t, int); 127 static void AscMemWordCopyToLram(bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int); 129 static void AscMemWordCopyFromLram(bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int16_t *, int); 131 static void AscMemDWordCopyToLram(bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, u_int32_t *, int); 133 static u_int32_t AscMemSumLramWord(bus_space_tag_t, bus_space_handle_t, 134 u_int16_t, int); 135 static int AscTestExternalLram(bus_space_tag_t, bus_space_handle_t); 136 137 /* MicroCode routines */ 138 static u_int16_t AscInitMicroCodeVar(ASC_SOFTC *); 139 140 /* EEProm routines */ 141 static int AscWriteEEPCmdReg(bus_space_tag_t, bus_space_handle_t, u_int8_t); 142 static int AscWriteEEPDataReg(bus_space_tag_t, bus_space_handle_t, u_int16_t); 143 static void AscWaitEEPRead(void); 144 static void AscWaitEEPWrite(void); 145 static u_int16_t AscReadEEPWord(bus_space_tag_t, bus_space_handle_t, u_int8_t); 146 static u_int16_t AscWriteEEPWord(bus_space_tag_t, bus_space_handle_t, 147 u_int8_t, u_int16_t); 148 static u_int16_t AscGetEEPConfig(bus_space_tag_t, bus_space_handle_t, 149 ASCEEP_CONFIG *, u_int16_t); 150 static int AscSetEEPConfig(bus_space_tag_t, bus_space_handle_t, 151 ASCEEP_CONFIG *, u_int16_t); 152 static int AscSetEEPConfigOnce(bus_space_tag_t, bus_space_handle_t, 153 ASCEEP_CONFIG *, u_int16_t); 154 #ifdef ASC_DEBUG 155 static void AscPrintEEPConfig(ASCEEP_CONFIG *, u_int16_t); 156 #endif 157 158 /* Interrupt routines */ 159 static void AscIsrChipHalted(ASC_SOFTC *); 160 static int AscIsrQDone(ASC_SOFTC *); 161 static int AscWaitTixISRDone(ASC_SOFTC *, u_int8_t); 162 static int AscWaitISRDone(ASC_SOFTC *); 163 static u_int8_t _AscCopyLramScsiDoneQ(bus_space_tag_t, bus_space_handle_t, 164 u_int16_t, ASC_QDONE_INFO *, u_int32_t); 165 static void AscGetQDoneInfo(bus_space_tag_t, bus_space_handle_t, u_int16_t, 166 ASC_QDONE_INFO *); 167 static void AscToggleIRQAct(bus_space_tag_t, bus_space_handle_t); 168 static void AscDisableInterrupt(bus_space_tag_t, bus_space_handle_t); 169 static void AscEnableInterrupt(bus_space_tag_t, bus_space_handle_t); 170 static u_int8_t AscSetChipIRQ(bus_space_tag_t, bus_space_handle_t, 171 u_int8_t, u_int16_t); 172 static void AscAckInterrupt(bus_space_tag_t, bus_space_handle_t); 173 static u_int32_t AscGetMaxDmaCount(u_int16_t); 174 static u_int16_t AscSetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t, 175 u_int16_t); 176 static u_int8_t AscGetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t); 177 static u_int8_t AscSetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t, 178 u_int8_t); 179 180 /* Messages routines */ 181 static void AscHandleExtMsgIn(ASC_SOFTC *, u_int16_t, u_int8_t, 182 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t); 183 static u_int8_t AscMsgOutSDTR(ASC_SOFTC *, u_int8_t, u_int8_t); 184 185 /* SDTR routines */ 186 static void AscSetChipSDTR(bus_space_tag_t, bus_space_handle_t, 187 u_int8_t, u_int8_t); 188 static u_int8_t AscCalSDTRData(ASC_SOFTC *, u_int8_t, u_int8_t); 189 static u_int8_t AscGetSynPeriodIndex(ASC_SOFTC *, u_int8_t); 190 191 /* Queue routines */ 192 static int AscSendScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 193 static int AscSgListToQueue(int); 194 static u_int AscGetNumOfFreeQueue(ASC_SOFTC *, u_int8_t, u_int8_t); 195 static int AscPutReadyQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 196 static void AscPutSCSIQ(bus_space_tag_t, bus_space_handle_t, 197 u_int16_t, ASC_SCSI_Q *); 198 static int AscPutReadySgListQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 199 static u_int8_t AscAllocFreeQueue(bus_space_tag_t, bus_space_handle_t, 200 u_int8_t); 201 static u_int8_t AscAllocMultipleFreeQueue(bus_space_tag_t, bus_space_handle_t, 202 u_int8_t, u_int8_t); 203 static int AscStopQueueExe(bus_space_tag_t, bus_space_handle_t); 204 static void AscStartQueueExe(bus_space_tag_t, bus_space_handle_t); 205 static void AscCleanUpBusyQueue(bus_space_tag_t, bus_space_handle_t); 206 static int _AscWaitQDone(bus_space_tag_t, bus_space_handle_t, 207 ASC_SCSI_Q *); 208 static int AscCleanUpDiscQueue(bus_space_tag_t, bus_space_handle_t); 209 210 /* Abort and Reset CCB routines */ 211 static int AscRiscHaltedAbortCCB(ASC_SOFTC *, ADV_CCB *); 212 static int AscRiscHaltedAbortTIX(ASC_SOFTC *, u_int8_t); 213 214 /* Error Handling routines */ 215 static int AscSetLibErrorCode(ASC_SOFTC *, u_int16_t); 216 217 /* Handle bugged borads routines */ 218 static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *); 219 static void AscAsyncFix(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *); 220 221 /* Miscellaneous routines */ 222 static int AscCompareString(u_char *, u_char *, int); 223 224 /* Device oriented routines */ 225 static int DvcEnterCritical(void); 226 static void DvcLeaveCritical(int); 227 static void DvcSleepMilliSecond(u_int32_t); 228 #if 0 229 static void DvcDelayMicroSecond(u_int32_t); 230 #endif 231 static void DvcDelayNanoSecond(u_int32_t); 232 233 234 /******************************************************************************/ 235 /* Initializzation routines */ 236 /******************************************************************************/ 237 238 /* 239 * This function perform the following steps: 240 * - initialize ASC_SOFTC structure with defaults values. 241 * - inquire board registers to know what kind of board it is. 242 * - keep track of bugged borads. 243 */ 244 void 245 AscInitASC_SOFTC(ASC_SOFTC *sc) 246 { 247 bus_space_tag_t iot = sc->sc_iot; 248 bus_space_handle_t ioh = sc->sc_ioh; 249 int i; 250 251 252 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 253 ASC_SET_CHIP_STATUS(iot, ioh, 0); 254 255 sc->bug_fix_cntl = 0; 256 sc->pci_fix_asyn_xfer = 0; 257 sc->pci_fix_asyn_xfer_always = 0; 258 sc->sdtr_done = 0; 259 sc->cur_total_qng = 0; 260 sc->last_q_shortage = 0; 261 sc->use_tagged_qng = 0; 262 sc->unit_not_ready = 0; 263 sc->queue_full_or_busy = 0; 264 sc->host_init_sdtr_index = 0; 265 sc->can_tagged_qng = 0; 266 sc->cmd_qng_enabled = 0; 267 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 268 sc->init_sdtr = 0; 269 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 270 sc->scsi_reset_wait = 3; 271 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 272 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 273 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 274 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 275 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 276 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 277 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 278 if ((sc->bus_type & ASC_IS_PCI) && 279 (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 280 sc->bus_type = ASC_IS_PCI_ULTRA; 281 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 282 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 283 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 284 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 285 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 286 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 287 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 288 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 289 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 290 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 291 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 292 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 293 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 294 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 295 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 296 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 297 sc->max_sdtr_index = 15; 298 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 299 ASC_SET_EXTRA_CONTROL(iot, ioh, 300 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 301 else if (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 302 ASC_SET_EXTRA_CONTROL(iot, ioh, 303 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 304 } else { 305 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 306 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 307 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 308 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 309 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 310 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 311 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 312 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 313 sc->max_sdtr_index = 7; 314 } 315 316 if (sc->bus_type == ASC_IS_PCI) 317 ASC_SET_EXTRA_CONTROL(iot, ioh, 318 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 319 320 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 321 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 322 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 323 sc->bus_type = ASC_IS_ISAPNP; 324 } 325 if ((sc->bus_type & ASC_IS_ISA) != 0) 326 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 327 328 for (i = 0; i <= ASC_MAX_TID; i++) { 329 sc->cur_dvc_qng[i] = 0; 330 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 331 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 332 } 333 } 334 335 336 /* 337 * This function initialize some ASC_SOFTC fields with values read from 338 * on-board EEProm. 339 */ 340 int16_t 341 AscInitFromEEP(ASC_SOFTC *sc) 342 { 343 bus_space_tag_t iot = sc->sc_iot; 344 bus_space_handle_t ioh = sc->sc_ioh; 345 ASCEEP_CONFIG eep_config_buf; 346 ASCEEP_CONFIG *eep_config; 347 u_int16_t chksum; 348 u_int16_t warn_code; 349 u_int16_t cfg_msw, cfg_lsw; 350 int i; 351 int write_eep = 0; 352 353 354 warn_code = 0; 355 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 356 AscStopQueueExe(iot, ioh); 357 358 AscStopChip(iot, ioh); 359 AscResetChipAndScsiBus(iot, ioh); 360 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 361 362 if ((AscStopChip(iot, ioh) == FALSE) || 363 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 364 AscResetChipAndScsiBus(iot, ioh); 365 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 366 } 367 if (AscIsChipHalted(iot, ioh) == FALSE) 368 return (-1); 369 370 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 371 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 372 return (-2); 373 374 eep_config = &eep_config_buf; 375 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 376 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 377 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 378 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 379 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 380 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 381 } 382 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 383 #ifdef ASC_DEBUG 384 AscPrintEEPConfig(eep_config, chksum); 385 #endif 386 if (chksum == 0) 387 chksum = 0xAA55; 388 389 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 390 warn_code |= ASC_WARN_AUTO_CONFIG; 391 if (sc->chip_version == 3) { 392 if (eep_config->cfg_lsw != cfg_lsw) { 393 warn_code |= ASC_WARN_EEPROM_RECOVER; 394 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 395 } 396 if (eep_config->cfg_msw != cfg_msw) { 397 warn_code |= ASC_WARN_EEPROM_RECOVER; 398 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 399 } 400 } 401 } 402 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 403 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 404 405 if (chksum != eep_config->chksum) { 406 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3050) { 407 eep_config->init_sdtr = 0xFF; 408 eep_config->disc_enable = 0xFF; 409 eep_config->start_motor = 0xFF; 410 eep_config->use_cmd_qng = 0; 411 eep_config->max_total_qng = 0xF0; 412 eep_config->max_tag_qng = 0x20; 413 eep_config->cntl = 0xBFFF; 414 eep_config->chip_scsi_id = 7; 415 eep_config->no_scam = 0; 416 eep_config->adapter_info[0] = 0; 417 eep_config->adapter_info[1] = 0; 418 eep_config->adapter_info[2] = 0; 419 eep_config->adapter_info[3] = 0; 420 #if BYTE_ORDER == BIG_ENDIAN 421 eep_config->adapter_info[5] = 0; 422 /* Indicate EEPROM-less board. */ 423 eep_config->adapter_info[4] = 0xBB; 424 #else 425 eep_config->adapter_info[4] = 0; 426 /* Indicate EEPROM-less board. */ 427 eep_config->adapter_info[5] = 0xBB; 428 #endif 429 } else { 430 write_eep = 1; 431 warn_code |= ASC_WARN_EEPROM_CHKSUM; 432 } 433 } 434 sc->sdtr_enable = eep_config->init_sdtr; 435 sc->disc_enable = eep_config->disc_enable; 436 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 437 sc->isa_dma_speed = eep_config->isa_dma_speed; 438 sc->start_motor = eep_config->start_motor; 439 sc->dvc_cntl = eep_config->cntl; 440 #if BYTE_ORDER == BIG_ENDIAN 441 sc->adapter_info[0] = eep_config->adapter_info[1]; 442 sc->adapter_info[1] = eep_config->adapter_info[0]; 443 sc->adapter_info[2] = eep_config->adapter_info[3]; 444 sc->adapter_info[3] = eep_config->adapter_info[2]; 445 sc->adapter_info[4] = eep_config->adapter_info[5]; 446 sc->adapter_info[5] = eep_config->adapter_info[4]; 447 #else 448 sc->adapter_info[0] = eep_config->adapter_info[0]; 449 sc->adapter_info[1] = eep_config->adapter_info[1]; 450 sc->adapter_info[2] = eep_config->adapter_info[2]; 451 sc->adapter_info[3] = eep_config->adapter_info[3]; 452 sc->adapter_info[4] = eep_config->adapter_info[4]; 453 sc->adapter_info[5] = eep_config->adapter_info[5]; 454 #endif 455 456 if (!AscTestExternalLram(iot, ioh)) { 457 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 458 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 459 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 460 } else { 461 eep_config->cfg_msw |= 0x0800; 462 cfg_msw |= 0x0800; 463 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 464 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 465 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 466 } 467 } 468 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 469 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 470 471 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 472 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 473 474 if (eep_config->max_tag_qng > eep_config->max_total_qng) 475 eep_config->max_tag_qng = eep_config->max_total_qng; 476 477 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 478 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 479 480 sc->max_total_qng = eep_config->max_total_qng; 481 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 482 eep_config->use_cmd_qng) { 483 eep_config->disc_enable = eep_config->use_cmd_qng; 484 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 485 } 486 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 487 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 488 489 eep_config->chip_scsi_id &= ASC_MAX_TID; 490 sc->chip_scsi_id = eep_config->chip_scsi_id; 491 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 492 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 493 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 494 } 495 for (i = 0; i <= ASC_MAX_TID; i++) { 496 sc->max_tag_qng[i] = eep_config->max_tag_qng; 497 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 498 (sc->host_init_sdtr_index << 4); 499 } 500 501 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 502 if (write_eep) { 503 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 504 #ifdef ASC_DEBUG 505 AscPrintEEPConfig(eep_config, 0); 506 #endif 507 } 508 509 return (warn_code); 510 } 511 512 513 u_int16_t 514 AscInitFromASC_SOFTC(ASC_SOFTC *sc) 515 { 516 bus_space_tag_t iot = sc->sc_iot; 517 bus_space_handle_t ioh = sc->sc_ioh; 518 u_int16_t cfg_msw; 519 u_int16_t warn_code; 520 u_int16_t pci_device_id = sc->pci_device_id; 521 522 523 warn_code = 0; 524 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 525 526 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 527 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 528 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 529 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 530 } 531 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 532 sc->disc_enable = sc->cmd_qng_enabled; 533 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 534 } 535 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 536 warn_code |= ASC_WARN_AUTO_CONFIG; 537 } 538 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 539 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 540 } 541 if (sc->bus_type & ASC_IS_PCI) { 542 cfg_msw &= 0xFFC0; 543 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 544 545 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 546 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 547 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 548 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 549 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 550 } 551 } 552 } else if (sc->bus_type == ASC_IS_ISAPNP) { 553 if (sc->chip_version == ASC_CHIP_VER_ASYN_BUG) { 554 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 555 } 556 } 557 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 558 559 if (sc->bus_type & ASC_IS_ISA) { 560 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 561 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 562 } 563 return (warn_code); 564 } 565 566 567 /* 568 * - Initialize RISC chip 569 * - Intialize Lram 570 * - Load uCode into Lram 571 * - Enable Interrupts 572 */ 573 int 574 AscInitDriver(ASC_SOFTC *sc) 575 { 576 bus_space_tag_t iot = sc->sc_iot; 577 bus_space_handle_t ioh = sc->sc_ioh; 578 u_int32_t chksum; 579 580 581 if (!AscFindSignature(iot, ioh)) 582 return (1); 583 584 AscDisableInterrupt(iot, ioh); 585 586 AscInitLram(sc); 587 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 588 asc_mcode_size); 589 if (chksum != asc_mcode_chksum) 590 return (2); 591 592 if (AscInitMicroCodeVar(sc) == 0) 593 return (3); 594 595 AscEnableInterrupt(iot, ioh); 596 597 return (0); 598 } 599 600 601 int 602 AscFindSignature(bus_space_tag_t iot, bus_space_handle_t ioh) 603 { 604 u_int16_t sig_word; 605 606 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 607 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 608 if (sig_word == ASC_1000_ID0W || 609 sig_word == ASC_1000_ID0W_FIX) 610 return (1); 611 } 612 return (0); 613 } 614 615 616 static void 617 AscInitLram(ASC_SOFTC *sc) 618 { 619 bus_space_tag_t iot = sc->sc_iot; 620 bus_space_handle_t ioh = sc->sc_ioh; 621 u_int8_t i; 622 u_int16_t s_addr; 623 624 625 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 626 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 627 628 i = ASC_MIN_ACTIVE_QNO; 629 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 630 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 631 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 632 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 633 i++; 634 s_addr += ASC_QBLK_SIZE; 635 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 636 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 637 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 638 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 639 } 640 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 641 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 642 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 643 i++; 644 s_addr += ASC_QBLK_SIZE; 645 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 647 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 648 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 649 } 650 } 651 652 653 void 654 AscReInitLram(ASC_SOFTC *sc) 655 { 656 657 AscInitLram(sc); 658 AscInitQLinkVar(sc); 659 } 660 661 662 static void 663 AscInitQLinkVar(ASC_SOFTC *sc) 664 { 665 bus_space_tag_t iot = sc->sc_iot; 666 bus_space_handle_t ioh = sc->sc_ioh; 667 u_int8_t i; 668 u_int16_t lram_addr; 669 670 671 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 672 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 673 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 674 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 675 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 676 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 677 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 678 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 679 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 680 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 681 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 682 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 683 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 684 lram_addr = ASC_QADR_BEG; 685 for (i = 0; i < 32; i++, lram_addr += 2) 686 AscWriteLramWord(iot, ioh, lram_addr, 0); 687 } 688 689 690 static int 691 AscResetChipAndScsiBus(bus_space_tag_t iot, bus_space_handle_t ioh) 692 { 693 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 694 695 AscStopChip(iot, ioh); 696 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 697 698 DvcDelayNanoSecond(60000); 699 700 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 701 AscSetChipIH(iot, ioh, ASC_INS_HALT); 702 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 703 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 704 705 DvcSleepMilliSecond(200); 706 707 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 708 ASC_SET_CHIP_STATUS(iot, ioh, 0); 709 710 DvcSleepMilliSecond(200); 711 712 return (AscIsChipHalted(iot, ioh)); 713 } 714 715 716 static u_int16_t 717 AscGetChipBusType(bus_space_tag_t iot, bus_space_handle_t ioh) 718 { 719 u_int16_t chip_ver; 720 721 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 722 #if 0 723 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 724 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 725 if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) { 726 return (ASC_IS_EISA); 727 } 728 else { 729 return (ASC_IS_VL); 730 } 731 } 732 #endif 733 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 734 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 735 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 736 return (ASC_IS_ISAPNP); 737 738 return (ASC_IS_ISA); 739 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 740 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 741 return (ASC_IS_PCI); 742 743 return (0); 744 } 745 746 /* 747 static u_int16_t 748 AscGetEisaChipCfg(bus_space_tag_t iot, bus_space_handle_t ioh) 749 { 750 int eisa_cfg_iop; 751 752 eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK); 753 return (inw(eisa_cfg_iop)); 754 } 755 */ 756 757 /******************************************************************************/ 758 /* Chip register routines */ 759 /******************************************************************************/ 760 761 762 static void 763 AscSetBank(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bank) 764 { 765 u_int8_t val; 766 767 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 768 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 769 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 770 ASC_CC_CHIP_RESET)); 771 772 switch (bank) { 773 case 1: 774 val |= ASC_CC_BANK_ONE; 775 break; 776 777 case 2: 778 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 779 break; 780 781 default: 782 val &= ~ASC_CC_BANK_ONE; 783 } 784 785 ASC_SET_CHIP_CONTROL(iot, ioh, val); 786 return; 787 } 788 789 790 /******************************************************************************/ 791 /* Chip routines */ 792 /******************************************************************************/ 793 794 795 static int 796 AscStartChip(bus_space_tag_t iot, bus_space_handle_t ioh) 797 { 798 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 799 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 800 return (0); 801 802 return (1); 803 } 804 805 806 static int 807 AscStopChip(bus_space_tag_t iot, bus_space_handle_t ioh) 808 { 809 u_int8_t cc_val; 810 811 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 812 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 813 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 814 AscSetChipIH(iot, ioh, ASC_INS_HALT); 815 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 816 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 817 return (0); 818 819 return (1); 820 } 821 822 823 static u_int8_t 824 AscSetChipScsiID(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t new_id) 825 { 826 u_int16_t cfg_lsw; 827 828 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 829 return (new_id); 830 831 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 832 cfg_lsw &= 0xF8FF; 833 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 834 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 835 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 836 } 837 838 839 static u_int8_t 840 AscGetChipScsiCtrl(bus_space_tag_t iot, bus_space_handle_t ioh) 841 { 842 u_int8_t scsi_ctrl; 843 844 AscSetBank(iot, ioh, 1); 845 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 846 AscSetBank(iot, ioh, 0); 847 return (scsi_ctrl); 848 } 849 850 851 static int 852 AscSetRunChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh, 853 u_int8_t tid_no, u_int8_t sdtr_data) 854 { 855 int retval = FALSE; 856 857 if (AscHostReqRiscHalt(iot, ioh)) { 858 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 859 AscStartChip(iot, ioh); 860 } 861 return (retval); 862 } 863 864 865 static int 866 AscSetChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh, 867 u_int8_t id, u_int8_t sdtr_data) 868 { 869 ASC_SCSI_BIT_ID_TYPE org_id; 870 int i; 871 int sta = TRUE; 872 873 AscSetBank(iot, ioh, 1); 874 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 875 for (i = 0; i <= ASC_MAX_TID; i++) 876 if (org_id == (0x01 << i)) 877 break; 878 879 org_id = i; 880 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 881 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 882 AscSetBank(iot, ioh, 0); 883 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 884 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 885 sta = FALSE; 886 } else 887 sta = FALSE; 888 889 AscSetBank(iot, ioh, 1); 890 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 891 AscSetBank(iot, ioh, 0); 892 return (sta); 893 } 894 895 896 static int 897 AscHostReqRiscHalt(bus_space_tag_t iot, bus_space_handle_t ioh) 898 { 899 int count = 0; 900 int retval = 0; 901 u_int8_t saved_stop_code; 902 903 904 if (AscIsChipHalted(iot, ioh)) 905 return (1); 906 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 907 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 908 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 909 910 do { 911 if (AscIsChipHalted(iot, ioh)) { 912 retval = 1; 913 break; 914 } 915 DvcSleepMilliSecond(100); 916 } while (count++ < 20); 917 918 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 919 920 return (retval); 921 } 922 923 924 static int 925 AscIsChipHalted(bus_space_tag_t iot, bus_space_handle_t ioh) 926 { 927 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 928 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 929 return (1); 930 931 return (0); 932 } 933 934 935 static void 936 AscSetChipIH(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t ins_code) 937 { 938 AscSetBank(iot, ioh, 1); 939 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 940 AscSetBank(iot, ioh, 0); 941 942 return; 943 } 944 945 946 /******************************************************************************/ 947 /* Lram routines */ 948 /******************************************************************************/ 949 950 951 static u_int8_t 952 AscReadLramByte(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr) 953 { 954 u_int8_t byte_data; 955 u_int16_t word_data; 956 957 958 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 959 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 960 961 if (addr & 1) { 962 /* odd address */ 963 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 964 } else { 965 /* even address */ 966 byte_data = (u_int8_t) (word_data & 0xFF); 967 } 968 969 return (byte_data); 970 } 971 972 973 static void 974 AscWriteLramByte(bus_space_tag_t iot, bus_space_handle_t ioh, 975 u_int16_t addr, u_int8_t data) 976 { 977 u_int16_t word_data; 978 979 980 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 981 982 if (addr & 1) { 983 /* odd address */ 984 word_data &= 0x00FF; 985 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 986 } else { 987 /* even address */ 988 word_data &= 0xFF00; 989 word_data |= ((u_int16_t) data) & 0x00FF; 990 } 991 992 AscWriteLramWord(iot, ioh, addr & 0xFFFE, word_data); 993 } 994 995 996 static u_int16_t 997 AscReadLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr) 998 { 999 1000 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1001 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1002 } 1003 1004 1005 static void 1006 AscWriteLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1007 u_int16_t addr, u_int16_t data) 1008 { 1009 1010 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1011 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1012 } 1013 1014 1015 static u_int32_t 1016 AscReadLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr) 1017 { 1018 u_int16_t low_word, hi_word; 1019 1020 1021 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1022 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1023 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1024 1025 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1026 } 1027 1028 1029 static void 1030 AscWriteLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1031 u_int16_t addr, u_int32_t data) 1032 { 1033 1034 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1035 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1036 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1037 } 1038 1039 1040 static void 1041 AscMemWordSetLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1042 u_int16_t s_addr, u_int16_t s_words, int count) 1043 { 1044 int i; 1045 1046 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1047 for (i = 0; i < count; i++) 1048 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1049 } 1050 1051 1052 static void 1053 AscMemWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1054 u_int16_t s_addr, u_int16_t *s_buffer, int words) 1055 { 1056 int i; 1057 1058 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1059 for (i = 0; i < words; i++, s_buffer++) 1060 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1061 } 1062 1063 1064 static void 1065 AscMemWordCopyFromLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1066 u_int16_t s_addr, u_int16_t *s_buffer, int words) 1067 { 1068 int i; 1069 1070 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1071 for (i = 0; i < words; i++, s_buffer++) 1072 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1073 } 1074 1075 1076 static void 1077 AscMemDWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1078 u_int16_t s_addr, u_int32_t *s_buffer, int dwords) 1079 { 1080 int i; 1081 u_int32_t *pw; 1082 1083 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1084 1085 pw = s_buffer; 1086 for (i = 0; i < dwords; i++, pw++) { 1087 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1088 DELAY(1); 1089 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1090 } 1091 } 1092 1093 1094 static u_int32_t 1095 AscMemSumLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1096 u_int16_t s_addr, int words) 1097 { 1098 u_int32_t sum = 0L; 1099 u_int16_t i; 1100 1101 1102 for (i = 0; i < words; i++, s_addr += 2) 1103 sum += AscReadLramWord(iot, ioh, s_addr); 1104 1105 return (sum); 1106 } 1107 1108 1109 static int 1110 AscTestExternalLram(bus_space_tag_t iot, bus_space_handle_t ioh) 1111 { 1112 u_int16_t q_addr; 1113 u_int16_t saved_word; 1114 int retval; 1115 1116 1117 retval = 0; 1118 q_addr = ASC_QNO_TO_QADDR(241); 1119 saved_word = AscReadLramWord(iot, ioh, q_addr); 1120 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1121 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1122 DvcSleepMilliSecond(10); 1123 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1124 1125 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1126 retval = 1; 1127 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1128 } 1129 return (retval); 1130 } 1131 1132 1133 /******************************************************************************/ 1134 /* MicroCode routines */ 1135 /******************************************************************************/ 1136 1137 1138 static u_int16_t 1139 AscInitMicroCodeVar(ASC_SOFTC *sc) 1140 { 1141 bus_space_tag_t iot = sc->sc_iot; 1142 bus_space_handle_t ioh = sc->sc_ioh; 1143 u_int32_t phy_addr; 1144 int i; 1145 1146 1147 for (i = 0; i <= ASC_MAX_TID; i++) 1148 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1149 sc->sdtr_period_offset[i]); 1150 1151 AscInitQLinkVar(sc); 1152 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1153 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1154 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1155 1156 phy_addr = (sc->overrun_buf & 0xfffffff8) + 8; 1157 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1158 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1159 ASC_OVERRUN_BSIZE - 8); 1160 1161 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1162 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1163 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1164 1165 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1166 return (0); 1167 } 1168 if (AscStartChip(iot, ioh) != 1) { 1169 return (0); 1170 } 1171 return (1); 1172 } 1173 1174 1175 static u_int32_t 1176 AscLoadMicroCode(bus_space_tag_t iot, bus_space_handle_t ioh, 1177 u_int16_t s_addr, u_int16_t *mcode_buf, u_int16_t mcode_size) 1178 { 1179 u_int32_t chksum; 1180 u_int16_t mcode_word_size; 1181 u_int16_t mcode_chksum; 1182 1183 mcode_word_size = mcode_size >> 1; 1184 /* clear board memory */ 1185 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1186 /* copy uCode to board memory */ 1187 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1188 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1189 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1190 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1191 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1192 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1193 1194 return (chksum); 1195 } 1196 1197 1198 /******************************************************************************/ 1199 /* EEProm routines */ 1200 /******************************************************************************/ 1201 1202 1203 static int 1204 AscWriteEEPCmdReg(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t cmd_reg) 1205 { 1206 u_int8_t read_back; 1207 int retry; 1208 1209 retry = 0; 1210 1211 while (TRUE) { 1212 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1213 DvcSleepMilliSecond(1); 1214 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1215 if (read_back == cmd_reg) 1216 return (1); 1217 1218 if (retry++ > ASC_EEP_MAX_RETRY) 1219 return (0); 1220 } 1221 } 1222 1223 1224 static int 1225 AscWriteEEPDataReg(bus_space_tag_t iot, bus_space_handle_t ioh, 1226 u_int16_t data_reg) 1227 { 1228 u_int16_t read_back; 1229 int retry; 1230 1231 retry = 0; 1232 while (TRUE) { 1233 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1234 DvcSleepMilliSecond(1); 1235 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1236 if (read_back == data_reg) 1237 return (1); 1238 1239 if (retry++ > ASC_EEP_MAX_RETRY) 1240 return (0); 1241 } 1242 } 1243 1244 1245 static void 1246 AscWaitEEPRead(void) 1247 { 1248 1249 DvcSleepMilliSecond(1); 1250 } 1251 1252 1253 static void 1254 AscWaitEEPWrite(void) 1255 { 1256 1257 DvcSleepMilliSecond(1); 1258 } 1259 1260 1261 static u_int16_t 1262 AscReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t addr) 1263 { 1264 u_int16_t read_wval; 1265 u_int8_t cmd_reg; 1266 1267 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1268 AscWaitEEPRead(); 1269 cmd_reg = addr | ASC_EEP_CMD_READ; 1270 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1271 AscWaitEEPRead(); 1272 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1273 AscWaitEEPRead(); 1274 1275 return (read_wval); 1276 } 1277 1278 1279 static u_int16_t 1280 AscWriteEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1281 u_int8_t addr, u_int16_t word_val) 1282 { 1283 u_int16_t read_wval; 1284 1285 read_wval = AscReadEEPWord(iot, ioh, addr); 1286 if (read_wval != word_val) { 1287 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1288 AscWaitEEPRead(); 1289 AscWriteEEPDataReg(iot, ioh, word_val); 1290 AscWaitEEPRead(); 1291 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1292 AscWaitEEPWrite(); 1293 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1294 AscWaitEEPRead(); 1295 return (AscReadEEPWord(iot, ioh, addr)); 1296 } 1297 return (read_wval); 1298 } 1299 1300 1301 static u_int16_t 1302 AscGetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh, 1303 ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type) 1304 { 1305 u_int16_t wval; 1306 u_int16_t sum; 1307 u_int16_t *wbuf; 1308 int cfg_beg; 1309 int cfg_end; 1310 int s_addr; 1311 int isa_pnp_wsize; 1312 1313 1314 wbuf = (u_int16_t *) cfg_buf; 1315 sum = 0; 1316 isa_pnp_wsize = 0; 1317 1318 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1319 wval = AscReadEEPWord(iot, ioh, s_addr); 1320 sum += wval; 1321 *wbuf = wval; 1322 } 1323 1324 if (bus_type & ASC_IS_VL) { 1325 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1326 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1327 } else { 1328 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1329 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1330 } 1331 1332 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1333 wval = AscReadEEPWord(iot, ioh, s_addr); 1334 sum += wval; 1335 *wbuf = wval; 1336 } 1337 1338 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1339 1340 return (sum); 1341 } 1342 1343 1344 static int 1345 AscSetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh, 1346 ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type) 1347 { 1348 int retry; 1349 int n_error; 1350 1351 retry = 0; 1352 while (TRUE) { 1353 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1354 break; 1355 1356 if (++retry > ASC_EEP_MAX_RETRY) 1357 break; 1358 } 1359 1360 return (n_error); 1361 } 1362 1363 1364 static int 1365 AscSetEEPConfigOnce(bus_space_tag_t iot, bus_space_handle_t ioh, 1366 ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type) 1367 { 1368 int n_error; 1369 u_int16_t *wbuf; 1370 u_int16_t sum; 1371 int s_addr; 1372 int cfg_beg; 1373 int cfg_end; 1374 1375 wbuf = (u_int16_t *) cfg_buf; 1376 n_error = 0; 1377 sum = 0; 1378 1379 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1380 sum += *wbuf; 1381 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1382 n_error++; 1383 } 1384 1385 if (bus_type & ASC_IS_VL) { 1386 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1387 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1388 } else { 1389 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1390 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1391 } 1392 1393 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1394 sum += *wbuf; 1395 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1396 n_error++; 1397 } 1398 1399 *wbuf = sum; 1400 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1401 n_error++; 1402 1403 wbuf = (u_int16_t *) cfg_buf; 1404 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1405 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1406 n_error++; 1407 } 1408 1409 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1410 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1411 n_error++; 1412 } 1413 1414 return (n_error); 1415 } 1416 1417 1418 #ifdef ASC_DEBUG 1419 static void 1420 AscPrintEEPConfig(ASCEEP_CONFIG *eep_config, u_int16_t chksum) 1421 { 1422 printf("---- ASC EEprom settings ----\n"); 1423 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1424 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1425 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1426 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1427 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1428 printf("start_motor = 0x%x\n", eep_config->start_motor); 1429 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1430 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1431 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1432 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1433 printf("no_scam = %d\n", eep_config->no_scam); 1434 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1435 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1436 printf("cntl = 0x%x\n", eep_config->cntl); 1437 #if BYTE_ORDER == BIG_ENDIAN 1438 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1439 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1440 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1441 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1442 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1443 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1444 #else 1445 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1446 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1447 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1448 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1449 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1450 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1451 #endif 1452 printf("checksum = 0x%x\n", eep_config->chksum); 1453 printf("calculated checksum = 0x%x\n", chksum); 1454 printf("-----------------------------\n"); 1455 } 1456 #endif 1457 1458 1459 /******************************************************************************/ 1460 /* Interrupt routines */ 1461 /******************************************************************************/ 1462 1463 1464 int 1465 AscISR(ASC_SOFTC *sc) 1466 { 1467 bus_space_tag_t iot = sc->sc_iot; 1468 bus_space_handle_t ioh = sc->sc_ioh; 1469 u_int16_t chipstat; 1470 u_int16_t saved_ram_addr; 1471 u_int8_t ctrl_reg; 1472 u_int8_t saved_ctrl_reg; 1473 int int_pending; 1474 int status; 1475 u_int8_t host_flag; 1476 1477 1478 int_pending = FALSE; 1479 1480 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1481 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1482 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1483 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1484 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1485 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1486 int_pending = TRUE; 1487 sc->sdtr_done = 0; 1488 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1489 1490 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1491 1492 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1493 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1494 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1495 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1496 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1497 } 1498 } 1499 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1500 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1501 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1502 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1503 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1504 1505 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1506 AscAckInterrupt(iot, ioh); 1507 int_pending = TRUE; 1508 1509 if ((chipstat & ASC_CSW_HALTED) && 1510 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1511 AscIsrChipHalted(sc); 1512 saved_ctrl_reg &= ~ASC_CC_HALT; 1513 } else { 1514 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1515 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1516 } else { 1517 do { 1518 if ((status = AscIsrQDone(sc)) == 1) 1519 break; 1520 } while (status == 0x11); 1521 } 1522 1523 if (status & 0x80) 1524 int_pending = -1; 1525 } 1526 } 1527 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1528 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1529 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1530 1531 return (1); 1532 /* return(int_pending); */ 1533 } 1534 1535 1536 static int 1537 AscIsrQDone(ASC_SOFTC *sc) 1538 { 1539 u_int8_t next_qp; 1540 u_int8_t n_q_used; 1541 u_int8_t sg_list_qp; 1542 u_int8_t sg_queue_cnt; 1543 u_int8_t q_cnt; 1544 u_int8_t done_q_tail; 1545 u_int8_t tid_no; 1546 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1547 ASC_SCSI_BIT_ID_TYPE target_id; 1548 bus_space_tag_t iot = sc->sc_iot; 1549 bus_space_handle_t ioh = sc->sc_ioh; 1550 u_int16_t q_addr; 1551 u_int16_t sg_q_addr; 1552 u_int8_t cur_target_qng; 1553 ASC_QDONE_INFO scsiq_buf; 1554 ASC_QDONE_INFO *scsiq; 1555 ASC_ISR_CALLBACK asc_isr_callback; 1556 1557 1558 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1559 n_q_used = 1; 1560 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1561 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1562 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1563 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1564 1565 if (next_qp != ASC_QLINK_END) { 1566 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1567 q_addr = ASC_QNO_TO_QADDR(next_qp); 1568 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1569 sc->max_dma_count); 1570 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1571 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1572 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1573 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1574 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1575 sg_q_addr = q_addr; 1576 sg_list_qp = next_qp; 1577 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1578 sg_list_qp = AscReadLramByte(iot, ioh, 1579 sg_q_addr + ASC_SCSIQ_B_FWD); 1580 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1581 if (sg_list_qp == ASC_QLINK_END) { 1582 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1583 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1584 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1585 panic("AscIsrQDone: Corrupted SG list encountered"); 1586 } 1587 AscWriteLramByte(iot, ioh, 1588 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1589 } 1590 n_q_used = sg_queue_cnt + 1; 1591 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1592 } 1593 if (sc->queue_full_or_busy & target_id) { 1594 cur_target_qng = AscReadLramByte(iot, ioh, 1595 ASC_QADR_BEG + scsiq->d2.target_ix); 1596 1597 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1598 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1599 scsi_busy &= ~target_id; 1600 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1601 sc->queue_full_or_busy &= ~target_id; 1602 } 1603 } 1604 if (sc->cur_total_qng >= n_q_used) { 1605 sc->cur_total_qng -= n_q_used; 1606 if (sc->cur_dvc_qng[tid_no] != 0) { 1607 sc->cur_dvc_qng[tid_no]--; 1608 } 1609 } else { 1610 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1611 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1612 panic("AscIsrQDone: Attempting to free more queues than are active"); 1613 } 1614 1615 if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) || 1616 ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1617 return (0x11); 1618 } else if (scsiq->q_status == ASC_QS_DONE) { 1619 scsiq->remain_bytes += scsiq->extra_bytes; 1620 1621 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1622 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1623 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1624 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1625 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1626 } 1627 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1628 AscStopChip(iot, ioh); 1629 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1630 DvcDelayNanoSecond(60000); 1631 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1632 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1633 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1634 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1635 } 1636 } 1637 (*asc_isr_callback) (sc, scsiq); 1638 1639 return (1); 1640 } else { 1641 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1642 panic("AscIsrQDone: completed scsiq with unknown status"); 1643 1644 return (0x80); 1645 } 1646 } 1647 return (0); 1648 } 1649 1650 1651 /* 1652 * handle all the conditions that may halt the board 1653 * waiting us to intervene 1654 */ 1655 static void 1656 AscIsrChipHalted(ASC_SOFTC *sc) 1657 { 1658 bus_space_tag_t iot = sc->sc_iot; 1659 bus_space_handle_t ioh = sc->sc_ioh; 1660 EXT_MSG out_msg; 1661 u_int16_t int_halt_code; 1662 u_int16_t halt_q_addr; 1663 u_int8_t halt_qp; 1664 u_int8_t target_ix; 1665 u_int8_t tag_code; 1666 u_int8_t q_status; 1667 u_int8_t q_cntl; 1668 u_int8_t tid_no; 1669 u_int8_t cur_dvc_qng; 1670 u_int8_t asyn_sdtr; 1671 u_int8_t scsi_status; 1672 u_int8_t sdtr_data; 1673 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1674 ASC_SCSI_BIT_ID_TYPE target_id; 1675 1676 1677 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1678 1679 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1680 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1681 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1682 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1683 tid_no = ASC_TIX_TO_TID(target_ix); 1684 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1685 1686 if (sc->pci_fix_asyn_xfer & target_id) { 1687 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1688 } else { 1689 asyn_sdtr = 0; 1690 } 1691 1692 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1693 if (sc->pci_fix_asyn_xfer & target_id) { 1694 AscSetChipSDTR(iot, ioh, 0, tid_no); 1695 sc->sdtr_data[tid_no] = 0; 1696 } 1697 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1698 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1699 if (sc->pci_fix_asyn_xfer & target_id) { 1700 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1701 sc->sdtr_data[tid_no] = asyn_sdtr; 1702 } 1703 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1704 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1705 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1706 tid_no, asyn_sdtr); 1707 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1708 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1709 q_cntl |= ASC_QC_REQ_SENSE; 1710 1711 if (sc->init_sdtr & target_id) { 1712 sc->sdtr_done &= ~target_id; 1713 1714 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1715 q_cntl |= ASC_QC_MSG_OUT; 1716 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1717 (sc->max_sdtr_index - 1)], 1718 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1719 } 1720 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1721 1722 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1723 tag_code &= 0xDC; 1724 1725 if ((sc->pci_fix_asyn_xfer & target_id) && 1726 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1727 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1728 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1729 } 1730 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1731 1732 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1733 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1734 1735 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1736 1737 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1738 scsi_busy &= ~target_id; 1739 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1740 1741 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1742 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1743 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1744 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1745 1746 if ((out_msg.msg_type == MS_EXTEND) && 1747 (out_msg.msg_len == MS_SDTR_LEN) && 1748 (out_msg.msg_req == MS_SDTR_CODE)) { 1749 sc->init_sdtr &= ~target_id; 1750 sc->sdtr_done &= ~target_id; 1751 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1752 sc->sdtr_data[tid_no] = asyn_sdtr; 1753 } 1754 q_cntl &= ~ASC_QC_MSG_OUT; 1755 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1756 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1757 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1758 scsi_status = AscReadLramByte(iot, ioh, 1759 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1760 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1761 1762 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1763 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1764 scsi_busy |= target_id; 1765 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1766 sc->queue_full_or_busy |= target_id; 1767 1768 if (scsi_status == SS_QUEUE_FULL) { 1769 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1770 cur_dvc_qng -= 1; 1771 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1772 1773 AscWriteLramByte(iot, ioh, 1774 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1775 1776 #if ASC_QUEUE_FLOW_CONTROL 1777 if ((sc->device[tid_no] != NULL) && 1778 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1779 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1780 } 1781 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1782 } 1783 } 1784 } 1785 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1786 } 1787 return; 1788 } 1789 1790 1791 static int 1792 AscWaitTixISRDone(ASC_SOFTC *sc, u_int8_t target_ix) 1793 { 1794 u_int8_t cur_req; 1795 u_int8_t tid_no; 1796 int i = 0; 1797 1798 tid_no = ASC_TIX_TO_TID(target_ix); 1799 while (i++ < 10) { 1800 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1801 break; 1802 1803 DvcSleepMilliSecond(1000L); 1804 if (sc->cur_dvc_qng[tid_no] == cur_req) 1805 break; 1806 } 1807 return (1); 1808 } 1809 1810 static int 1811 AscWaitISRDone(ASC_SOFTC *sc) 1812 { 1813 int tid; 1814 1815 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1816 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1817 1818 return (1); 1819 } 1820 1821 1822 static u_int8_t 1823 _AscCopyLramScsiDoneQ(bus_space_tag_t iot, bus_space_handle_t ioh, 1824 u_int16_t q_addr, ASC_QDONE_INFO *scsiq, u_int32_t max_dma_count) 1825 { 1826 u_int16_t _val; 1827 u_int8_t sg_queue_cnt; 1828 1829 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 1830 1831 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1832 scsiq->q_status = LO_BYTE(_val); 1833 scsiq->q_no = HI_BYTE(_val); 1834 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1835 scsiq->cntl = LO_BYTE(_val); 1836 sg_queue_cnt = HI_BYTE(_val); 1837 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 1838 scsiq->sense_len = LO_BYTE(_val); 1839 scsiq->extra_bytes = HI_BYTE(_val); 1840 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 1841 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 1842 scsiq->remain_bytes &= max_dma_count; 1843 1844 return (sg_queue_cnt); 1845 } 1846 1847 1848 static void 1849 AscGetQDoneInfo(bus_space_tag_t iot, bus_space_handle_t ioh, 1850 u_int16_t addr, ASC_QDONE_INFO *scsiq) 1851 { 1852 u_int16_t val; 1853 1854 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1855 1856 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1857 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1858 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1859 scsiq->d2.target_ix = LO_BYTE(val); 1860 scsiq->d2.flag = HI_BYTE(val); 1861 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1862 scsiq->d2.cdb_len = LO_BYTE(val); 1863 scsiq->d2.tag_code = HI_BYTE(val); 1864 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1865 1866 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1867 scsiq->d3.done_stat = LO_BYTE(val); 1868 scsiq->d3.host_stat = HI_BYTE(val); 1869 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1870 scsiq->d3.scsi_stat = LO_BYTE(val); 1871 scsiq->d3.scsi_msg = HI_BYTE(val); 1872 } 1873 1874 1875 static void 1876 AscToggleIRQAct(bus_space_tag_t iot, bus_space_handle_t ioh) 1877 { 1878 1879 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 1880 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1881 } 1882 1883 1884 static void 1885 AscDisableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh) 1886 { 1887 u_int16_t cfg; 1888 1889 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1890 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 1891 } 1892 1893 1894 static void 1895 AscEnableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh) 1896 { 1897 u_int16_t cfg; 1898 1899 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1900 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 1901 } 1902 1903 1904 u_int8_t 1905 AscGetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t bus_type) 1906 { 1907 u_int16_t cfg_lsw; 1908 u_int8_t chip_irq; 1909 1910 1911 #if 0 1912 if (bus_type & ASC_IS_EISA) { 1913 cfg_lsw = AscGetEisaChipCfg(iot, ioh); 1914 chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 1915 if((chip_irq == 13) || (chip_irq > 15)) 1916 return (0); 1917 return(chip_irq); 1918 } 1919 #endif 1920 if ((bus_type & ASC_IS_VL) != 0) { 1921 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1922 chip_irq = (cfg_lsw >> 2) & 0x07; 1923 if ((chip_irq == 0) || 1924 (chip_irq == 4) || 1925 (chip_irq == 7)) { 1926 return (0); 1927 } 1928 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 1929 } 1930 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1931 chip_irq = (cfg_lsw >> 2) & 0x03; 1932 if (chip_irq == 3) 1933 chip_irq += 2; 1934 return (chip_irq + ASC_MIN_IRQ_NO); 1935 } 1936 1937 1938 static u_int8_t 1939 AscSetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh, 1940 u_int8_t irq_no, u_int16_t bus_type) 1941 { 1942 u_int16_t cfg_lsw; 1943 1944 1945 if (bus_type & ASC_IS_VL) { 1946 if (irq_no) { 1947 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 1948 irq_no = 0; 1949 else 1950 irq_no -= ASC_MIN_IRQ_NO - 1; 1951 } 1952 1953 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 1954 cfg_lsw |= 0x0010; 1955 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 1956 AscToggleIRQAct(iot, ioh); 1957 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 1958 cfg_lsw |= (irq_no & 0x07) << 2; 1959 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 1960 AscToggleIRQAct(iot, ioh); 1961 1962 return (AscGetChipIRQ(iot, ioh, bus_type)); 1963 } 1964 if (bus_type & ASC_IS_ISA) { 1965 if (irq_no == 15) 1966 irq_no -= 2; 1967 irq_no -= ASC_MIN_IRQ_NO; 1968 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 1969 cfg_lsw |= (irq_no & 0x03) << 2; 1970 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 1971 1972 return (AscGetChipIRQ(iot, ioh, bus_type)); 1973 } 1974 return (0); 1975 } 1976 1977 1978 static void 1979 AscAckInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh) 1980 { 1981 u_int8_t host_flag; 1982 u_int8_t risc_flag; 1983 u_int16_t loop; 1984 1985 1986 loop = 0; 1987 do { 1988 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 1989 if (loop++ > 0x7FFF) 1990 break; 1991 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 1992 1993 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1994 (~ASC_HOST_FLAG_ACK_INT); 1995 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1996 host_flag | ASC_HOST_FLAG_ACK_INT); 1997 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 1998 1999 loop = 0; 2000 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2001 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2002 if (loop++ > 3) 2003 break; 2004 } 2005 2006 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2007 } 2008 2009 2010 static u_int32_t 2011 AscGetMaxDmaCount(u_int16_t bus_type) 2012 { 2013 if (bus_type & ASC_IS_ISA) 2014 return (ASC_MAX_ISA_DMA_COUNT); 2015 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2016 return (ASC_MAX_VL_DMA_COUNT); 2017 return (ASC_MAX_PCI_DMA_COUNT); 2018 } 2019 2020 2021 u_int16_t 2022 AscGetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh) 2023 { 2024 u_int16_t channel; 2025 2026 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2027 if (channel == 0x03) 2028 return (0); 2029 else if (channel == 0x00) 2030 return (7); 2031 return (channel + 4); 2032 } 2033 2034 2035 static u_int16_t 2036 AscSetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh, 2037 u_int16_t dma_channel) 2038 { 2039 u_int16_t cfg_lsw; 2040 u_int8_t value; 2041 2042 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2043 if (dma_channel == 7) 2044 value = 0x00; 2045 else 2046 value = dma_channel - 4; 2047 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2048 cfg_lsw |= value; 2049 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2050 return (AscGetIsaDmaChannel(iot, ioh)); 2051 } 2052 return (0); 2053 } 2054 2055 2056 static u_int8_t 2057 AscGetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh) 2058 { 2059 u_int8_t speed_value; 2060 2061 AscSetBank(iot, ioh, 1); 2062 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2063 speed_value &= 0x07; 2064 AscSetBank(iot, ioh, 0); 2065 return (speed_value); 2066 } 2067 2068 2069 static u_int8_t 2070 AscSetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh, 2071 u_int8_t speed_value) 2072 { 2073 speed_value &= 0x07; 2074 AscSetBank(iot, ioh, 1); 2075 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2076 AscSetBank(iot, ioh, 0); 2077 return (AscGetIsaDmaSpeed(iot, ioh)); 2078 } 2079 2080 2081 /******************************************************************************/ 2082 /* Messages routines */ 2083 /******************************************************************************/ 2084 2085 2086 static void 2087 AscHandleExtMsgIn(ASC_SOFTC *sc, u_int16_t halt_q_addr, u_int8_t q_cntl, 2088 ASC_SCSI_BIT_ID_TYPE target_id, int tid_no, u_int8_t asyn_sdtr) 2089 { 2090 bus_space_tag_t iot = sc->sc_iot; 2091 bus_space_handle_t ioh = sc->sc_ioh; 2092 EXT_MSG ext_msg; 2093 u_int8_t sdtr_data; 2094 int sdtr_accept; 2095 2096 2097 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2098 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2099 2100 if (ext_msg.msg_type == MS_EXTEND && 2101 ext_msg.msg_req == MS_SDTR_CODE && 2102 ext_msg.msg_len == MS_SDTR_LEN) { 2103 sdtr_accept = TRUE; 2104 2105 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2106 sdtr_accept = FALSE; 2107 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2108 } 2109 if ((ext_msg.xfer_period < 2110 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2111 (ext_msg.xfer_period > 2112 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2113 sdtr_accept = FALSE; 2114 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2115 } 2116 if (sdtr_accept) { 2117 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2118 ext_msg.req_ack_offset); 2119 if (sdtr_data == 0xFF) { 2120 q_cntl |= ASC_QC_MSG_OUT; 2121 sc->init_sdtr &= ~target_id; 2122 sc->sdtr_done &= ~target_id; 2123 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2124 sc->sdtr_data[tid_no] = asyn_sdtr; 2125 } 2126 } 2127 if (ext_msg.req_ack_offset == 0) { 2128 q_cntl &= ~ASC_QC_MSG_OUT; 2129 sc->init_sdtr &= ~target_id; 2130 sc->sdtr_done &= ~target_id; 2131 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2132 } else { 2133 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2134 q_cntl &= ~ASC_QC_MSG_OUT; 2135 sc->sdtr_done |= target_id; 2136 sc->init_sdtr |= target_id; 2137 sc->pci_fix_asyn_xfer &= ~target_id; 2138 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2139 ext_msg.req_ack_offset); 2140 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2141 sc->sdtr_data[tid_no] = sdtr_data; 2142 } else { 2143 q_cntl |= ASC_QC_MSG_OUT; 2144 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2145 ext_msg.req_ack_offset); 2146 sc->pci_fix_asyn_xfer &= ~target_id; 2147 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2148 ext_msg.req_ack_offset); 2149 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2150 sc->sdtr_data[tid_no] = sdtr_data; 2151 sc->sdtr_done |= target_id; 2152 sc->init_sdtr |= target_id; 2153 } 2154 } 2155 } else if (ext_msg.msg_type == MS_EXTEND && 2156 ext_msg.msg_req == MS_WDTR_CODE && 2157 ext_msg.msg_len == MS_WDTR_LEN) { 2158 ext_msg.wdtr_width = 0; 2159 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2160 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2161 q_cntl |= ASC_QC_MSG_OUT; 2162 } else { 2163 ext_msg.msg_type = M1_MSG_REJECT; 2164 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2165 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2166 q_cntl |= ASC_QC_MSG_OUT; 2167 } 2168 2169 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2170 } 2171 2172 2173 static u_int8_t 2174 AscMsgOutSDTR(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t sdtr_offset) 2175 { 2176 bus_space_tag_t iot = sc->sc_iot; 2177 bus_space_handle_t ioh = sc->sc_ioh; 2178 EXT_MSG sdtr_buf; 2179 u_int8_t sdtr_period_index; 2180 2181 2182 sdtr_buf.msg_type = MS_EXTEND; 2183 sdtr_buf.msg_len = MS_SDTR_LEN; 2184 sdtr_buf.msg_req = MS_SDTR_CODE; 2185 sdtr_buf.xfer_period = sdtr_period; 2186 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2187 sdtr_buf.req_ack_offset = sdtr_offset; 2188 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2189 sc->max_sdtr_index) { 2190 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2191 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2192 return ((sdtr_period_index << 4) | sdtr_offset); 2193 } else { 2194 sdtr_buf.req_ack_offset = 0; 2195 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2196 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2197 return (0); 2198 } 2199 } 2200 2201 2202 /******************************************************************************/ 2203 /* SDTR routines */ 2204 /******************************************************************************/ 2205 2206 2207 static void 2208 AscSetChipSDTR(bus_space_tag_t iot, bus_space_handle_t ioh, 2209 u_int8_t sdtr_data, u_int8_t tid_no) 2210 { 2211 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2212 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2213 } 2214 2215 2216 static u_int8_t 2217 AscCalSDTRData(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t syn_offset) 2218 { 2219 u_int8_t byte; 2220 u_int8_t sdtr_period_ix; 2221 2222 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2223 if (sdtr_period_ix > sc->max_sdtr_index) 2224 return (0xFF); 2225 2226 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2227 return (byte); 2228 } 2229 2230 2231 static u_int8_t 2232 AscGetSynPeriodIndex(ASC_SOFTC *sc, u_int8_t syn_time) 2233 { 2234 u_int8_t *period_table; 2235 int max_index; 2236 int min_index; 2237 int i; 2238 2239 period_table = sc->sdtr_period_tbl; 2240 max_index = sc->max_sdtr_index; 2241 min_index = sc->host_init_sdtr_index; 2242 if ((syn_time <= period_table[max_index])) { 2243 for (i = min_index; i < (max_index - 1); i++) { 2244 if (syn_time <= period_table[i]) 2245 return (i); 2246 } 2247 2248 return (max_index); 2249 } else 2250 return (max_index + 1); 2251 } 2252 2253 2254 /******************************************************************************/ 2255 /* Queue routines */ 2256 /******************************************************************************/ 2257 2258 /* 2259 * Send a command to the board 2260 */ 2261 int 2262 AscExeScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq) 2263 { 2264 bus_space_tag_t iot = sc->sc_iot; 2265 bus_space_handle_t ioh = sc->sc_ioh; 2266 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2267 int retval; 2268 int n_q_required; 2269 int disable_syn_offset_one_fix; 2270 int i; 2271 u_int32_t addr; 2272 u_int16_t sg_entry_cnt = 0; 2273 u_int16_t sg_entry_cnt_minus_one = 0; 2274 u_int8_t target_ix; 2275 u_int8_t tid_no; 2276 u_int8_t sdtr_data; 2277 u_int8_t extra_bytes; 2278 u_int8_t scsi_cmd; 2279 u_int32_t data_cnt; 2280 2281 2282 scsiq->q1.q_no = 0; 2283 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2284 scsiq->q1.extra_bytes = 0; 2285 2286 retval = ASC_BUSY; 2287 target_ix = scsiq->q2.target_ix; 2288 tid_no = ASC_TIX_TO_TID(target_ix); 2289 n_q_required = 1; 2290 2291 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2292 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2293 sc->sdtr_done &= ~scsiq->q1.target_id; 2294 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2295 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2296 (sc->max_sdtr_index - 1)], 2297 sdtr_data & ASC_SYN_MAX_OFFSET); 2298 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2299 } 2300 /* 2301 * if there is just one segment into S/G list then 2302 * map it as it was a single request, filling 2303 * data_addr and data_cnt of ASC_SCSIQ structure. 2304 */ 2305 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2306 sg_entry_cnt = sg_head->entry_cnt; 2307 2308 if (sg_entry_cnt < 1) 2309 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2310 sg_entry_cnt); 2311 2312 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2313 panic("AscExeScsiQueue: Queue with too many segs."); 2314 2315 if (sg_entry_cnt == 1) { 2316 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2317 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2318 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2319 } 2320 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2321 } 2322 scsi_cmd = scsiq->cdbptr[0]; 2323 disable_syn_offset_one_fix = FALSE; 2324 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2325 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2326 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2327 data_cnt = 0; 2328 for (i = 0; i < sg_entry_cnt; i++) 2329 data_cnt += sg_head->sg_list[i].bytes; 2330 } else { 2331 data_cnt = scsiq->q1.data_cnt; 2332 } 2333 2334 if (data_cnt != 0ul) { 2335 if (data_cnt < 512ul) { 2336 disable_syn_offset_one_fix = TRUE; 2337 } else { 2338 if (scsi_cmd == SCSICMD_Inquiry || 2339 scsi_cmd == SCSICMD_RequestSense || 2340 scsi_cmd == SCSICMD_ReadCapacity || 2341 scsi_cmd == SCSICMD_ReadTOC || 2342 scsi_cmd == SCSICMD_ModeSelect6 || 2343 scsi_cmd == SCSICMD_ModeSense6 || 2344 scsi_cmd == SCSICMD_ModeSelect10 || 2345 scsi_cmd == SCSICMD_ModeSense10) { 2346 disable_syn_offset_one_fix = TRUE; 2347 } 2348 } 2349 } 2350 } 2351 if (disable_syn_offset_one_fix) { 2352 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2353 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2354 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2355 } else { 2356 scsiq->q2.tag_code &= 0x23; 2357 } 2358 2359 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2360 if (sc->bug_fix_cntl) { 2361 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2362 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2363 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2364 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2365 extra_bytes = addr & 0x0003; 2366 if ((extra_bytes != 0) && 2367 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2368 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2369 scsiq->q1.extra_bytes = extra_bytes; 2370 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2371 extra_bytes; 2372 } 2373 } 2374 } 2375 } 2376 sg_head->entry_to_copy = sg_head->entry_cnt; 2377 n_q_required = AscSgListToQueue(sg_entry_cnt); 2378 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2379 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2380 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2381 } 2382 } else { 2383 if (sc->bug_fix_cntl) { 2384 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2385 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2386 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2387 extra_bytes = addr & 0x0003; 2388 if ((extra_bytes != 0) && 2389 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2390 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2391 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2392 scsiq->q1.data_cnt -= extra_bytes; 2393 scsiq->q1.extra_bytes = extra_bytes; 2394 } 2395 } 2396 } 2397 } 2398 } 2399 n_q_required = 1; 2400 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2401 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2402 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2403 } 2404 } 2405 2406 return (retval); 2407 } 2408 2409 2410 static int 2411 AscSendScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t n_q_required) 2412 { 2413 bus_space_tag_t iot = sc->sc_iot; 2414 bus_space_handle_t ioh = sc->sc_ioh; 2415 u_int8_t free_q_head; 2416 u_int8_t next_qp; 2417 u_int8_t tid_no; 2418 u_int8_t target_ix; 2419 int retval; 2420 2421 2422 target_ix = scsiq->q2.target_ix; 2423 tid_no = ASC_TIX_TO_TID(target_ix); 2424 retval = ASC_BUSY; 2425 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2426 2427 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2428 != ASC_QLINK_END) { 2429 if (n_q_required > 1) { 2430 sc->last_q_shortage = 0; 2431 scsiq->sg_head->queue_cnt = n_q_required - 1; 2432 } 2433 scsiq->q1.q_no = free_q_head; 2434 2435 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2436 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2437 sc->cur_total_qng += n_q_required; 2438 sc->cur_dvc_qng[tid_no]++; 2439 } 2440 } 2441 return (retval); 2442 } 2443 2444 2445 static int 2446 AscPutReadySgListQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no) 2447 { 2448 bus_space_tag_t iot = sc->sc_iot; 2449 bus_space_handle_t ioh = sc->sc_ioh; 2450 int retval; 2451 int i; 2452 ASC_SG_HEAD *sg_head; 2453 ASC_SG_LIST_Q scsi_sg_q; 2454 u_int32_t saved_data_addr; 2455 u_int32_t saved_data_cnt; 2456 u_int16_t sg_list_dwords; 2457 u_int16_t sg_index; 2458 u_int16_t sg_entry_cnt; 2459 u_int16_t q_addr; 2460 u_int8_t next_qp; 2461 2462 2463 saved_data_addr = scsiq->q1.data_addr; 2464 saved_data_cnt = scsiq->q1.data_cnt; 2465 2466 if ((sg_head = scsiq->sg_head) != 0) { 2467 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2468 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2469 sg_entry_cnt = sg_head->entry_cnt - 1; 2470 if (sg_entry_cnt != 0) { 2471 q_addr = ASC_QNO_TO_QADDR(q_no); 2472 sg_index = 1; 2473 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2474 scsi_sg_q.sg_head_qp = q_no; 2475 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2476 2477 for (i = 0; i < sg_head->queue_cnt; i++) { 2478 scsi_sg_q.seq_no = i + 1; 2479 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2480 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2481 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2482 if (i == 0) { 2483 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2484 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2485 } else { 2486 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2487 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2488 } 2489 } else { 2490 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2491 sg_list_dwords = sg_entry_cnt << 1; 2492 if (i == 0) { 2493 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2494 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2495 } else { 2496 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2497 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2498 } 2499 2500 sg_entry_cnt = 0; 2501 } 2502 2503 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2504 scsi_sg_q.q_no = next_qp; 2505 q_addr = ASC_QNO_TO_QADDR(next_qp); 2506 2507 /* 2508 * Tell the board how many entries are in the S/G list 2509 */ 2510 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2511 (u_int16_t *) & scsi_sg_q, 2512 sizeof(ASC_SG_LIST_Q) >> 1); 2513 /* 2514 * Tell the board the addresses of the S/G list segments 2515 */ 2516 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2517 (u_int32_t *) & sg_head->sg_list[sg_index], 2518 sg_list_dwords); 2519 sg_index += ASC_SG_LIST_PER_Q; 2520 } 2521 } 2522 } 2523 retval = AscPutReadyQueue(sc, scsiq, q_no); 2524 scsiq->q1.data_addr = saved_data_addr; 2525 scsiq->q1.data_cnt = saved_data_cnt; 2526 return (retval); 2527 } 2528 2529 2530 static int 2531 AscPutReadyQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no) 2532 { 2533 bus_space_tag_t iot = sc->sc_iot; 2534 bus_space_handle_t ioh = sc->sc_ioh; 2535 u_int16_t q_addr; 2536 u_int8_t tid_no; 2537 u_int8_t sdtr_data; 2538 u_int8_t syn_period_ix; 2539 u_int8_t syn_offset; 2540 2541 2542 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2543 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2544 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2545 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2546 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2547 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2548 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2549 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2550 } 2551 q_addr = ASC_QNO_TO_QADDR(q_no); 2552 2553 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2554 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2555 } 2556 scsiq->q1.status = ASC_QS_FREE; 2557 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2558 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2559 2560 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2561 2562 /* 2563 * Let's start the command 2564 */ 2565 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2566 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2567 2568 return (ASC_NOERROR); 2569 } 2570 2571 2572 static void 2573 AscPutSCSIQ(bus_space_tag_t iot, bus_space_handle_t ioh, 2574 u_int16_t addr, ASC_SCSI_Q *scsiq) 2575 { 2576 u_int16_t val; 2577 2578 2579 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2580 2581 /* ASC_SCSIQ_1 */ 2582 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2583 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2584 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2585 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2586 val = LO_WORD(scsiq->q1.data_addr); 2587 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2588 val = HI_WORD(scsiq->q1.data_addr); 2589 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2590 val = LO_WORD(scsiq->q1.data_cnt); 2591 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2592 val = HI_WORD(scsiq->q1.data_cnt); 2593 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2594 val = LO_WORD(scsiq->q1.sense_addr); 2595 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2596 val = HI_WORD(scsiq->q1.sense_addr); 2597 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2598 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2599 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2600 2601 /* ASC_SCSIQ_2 */ 2602 val = LO_WORD(scsiq->q2.ccb_ptr); 2603 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2604 val = HI_WORD(scsiq->q2.ccb_ptr); 2605 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2606 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2607 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2608 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2609 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2610 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2611 } 2612 2613 2614 static int 2615 AscSgListToQueue(int sg_list) 2616 { 2617 int n_sg_list_qs; 2618 2619 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2620 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2621 n_sg_list_qs++; 2622 2623 return (n_sg_list_qs + 1); 2624 } 2625 2626 2627 static u_int 2628 AscGetNumOfFreeQueue(ASC_SOFTC *sc, u_int8_t target_ix, u_int8_t n_qs) 2629 { 2630 u_int cur_used_qs; 2631 u_int cur_free_qs; 2632 2633 2634 if (n_qs == 1) { 2635 cur_used_qs = sc->cur_total_qng + 2636 sc->last_q_shortage + 2637 ASC_MIN_FREE_Q; 2638 } else { 2639 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2640 } 2641 2642 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2643 cur_free_qs = sc->max_total_qng - cur_used_qs; 2644 return (cur_free_qs); 2645 } 2646 if (n_qs > 1) 2647 if ((n_qs > sc->last_q_shortage) && 2648 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2649 sc->last_q_shortage = n_qs; 2650 } 2651 return (0); 2652 } 2653 2654 2655 static u_int8_t 2656 AscAllocFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh, 2657 u_int8_t free_q_head) 2658 { 2659 u_int16_t q_addr; 2660 u_int8_t next_qp; 2661 u_int8_t q_status; 2662 2663 2664 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2665 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2666 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2667 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2668 return (next_qp); 2669 2670 return (ASC_QLINK_END); 2671 } 2672 2673 2674 static u_int8_t 2675 AscAllocMultipleFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh, 2676 u_int8_t free_q_head, u_int8_t n_free_q) 2677 { 2678 u_int8_t i; 2679 2680 for (i = 0; i < n_free_q; i++) { 2681 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2682 if (free_q_head == ASC_QLINK_END) 2683 break; 2684 } 2685 2686 return (free_q_head); 2687 } 2688 2689 2690 static int 2691 AscStopQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh) 2692 { 2693 int count = 0; 2694 2695 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2696 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2697 do { 2698 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2699 ASC_STOP_ACK_RISC_STOP) 2700 return (1); 2701 2702 DvcSleepMilliSecond(100); 2703 } while (count++ < 20); 2704 } 2705 return (0); 2706 } 2707 2708 2709 static void 2710 AscStartQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh) 2711 { 2712 2713 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2714 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2715 } 2716 2717 2718 static void 2719 AscCleanUpBusyQueue(bus_space_tag_t iot, bus_space_handle_t ioh) 2720 { 2721 int count = 0; 2722 u_int8_t stop_code; 2723 2724 2725 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2726 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2727 do { 2728 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2729 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2730 break; 2731 2732 DvcSleepMilliSecond(100); 2733 } while (count++ < 20); 2734 } 2735 } 2736 2737 2738 static int 2739 _AscWaitQDone(bus_space_tag_t iot, bus_space_handle_t ioh, ASC_SCSI_Q *scsiq) 2740 { 2741 u_int16_t q_addr; 2742 u_int8_t q_status; 2743 int count = 0; 2744 2745 while (scsiq->q1.q_no == 0); 2746 2747 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2748 do { 2749 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2750 DvcSleepMilliSecond(100L); 2751 if (count++ > 30) 2752 return (0); 2753 2754 } while ((q_status & ASC_QS_READY) != 0); 2755 2756 return (1); 2757 } 2758 2759 2760 static int 2761 AscCleanUpDiscQueue(bus_space_tag_t iot, bus_space_handle_t ioh) 2762 { 2763 int count; 2764 u_int8_t stop_code; 2765 2766 count = 0; 2767 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2768 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 2769 do { 2770 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2771 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 2772 break; 2773 2774 DvcSleepMilliSecond(100); 2775 } while (count++ < 20); 2776 } 2777 return (1); 2778 } 2779 2780 2781 /******************************************************************************/ 2782 /* Abort and Reset CCB routines */ 2783 /******************************************************************************/ 2784 2785 2786 int 2787 AscAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb) 2788 { 2789 bus_space_tag_t iot = sc->sc_iot; 2790 bus_space_handle_t ioh = sc->sc_ioh; 2791 int retval; 2792 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2793 2794 2795 retval = -1; 2796 saved_unit_not_ready = sc->unit_not_ready; 2797 sc->unit_not_ready = 0xFF; 2798 AscWaitISRDone(sc); 2799 if (AscStopQueueExe(iot, ioh) == 1) { 2800 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 2801 retval = 1; 2802 AscCleanUpBusyQueue(iot, ioh); 2803 AscStartQueueExe(iot, ioh); 2804 } else { 2805 retval = 0; 2806 AscStartQueueExe(iot, ioh); 2807 } 2808 } 2809 sc->unit_not_ready = saved_unit_not_ready; 2810 2811 return (retval); 2812 } 2813 2814 2815 static int 2816 AscRiscHaltedAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb) 2817 { 2818 bus_space_tag_t iot = sc->sc_iot; 2819 bus_space_handle_t ioh = sc->sc_ioh; 2820 u_int16_t q_addr; 2821 u_int8_t q_no; 2822 ASC_QDONE_INFO scsiq_buf; 2823 ASC_QDONE_INFO *scsiq; 2824 ASC_ISR_CALLBACK asc_isr_callback; 2825 int last_int_level; 2826 2827 2828 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2829 last_int_level = DvcEnterCritical(); 2830 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2831 2832 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2833 q_addr = ASC_QNO_TO_QADDR(q_no); 2834 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 2835 q_addr + ASC_SCSIQ_D_CCBPTR); 2836 if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) { 2837 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2838 if (((scsiq->q_status & ASC_QS_READY) != 0) 2839 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 2840 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2841 scsiq->q_status |= ASC_QS_ABORTED; 2842 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2843 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2844 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2845 scsiq->q_status); 2846 (*asc_isr_callback) (sc, scsiq); 2847 return (1); 2848 } 2849 } 2850 } 2851 2852 DvcLeaveCritical(last_int_level); 2853 return (0); 2854 } 2855 2856 2857 static int 2858 AscRiscHaltedAbortTIX(ASC_SOFTC *sc, u_int8_t target_ix) 2859 { 2860 bus_space_tag_t iot = sc->sc_iot; 2861 bus_space_handle_t ioh = sc->sc_ioh; 2862 u_int16_t q_addr; 2863 u_int8_t q_no; 2864 ASC_QDONE_INFO scsiq_buf; 2865 ASC_QDONE_INFO *scsiq; 2866 ASC_ISR_CALLBACK asc_isr_callback; 2867 int last_int_level; 2868 2869 2870 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2871 last_int_level = DvcEnterCritical(); 2872 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2873 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2874 q_addr = ASC_QNO_TO_QADDR(q_no); 2875 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2876 if (((scsiq->q_status & ASC_QS_READY) != 0) && 2877 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 2878 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2879 if (scsiq->d2.target_ix == target_ix) { 2880 scsiq->q_status |= ASC_QS_ABORTED; 2881 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2882 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2883 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2884 scsiq->q_status); 2885 (*asc_isr_callback) (sc, scsiq); 2886 } 2887 } 2888 } 2889 DvcLeaveCritical(last_int_level); 2890 return (1); 2891 } 2892 2893 2894 /* 2895 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 2896 * so we cannot use this function with the actual NetBSD SCSI layer 2897 * because at boot time interrupts are disabled. 2898 */ 2899 int 2900 AscResetDevice(ASC_SOFTC *sc, u_char target_ix) 2901 { 2902 bus_space_tag_t iot = sc->sc_iot; 2903 bus_space_handle_t ioh = sc->sc_ioh; 2904 int retval; 2905 u_int8_t tid_no; 2906 ASC_SCSI_BIT_ID_TYPE target_id; 2907 int i; 2908 ASC_SCSI_REQ_Q scsiq_buf; 2909 ASC_SCSI_REQ_Q *scsiq; 2910 u_int8_t *buf; 2911 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2912 2913 2914 tid_no = ASC_TIX_TO_TID(target_ix); 2915 target_id = ASC_TID_TO_TARGET_ID(tid_no); 2916 saved_unit_not_ready = sc->unit_not_ready; 2917 sc->unit_not_ready = target_id; 2918 retval = ASC_ERROR; 2919 2920 AscWaitTixISRDone(sc, target_ix); 2921 2922 if (AscStopQueueExe(iot, ioh) == 1) { 2923 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 2924 AscCleanUpBusyQueue(iot, ioh); 2925 AscStartQueueExe(iot, ioh); 2926 AscWaitTixISRDone(sc, target_ix); 2927 retval = ASC_NOERROR; 2928 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 2929 buf = (u_char *) & scsiq_buf; 2930 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 2931 *buf++ = 0x00; 2932 scsiq->q1.status = (u_char) ASC_QS_READY; 2933 scsiq->q2.cdb_len = 6; 2934 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 2935 scsiq->q1.target_id = target_id; 2936 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 2937 scsiq->cdbptr = scsiq->cdb; 2938 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 2939 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 2940 sc->unit_not_ready &= ~target_id; 2941 sc->sdtr_done |= target_id; 2942 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 2943 sc->unit_not_ready = target_id; 2944 DvcSleepMilliSecond(1000); 2945 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 2946 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 2947 AscCleanUpDiscQueue(iot, ioh); 2948 AscStartQueueExe(iot, ioh); 2949 if (sc->pci_fix_asyn_xfer & target_id) 2950 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 2951 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 2952 AscWaitTixISRDone(sc, target_ix); 2953 } 2954 } else 2955 retval = ASC_BUSY; 2956 sc->sdtr_done &= ~target_id; 2957 } else { 2958 retval = ASC_ERROR; 2959 AscStartQueueExe(iot, ioh); 2960 } 2961 } 2962 sc->unit_not_ready = saved_unit_not_ready; 2963 return (retval); 2964 } 2965 2966 2967 int 2968 AscResetBus(ASC_SOFTC *sc) 2969 { 2970 bus_space_tag_t iot = sc->sc_iot; 2971 bus_space_handle_t ioh = sc->sc_ioh; 2972 int retval; 2973 int i; 2974 2975 2976 sc->unit_not_ready = 0xFF; 2977 retval = ASC_NOERROR; 2978 2979 AscWaitISRDone(sc); 2980 AscStopQueueExe(iot, ioh); 2981 sc->sdtr_done = 0; 2982 AscResetChipAndScsiBus(iot, ioh); 2983 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 2984 AscReInitLram(sc); 2985 for (i = 0; i <= ASC_MAX_TID; i++) { 2986 sc->cur_dvc_qng[i] = 0; 2987 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 2988 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 2989 } 2990 2991 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 2992 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 2993 retval = ASC_ERROR; 2994 2995 if (AscStartChip(iot, ioh) == 0) 2996 retval = ASC_ERROR; 2997 2998 AscStartQueueExe(iot, ioh); 2999 sc->unit_not_ready = 0; 3000 sc->queue_full_or_busy = 0; 3001 return (retval); 3002 } 3003 3004 3005 /******************************************************************************/ 3006 /* Error Handling routines */ 3007 /******************************************************************************/ 3008 3009 3010 static int 3011 AscSetLibErrorCode(ASC_SOFTC *sc, u_int16_t err_code) 3012 { 3013 /* 3014 * if(sc->err_code == 0) { sc->err_code = err_code; 3015 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3016 err_code); 3017 /* 3018 * } 3019 */ 3020 return (err_code); 3021 } 3022 3023 3024 /******************************************************************************/ 3025 /* Handle bugged borads routines */ 3026 /******************************************************************************/ 3027 3028 3029 void 3030 AscInquiryHandling(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq) 3031 { 3032 bus_space_tag_t iot = sc->sc_iot; 3033 bus_space_handle_t ioh = sc->sc_ioh; 3034 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3035 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3036 3037 orig_init_sdtr = sc->init_sdtr; 3038 orig_use_tagged_qng = sc->use_tagged_qng; 3039 3040 sc->init_sdtr &= ~tid_bit; 3041 sc->can_tagged_qng &= ~tid_bit; 3042 sc->use_tagged_qng &= ~tid_bit; 3043 3044 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3045 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3046 sc->init_sdtr |= tid_bit; 3047 3048 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3049 if (AscTagQueuingSafe(inq)) { 3050 sc->use_tagged_qng |= tid_bit; 3051 sc->can_tagged_qng |= tid_bit; 3052 } 3053 } 3054 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3055 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3056 sc->disc_enable); 3057 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3058 sc->use_tagged_qng); 3059 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3060 sc->can_tagged_qng); 3061 3062 sc->max_dvc_qng[tid_no] = 3063 sc->max_tag_qng[tid_no]; 3064 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3065 sc->max_dvc_qng[tid_no]); 3066 } 3067 if (orig_init_sdtr != sc->init_sdtr) 3068 AscAsyncFix(sc, tid_no, inq); 3069 } 3070 3071 3072 static int 3073 AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq) 3074 { 3075 if ((inq->add_len >= 32) && 3076 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3077 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3078 return 0; 3079 } 3080 return 1; 3081 } 3082 3083 3084 static void 3085 AscAsyncFix(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq) 3086 { 3087 u_int8_t dvc_type; 3088 ASC_SCSI_BIT_ID_TYPE tid_bits; 3089 3090 3091 dvc_type = inq->byte0.peri_dvc_type; 3092 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3093 3094 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3095 if (!(sc->init_sdtr & tid_bits)) { 3096 if ((dvc_type == SCSI_TYPE_CDROM) && 3097 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3098 sc->pci_fix_asyn_xfer_always |= tid_bits; 3099 } 3100 sc->pci_fix_asyn_xfer |= tid_bits; 3101 if ((dvc_type == SCSI_TYPE_PROC) || 3102 (dvc_type == SCSI_TYPE_SCANNER)) { 3103 sc->pci_fix_asyn_xfer &= ~tid_bits; 3104 } 3105 if ((dvc_type == SCSI_TYPE_SASD) && 3106 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3107 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3108 sc->pci_fix_asyn_xfer &= ~tid_bits; 3109 } 3110 if ((dvc_type == SCSI_TYPE_SASD) && 3111 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3112 sc->pci_fix_asyn_xfer &= ~tid_bits; 3113 } 3114 if ((dvc_type == SCSI_TYPE_CDROM) && 3115 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3116 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3117 sc->pci_fix_asyn_xfer &= ~tid_bits; 3118 } 3119 if ((dvc_type == SCSI_TYPE_CDROM) && 3120 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3121 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3122 sc->pci_fix_asyn_xfer &= ~tid_bits; 3123 } 3124 if (sc->pci_fix_asyn_xfer & tid_bits) { 3125 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3126 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3127 } 3128 } 3129 } 3130 } 3131 3132 3133 /******************************************************************************/ 3134 /* Miscellaneous routines */ 3135 /******************************************************************************/ 3136 3137 3138 static int 3139 AscCompareString(u_char *str1, u_char *str2, int len) 3140 { 3141 int i; 3142 int diff; 3143 3144 for (i = 0; i < len; i++) { 3145 diff = (int) (str1[i] - str2[i]); 3146 if (diff != 0) 3147 return (diff); 3148 } 3149 3150 return (0); 3151 } 3152 3153 3154 /******************************************************************************/ 3155 /* Device oriented routines */ 3156 /******************************************************************************/ 3157 3158 3159 static int 3160 DvcEnterCritical(void) 3161 { 3162 int s; 3163 3164 s = splbio(); 3165 return (s); 3166 } 3167 3168 3169 static void 3170 DvcLeaveCritical(int s) 3171 { 3172 3173 splx(s); 3174 } 3175 3176 3177 static void 3178 DvcSleepMilliSecond(u_int32_t n) 3179 { 3180 3181 DELAY(n * 1000); 3182 } 3183 3184 #ifdef UNUSED 3185 static void 3186 DvcDelayMicroSecond(u_int32_t n) 3187 { 3188 3189 DELAY(n); 3190 } 3191 #endif 3192 3193 static void 3194 DvcDelayNanoSecond(u_int32_t n) 3195 { 3196 3197 DELAY((n + 999) / 1000); 3198 } 3199
Indexes created Thu Oct 02 10:09:58 GMT 2025