advlib.c revision 1.2
1 /* 2 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 3 * 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Ported from: 39 */ 40 /* 41 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 42 * 43 * Copyright (c) 1995-1998 Advanced System Products, Inc. 44 * All Rights Reserved. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that redistributions of source 48 * code retain the above copyright notice and this comment without 49 * modification. 50 * 51 */ 52 53 #include <sys/types.h> 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/queue.h> 59 #include <sys/device.h> 60 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsiconf.h> 67 68 #include <vm/vm.h> 69 #include <vm/vm_param.h> 70 #include <vm/pmap.h> 71 72 #include <dev/ic/adv.h> 73 #include <dev/ic/advlib.h> 74 #include <dev/ic/advmcode.h> 75 76 77 /******************************************************************************/ 78 /* Static functions */ 79 /******************************************************************************/ 80 81 /* Initializzation routines */ 82 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 83 u_int16_t, u_int16_t *, u_int16_t)); 84 static void AscInitLram __P((ASC_SOFTC *)); 85 static void AscInitQLinkVar __P((ASC_SOFTC *)); 86 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 87 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 88 89 /* Chip register routines */ 90 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 91 92 /* RISC Chip routines */ 93 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 94 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 95 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 96 u_int8_t)); 97 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 98 static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t, 99 u_int16_t)); 100 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 101 u_int8_t, u_int8_t)); 102 static int ASC_SET_CHIP_SYNRegAtID __P((bus_space_tag_t, bus_space_handle_t, 103 u_int8_t, u_int8_t)); 104 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 105 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 106 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 107 108 /* Lram routines */ 109 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 110 u_int16_t)); 111 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 112 u_int16_t, u_int8_t)); 113 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t)); 115 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int16_t)); 117 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t)); 119 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int32_t)); 121 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t, u_int16_t, int)); 123 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int16_t *, int)); 125 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t *, int)); 127 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int32_t *, int)); 129 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, int)); 131 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 132 133 /* MicroCode routines */ 134 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 135 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 136 137 /* EEProm routines */ 138 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 139 u_int8_t)); 140 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 141 u_int16_t)); 142 static void AscWaitEEPRead __P((void)); 143 static void AscWaitEEPWrite __P((void)); 144 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 145 u_int8_t)); 146 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 147 u_int8_t, u_int16_t)); 148 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 149 ASCEEP_CONFIG *, u_int16_t)); 150 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 151 ASCEEP_CONFIG *, u_int16_t)); 152 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 153 ASCEEP_CONFIG *, u_int16_t)); 154 155 /* Interrupt routines */ 156 static void AscIsrChipHalted __P((ASC_SOFTC *)); 157 static int AscIsrQDone __P((ASC_SOFTC *)); 158 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 159 static int AscWaitISRDone __P((ASC_SOFTC *)); 160 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 161 u_int16_t, ASC_QDONE_INFO *, 162 u_int32_t)); 163 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 164 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 165 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 166 static u_int8_t AscGetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 167 u_int16_t)); 168 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 169 u_int8_t, u_int16_t)); 170 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 171 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 172 static u_int16_t AscGetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t)); 173 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 174 u_int16_t)); 175 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 176 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 177 u_int8_t)); 178 179 /* Messages routines */ 180 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 181 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 182 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 183 184 /* SDTR routines */ 185 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 186 u_int8_t, u_int8_t)); 187 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 188 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 189 190 /* Queue routines */ 191 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 192 static int AscSgListToQueue __P((int)); 193 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 194 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 195 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 196 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 197 u_int8_t)); 198 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 199 bus_space_handle_t, 200 u_int8_t, u_int8_t)); 201 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 202 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 203 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 204 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 205 ASC_SCSI_Q *)); 206 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 207 208 /* Abort and Reset CCB routines */ 209 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, u_int32_t)); 210 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 211 212 /* Error Handling routines */ 213 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 214 215 /* Handle bugged borads routines */ 216 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 217 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 218 219 /* Miscellaneous routines */ 220 static int AscCompareString __P((u_char *, u_char *, int)); 221 222 /* Device oriented routines */ 223 static int DvcEnterCritical __P((void)); 224 static void DvcLeaveCritical __P((int)); 225 static void DvcSleepMilliSecond __P((u_int32_t)); 226 //static void DvcDelayMicroSecond __P((u_int32_t)); 227 static void DvcDelayNanoSecond __P((u_int32_t)); 228 static u_int32_t DvcGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 229 ASC_SG_HEAD *)); 230 static void DvcPutScsiQ __P((bus_space_tag_t, bus_space_handle_t, 231 u_int16_t, u_int16_t *, int)); 232 static void DvcGetQinfo __P((bus_space_tag_t, bus_space_handle_t, 233 u_int16_t, u_int16_t *, int words)); 234 235 236 /******************************************************************************/ 237 /* Initializzation routines */ 238 /******************************************************************************/ 239 240 /* 241 * This function perform the following steps: 242 * - initialize ASC_SOFTC structure with defaults values. 243 * - inquire board registers to know what kind of board it is. 244 * - keep track of bugged borads. 245 */ 246 void 247 AscInitASC_SOFTC(sc) 248 ASC_SOFTC *sc; 249 { 250 bus_space_tag_t iot = sc->sc_iot; 251 bus_space_handle_t ioh = sc->sc_ioh; 252 int i; 253 u_int8_t chip_version; 254 255 256 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 257 ASC_SET_CHIP_STATUS(iot, ioh, 0); 258 259 sc->bug_fix_cntl = 0; 260 sc->pci_fix_asyn_xfer = 0; 261 sc->pci_fix_asyn_xfer_always = 0; 262 sc->sdtr_done = 0; 263 sc->cur_total_qng = 0; 264 sc->last_q_shortage = 0; 265 sc->use_tagged_qng = 0; 266 sc->unit_not_ready = 0; 267 sc->queue_full_or_busy = 0; 268 sc->host_init_sdtr_index = 0; 269 sc->can_tagged_qng = 0; 270 sc->cmd_qng_enabled = 0; 271 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 272 sc->init_sdtr = 0; 273 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 274 sc->scsi_reset_wait = 3; 275 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 276 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 277 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 278 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 279 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 280 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 281 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 282 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 283 sc->chip_version = chip_version; 284 if ((sc->bus_type & ASC_IS_PCI) && 285 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 286 sc->bus_type = ASC_IS_PCI_ULTRA; 287 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 288 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 289 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 290 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 291 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 292 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 293 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 294 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 295 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 296 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 297 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 298 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 299 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 300 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 301 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 302 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 303 sc->max_sdtr_index = 15; 304 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 305 ASC_SET_EXTRA_CONTROL(iot, ioh, 306 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 307 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 308 ASC_SET_EXTRA_CONTROL(iot, ioh, 309 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 310 } else { 311 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 312 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 313 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 314 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 315 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 316 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 317 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 318 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 319 sc->max_sdtr_index = 7; 320 } 321 322 if (sc->bus_type == ASC_IS_PCI) 323 ASC_SET_EXTRA_CONTROL(iot, ioh, 324 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 325 326 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 327 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 328 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 329 sc->bus_type = ASC_IS_ISAPNP; 330 } 331 if ((sc->bus_type & ASC_IS_ISA) != 0) 332 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 333 334 for (i = 0; i <= ASC_MAX_TID; i++) { 335 sc->cur_dvc_qng[i] = 0; 336 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 337 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 338 } 339 } 340 341 342 /* 343 * This function initialize some ASC_SOFTC fields with values read from 344 * on-board EEProm. 345 */ 346 u_int16_t 347 AscInitFromEEP(sc) 348 ASC_SOFTC *sc; 349 { 350 bus_space_tag_t iot = sc->sc_iot; 351 bus_space_handle_t ioh = sc->sc_ioh; 352 ASCEEP_CONFIG eep_config_buf; 353 ASCEEP_CONFIG *eep_config; 354 u_int16_t chksum; 355 u_int16_t warn_code; 356 u_int16_t cfg_msw, cfg_lsw; 357 int i; 358 int write_eep = 0; 359 360 361 warn_code = 0; 362 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 363 AscStopQueueExe(iot, ioh); 364 if ((AscStopChip(iot, ioh) == FALSE) || 365 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 366 AscResetChipAndScsiBus(iot, ioh); 367 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 368 } 369 if (AscIsChipHalted(iot, ioh) == FALSE) 370 return (-1); 371 372 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 373 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 374 return (-2); 375 376 eep_config = (ASCEEP_CONFIG *) & eep_config_buf; 377 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 378 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 379 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 380 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 381 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 382 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 383 } 384 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 385 if (chksum == 0) 386 chksum = 0xAA55; 387 388 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 389 warn_code |= ASC_WARN_AUTO_CONFIG; 390 if (sc->chip_version == 3) { 391 if (eep_config->cfg_lsw != cfg_lsw) { 392 warn_code |= ASC_WARN_EEPROM_RECOVER; 393 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 394 } 395 if (eep_config->cfg_msw != cfg_msw) { 396 warn_code |= ASC_WARN_EEPROM_RECOVER; 397 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 398 } 399 } 400 } 401 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 402 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 403 404 if (chksum != eep_config->chksum) { 405 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 406 ASC_CHIP_VER_PCI_ULTRA_3050) { 407 eep_config->init_sdtr = 0xFF; 408 eep_config->disc_enable = 0xFF; 409 eep_config->start_motor = 0xFF; 410 eep_config->use_cmd_qng = 0; 411 eep_config->max_total_qng = 0xF0; 412 eep_config->max_tag_qng = 0x20; 413 eep_config->cntl = 0xBFFF; 414 eep_config->chip_scsi_id = 7; 415 eep_config->no_scam = 0; 416 eep_config->adapter_info[0] = 0; 417 eep_config->adapter_info[1] = 0; 418 eep_config->adapter_info[2] = 0; 419 eep_config->adapter_info[3] = 0; 420 eep_config->adapter_info[4] = 0; 421 /* Indicate EEPROM-less board. */ 422 eep_config->adapter_info[5] = 0xBB; 423 } else { 424 write_eep = 1; 425 warn_code |= ASC_WARN_EEPROM_CHKSUM; 426 } 427 } 428 sc->sdtr_enable = eep_config->init_sdtr; 429 sc->disc_enable = eep_config->disc_enable; 430 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 431 sc->isa_dma_speed = eep_config->isa_dma_speed; 432 sc->start_motor = eep_config->start_motor; 433 sc->dvc_cntl = eep_config->cntl; 434 sc->adapter_info[0] = eep_config->adapter_info[0]; 435 sc->adapter_info[1] = eep_config->adapter_info[1]; 436 sc->adapter_info[2] = eep_config->adapter_info[2]; 437 sc->adapter_info[3] = eep_config->adapter_info[3]; 438 sc->adapter_info[4] = eep_config->adapter_info[4]; 439 sc->adapter_info[5] = eep_config->adapter_info[5]; 440 441 if (!AscTestExternalLram(iot, ioh)) { 442 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 443 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 444 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 445 } else { 446 eep_config->cfg_msw |= 0x0800; 447 cfg_msw |= 0x0800; 448 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 449 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 450 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 451 } 452 } 453 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 454 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 455 456 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 457 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 458 459 if (eep_config->max_tag_qng > eep_config->max_total_qng) 460 eep_config->max_tag_qng = eep_config->max_total_qng; 461 462 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 463 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 464 465 sc->max_total_qng = eep_config->max_total_qng; 466 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 467 eep_config->use_cmd_qng) { 468 eep_config->disc_enable = eep_config->use_cmd_qng; 469 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 470 } 471 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 472 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 473 474 eep_config->chip_scsi_id &= ASC_MAX_TID; 475 sc->chip_scsi_id = eep_config->chip_scsi_id; 476 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 477 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 478 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 479 } 480 for (i = 0; i <= ASC_MAX_TID; i++) { 481 sc->max_tag_qng[i] = eep_config->max_tag_qng; 482 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 483 (sc->host_init_sdtr_index << 4); 484 } 485 486 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 487 if (write_eep) 488 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 489 490 return (warn_code); 491 } 492 493 494 u_int16_t 495 AscInitFromASC_SOFTC(sc) 496 ASC_SOFTC *sc; 497 { 498 bus_space_tag_t iot = sc->sc_iot; 499 bus_space_handle_t ioh = sc->sc_ioh; 500 u_int16_t cfg_msw; 501 u_int16_t warn_code; 502 u_int16_t pci_device_id = sc->pci_device_id; 503 504 505 warn_code = 0; 506 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 507 508 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 509 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 510 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 511 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 512 } 513 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 514 sc->disc_enable = sc->cmd_qng_enabled; 515 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 516 } 517 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 518 warn_code |= ASC_WARN_AUTO_CONFIG; 519 } 520 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 521 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 522 } 523 if (sc->bus_type & ASC_IS_PCI) { 524 cfg_msw &= 0xFFC0; 525 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 526 527 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 528 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 529 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 530 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 531 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 532 } 533 } 534 } else if (sc->bus_type == ASC_IS_ISAPNP) { 535 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 536 ASC_CHIP_VER_ASYN_BUG) { 537 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 538 } 539 } 540 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 541 542 if (sc->bus_type & ASC_IS_ISA) { 543 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 544 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 545 } 546 return (warn_code); 547 } 548 549 550 /* 551 * - Initialize RISC chip 552 * - Intialize Lram 553 * - Load uCode into Lram 554 * - Enable Interrupts 555 */ 556 int 557 AscInitDriver(sc) 558 ASC_SOFTC *sc; 559 { 560 bus_space_tag_t iot = sc->sc_iot; 561 bus_space_handle_t ioh = sc->sc_ioh; 562 u_int32_t chksum; 563 564 565 if (!AscFindSignature(iot, ioh)) 566 return (1); 567 568 AscDisableInterrupt(iot, ioh); 569 570 AscInitLram(sc); 571 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 572 asc_mcode_size); 573 if (chksum != asc_mcode_chksum) 574 return (2); 575 576 if (AscInitMicroCodeVar(sc) == 0) 577 return (3); 578 579 AscEnableInterrupt(iot, ioh); 580 581 return (0); 582 } 583 584 585 int 586 AscFindSignature(iot, ioh) 587 bus_space_tag_t iot; 588 bus_space_handle_t ioh; 589 { 590 u_int16_t sig_word; 591 592 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 593 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 594 if (sig_word == ASC_1000_ID0W || 595 sig_word == ASC_1000_ID0W_FIX) 596 return (1); 597 } 598 return (0); 599 } 600 601 602 static u_int32_t 603 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 604 bus_space_tag_t iot; 605 bus_space_handle_t ioh; 606 u_int16_t s_addr; 607 u_int16_t *mcode_buf; 608 u_int16_t mcode_size; 609 { 610 u_int32_t chksum; 611 u_int16_t mcode_word_size; 612 u_int16_t mcode_chksum; 613 614 mcode_word_size = mcode_size >> 1; 615 /* clear board memory */ 616 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 617 /* copy uCode to board memory */ 618 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 619 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 620 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 621 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 622 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 623 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 624 625 return (chksum); 626 } 627 628 629 static void 630 AscInitLram(sc) 631 ASC_SOFTC *sc; 632 { 633 bus_space_tag_t iot = sc->sc_iot; 634 bus_space_handle_t ioh = sc->sc_ioh; 635 u_int8_t i; 636 u_int16_t s_addr; 637 638 639 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 640 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 641 642 i = ASC_MIN_ACTIVE_QNO; 643 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 644 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 645 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 647 i++; 648 s_addr += ASC_QBLK_SIZE; 649 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 651 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 652 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 653 } 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 655 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 657 i++; 658 s_addr += ASC_QBLK_SIZE; 659 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 660 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 661 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 662 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 663 } 664 } 665 666 667 void 668 AscReInitLram(sc) 669 ASC_SOFTC *sc; 670 { 671 672 AscInitLram(sc); 673 AscInitQLinkVar(sc); 674 } 675 676 677 static void 678 AscInitQLinkVar(sc) 679 ASC_SOFTC *sc; 680 { 681 bus_space_tag_t iot = sc->sc_iot; 682 bus_space_handle_t ioh = sc->sc_ioh; 683 u_int8_t i; 684 u_int16_t lram_addr; 685 686 687 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 688 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 689 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 690 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 691 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 692 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 693 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 694 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 695 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 696 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 697 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 698 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 699 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 700 lram_addr = ASC_QADR_BEG; 701 for (i = 0; i < 32; i++, lram_addr += 2) 702 AscWriteLramWord(iot, ioh, lram_addr, 0); 703 } 704 705 706 static int 707 AscResetChipAndScsiBus(bus_space_tag_t iot, 708 bus_space_handle_t ioh) 709 { 710 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 711 712 AscStopChip(iot, ioh); 713 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 714 715 DvcDelayNanoSecond(60000); 716 717 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 718 AscSetChipIH(iot, ioh, ASC_INS_HALT); 719 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 720 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 721 722 DvcSleepMilliSecond(200); 723 724 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 725 AscStartChip(iot, ioh); 726 727 DvcSleepMilliSecond(200); 728 729 return (AscIsChipHalted(iot, ioh)); 730 } 731 732 733 static u_int16_t 734 AscGetChipBusType(iot, ioh) 735 bus_space_tag_t iot; 736 bus_space_handle_t ioh; 737 { 738 u_int16_t chip_ver; 739 740 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 741 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 742 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 743 /* 744 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50) 745 * == 0x0C50)) return (ASC_IS_EISA); 746 */ 747 return (ASC_IS_VL); 748 } 749 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 750 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 751 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 752 return (ASC_IS_ISAPNP); 753 754 return (ASC_IS_ISA); 755 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 756 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 757 return (ASC_IS_PCI); 758 759 return (0); 760 } 761 762 763 /******************************************************************************/ 764 /* Chip register routines */ 765 /******************************************************************************/ 766 767 768 static void 769 AscSetBank(iot, ioh, bank) 770 bus_space_tag_t iot; 771 bus_space_handle_t ioh; 772 u_int8_t bank; 773 { 774 u_int8_t val; 775 776 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 777 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 778 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 779 ASC_CC_CHIP_RESET)); 780 781 switch (bank) { 782 case 1: 783 val |= ASC_CC_BANK_ONE; 784 break; 785 786 case 2: 787 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 788 break; 789 790 default: 791 val &= ~ASC_CC_BANK_ONE; 792 } 793 794 ASC_SET_CHIP_CONTROL(iot, ioh, val); 795 return; 796 } 797 798 799 /******************************************************************************/ 800 /* Chip routines */ 801 /******************************************************************************/ 802 803 804 static int 805 AscStartChip(iot, ioh) 806 bus_space_tag_t iot; 807 bus_space_handle_t ioh; 808 { 809 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 810 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 811 return (0); 812 813 return (1); 814 } 815 816 817 static int 818 AscStopChip(iot, ioh) 819 bus_space_tag_t iot; 820 bus_space_handle_t ioh; 821 { 822 u_int8_t cc_val; 823 824 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 825 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 826 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 827 AscSetChipIH(iot, ioh, ASC_INS_HALT); 828 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 829 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 830 return (0); 831 832 return (1); 833 } 834 835 836 static u_int8_t 837 AscGetChipVersion(iot, ioh, bus_type) 838 bus_space_tag_t iot; 839 bus_space_handle_t ioh; 840 u_int16_t bus_type; 841 { 842 if (bus_type & ASC_IS_EISA) { 843 /* 844 * u_int16_t eisa_iop; u_int8_t revision; 845 * 846 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) | 847 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop); 848 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 849 */ 850 } 851 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 852 } 853 854 855 static u_int8_t 856 AscSetChipScsiID(iot, ioh, new_id) 857 bus_space_tag_t iot; 858 bus_space_handle_t ioh; 859 u_int8_t new_id; 860 { 861 u_int16_t cfg_lsw; 862 863 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 864 return (new_id); 865 866 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 867 cfg_lsw &= 0xF8FF; 868 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 869 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 870 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 871 } 872 873 874 static u_int8_t 875 AscGetChipScsiCtrl(iot, ioh) 876 bus_space_tag_t iot; 877 bus_space_handle_t ioh; 878 { 879 u_int8_t scsi_ctrl; 880 881 AscSetBank(iot, ioh, 1); 882 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 883 AscSetBank(iot, ioh, 0); 884 return (scsi_ctrl); 885 } 886 887 888 static int 889 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 890 bus_space_tag_t iot; 891 bus_space_handle_t ioh; 892 u_int8_t tid_no; 893 u_int8_t sdtr_data; 894 { 895 int retval = FALSE; 896 897 if (AscHostReqRiscHalt(iot, ioh)) { 898 retval = ASC_SET_CHIP_SYNRegAtID(iot, ioh, tid_no, sdtr_data); 899 AscStartChip(iot, ioh); 900 } 901 return (retval); 902 } 903 904 905 static int 906 ASC_SET_CHIP_SYNRegAtID(iot, ioh, id, sdtr_data) 907 bus_space_tag_t iot; 908 bus_space_handle_t ioh; 909 u_int8_t id; 910 u_int8_t sdtr_data; 911 { 912 ASC_SCSI_BIT_ID_TYPE org_id; 913 int i; 914 int sta = TRUE; 915 916 AscSetBank(iot, ioh, 1); 917 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 918 for (i = 0; i <= ASC_MAX_TID; i++) 919 if (org_id == (0x01 << i)) 920 break; 921 922 org_id = i; 923 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 924 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 925 AscSetBank(iot, ioh, 0); 926 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 927 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 928 sta = FALSE; 929 } else 930 sta = FALSE; 931 932 AscSetBank(iot, ioh, 1); 933 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 934 AscSetBank(iot, ioh, 0); 935 return (sta); 936 } 937 938 939 static int 940 AscHostReqRiscHalt(iot, ioh) 941 bus_space_tag_t iot; 942 bus_space_handle_t ioh; 943 { 944 int count = 0; 945 int retval = 0; 946 u_int8_t saved_stop_code; 947 948 949 if (AscIsChipHalted(iot, ioh)) 950 return (1); 951 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 952 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 953 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 954 955 do { 956 if (AscIsChipHalted(iot, ioh)) { 957 retval = 1; 958 break; 959 } 960 DvcSleepMilliSecond(100); 961 } while (count++ < 20); 962 963 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 964 965 return (retval); 966 } 967 968 969 static int 970 AscIsChipHalted(iot, ioh) 971 bus_space_tag_t iot; 972 bus_space_handle_t ioh; 973 { 974 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 975 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 976 return (1); 977 978 return (0); 979 } 980 981 982 static void 983 AscSetChipIH(iot, ioh, ins_code) 984 bus_space_tag_t iot; 985 bus_space_handle_t ioh; 986 u_int16_t ins_code; 987 { 988 AscSetBank(iot, ioh, 1); 989 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 990 AscSetBank(iot, ioh, 0); 991 992 return; 993 } 994 995 996 /******************************************************************************/ 997 /* Lram routines */ 998 /******************************************************************************/ 999 1000 1001 static u_int8_t 1002 AscReadLramByte(iot, ioh, addr) 1003 bus_space_tag_t iot; 1004 bus_space_handle_t ioh; 1005 u_int16_t addr; 1006 { 1007 u_int8_t byte_data; 1008 u_int16_t word_data; 1009 1010 1011 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1012 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1013 #if BYTE_ORDER == BIG_ENDIAN 1014 if (addr & 1) 1015 //odd address 1016 byte_data = (u_int8_t) (word_data & 0xFF); 1017 else 1018 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1019 #else 1020 if (addr & 1) 1021 //odd address 1022 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1023 else 1024 byte_data = (u_int8_t) (word_data & 0xFF); 1025 #endif 1026 return (byte_data); 1027 } 1028 1029 1030 static void 1031 AscWriteLramByte(iot, ioh, addr, data) 1032 bus_space_tag_t iot; 1033 bus_space_handle_t ioh; 1034 u_int16_t addr; 1035 u_int8_t data; 1036 { 1037 u_int16_t word_data; 1038 1039 1040 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1041 #if BYTE_ORDER == BIG_ENDIAN 1042 if (addr & 1) 1043 //odd address 1044 { 1045 word_data &= 0xFF00; 1046 word_data |= ((u_int16_t) data) & 0x00FF; 1047 } else { 1048 word_data &= 0xFF00; 1049 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1050 } 1051 #else 1052 if (addr & 1) 1053 //odd address 1054 { 1055 word_data &= 0x00FF; 1056 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1057 } else { 1058 word_data &= 0xFF00; 1059 word_data |= ((u_int16_t) data) & 0x00FF; 1060 } 1061 #endif 1062 AscWriteLramWord(iot, ioh, addr, word_data); 1063 } 1064 1065 1066 static u_int16_t 1067 AscReadLramWord(iot, ioh, addr) 1068 bus_space_tag_t iot; 1069 bus_space_handle_t ioh; 1070 u_int16_t addr; 1071 { 1072 1073 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1074 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1075 } 1076 1077 1078 static void 1079 AscWriteLramWord(iot, ioh, addr, data) 1080 bus_space_tag_t iot; 1081 bus_space_handle_t ioh; 1082 u_int16_t addr; 1083 u_int16_t data; 1084 { 1085 1086 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1087 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1088 } 1089 1090 1091 static u_int32_t 1092 AscReadLramDWord(iot, ioh, addr) 1093 bus_space_tag_t iot; 1094 bus_space_handle_t ioh; 1095 u_int16_t addr; 1096 { 1097 u_int16_t low_word, hi_word; 1098 1099 1100 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1101 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1102 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1103 1104 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1105 } 1106 1107 1108 static void 1109 AscWriteLramDWord(iot, ioh, addr, data) 1110 bus_space_tag_t iot; 1111 bus_space_handle_t ioh; 1112 u_int16_t addr; 1113 u_int32_t data; 1114 { 1115 1116 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1117 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1118 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1119 } 1120 1121 1122 static void 1123 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1124 bus_space_tag_t iot; 1125 bus_space_handle_t ioh; 1126 u_int16_t s_addr; 1127 u_int16_t s_words; 1128 int count; 1129 { 1130 int i; 1131 1132 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1133 for (i = 0; i < count; i++) 1134 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1135 } 1136 1137 1138 static void 1139 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1140 bus_space_tag_t iot; 1141 bus_space_handle_t ioh; 1142 u_int16_t s_addr; 1143 u_int16_t *s_buffer; 1144 int words; 1145 { 1146 int i; 1147 1148 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1149 for (i = 0; i < words; i++, s_buffer++) 1150 ASC_SET_CHIP_LRAM_DATA(iot, ioh, *s_buffer); 1151 } 1152 1153 1154 static void 1155 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1156 bus_space_tag_t iot; 1157 bus_space_handle_t ioh; 1158 u_int16_t s_addr; 1159 u_int16_t *s_buffer; 1160 int words; 1161 { 1162 int i; 1163 1164 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1165 for (i = 0; i < words; i++, s_buffer++) 1166 *s_buffer = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1167 } 1168 1169 1170 static void 1171 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1172 bus_space_tag_t iot; 1173 bus_space_handle_t ioh; 1174 u_int16_t s_addr; 1175 u_int32_t *s_buffer; 1176 int dwords; 1177 { 1178 int i; 1179 int words; 1180 u_int16_t *pw; 1181 1182 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1183 1184 pw = (u_int16_t *) s_buffer; 1185 words = dwords << 1; 1186 for (i = 0; i < words; i++, pw++) 1187 ASC_SET_CHIP_LRAM_DATA(iot, ioh, *pw); 1188 } 1189 1190 1191 static u_int32_t 1192 AscMemSumLramWord(iot, ioh, s_addr, words) 1193 bus_space_tag_t iot; 1194 bus_space_handle_t ioh; 1195 u_int16_t s_addr; 1196 int words; 1197 { 1198 u_int32_t sum = 0L; 1199 u_int16_t i; 1200 1201 1202 for (i = 0; i < words; i++, s_addr += 2) 1203 sum += AscReadLramWord(iot, ioh, s_addr); 1204 1205 return (sum); 1206 } 1207 1208 1209 static int 1210 AscTestExternalLram(iot, ioh) 1211 bus_space_tag_t iot; 1212 bus_space_handle_t ioh; 1213 { 1214 u_int16_t q_addr; 1215 u_int16_t saved_word; 1216 int retval; 1217 1218 1219 retval = 0; 1220 q_addr = ASC_QNO_TO_QADDR(241); 1221 saved_word = AscReadLramWord(iot, ioh, q_addr); 1222 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1223 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1224 DvcSleepMilliSecond(10); 1225 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1226 1227 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1228 retval = 1; 1229 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1230 } 1231 return (retval); 1232 } 1233 1234 1235 /******************************************************************************/ 1236 /* MicroCode routines */ 1237 /******************************************************************************/ 1238 1239 1240 static u_int16_t 1241 AscInitMicroCodeVar(sc) 1242 ASC_SOFTC *sc; 1243 { 1244 bus_space_tag_t iot = sc->sc_iot; 1245 bus_space_handle_t ioh = sc->sc_ioh; 1246 u_int32_t phy_addr; 1247 int i; 1248 1249 1250 for (i = 0; i <= ASC_MAX_TID; i++) 1251 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1252 sc->sdtr_period_offset[i]); 1253 1254 AscInitQLinkVar(sc); 1255 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1256 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1257 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1258 1259 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1260 ASC_OVERRUN_BSIZE)) == 0L) { 1261 return (0); 1262 } else { 1263 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1264 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1265 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1266 ASC_OVERRUN_BSIZE - 8); 1267 } 1268 1269 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1270 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1271 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1272 1273 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1274 return (0); 1275 } 1276 if (AscStartChip(iot, ioh) != 1) { 1277 return (0); 1278 } 1279 return (1); 1280 } 1281 1282 1283 static u_int32_t 1284 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1285 ASC_SOFTC *sc; 1286 u_int8_t *buf_addr; 1287 u_int32_t buf_size; 1288 { 1289 ASC_MIN_SG_HEAD sg_head; 1290 1291 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1292 if (DvcGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1293 buf_size) { 1294 return (0L); 1295 } 1296 if (sg_head.entry_cnt > 1) { 1297 return (0L); 1298 } 1299 return (sg_head.sg_list[0].addr); 1300 } 1301 /******************************************************************************/ 1302 /* EEProm routines */ 1303 /******************************************************************************/ 1304 1305 1306 static int 1307 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1308 bus_space_tag_t iot; 1309 bus_space_handle_t ioh; 1310 u_int8_t cmd_reg; 1311 { 1312 u_int8_t read_back; 1313 int retry; 1314 1315 retry = 0; 1316 1317 while (TRUE) { 1318 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1319 DvcSleepMilliSecond(1); 1320 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1321 if (read_back == cmd_reg) 1322 return (1); 1323 1324 if (retry++ > ASC_EEP_MAX_RETRY) 1325 return (0); 1326 } 1327 } 1328 1329 1330 static int 1331 AscWriteEEPDataReg(iot, ioh, data_reg) 1332 bus_space_tag_t iot; 1333 bus_space_handle_t ioh; 1334 u_int16_t data_reg; 1335 { 1336 u_int16_t read_back; 1337 int retry; 1338 1339 retry = 0; 1340 while (TRUE) { 1341 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1342 DvcSleepMilliSecond(1); 1343 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1344 if (read_back == data_reg) 1345 return (1); 1346 1347 if (retry++ > ASC_EEP_MAX_RETRY) 1348 return (0); 1349 } 1350 } 1351 1352 1353 static void 1354 AscWaitEEPRead(void) 1355 { 1356 1357 DvcSleepMilliSecond(1); 1358 } 1359 1360 1361 static void 1362 AscWaitEEPWrite(void) 1363 { 1364 1365 DvcSleepMilliSecond(1); 1366 } 1367 1368 1369 static u_int16_t 1370 AscReadEEPWord(iot, ioh, addr) 1371 bus_space_tag_t iot; 1372 bus_space_handle_t ioh; 1373 u_int8_t addr; 1374 { 1375 u_int16_t read_wval; 1376 u_int8_t cmd_reg; 1377 1378 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1379 AscWaitEEPRead(); 1380 cmd_reg = addr | ASC_EEP_CMD_READ; 1381 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1382 AscWaitEEPRead(); 1383 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1384 AscWaitEEPRead(); 1385 1386 return (read_wval); 1387 } 1388 1389 1390 static u_int16_t 1391 AscWriteEEPWord(iot, ioh, addr, word_val) 1392 bus_space_tag_t iot; 1393 bus_space_handle_t ioh; 1394 u_int8_t addr; 1395 u_int16_t word_val; 1396 { 1397 u_int16_t read_wval; 1398 1399 read_wval = AscReadEEPWord(iot, ioh, addr); 1400 if (read_wval != word_val) { 1401 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1402 AscWaitEEPRead(); 1403 AscWriteEEPDataReg(iot, ioh, word_val); 1404 AscWaitEEPRead(); 1405 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1406 AscWaitEEPWrite(); 1407 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1408 AscWaitEEPRead(); 1409 return (AscReadEEPWord(iot, ioh, addr)); 1410 } 1411 return (read_wval); 1412 } 1413 1414 1415 static u_int16_t 1416 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1417 bus_space_tag_t iot; 1418 bus_space_handle_t ioh; 1419 ASCEEP_CONFIG *cfg_buf; 1420 u_int16_t bus_type; 1421 { 1422 u_int16_t wval; 1423 u_int16_t sum; 1424 u_int16_t *wbuf; 1425 int cfg_beg; 1426 int cfg_end; 1427 int s_addr; 1428 int isa_pnp_wsize; 1429 1430 1431 wbuf = (u_int16_t *) cfg_buf; 1432 sum = 0; 1433 isa_pnp_wsize = 0; 1434 1435 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1436 wval = AscReadEEPWord(iot, ioh, s_addr); 1437 sum += wval; 1438 *wbuf = wval; 1439 } 1440 1441 if (bus_type & ASC_IS_VL) { 1442 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1443 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1444 } else { 1445 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1446 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1447 } 1448 1449 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1450 wval = AscReadEEPWord(iot, ioh, s_addr); 1451 sum += wval; 1452 *wbuf = wval; 1453 } 1454 1455 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1456 1457 return (sum); 1458 } 1459 1460 1461 static int 1462 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1463 bus_space_tag_t iot; 1464 bus_space_handle_t ioh; 1465 ASCEEP_CONFIG *cfg_buf; 1466 u_int16_t bus_type; 1467 { 1468 int retry; 1469 int n_error; 1470 1471 retry = 0; 1472 while (TRUE) { 1473 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1474 break; 1475 1476 if (++retry > ASC_EEP_MAX_RETRY) 1477 break; 1478 } 1479 1480 return (n_error); 1481 } 1482 1483 1484 static int 1485 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1486 bus_space_tag_t iot; 1487 bus_space_handle_t ioh; 1488 ASCEEP_CONFIG *cfg_buf; 1489 u_int16_t bus_type; 1490 { 1491 int n_error; 1492 u_int16_t *wbuf; 1493 u_int16_t sum; 1494 int s_addr; 1495 int cfg_beg; 1496 int cfg_end; 1497 1498 wbuf = (u_int16_t *) cfg_buf; 1499 n_error = 0; 1500 sum = 0; 1501 1502 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1503 sum += *wbuf; 1504 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1505 n_error++; 1506 } 1507 1508 if (bus_type & ASC_IS_VL) { 1509 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1510 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1511 } else { 1512 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1513 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1514 } 1515 1516 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1517 sum += *wbuf; 1518 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1519 n_error++; 1520 } 1521 1522 *wbuf = sum; 1523 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1524 n_error++; 1525 1526 wbuf = (u_int16_t *) cfg_buf; 1527 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) 1528 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1529 n_error++; 1530 1531 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) 1532 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1533 n_error++; 1534 1535 return (n_error); 1536 } 1537 1538 1539 /******************************************************************************/ 1540 /* Interrupt routines */ 1541 /******************************************************************************/ 1542 1543 1544 int 1545 AscISR(sc) 1546 ASC_SOFTC *sc; 1547 { 1548 bus_space_tag_t iot = sc->sc_iot; 1549 bus_space_handle_t ioh = sc->sc_ioh; 1550 u_int16_t chipstat; 1551 u_int16_t saved_ram_addr; 1552 u_int8_t ctrl_reg; 1553 u_int8_t saved_ctrl_reg; 1554 int int_pending; 1555 int status; 1556 u_int8_t host_flag; 1557 1558 1559 int_pending = FALSE; 1560 1561 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1562 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1563 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1564 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1565 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) 1566 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1567 int_pending = TRUE; 1568 sc->sdtr_done = 0; 1569 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1570 1571 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1572 1573 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1574 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1575 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1576 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1577 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1578 } 1579 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1580 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1581 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1582 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1583 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1584 1585 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1586 AscAckInterrupt(iot, ioh); 1587 int_pending = TRUE; 1588 1589 if ((chipstat & ASC_CSW_HALTED) && 1590 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1591 AscIsrChipHalted(sc); 1592 saved_ctrl_reg &= ~ASC_CC_HALT; 1593 } else { 1594 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1595 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1596 } else { 1597 do { 1598 if ((status = AscIsrQDone(sc)) == 1) 1599 break; 1600 } while (status == 0x11); 1601 } 1602 1603 if (status & 0x80) 1604 int_pending = -1; 1605 } 1606 } 1607 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1608 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1609 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1610 1611 return (1); 1612 /* return(int_pending); */ 1613 } 1614 1615 1616 static int 1617 AscIsrQDone(sc) 1618 ASC_SOFTC *sc; 1619 { 1620 u_int8_t next_qp; 1621 u_int8_t n_q_used; 1622 u_int8_t sg_list_qp; 1623 u_int8_t sg_queue_cnt; 1624 u_int8_t q_cnt; 1625 u_int8_t done_q_tail; 1626 u_int8_t tid_no; 1627 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1628 ASC_SCSI_BIT_ID_TYPE target_id; 1629 bus_space_tag_t iot = sc->sc_iot; 1630 bus_space_handle_t ioh = sc->sc_ioh; 1631 u_int16_t q_addr; 1632 u_int16_t sg_q_addr; 1633 u_int8_t cur_target_qng; 1634 ASC_QDONE_INFO scsiq_buf; 1635 ASC_QDONE_INFO *scsiq; 1636 ASC_ISR_CALLBACK asc_isr_callback; 1637 1638 1639 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1640 n_q_used = 1; 1641 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1642 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1643 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1644 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1645 1646 if (next_qp != ASC_QLINK_END) { 1647 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1648 q_addr = ASC_QNO_TO_QADDR(next_qp); 1649 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1650 sc->max_dma_count); 1651 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1652 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1653 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1654 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1655 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1656 sg_q_addr = q_addr; 1657 sg_list_qp = next_qp; 1658 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1659 sg_list_qp = AscReadLramByte(iot, ioh, 1660 sg_q_addr + ASC_SCSIQ_B_FWD); 1661 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1662 if (sg_list_qp == ASC_QLINK_END) { 1663 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1664 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1665 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1666 panic("AscIsrQDone: Corrupted SG list encountered"); 1667 } 1668 AscWriteLramByte(iot, ioh, 1669 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1670 } 1671 n_q_used = sg_queue_cnt + 1; 1672 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1673 } 1674 if (sc->queue_full_or_busy & target_id) { 1675 cur_target_qng = AscReadLramByte(iot, ioh, 1676 ASC_QADR_BEG + scsiq->d2.target_ix); 1677 1678 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1679 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1680 scsi_busy &= ~target_id; 1681 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1682 sc->queue_full_or_busy &= ~target_id; 1683 } 1684 } 1685 if (sc->cur_total_qng >= n_q_used) { 1686 sc->cur_total_qng -= n_q_used; 1687 if (sc->cur_dvc_qng[tid_no] != 0) 1688 sc->cur_dvc_qng[tid_no]--; 1689 } else { 1690 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1691 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1692 panic("AscIsrQDone: Attempting to free more queues than are active"); 1693 } 1694 1695 if ((scsiq->d2.ccb_ptr == 0UL) || ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1696 return (0x11); 1697 } else if (scsiq->q_status == ASC_QS_DONE) { 1698 scsiq->remain_bytes += scsiq->extra_bytes; 1699 1700 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1701 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1702 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1703 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1704 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1705 } 1706 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1707 AscStopChip(iot, ioh); 1708 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1709 DvcDelayNanoSecond(60000); 1710 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1711 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1712 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1713 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1714 } 1715 } 1716 (*asc_isr_callback) (sc, scsiq); 1717 1718 return (1); 1719 } else { 1720 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1721 panic("AscIsrQDone: completed scsiq with unknown status"); 1722 1723 return (0x80); 1724 } 1725 } 1726 return (0); 1727 } 1728 1729 1730 /* 1731 * handle all the conditions that may halt the board 1732 * waiting us to intervene 1733 */ 1734 static void 1735 AscIsrChipHalted(sc) 1736 ASC_SOFTC *sc; 1737 { 1738 bus_space_tag_t iot = sc->sc_iot; 1739 bus_space_handle_t ioh = sc->sc_ioh; 1740 EXT_MSG out_msg; 1741 u_int16_t int_halt_code; 1742 u_int16_t halt_q_addr; 1743 u_int8_t halt_qp; 1744 u_int8_t target_ix; 1745 u_int8_t tag_code; 1746 u_int8_t q_status; 1747 u_int8_t q_cntl; 1748 u_int8_t tid_no; 1749 u_int8_t cur_dvc_qng; 1750 u_int8_t asyn_sdtr; 1751 u_int8_t scsi_status; 1752 u_int8_t sdtr_data; 1753 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1754 ASC_SCSI_BIT_ID_TYPE target_id; 1755 1756 1757 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1758 1759 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1760 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1761 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1762 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1763 tid_no = ASC_TIX_TO_TID(target_ix); 1764 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1765 1766 if (sc->pci_fix_asyn_xfer & target_id) 1767 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1768 else 1769 asyn_sdtr = 0; 1770 1771 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1772 if (sc->pci_fix_asyn_xfer & target_id) { 1773 AscSetChipSDTR(iot, ioh, 0, tid_no); 1774 sc->sdtr_data[tid_no] = 0; 1775 } 1776 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1777 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1778 if (sc->pci_fix_asyn_xfer & target_id) { 1779 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1780 sc->sdtr_data[tid_no] = asyn_sdtr; 1781 } 1782 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1783 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1784 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1785 tid_no, asyn_sdtr); 1786 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1787 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1788 q_cntl |= ASC_QC_REQ_SENSE; 1789 1790 if (sc->init_sdtr & target_id) { 1791 sc->sdtr_done &= ~target_id; 1792 1793 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1794 q_cntl |= ASC_QC_MSG_OUT; 1795 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1796 (sc->max_sdtr_index - 1)], 1797 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1798 } 1799 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1800 1801 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1802 tag_code &= 0xDC; 1803 1804 if ((sc->pci_fix_asyn_xfer & target_id) && 1805 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1806 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1807 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1808 } 1809 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1810 1811 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1812 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1813 1814 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1815 1816 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1817 scsi_busy &= ~target_id; 1818 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1819 1820 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1821 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1822 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1823 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1824 1825 if ((out_msg.msg_type == MS_EXTEND) && 1826 (out_msg.msg_len == MS_SDTR_LEN) && 1827 (out_msg.msg_req == MS_SDTR_CODE)) { 1828 1829 sc->init_sdtr &= ~target_id; 1830 sc->sdtr_done &= ~target_id; 1831 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1832 sc->sdtr_data[tid_no] = asyn_sdtr; 1833 } 1834 q_cntl &= ~ASC_QC_MSG_OUT; 1835 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1836 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1837 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1838 scsi_status = AscReadLramByte(iot, ioh, 1839 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1840 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1841 1842 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1843 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1844 scsi_busy |= target_id; 1845 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1846 sc->queue_full_or_busy |= target_id; 1847 1848 if (scsi_status == SS_QUEUE_FULL) { 1849 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1850 cur_dvc_qng -= 1; 1851 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1852 1853 AscWriteLramByte(iot, ioh, 1854 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1855 1856 #if ASC_QUEUE_FLOW_CONTROL 1857 if ((sc->device[tid_no] != NULL) && 1858 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1859 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1860 } 1861 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1862 } 1863 } 1864 } 1865 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1866 } 1867 return; 1868 } 1869 1870 1871 static int 1872 AscWaitTixISRDone(sc, target_ix) 1873 ASC_SOFTC *sc; 1874 u_int8_t target_ix; 1875 { 1876 u_int8_t cur_req; 1877 u_int8_t tid_no; 1878 int i = 0; 1879 1880 tid_no = ASC_TIX_TO_TID(target_ix); 1881 while (i++ < 10) { 1882 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1883 break; 1884 1885 DvcSleepMilliSecond(1000L); 1886 if (sc->cur_dvc_qng[tid_no] == cur_req) 1887 break; 1888 } 1889 return (1); 1890 } 1891 1892 static int 1893 AscWaitISRDone(sc) 1894 ASC_SOFTC *sc; 1895 { 1896 int tid; 1897 1898 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1899 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1900 1901 return (1); 1902 } 1903 1904 1905 static u_int8_t 1906 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1907 bus_space_tag_t iot; 1908 bus_space_handle_t ioh; 1909 u_int16_t q_addr; 1910 ASC_QDONE_INFO *scsiq; 1911 u_int32_t max_dma_count; 1912 { 1913 u_int16_t _val; 1914 u_int8_t sg_queue_cnt; 1915 1916 DvcGetQinfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, (u_int16_t *) scsiq, 1917 ((sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2)); 1918 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1919 scsiq->q_status = _val; 1920 scsiq->q_no = (_val >> 8); 1921 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1922 scsiq->cntl = _val; 1923 sg_queue_cnt = (_val >> 8); 1924 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 1925 scsiq->sense_len = _val; 1926 scsiq->extra_bytes = (_val >> 8); 1927 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 1928 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 1929 scsiq->remain_bytes &= max_dma_count; 1930 1931 return (sg_queue_cnt); 1932 } 1933 1934 1935 static void 1936 AscToggleIRQAct(iot, ioh) 1937 bus_space_tag_t iot; 1938 bus_space_handle_t ioh; 1939 { 1940 1941 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 1942 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1943 } 1944 1945 1946 static void 1947 AscDisableInterrupt(iot, ioh) 1948 bus_space_tag_t iot; 1949 bus_space_handle_t ioh; 1950 { 1951 u_int16_t cfg; 1952 1953 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1954 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 1955 } 1956 1957 1958 static void 1959 AscEnableInterrupt(iot, ioh) 1960 bus_space_tag_t iot; 1961 bus_space_handle_t ioh; 1962 { 1963 u_int16_t cfg; 1964 1965 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1966 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 1967 } 1968 1969 1970 static u_int8_t 1971 AscGetChipIRQ(iot, ioh, bus_type) 1972 bus_space_tag_t iot; 1973 bus_space_handle_t ioh; 1974 u_int16_t bus_type; 1975 { 1976 u_int16_t cfg_lsw; 1977 u_int8_t chip_irq; 1978 1979 1980 if (bus_type & ASC_IS_EISA) { 1981 /* 1982 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq = 1983 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) || 1984 * (chip_irq > 15)) return (0); return(chip_irq); 1985 */ 1986 } 1987 if ((bus_type & ASC_IS_VL) != 0) { 1988 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1989 chip_irq = (cfg_lsw >> 2) & 0x07; 1990 if ((chip_irq == 0) || 1991 (chip_irq == 4) || 1992 (chip_irq == 7)) { 1993 return (0); 1994 } 1995 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 1996 } 1997 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1998 chip_irq = (cfg_lsw >> 2) & 0x03; 1999 if (chip_irq == 3) 2000 chip_irq += 2; 2001 return (chip_irq + ASC_MIN_IRQ_NO); 2002 } 2003 2004 2005 static u_int8_t 2006 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2007 bus_space_tag_t iot; 2008 bus_space_handle_t ioh; 2009 u_int8_t irq_no; 2010 u_int16_t bus_type; 2011 { 2012 u_int16_t cfg_lsw; 2013 2014 2015 if (bus_type & ASC_IS_VL) { 2016 if (irq_no) { 2017 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2018 irq_no = 0; 2019 else 2020 irq_no -= ASC_MIN_IRQ_NO - 1; 2021 } 2022 2023 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2024 cfg_lsw |= 0x0010; 2025 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2026 AscToggleIRQAct(iot, ioh); 2027 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2028 cfg_lsw |= (irq_no & 0x07) << 2; 2029 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2030 AscToggleIRQAct(iot, ioh); 2031 2032 return (AscGetChipIRQ(iot, ioh, bus_type)); 2033 } 2034 if (bus_type & ASC_IS_ISA) { 2035 if (irq_no == 15) 2036 irq_no -= 2; 2037 irq_no -= ASC_MIN_IRQ_NO; 2038 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2039 cfg_lsw |= (irq_no & 0x03) << 2; 2040 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2041 2042 return (AscGetChipIRQ(iot, ioh, bus_type)); 2043 } 2044 return (0); 2045 } 2046 2047 2048 static void 2049 AscAckInterrupt(iot, ioh) 2050 bus_space_tag_t iot; 2051 bus_space_handle_t ioh; 2052 { 2053 u_int8_t host_flag; 2054 u_int8_t risc_flag; 2055 u_int16_t loop; 2056 2057 2058 loop = 0; 2059 do { 2060 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2061 if (loop++ > 0x7FFF) 2062 break; 2063 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2064 2065 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2066 (~ASC_HOST_FLAG_ACK_INT); 2067 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2068 host_flag | ASC_HOST_FLAG_ACK_INT); 2069 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2070 2071 loop = 0; 2072 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2073 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2074 if (loop++ > 3) 2075 break; 2076 } 2077 2078 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2079 } 2080 2081 2082 static u_int32_t 2083 AscGetMaxDmaCount(bus_type) 2084 u_int16_t bus_type; 2085 { 2086 if (bus_type & ASC_IS_ISA) 2087 return (ASC_MAX_ISA_DMA_COUNT); 2088 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2089 return (ASC_MAX_VL_DMA_COUNT); 2090 return (ASC_MAX_PCI_DMA_COUNT); 2091 } 2092 2093 2094 static u_int16_t 2095 AscGetIsaDmaChannel(iot, ioh) 2096 bus_space_tag_t iot; 2097 bus_space_handle_t ioh; 2098 { 2099 u_int16_t channel; 2100 2101 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2102 if (channel == 0x03) 2103 return (0); 2104 else if (channel == 0x00) 2105 return (7); 2106 return (channel + 4); 2107 } 2108 2109 2110 static u_int16_t 2111 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2112 bus_space_tag_t iot; 2113 bus_space_handle_t ioh; 2114 u_int16_t dma_channel; 2115 { 2116 u_int16_t cfg_lsw; 2117 u_int8_t value; 2118 2119 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2120 if (dma_channel == 7) 2121 value = 0x00; 2122 else 2123 value = dma_channel - 4; 2124 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2125 cfg_lsw |= value; 2126 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2127 return (AscGetIsaDmaChannel(iot, ioh)); 2128 } 2129 return (0); 2130 } 2131 2132 2133 static u_int8_t 2134 AscGetIsaDmaSpeed(iot, ioh) 2135 bus_space_tag_t iot; 2136 bus_space_handle_t ioh; 2137 { 2138 u_int8_t speed_value; 2139 2140 AscSetBank(iot, ioh, 1); 2141 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2142 speed_value &= 0x07; 2143 AscSetBank(iot, ioh, 0); 2144 return (speed_value); 2145 } 2146 2147 2148 static u_int8_t 2149 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2150 bus_space_tag_t iot; 2151 bus_space_handle_t ioh; 2152 u_int8_t speed_value; 2153 { 2154 speed_value &= 0x07; 2155 AscSetBank(iot, ioh, 1); 2156 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2157 AscSetBank(iot, ioh, 0); 2158 return (AscGetIsaDmaSpeed(iot, ioh)); 2159 } 2160 2161 2162 /******************************************************************************/ 2163 /* Messages routines */ 2164 /******************************************************************************/ 2165 2166 2167 static void 2168 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2169 ASC_SOFTC *sc; 2170 u_int16_t halt_q_addr; 2171 u_int8_t q_cntl; 2172 ASC_SCSI_BIT_ID_TYPE target_id; 2173 int tid_no; 2174 u_int8_t asyn_sdtr; 2175 { 2176 bus_space_tag_t iot = sc->sc_iot; 2177 bus_space_handle_t ioh = sc->sc_ioh; 2178 EXT_MSG ext_msg; 2179 u_int8_t sdtr_data; 2180 int sdtr_accept; 2181 2182 2183 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2184 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2185 2186 if (ext_msg.msg_type == MS_EXTEND && 2187 ext_msg.msg_req == MS_SDTR_CODE && 2188 ext_msg.msg_len == MS_SDTR_LEN) { 2189 sdtr_accept = TRUE; 2190 2191 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2192 sdtr_accept = FALSE; 2193 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2194 } 2195 if ((ext_msg.xfer_period < 2196 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2197 (ext_msg.xfer_period > 2198 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2199 sdtr_accept = FALSE; 2200 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2201 } 2202 if (sdtr_accept) { 2203 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2204 ext_msg.req_ack_offset); 2205 if (sdtr_data == 0xFF) { 2206 q_cntl |= ASC_QC_MSG_OUT; 2207 sc->init_sdtr &= ~target_id; 2208 sc->sdtr_done &= ~target_id; 2209 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2210 sc->sdtr_data[tid_no] = asyn_sdtr; 2211 } 2212 } 2213 if (ext_msg.req_ack_offset == 0) { 2214 q_cntl &= ~ASC_QC_MSG_OUT; 2215 sc->init_sdtr &= ~target_id; 2216 sc->sdtr_done &= ~target_id; 2217 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2218 } else { 2219 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2220 q_cntl &= ~ASC_QC_MSG_OUT; 2221 sc->sdtr_done |= target_id; 2222 sc->init_sdtr |= target_id; 2223 sc->pci_fix_asyn_xfer &= ~target_id; 2224 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2225 ext_msg.req_ack_offset); 2226 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2227 sc->sdtr_data[tid_no] = sdtr_data; 2228 } else { 2229 q_cntl |= ASC_QC_MSG_OUT; 2230 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2231 ext_msg.req_ack_offset); 2232 sc->pci_fix_asyn_xfer &= ~target_id; 2233 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2234 ext_msg.req_ack_offset); 2235 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2236 sc->sdtr_data[tid_no] = sdtr_data; 2237 sc->sdtr_done |= target_id; 2238 sc->init_sdtr |= target_id; 2239 } 2240 } 2241 } else if (ext_msg.msg_type == MS_EXTEND && 2242 ext_msg.msg_req == MS_WDTR_CODE && 2243 ext_msg.msg_len == MS_WDTR_LEN) { 2244 ext_msg.wdtr_width = 0; 2245 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2246 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2247 q_cntl |= ASC_QC_MSG_OUT; 2248 } else { 2249 ext_msg.msg_type = M1_MSG_REJECT; 2250 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2251 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2252 q_cntl |= ASC_QC_MSG_OUT; 2253 } 2254 2255 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2256 } 2257 2258 2259 static u_int8_t 2260 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2261 ASC_SOFTC *sc; 2262 u_int8_t sdtr_period; 2263 u_int8_t sdtr_offset; 2264 { 2265 bus_space_tag_t iot = sc->sc_iot; 2266 bus_space_handle_t ioh = sc->sc_ioh; 2267 EXT_MSG sdtr_buf; 2268 u_int8_t sdtr_period_index; 2269 2270 2271 sdtr_buf.msg_type = MS_EXTEND; 2272 sdtr_buf.msg_len = MS_SDTR_LEN; 2273 sdtr_buf.msg_req = MS_SDTR_CODE; 2274 sdtr_buf.xfer_period = sdtr_period; 2275 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2276 sdtr_buf.req_ack_offset = sdtr_offset; 2277 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2278 sc->max_sdtr_index) { 2279 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2280 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2281 return ((sdtr_period_index << 4) | sdtr_offset); 2282 } else { 2283 sdtr_buf.req_ack_offset = 0; 2284 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2285 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2286 return (0); 2287 } 2288 } 2289 2290 2291 /******************************************************************************/ 2292 /* SDTR routines */ 2293 /******************************************************************************/ 2294 2295 2296 static void 2297 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2298 bus_space_tag_t iot; 2299 bus_space_handle_t ioh; 2300 u_int8_t sdtr_data; 2301 u_int8_t tid_no; 2302 { 2303 ASC_SET_CHIP_SYNRegAtID(iot, ioh, tid_no, sdtr_data); 2304 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2305 } 2306 2307 2308 static u_int8_t 2309 AscCalSDTRData(sc, sdtr_period, syn_offset) 2310 ASC_SOFTC *sc; 2311 u_int8_t sdtr_period; 2312 u_int8_t syn_offset; 2313 { 2314 u_int8_t byte; 2315 u_int8_t sdtr_period_ix; 2316 2317 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2318 if (sdtr_period_ix > sc->max_sdtr_index) 2319 return (0xFF); 2320 2321 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2322 return (byte); 2323 } 2324 2325 2326 static u_int8_t 2327 AscGetSynPeriodIndex(sc, syn_time) 2328 ASC_SOFTC *sc; 2329 u_int8_t syn_time; 2330 { 2331 u_int8_t *period_table; 2332 int max_index; 2333 int min_index; 2334 int i; 2335 2336 period_table = sc->sdtr_period_tbl; 2337 max_index = sc->max_sdtr_index; 2338 min_index = sc->host_init_sdtr_index; 2339 if ((syn_time <= period_table[max_index])) { 2340 for (i = min_index; i < (max_index - 1); i++) { 2341 if (syn_time <= period_table[i]) 2342 return (i); 2343 } 2344 2345 return (max_index); 2346 } else 2347 return (max_index + 1); 2348 } 2349 2350 2351 /******************************************************************************/ 2352 /* Queue routines */ 2353 /******************************************************************************/ 2354 2355 /* 2356 * Send a command to the board 2357 */ 2358 int 2359 AscExeScsiQueue(sc, scsiq) 2360 ASC_SOFTC *sc; 2361 ASC_SCSI_Q *scsiq; 2362 { 2363 bus_space_tag_t iot = sc->sc_iot; 2364 bus_space_handle_t ioh = sc->sc_ioh; 2365 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2366 int retval; 2367 int n_q_required; 2368 int disable_syn_offset_one_fix; 2369 int i; 2370 u_int32_t addr; 2371 u_int16_t sg_entry_cnt = 0; 2372 u_int16_t sg_entry_cnt_minus_one = 0; 2373 u_int8_t target_ix; 2374 u_int8_t tid_no; 2375 u_int8_t sdtr_data; 2376 u_int8_t extra_bytes; 2377 u_int8_t scsi_cmd; 2378 u_int32_t data_cnt; 2379 2380 2381 scsiq->q1.q_no = 0; 2382 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2383 scsiq->q1.extra_bytes = 0; 2384 2385 retval = ASC_BUSY; 2386 target_ix = scsiq->q2.target_ix; 2387 tid_no = ASC_TIX_TO_TID(target_ix); 2388 n_q_required = 1; 2389 2390 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2391 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2392 sc->sdtr_done &= ~scsiq->q1.target_id; 2393 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2394 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2395 (sc->max_sdtr_index - 1)], 2396 sdtr_data & ASC_SYN_MAX_OFFSET); 2397 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2398 } 2399 /* 2400 * if there is just one segment into S/G list then 2401 * map it as it was a single request, filling 2402 * data_addr and data_cnt of ASC_SCSIQ structure. 2403 */ 2404 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2405 sg_entry_cnt = sg_head->entry_cnt; 2406 2407 if (sg_entry_cnt < 1) 2408 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2409 sg_entry_cnt); 2410 2411 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2412 panic("AscExeScsiQueue: Queue with too many segs."); 2413 2414 if (sg_entry_cnt == 1) { 2415 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2416 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2417 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2418 } 2419 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2420 } 2421 scsi_cmd = scsiq->cdbptr[0]; 2422 disable_syn_offset_one_fix = FALSE; 2423 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2424 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2425 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2426 data_cnt = 0; 2427 for (i = 0; i < sg_entry_cnt; i++) 2428 data_cnt += sg_head->sg_list[i].bytes; 2429 } else { 2430 data_cnt = scsiq->q1.data_cnt; 2431 } 2432 2433 if (data_cnt != 0ul) { 2434 if (data_cnt < 512ul) { 2435 disable_syn_offset_one_fix = TRUE; 2436 } else { 2437 if (scsi_cmd == SCSICMD_Inquiry || 2438 scsi_cmd == SCSICMD_RequestSense || 2439 scsi_cmd == SCSICMD_ReadCapacity || 2440 scsi_cmd == SCSICMD_ReadTOC || 2441 scsi_cmd == SCSICMD_ModeSelect6 || 2442 scsi_cmd == SCSICMD_ModeSense6 || 2443 scsi_cmd == SCSICMD_ModeSelect10 || 2444 scsi_cmd == SCSICMD_ModeSense10) { 2445 disable_syn_offset_one_fix = TRUE; 2446 } 2447 } 2448 } 2449 } 2450 if (disable_syn_offset_one_fix) { 2451 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2452 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2453 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2454 } else { 2455 scsiq->q2.tag_code &= 0x23; 2456 } 2457 2458 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2459 if (sc->bug_fix_cntl) { 2460 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2461 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2462 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2463 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2464 extra_bytes = addr & 0x0003; 2465 if ((extra_bytes != 0) && 2466 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2467 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2468 scsiq->q1.extra_bytes = extra_bytes; 2469 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2470 extra_bytes; 2471 } 2472 } 2473 } 2474 } 2475 sg_head->entry_to_copy = sg_head->entry_cnt; 2476 n_q_required = AscSgListToQueue(sg_entry_cnt); 2477 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2478 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2479 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2480 } 2481 } else { 2482 if (sc->bug_fix_cntl) { 2483 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2484 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2485 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2486 extra_bytes = addr & 0x0003; 2487 if ((extra_bytes != 0) && 2488 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2489 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2490 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2491 scsiq->q1.data_cnt -= extra_bytes; 2492 scsiq->q1.extra_bytes = extra_bytes; 2493 } 2494 } 2495 } 2496 } 2497 } 2498 n_q_required = 1; 2499 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2500 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2501 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2502 } 2503 } 2504 2505 return (retval); 2506 } 2507 2508 2509 static int 2510 AscSendScsiQueue(sc, scsiq, n_q_required) 2511 ASC_SOFTC *sc; 2512 ASC_SCSI_Q *scsiq; 2513 u_int8_t n_q_required; 2514 { 2515 bus_space_tag_t iot = sc->sc_iot; 2516 bus_space_handle_t ioh = sc->sc_ioh; 2517 u_int8_t free_q_head; 2518 u_int8_t next_qp; 2519 u_int8_t tid_no; 2520 u_int8_t target_ix; 2521 int retval; 2522 2523 2524 target_ix = scsiq->q2.target_ix; 2525 tid_no = ASC_TIX_TO_TID(target_ix); 2526 retval = ASC_BUSY; 2527 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2528 2529 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2530 != ASC_QLINK_END) { 2531 if (n_q_required > 1) { 2532 sc->last_q_shortage = 0; 2533 scsiq->sg_head->queue_cnt = n_q_required - 1; 2534 } 2535 scsiq->q1.q_no = free_q_head; 2536 2537 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2538 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2539 sc->cur_total_qng += n_q_required; 2540 sc->cur_dvc_qng[tid_no]++; 2541 } 2542 } 2543 return (retval); 2544 } 2545 2546 2547 static int 2548 AscPutReadySgListQueue(sc, scsiq, q_no) 2549 ASC_SOFTC *sc; 2550 ASC_SCSI_Q *scsiq; 2551 u_int8_t q_no; 2552 { 2553 bus_space_tag_t iot = sc->sc_iot; 2554 bus_space_handle_t ioh = sc->sc_ioh; 2555 int retval; 2556 int i; 2557 ASC_SG_HEAD *sg_head; 2558 ASC_SG_LIST_Q scsi_sg_q; 2559 u_int32_t saved_data_addr; 2560 u_int32_t saved_data_cnt; 2561 u_int16_t sg_list_dwords; 2562 u_int16_t sg_index; 2563 u_int16_t sg_entry_cnt; 2564 u_int16_t q_addr; 2565 u_int8_t next_qp; 2566 2567 2568 saved_data_addr = scsiq->q1.data_addr; 2569 saved_data_cnt = scsiq->q1.data_cnt; 2570 2571 if ((sg_head = scsiq->sg_head) != 0) { 2572 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2573 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2574 sg_entry_cnt = sg_head->entry_cnt - 1; 2575 if (sg_entry_cnt != 0) { 2576 q_addr = ASC_QNO_TO_QADDR(q_no); 2577 sg_index = 1; 2578 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2579 scsi_sg_q.sg_head_qp = q_no; 2580 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2581 2582 for (i = 0; i < sg_head->queue_cnt; i++) { 2583 scsi_sg_q.seq_no = i + 1; 2584 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2585 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2586 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2587 if (i == 0) { 2588 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2589 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2590 } else { 2591 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2592 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2593 } 2594 } else { 2595 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2596 sg_list_dwords = sg_entry_cnt << 1; 2597 if (i == 0) { 2598 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2599 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2600 } else { 2601 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2602 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2603 } 2604 2605 sg_entry_cnt = 0; 2606 } 2607 2608 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2609 scsi_sg_q.q_no = next_qp; 2610 q_addr = ASC_QNO_TO_QADDR(next_qp); 2611 2612 /* 2613 * Tell the board how many entries are in the S/G list 2614 */ 2615 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2616 (u_int16_t *) & scsi_sg_q, sizeof(ASC_SG_LIST_Q) >> 1); 2617 /* 2618 * Tell the board the addresses of the S/G list segments 2619 */ 2620 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2621 (u_int32_t *) & sg_head->sg_list[sg_index], sg_list_dwords); 2622 sg_index += ASC_SG_LIST_PER_Q; 2623 } 2624 } 2625 } 2626 retval = AscPutReadyQueue(sc, scsiq, q_no); 2627 scsiq->q1.data_addr = saved_data_addr; 2628 scsiq->q1.data_cnt = saved_data_cnt; 2629 return (retval); 2630 } 2631 2632 2633 static int 2634 AscPutReadyQueue(sc, scsiq, q_no) 2635 ASC_SOFTC *sc; 2636 ASC_SCSI_Q *scsiq; 2637 u_int8_t q_no; 2638 { 2639 bus_space_tag_t iot = sc->sc_iot; 2640 bus_space_handle_t ioh = sc->sc_ioh; 2641 u_int16_t q_addr; 2642 u_int8_t tid_no; 2643 u_int8_t sdtr_data; 2644 u_int8_t syn_period_ix; 2645 u_int8_t syn_offset; 2646 2647 2648 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2649 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2650 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2651 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2652 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2653 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2654 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2655 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2656 } 2657 q_addr = ASC_QNO_TO_QADDR(q_no); 2658 2659 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2660 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2661 } 2662 scsiq->q1.status = ASC_QS_FREE; 2663 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2664 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2665 2666 DvcPutScsiQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, 2667 (u_int16_t *) & scsiq->q1.cntl, 2668 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 2669 2670 /* 2671 * Let's start the command 2672 */ 2673 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2674 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2675 2676 return (ASC_NOERROR); 2677 } 2678 2679 2680 static int 2681 AscSgListToQueue(sg_list) 2682 int sg_list; 2683 { 2684 int n_sg_list_qs; 2685 2686 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2687 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2688 n_sg_list_qs++; 2689 2690 return (n_sg_list_qs + 1); 2691 } 2692 2693 2694 static u_int 2695 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2696 ASC_SOFTC *sc; 2697 u_int8_t target_ix; 2698 u_int8_t n_qs; 2699 { 2700 u_int cur_used_qs; 2701 u_int cur_free_qs; 2702 2703 2704 if (n_qs == 1) { 2705 cur_used_qs = sc->cur_total_qng + 2706 sc->last_q_shortage + 2707 ASC_MIN_FREE_Q; 2708 } else { 2709 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2710 } 2711 2712 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2713 cur_free_qs = sc->max_total_qng - cur_used_qs; 2714 return (cur_free_qs); 2715 } 2716 if (n_qs > 1) 2717 if ((n_qs > sc->last_q_shortage) && 2718 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2719 sc->last_q_shortage = n_qs; 2720 } 2721 return (0); 2722 } 2723 2724 2725 static u_int8_t 2726 AscAllocFreeQueue(iot, ioh, free_q_head) 2727 bus_space_tag_t iot; 2728 bus_space_handle_t ioh; 2729 u_int8_t free_q_head; 2730 { 2731 u_int16_t q_addr; 2732 u_int8_t next_qp; 2733 u_int8_t q_status; 2734 2735 2736 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2737 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2738 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2739 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2740 return (next_qp); 2741 2742 return (ASC_QLINK_END); 2743 } 2744 2745 2746 static u_int8_t 2747 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2748 bus_space_tag_t iot; 2749 bus_space_handle_t ioh; 2750 u_int8_t free_q_head; 2751 u_int8_t n_free_q; 2752 { 2753 u_int8_t i; 2754 2755 for (i = 0; i < n_free_q; i++) { 2756 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2757 if (free_q_head == ASC_QLINK_END) 2758 break; 2759 } 2760 2761 return (free_q_head); 2762 } 2763 2764 2765 static int 2766 AscStopQueueExe(iot, ioh) 2767 bus_space_tag_t iot; 2768 bus_space_handle_t ioh; 2769 { 2770 int count = 0; 2771 2772 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2773 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2774 do { 2775 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2776 ASC_STOP_ACK_RISC_STOP) 2777 return (1); 2778 2779 DvcSleepMilliSecond(100); 2780 } while (count++ < 20); 2781 } 2782 return (0); 2783 } 2784 2785 2786 static void 2787 AscStartQueueExe(iot, ioh) 2788 bus_space_tag_t iot; 2789 bus_space_handle_t ioh; 2790 { 2791 2792 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2793 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2794 } 2795 2796 2797 static void 2798 AscCleanUpBusyQueue(iot, ioh) 2799 bus_space_tag_t iot; 2800 bus_space_handle_t ioh; 2801 { 2802 int count = 0; 2803 u_int8_t stop_code; 2804 2805 2806 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2807 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2808 do { 2809 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2810 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2811 break; 2812 2813 DvcSleepMilliSecond(100); 2814 } while (count++ < 20); 2815 } 2816 } 2817 2818 2819 static int 2820 _AscWaitQDone(iot, ioh, scsiq) 2821 bus_space_tag_t iot; 2822 bus_space_handle_t ioh; 2823 ASC_SCSI_Q *scsiq; 2824 { 2825 u_int16_t q_addr; 2826 u_int8_t q_status; 2827 int count = 0; 2828 2829 while (scsiq->q1.q_no == 0); 2830 2831 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2832 do { 2833 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2834 DvcSleepMilliSecond(100L); 2835 if (count++ > 30) 2836 return (0); 2837 2838 } while ((q_status & ASC_QS_READY) != 0); 2839 2840 return (1); 2841 } 2842 2843 2844 static int 2845 AscCleanUpDiscQueue(iot, ioh) 2846 bus_space_tag_t iot; 2847 bus_space_handle_t ioh; 2848 { 2849 int count; 2850 u_int8_t stop_code; 2851 2852 count = 0; 2853 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2854 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 2855 do { 2856 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2857 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 2858 break; 2859 2860 DvcSleepMilliSecond(100); 2861 } while (count++ < 20); 2862 } 2863 return (1); 2864 } 2865 2866 2867 /******************************************************************************/ 2868 /* Abort and Reset CCB routines */ 2869 /******************************************************************************/ 2870 2871 2872 int 2873 AscAbortCCB(sc, ccb) 2874 ASC_SOFTC *sc; 2875 u_int32_t ccb; 2876 { 2877 bus_space_tag_t iot = sc->sc_iot; 2878 bus_space_handle_t ioh = sc->sc_ioh; 2879 int retval; 2880 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2881 2882 2883 retval = -1; 2884 saved_unit_not_ready = sc->unit_not_ready; 2885 sc->unit_not_ready = 0xFF; 2886 AscWaitISRDone(sc); 2887 if (AscStopQueueExe(iot, ioh) == 1) { 2888 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 2889 retval = 1; 2890 AscCleanUpBusyQueue(iot, ioh); 2891 AscStartQueueExe(iot, ioh); 2892 } else { 2893 retval = 0; 2894 AscStartQueueExe(iot, ioh); 2895 } 2896 } 2897 sc->unit_not_ready = saved_unit_not_ready; 2898 2899 return (retval); 2900 } 2901 2902 2903 static int 2904 AscRiscHaltedAbortCCB(sc, ccb) 2905 ASC_SOFTC *sc; 2906 u_int32_t ccb; 2907 { 2908 bus_space_tag_t iot = sc->sc_iot; 2909 bus_space_handle_t ioh = sc->sc_ioh; 2910 u_int16_t q_addr; 2911 u_int8_t q_no; 2912 ASC_QDONE_INFO scsiq_buf; 2913 ASC_QDONE_INFO *scsiq; 2914 ASC_ISR_CALLBACK asc_isr_callback; 2915 int last_int_level; 2916 2917 2918 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2919 last_int_level = DvcEnterCritical(); 2920 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2921 2922 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2923 q_addr = ASC_QNO_TO_QADDR(q_no); 2924 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 2925 q_addr + ASC_SCSIQ_D_CCBPTR); 2926 if (scsiq->d2.ccb_ptr == ccb) { 2927 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2928 if (((scsiq->q_status & ASC_QS_READY) != 0) 2929 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 2930 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2931 scsiq->q_status |= ASC_QS_ABORTED; 2932 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2933 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2934 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2935 scsiq->q_status); 2936 (*asc_isr_callback) (sc, scsiq); 2937 return (1); 2938 } 2939 } 2940 } 2941 2942 DvcLeaveCritical(last_int_level); 2943 return (0); 2944 } 2945 2946 2947 static int 2948 AscRiscHaltedAbortTIX(sc, target_ix) 2949 ASC_SOFTC *sc; 2950 u_int8_t target_ix; 2951 { 2952 bus_space_tag_t iot = sc->sc_iot; 2953 bus_space_handle_t ioh = sc->sc_ioh; 2954 u_int16_t q_addr; 2955 u_int8_t q_no; 2956 ASC_QDONE_INFO scsiq_buf; 2957 ASC_QDONE_INFO *scsiq; 2958 ASC_ISR_CALLBACK asc_isr_callback; 2959 int last_int_level; 2960 2961 2962 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2963 last_int_level = DvcEnterCritical(); 2964 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2965 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2966 q_addr = ASC_QNO_TO_QADDR(q_no); 2967 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2968 if (((scsiq->q_status & ASC_QS_READY) != 0) && 2969 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 2970 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2971 if (scsiq->d2.target_ix == target_ix) { 2972 scsiq->q_status |= ASC_QS_ABORTED; 2973 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2974 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2975 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2976 scsiq->q_status); 2977 (*asc_isr_callback) (sc, scsiq); 2978 } 2979 } 2980 } 2981 DvcLeaveCritical(last_int_level); 2982 return (1); 2983 } 2984 2985 2986 /* 2987 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 2988 * so we cannot use this function with the actual NetBSD SCSI layer 2989 * because at boot time interrupts are disabled. 2990 */ 2991 int 2992 AscResetDevice(sc, target_ix) 2993 ASC_SOFTC *sc; 2994 u_char target_ix; 2995 { 2996 bus_space_tag_t iot = sc->sc_iot; 2997 bus_space_handle_t ioh = sc->sc_ioh; 2998 int retval; 2999 u_int8_t tid_no; 3000 ASC_SCSI_BIT_ID_TYPE target_id; 3001 int i; 3002 ASC_SCSI_REQ_Q scsiq_buf; 3003 ASC_SCSI_REQ_Q *scsiq; 3004 u_int8_t *buf; 3005 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3006 3007 3008 tid_no = ASC_TIX_TO_TID(target_ix); 3009 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3010 saved_unit_not_ready = sc->unit_not_ready; 3011 sc->unit_not_ready = target_id; 3012 retval = ASC_ERROR; 3013 3014 AscWaitTixISRDone(sc, target_ix); 3015 3016 if (AscStopQueueExe(iot, ioh) == 1) { 3017 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3018 AscCleanUpBusyQueue(iot, ioh); 3019 AscStartQueueExe(iot, ioh); 3020 AscWaitTixISRDone(sc, target_ix); 3021 retval = ASC_NOERROR; 3022 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3023 buf = (u_char *) & scsiq_buf; 3024 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3025 *buf++ = 0x00; 3026 scsiq->q1.status = (u_char) ASC_QS_READY; 3027 scsiq->q2.cdb_len = 6; 3028 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3029 scsiq->q1.target_id = target_id; 3030 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3031 scsiq->cdbptr = (u_int8_t *) scsiq->cdb; 3032 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3033 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3034 sc->unit_not_ready &= ~target_id; 3035 sc->sdtr_done |= target_id; 3036 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3037 sc->unit_not_ready = target_id; 3038 DvcSleepMilliSecond(1000); 3039 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3040 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3041 AscCleanUpDiscQueue(iot, ioh); 3042 AscStartQueueExe(iot, ioh); 3043 if (sc->pci_fix_asyn_xfer & target_id) 3044 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3045 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3046 AscWaitTixISRDone(sc, target_ix); 3047 } 3048 } else 3049 retval = ASC_BUSY; 3050 sc->sdtr_done &= ~target_id; 3051 } else { 3052 retval = ASC_ERROR; 3053 AscStartQueueExe(iot, ioh); 3054 } 3055 } 3056 sc->unit_not_ready = saved_unit_not_ready; 3057 return (retval); 3058 } 3059 3060 3061 int 3062 AscResetBus(sc) 3063 ASC_SOFTC *sc; 3064 { 3065 bus_space_tag_t iot = sc->sc_iot; 3066 bus_space_handle_t ioh = sc->sc_ioh; 3067 int retval; 3068 int i; 3069 3070 3071 sc->unit_not_ready = 0xFF; 3072 retval = ASC_NOERROR; 3073 3074 AscWaitISRDone(sc); 3075 AscStopQueueExe(iot, ioh); 3076 sc->sdtr_done = 0; 3077 AscResetChipAndScsiBus(iot, ioh); 3078 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3079 AscReInitLram(sc); 3080 for (i = 0; i <= ASC_MAX_TID; i++) { 3081 sc->cur_dvc_qng[i] = 0; 3082 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3083 ASC_SET_CHIP_SYNRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3084 } 3085 3086 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3087 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3088 retval = ASC_ERROR; 3089 3090 if (AscStartChip(iot, ioh) == 0) 3091 retval = ASC_ERROR; 3092 3093 AscStartQueueExe(iot, ioh); 3094 sc->unit_not_ready = 0; 3095 sc->queue_full_or_busy = 0; 3096 return (retval); 3097 } 3098 3099 3100 /******************************************************************************/ 3101 /* Error Handling routines */ 3102 /******************************************************************************/ 3103 3104 3105 static int 3106 AscSetLibErrorCode(sc, err_code) 3107 ASC_SOFTC *sc; 3108 u_int16_t err_code; 3109 { 3110 /* 3111 * if(sc->err_code == 0) { sc->err_code = err_code; 3112 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3113 err_code); 3114 /* 3115 * } 3116 */ 3117 return (err_code); 3118 } 3119 3120 3121 /******************************************************************************/ 3122 /* Handle bugged borads routines */ 3123 /******************************************************************************/ 3124 3125 3126 void 3127 AscInquiryHandling(sc, tid_no, inq) 3128 ASC_SOFTC *sc; 3129 u_int8_t tid_no; 3130 ASC_SCSI_INQUIRY *inq; 3131 { 3132 bus_space_tag_t iot = sc->sc_iot; 3133 bus_space_handle_t ioh = sc->sc_ioh; 3134 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3135 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3136 3137 3138 orig_init_sdtr = sc->init_sdtr; 3139 orig_use_tagged_qng = sc->use_tagged_qng; 3140 3141 sc->init_sdtr &= ~tid_bit; 3142 sc->can_tagged_qng &= ~tid_bit; 3143 sc->use_tagged_qng &= ~tid_bit; 3144 3145 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3146 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3147 sc->init_sdtr |= tid_bit; 3148 3149 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3150 if (AscTagQueuingSafe(inq)) { 3151 sc->use_tagged_qng |= tid_bit; 3152 sc->can_tagged_qng |= tid_bit; 3153 } 3154 } 3155 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3156 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3157 sc->disc_enable); 3158 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3159 sc->use_tagged_qng); 3160 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3161 sc->can_tagged_qng); 3162 3163 sc->max_dvc_qng[tid_no] = 3164 sc->max_tag_qng[tid_no]; 3165 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3166 sc->max_dvc_qng[tid_no]); 3167 } 3168 if (orig_init_sdtr != sc->init_sdtr) 3169 AscAsyncFix(sc, tid_no, inq); 3170 } 3171 3172 3173 static int 3174 AscTagQueuingSafe(inq) 3175 ASC_SCSI_INQUIRY *inq; 3176 { 3177 if ((inq->add_len >= 32) && 3178 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3179 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3180 return 0; 3181 } 3182 return 1; 3183 } 3184 3185 3186 static void 3187 AscAsyncFix(sc, tid_no, inq) 3188 ASC_SOFTC *sc; 3189 u_int8_t tid_no; 3190 ASC_SCSI_INQUIRY *inq; 3191 { 3192 u_int8_t dvc_type; 3193 ASC_SCSI_BIT_ID_TYPE tid_bits; 3194 3195 3196 dvc_type = inq->byte0.peri_dvc_type; 3197 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3198 3199 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3200 if (!(sc->init_sdtr & tid_bits)) { 3201 if ((dvc_type == SCSI_TYPE_CDROM) && 3202 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3203 sc->pci_fix_asyn_xfer_always |= tid_bits; 3204 } 3205 sc->pci_fix_asyn_xfer |= tid_bits; 3206 if ((dvc_type == SCSI_TYPE_PROC) || 3207 (dvc_type == SCSI_TYPE_SCANNER)) { 3208 sc->pci_fix_asyn_xfer &= ~tid_bits; 3209 } 3210 if ((dvc_type == SCSI_TYPE_SASD) && 3211 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3212 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3213 sc->pci_fix_asyn_xfer &= ~tid_bits; 3214 } 3215 if ((dvc_type == SCSI_TYPE_SASD) && 3216 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3217 sc->pci_fix_asyn_xfer &= ~tid_bits; 3218 } 3219 if ((dvc_type == SCSI_TYPE_CDROM) && 3220 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3221 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3222 sc->pci_fix_asyn_xfer &= ~tid_bits; 3223 } 3224 if ((dvc_type == SCSI_TYPE_CDROM) && 3225 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3226 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3227 sc->pci_fix_asyn_xfer &= ~tid_bits; 3228 } 3229 if (sc->pci_fix_asyn_xfer & tid_bits) { 3230 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3231 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3232 } 3233 } 3234 } 3235 } 3236 3237 3238 /******************************************************************************/ 3239 /* Miscellaneous routines */ 3240 /******************************************************************************/ 3241 3242 3243 static int 3244 AscCompareString(str1, str2, len) 3245 u_char *str1; 3246 u_char *str2; 3247 int len; 3248 { 3249 int i; 3250 int diff; 3251 3252 for (i = 0; i < len; i++) { 3253 diff = (int) (str1[i] - str2[i]); 3254 if (diff != 0) 3255 return (diff); 3256 } 3257 3258 return (0); 3259 } 3260 3261 3262 /******************************************************************************/ 3263 /* Device oriented routines */ 3264 /******************************************************************************/ 3265 3266 3267 static int 3268 DvcEnterCritical(void) 3269 { 3270 int s; 3271 3272 s = splbio(); 3273 return (s); 3274 } 3275 3276 3277 static void 3278 DvcLeaveCritical(s) 3279 int s; 3280 { 3281 3282 splx(s); 3283 } 3284 3285 3286 static void 3287 DvcSleepMilliSecond(n) 3288 u_int32_t n; 3289 { 3290 3291 DELAY(n * 1000); 3292 } 3293 3294 #ifdef UNUSED 3295 static void 3296 DvcDelayMicroSecond(n) 3297 u_int32_t n; 3298 { 3299 3300 DELAY(n); 3301 } 3302 #endif 3303 3304 static void 3305 DvcDelayNanoSecond(n) 3306 u_int32_t n; 3307 { 3308 3309 DELAY((n + 999) / 1000); 3310 } 3311 3312 3313 static u_int32_t 3314 DvcGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 3315 ASC_SOFTC *sc; 3316 u_int8_t *buf_addr; 3317 u_int32_t buf_len; 3318 ASC_SG_HEAD *asc_sg_head_ptr; 3319 { 3320 u_int32_t buf_size; 3321 3322 buf_size = buf_len; 3323 asc_sg_head_ptr->entry_cnt = 1; 3324 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 3325 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 3326 3327 return (buf_size); 3328 } 3329 3330 3331 static void 3332 DvcPutScsiQ(iot, ioh, s_addr, outbuf, words) 3333 bus_space_tag_t iot; 3334 bus_space_handle_t ioh; 3335 u_int16_t s_addr; 3336 u_int16_t *outbuf; 3337 int words; 3338 { 3339 int i; 3340 3341 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 3342 for (i = 0; i < words; i++, outbuf++) { 3343 if (i == 2 || i == 10) 3344 continue; 3345 3346 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *outbuf); 3347 } 3348 } 3349 3350 3351 static void 3352 DvcGetQinfo(iot, ioh, s_addr, inbuf, words) 3353 bus_space_tag_t iot; 3354 bus_space_handle_t ioh; 3355 u_int16_t s_addr; 3356 u_int16_t *inbuf; 3357 int words; 3358 { 3359 int i; 3360 3361 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 3362 for (i = 0; i < words; i++, inbuf++) { 3363 if (i == 5) 3364 continue; 3365 3366 *inbuf = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 3367 } 3368 } 3369
Indexes created Mon Sep 22 21:09:42 GMT 2025