advlib.c revision 1.27.60.1
1 /* $NetBSD: advlib.c,v 1.27.60.1 2020/04/08 14:08:05 martin Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from: 34 */ 35 /* 36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 37 * 38 * Copyright (c) 1995-1998 Advanced System Products, Inc. 39 * All Rights Reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that redistributions of source 43 * code retain the above copyright notice and this comment without 44 * modification. 45 * 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: advlib.c,v 1.27.60.1 2020/04/08 14:08:05 martin Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/queue.h> 56 #include <sys/device.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/ic/advlib.h> 66 #include <dev/ic/adv.h> 67 #include <dev/ic/advmcode.h> 68 69 70 /* #define ASC_DEBUG */ 71 72 /******************************************************************************/ 73 /* Static functions */ 74 /******************************************************************************/ 75 76 /* Initialization routines */ 77 static u_int32_t AscLoadMicroCode(bus_space_tag_t, bus_space_handle_t, 78 u_int16_t, const u_int16_t *, u_int16_t); 79 static void AscInitLram(ASC_SOFTC *); 80 static void AscInitQLinkVar(ASC_SOFTC *); 81 static int AscResetChipAndScsiBus(bus_space_tag_t, bus_space_handle_t); 82 static u_int16_t AscGetChipBusType(bus_space_tag_t, bus_space_handle_t); 83 #if 0 84 static u_int16_t AscGetEisaChipCfg(bus_space_tag_t, bus_space_handle_t); 85 #endif 86 87 /* Chip register routines */ 88 static void AscSetBank(bus_space_tag_t, bus_space_handle_t, u_int8_t); 89 90 /* RISC Chip routines */ 91 static int AscStartChip(bus_space_tag_t, bus_space_handle_t); 92 static int AscStopChip(bus_space_tag_t, bus_space_handle_t); 93 static u_int8_t AscSetChipScsiID(bus_space_tag_t, bus_space_handle_t, u_int8_t); 94 static u_int8_t AscGetChipScsiCtrl(bus_space_tag_t, bus_space_handle_t); 95 static int AscSetRunChipSynRegAtID(bus_space_tag_t, bus_space_handle_t, 96 u_int8_t, u_int8_t); 97 static int AscSetChipSynRegAtID(bus_space_tag_t, bus_space_handle_t, 98 u_int8_t, u_int8_t); 99 static int AscHostReqRiscHalt(bus_space_tag_t, bus_space_handle_t); 100 static int AscIsChipHalted(bus_space_tag_t, bus_space_handle_t); 101 static void AscSetChipIH(bus_space_tag_t, bus_space_handle_t, u_int16_t); 102 103 /* Lram routines */ 104 static u_int8_t AscReadLramByte(bus_space_tag_t, bus_space_handle_t, u_int16_t); 105 static void AscWriteLramByte(bus_space_tag_t, bus_space_handle_t, 106 u_int16_t, u_int8_t); 107 static u_int16_t AscReadLramWord(bus_space_tag_t, bus_space_handle_t, 108 u_int16_t); 109 static void AscWriteLramWord(bus_space_tag_t, bus_space_handle_t, 110 u_int16_t, u_int16_t); 111 static u_int32_t AscReadLramDWord(bus_space_tag_t, bus_space_handle_t, 112 u_int16_t); 113 static void AscWriteLramDWord(bus_space_tag_t, bus_space_handle_t, 114 u_int16_t, u_int32_t); 115 static void AscMemWordSetLram(bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int16_t, int); 117 static void AscMemWordCopyToLram(bus_space_tag_t, bus_space_handle_t, 118 u_int16_t, const u_int16_t *, int); 119 static void AscMemWordCopyFromLram(bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int16_t *, int); 121 static void AscMemDWordCopyToLram(bus_space_tag_t, bus_space_handle_t, 122 u_int16_t, u_int32_t *, int); 123 static u_int32_t AscMemSumLramWord(bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, int); 125 static int AscTestExternalLram(bus_space_tag_t, bus_space_handle_t); 126 127 /* MicroCode routines */ 128 static u_int16_t AscInitMicroCodeVar(ASC_SOFTC *); 129 130 /* EEProm routines */ 131 static int AscWriteEEPCmdReg(bus_space_tag_t, bus_space_handle_t, u_int8_t); 132 static int AscWriteEEPDataReg(bus_space_tag_t, bus_space_handle_t, u_int16_t); 133 static void AscWaitEEPRead(void); 134 static void AscWaitEEPWrite(void); 135 static u_int16_t AscReadEEPWord(bus_space_tag_t, bus_space_handle_t, u_int8_t); 136 static u_int16_t AscWriteEEPWord(bus_space_tag_t, bus_space_handle_t, 137 u_int8_t, u_int16_t); 138 static u_int16_t AscGetEEPConfig(bus_space_tag_t, bus_space_handle_t, 139 ASCEEP_CONFIG *, u_int16_t); 140 static int AscSetEEPConfig(bus_space_tag_t, bus_space_handle_t, 141 ASCEEP_CONFIG *, u_int16_t); 142 static int AscSetEEPConfigOnce(bus_space_tag_t, bus_space_handle_t, 143 ASCEEP_CONFIG *, u_int16_t); 144 #ifdef ASC_DEBUG 145 static void AscPrintEEPConfig(ASCEEP_CONFIG *, u_int16_t); 146 #endif 147 148 /* Interrupt routines */ 149 static void AscIsrChipHalted(ASC_SOFTC *); 150 static int AscIsrQDone(ASC_SOFTC *); 151 static int AscWaitTixISRDone(ASC_SOFTC *, u_int8_t); 152 static int AscWaitISRDone(ASC_SOFTC *); 153 static u_int8_t _AscCopyLramScsiDoneQ(bus_space_tag_t, bus_space_handle_t, 154 u_int16_t, ASC_QDONE_INFO *, u_int32_t); 155 static void AscGetQDoneInfo(bus_space_tag_t, bus_space_handle_t, u_int16_t, 156 ASC_QDONE_INFO *); 157 static void AscToggleIRQAct(bus_space_tag_t, bus_space_handle_t); 158 static void AscDisableInterrupt(bus_space_tag_t, bus_space_handle_t); 159 static void AscEnableInterrupt(bus_space_tag_t, bus_space_handle_t); 160 static u_int8_t AscSetChipIRQ(bus_space_tag_t, bus_space_handle_t, 161 u_int8_t, u_int16_t); 162 static void AscAckInterrupt(bus_space_tag_t, bus_space_handle_t); 163 static u_int32_t AscGetMaxDmaCount(u_int16_t); 164 static u_int16_t AscSetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t, 165 u_int16_t); 166 static u_int8_t AscGetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t); 167 static u_int8_t AscSetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t, 168 u_int8_t); 169 170 /* Messages routines */ 171 static void AscHandleExtMsgIn(ASC_SOFTC *, u_int16_t, u_int8_t, 172 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t); 173 static u_int8_t AscMsgOutSDTR(ASC_SOFTC *, u_int8_t, u_int8_t); 174 175 /* SDTR routines */ 176 static void AscSetChipSDTR(bus_space_tag_t, bus_space_handle_t, 177 u_int8_t, u_int8_t); 178 static u_int8_t AscCalSDTRData(ASC_SOFTC *, u_int8_t, u_int8_t); 179 static u_int8_t AscGetSynPeriodIndex(ASC_SOFTC *, u_int8_t); 180 181 /* Queue routines */ 182 static int AscSendScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 183 static int AscSgListToQueue(int); 184 static u_int AscGetNumOfFreeQueue(ASC_SOFTC *, u_int8_t, u_int8_t); 185 static int AscPutReadyQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 186 static void AscPutSCSIQ(bus_space_tag_t, bus_space_handle_t, 187 u_int16_t, ASC_SCSI_Q *); 188 static int AscPutReadySgListQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 189 static u_int8_t AscAllocFreeQueue(bus_space_tag_t, bus_space_handle_t, 190 u_int8_t); 191 static u_int8_t AscAllocMultipleFreeQueue(bus_space_tag_t, bus_space_handle_t, 192 u_int8_t, u_int8_t); 193 static int AscStopQueueExe(bus_space_tag_t, bus_space_handle_t); 194 static void AscStartQueueExe(bus_space_tag_t, bus_space_handle_t); 195 static void AscCleanUpBusyQueue(bus_space_tag_t, bus_space_handle_t); 196 static int _AscWaitQDone(bus_space_tag_t, bus_space_handle_t, 197 ASC_SCSI_Q *); 198 static int AscCleanUpDiscQueue(bus_space_tag_t, bus_space_handle_t); 199 200 /* Abort and Reset CCB routines */ 201 static int AscRiscHaltedAbortCCB(ASC_SOFTC *, ADV_CCB *); 202 static int AscRiscHaltedAbortTIX(ASC_SOFTC *, u_int8_t); 203 204 /* Error Handling routines */ 205 static int AscSetLibErrorCode(ASC_SOFTC *, u_int16_t); 206 207 /* Handle bugged borads routines */ 208 static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *); 209 static void AscAsyncFix(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *); 210 211 /* Miscellaneous routines */ 212 static int AscCompareString(const u_char *, const u_char *, int); 213 214 /* Device oriented routines */ 215 static int DvcEnterCritical(void); 216 static void DvcLeaveCritical(int); 217 static void DvcSleepMilliSecond(u_int32_t); 218 #if 0 219 static void DvcDelayMicroSecond(u_int32_t); 220 #endif 221 static void DvcDelayNanoSecond(u_int32_t); 222 223 224 /******************************************************************************/ 225 /* Initialization routines */ 226 /******************************************************************************/ 227 228 /* 229 * This function perform the following steps: 230 * - initialize ASC_SOFTC structure with defaults values. 231 * - inquire board registers to know what kind of board it is. 232 * - keep track of bugged borads. 233 */ 234 void 235 AscInitASC_SOFTC(ASC_SOFTC *sc) 236 { 237 bus_space_tag_t iot = sc->sc_iot; 238 bus_space_handle_t ioh = sc->sc_ioh; 239 int i; 240 241 242 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 243 ASC_SET_CHIP_STATUS(iot, ioh, 0); 244 245 sc->bug_fix_cntl = 0; 246 sc->pci_fix_asyn_xfer = 0; 247 sc->pci_fix_asyn_xfer_always = 0; 248 sc->sdtr_done = 0; 249 sc->cur_total_qng = 0; 250 sc->last_q_shortage = 0; 251 sc->use_tagged_qng = 0; 252 sc->unit_not_ready = 0; 253 sc->queue_full_or_busy = 0; 254 sc->host_init_sdtr_index = 0; 255 sc->can_tagged_qng = 0; 256 sc->cmd_qng_enabled = 0; 257 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 258 sc->init_sdtr = 0; 259 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 260 sc->scsi_reset_wait = 3; 261 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 262 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 263 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 264 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 265 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 266 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 267 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 268 if ((sc->bus_type & ASC_IS_PCI) && 269 (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 270 sc->bus_type = ASC_IS_PCI_ULTRA; 271 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 272 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 273 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 274 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 275 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 276 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 277 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 278 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 279 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 280 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 281 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 282 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 283 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 284 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 285 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 286 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 287 sc->max_sdtr_index = 15; 288 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 289 ASC_SET_EXTRA_CONTROL(iot, ioh, 290 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 291 else if (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 292 ASC_SET_EXTRA_CONTROL(iot, ioh, 293 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 294 } else { 295 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 296 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 297 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 298 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 299 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 300 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 301 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 302 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 303 sc->max_sdtr_index = 7; 304 } 305 306 if (sc->bus_type == ASC_IS_PCI) 307 ASC_SET_EXTRA_CONTROL(iot, ioh, 308 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 309 310 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 311 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 312 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 313 sc->bus_type = ASC_IS_ISAPNP; 314 } 315 if ((sc->bus_type & ASC_IS_ISA) != 0) 316 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 317 318 for (i = 0; i <= ASC_MAX_TID; i++) { 319 sc->cur_dvc_qng[i] = 0; 320 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 321 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 322 } 323 } 324 325 326 /* 327 * This function initialize some ASC_SOFTC fields with values read from 328 * on-board EEProm. 329 */ 330 int16_t 331 AscInitFromEEP(ASC_SOFTC *sc) 332 { 333 bus_space_tag_t iot = sc->sc_iot; 334 bus_space_handle_t ioh = sc->sc_ioh; 335 ASCEEP_CONFIG eep_config_buf; 336 ASCEEP_CONFIG *eep_config; 337 u_int16_t chksum; 338 u_int16_t warn_code; 339 u_int16_t cfg_msw, cfg_lsw; 340 int i; 341 int write_eep = 0; 342 343 344 warn_code = 0; 345 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 346 AscStopQueueExe(iot, ioh); 347 348 AscStopChip(iot, ioh); 349 AscResetChipAndScsiBus(iot, ioh); 350 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 351 352 if ((AscStopChip(iot, ioh) == FALSE) || 353 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 354 AscResetChipAndScsiBus(iot, ioh); 355 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 356 } 357 if (AscIsChipHalted(iot, ioh) == FALSE) 358 return (-1); 359 360 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 361 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 362 return (-2); 363 364 eep_config = &eep_config_buf; 365 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 366 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 367 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 368 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 369 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 370 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 371 } 372 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 373 #ifdef ASC_DEBUG 374 AscPrintEEPConfig(eep_config, chksum); 375 #endif 376 if (chksum == 0) 377 chksum = 0xAA55; 378 379 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 380 warn_code |= ASC_WARN_AUTO_CONFIG; 381 if (sc->chip_version == 3) { 382 if (eep_config->cfg_lsw != cfg_lsw) { 383 warn_code |= ASC_WARN_EEPROM_RECOVER; 384 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 385 } 386 if (eep_config->cfg_msw != cfg_msw) { 387 warn_code |= ASC_WARN_EEPROM_RECOVER; 388 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 389 } 390 } 391 } 392 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 393 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 394 395 if (chksum != eep_config->chksum) { 396 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3050) { 397 eep_config->init_sdtr = 0xFF; 398 eep_config->disc_enable = 0xFF; 399 eep_config->start_motor = 0xFF; 400 eep_config->use_cmd_qng = 0; 401 eep_config->max_total_qng = 0xF0; 402 eep_config->max_tag_qng = 0x20; 403 eep_config->cntl = 0xBFFF; 404 eep_config->chip_scsi_id = 7; 405 eep_config->no_scam = 0; 406 eep_config->adapter_info[0] = 0; 407 eep_config->adapter_info[1] = 0; 408 eep_config->adapter_info[2] = 0; 409 eep_config->adapter_info[3] = 0; 410 #if BYTE_ORDER == BIG_ENDIAN 411 eep_config->adapter_info[5] = 0; 412 /* Indicate EEPROM-less board. */ 413 eep_config->adapter_info[4] = 0xBB; 414 #else 415 eep_config->adapter_info[4] = 0; 416 /* Indicate EEPROM-less board. */ 417 eep_config->adapter_info[5] = 0xBB; 418 #endif 419 } else { 420 write_eep = 1; 421 warn_code |= ASC_WARN_EEPROM_CHKSUM; 422 } 423 } 424 sc->sdtr_enable = eep_config->init_sdtr; 425 sc->disc_enable = eep_config->disc_enable; 426 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 427 sc->isa_dma_speed = eep_config->isa_dma_speed; 428 sc->start_motor = eep_config->start_motor; 429 sc->dvc_cntl = eep_config->cntl; 430 #if BYTE_ORDER == BIG_ENDIAN 431 sc->adapter_info[0] = eep_config->adapter_info[1]; 432 sc->adapter_info[1] = eep_config->adapter_info[0]; 433 sc->adapter_info[2] = eep_config->adapter_info[3]; 434 sc->adapter_info[3] = eep_config->adapter_info[2]; 435 sc->adapter_info[4] = eep_config->adapter_info[5]; 436 sc->adapter_info[5] = eep_config->adapter_info[4]; 437 #else 438 sc->adapter_info[0] = eep_config->adapter_info[0]; 439 sc->adapter_info[1] = eep_config->adapter_info[1]; 440 sc->adapter_info[2] = eep_config->adapter_info[2]; 441 sc->adapter_info[3] = eep_config->adapter_info[3]; 442 sc->adapter_info[4] = eep_config->adapter_info[4]; 443 sc->adapter_info[5] = eep_config->adapter_info[5]; 444 #endif 445 446 if (!AscTestExternalLram(iot, ioh)) { 447 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 448 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 449 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 450 } else { 451 eep_config->cfg_msw |= 0x0800; 452 cfg_msw |= 0x0800; 453 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 454 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 455 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 456 } 457 } 458 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 459 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 460 461 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 462 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 463 464 if (eep_config->max_tag_qng > eep_config->max_total_qng) 465 eep_config->max_tag_qng = eep_config->max_total_qng; 466 467 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 468 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 469 470 sc->max_total_qng = eep_config->max_total_qng; 471 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 472 eep_config->use_cmd_qng) { 473 eep_config->disc_enable = eep_config->use_cmd_qng; 474 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 475 } 476 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 477 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 478 479 eep_config->chip_scsi_id &= ASC_MAX_TID; 480 sc->chip_scsi_id = eep_config->chip_scsi_id; 481 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 482 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 483 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 484 } 485 for (i = 0; i <= ASC_MAX_TID; i++) { 486 sc->max_tag_qng[i] = eep_config->max_tag_qng; 487 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 488 (sc->host_init_sdtr_index << 4); 489 } 490 491 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 492 if (write_eep) { 493 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 494 #ifdef ASC_DEBUG 495 AscPrintEEPConfig(eep_config, 0); 496 #endif 497 } 498 499 return (warn_code); 500 } 501 502 503 u_int16_t 504 AscInitFromASC_SOFTC(ASC_SOFTC *sc) 505 { 506 bus_space_tag_t iot = sc->sc_iot; 507 bus_space_handle_t ioh = sc->sc_ioh; 508 u_int16_t cfg_msw; 509 u_int16_t warn_code; 510 u_int16_t pci_device_id = sc->pci_device_id; 511 512 513 warn_code = 0; 514 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 515 516 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 517 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 518 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 519 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 520 } 521 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 522 sc->disc_enable = sc->cmd_qng_enabled; 523 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 524 } 525 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 526 warn_code |= ASC_WARN_AUTO_CONFIG; 527 } 528 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 529 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 530 } 531 if (sc->bus_type & ASC_IS_PCI) { 532 cfg_msw &= 0xFFC0; 533 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 534 535 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 536 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 537 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 538 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 539 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 540 } 541 } 542 } else if (sc->bus_type == ASC_IS_ISAPNP) { 543 if (sc->chip_version == ASC_CHIP_VER_ASYN_BUG) { 544 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 545 } 546 } 547 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 548 549 if (sc->bus_type & ASC_IS_ISA) { 550 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 551 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 552 } 553 return (warn_code); 554 } 555 556 557 /* 558 * - Initialize RISC chip 559 * - Initialize Lram 560 * - Load uCode into Lram 561 * - Enable Interrupts 562 */ 563 int 564 AscInitDriver(ASC_SOFTC *sc) 565 { 566 bus_space_tag_t iot = sc->sc_iot; 567 bus_space_handle_t ioh = sc->sc_ioh; 568 u_int32_t chksum; 569 570 571 if (!AscFindSignature(iot, ioh)) 572 return (1); 573 574 AscDisableInterrupt(iot, ioh); 575 576 AscInitLram(sc); 577 chksum = AscLoadMicroCode(iot, ioh, 0, (const u_int16_t *) asc_mcode, 578 asc_mcode_size); 579 if (chksum != asc_mcode_chksum) 580 return (2); 581 582 if (AscInitMicroCodeVar(sc) == 0) 583 return (3); 584 585 AscEnableInterrupt(iot, ioh); 586 587 return (0); 588 } 589 590 591 int 592 AscFindSignature(bus_space_tag_t iot, bus_space_handle_t ioh) 593 { 594 u_int16_t sig_word; 595 596 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 597 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 598 if (sig_word == ASC_1000_ID0W || 599 sig_word == ASC_1000_ID0W_FIX) 600 return (1); 601 } 602 return (0); 603 } 604 605 606 static void 607 AscInitLram(ASC_SOFTC *sc) 608 { 609 bus_space_tag_t iot = sc->sc_iot; 610 bus_space_handle_t ioh = sc->sc_ioh; 611 u_int8_t i; 612 u_int16_t s_addr; 613 614 615 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 616 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 617 618 i = ASC_MIN_ACTIVE_QNO; 619 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 620 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 621 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 622 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 623 i++; 624 s_addr += ASC_QBLK_SIZE; 625 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 626 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 627 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 628 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 629 } 630 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 631 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 632 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 633 i++; 634 s_addr += ASC_QBLK_SIZE; 635 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 636 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 637 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 638 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 639 } 640 } 641 642 643 void 644 AscReInitLram(ASC_SOFTC *sc) 645 { 646 647 AscInitLram(sc); 648 AscInitQLinkVar(sc); 649 } 650 651 652 static void 653 AscInitQLinkVar(ASC_SOFTC *sc) 654 { 655 bus_space_tag_t iot = sc->sc_iot; 656 bus_space_handle_t ioh = sc->sc_ioh; 657 u_int8_t i; 658 u_int16_t lram_addr; 659 660 661 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 662 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 663 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 664 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 665 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 666 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 667 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 668 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 669 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 670 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 671 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 672 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 673 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 674 lram_addr = ASC_QADR_BEG; 675 for (i = 0; i < 32; i++, lram_addr += 2) 676 AscWriteLramWord(iot, ioh, lram_addr, 0); 677 } 678 679 680 static int 681 AscResetChipAndScsiBus(bus_space_tag_t iot, bus_space_handle_t ioh) 682 { 683 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 684 685 AscStopChip(iot, ioh); 686 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 687 688 DvcDelayNanoSecond(60000); 689 690 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 691 AscSetChipIH(iot, ioh, ASC_INS_HALT); 692 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 693 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 694 695 DvcSleepMilliSecond(200); 696 697 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 698 ASC_SET_CHIP_STATUS(iot, ioh, 0); 699 700 DvcSleepMilliSecond(200); 701 702 return (AscIsChipHalted(iot, ioh)); 703 } 704 705 706 static u_int16_t 707 AscGetChipBusType(bus_space_tag_t iot, bus_space_handle_t ioh) 708 { 709 u_int16_t chip_ver; 710 711 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 712 #if 0 713 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 714 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 715 if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) { 716 return (ASC_IS_EISA); 717 } 718 else { 719 return (ASC_IS_VL); 720 } 721 } 722 #endif 723 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 724 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 725 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 726 return (ASC_IS_ISAPNP); 727 728 return (ASC_IS_ISA); 729 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 730 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 731 return (ASC_IS_PCI); 732 733 return (0); 734 } 735 736 /* 737 static u_int16_t 738 AscGetEisaChipCfg(bus_space_tag_t iot, bus_space_handle_t ioh) 739 { 740 int eisa_cfg_iop; 741 742 eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK); 743 return (inw(eisa_cfg_iop)); 744 } 745 */ 746 747 /******************************************************************************/ 748 /* Chip register routines */ 749 /******************************************************************************/ 750 751 752 static void 753 AscSetBank(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bank) 754 { 755 u_int8_t val; 756 757 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 758 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 759 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 760 ASC_CC_CHIP_RESET)); 761 762 switch (bank) { 763 case 1: 764 val |= ASC_CC_BANK_ONE; 765 break; 766 767 case 2: 768 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 769 break; 770 771 default: 772 val &= ~ASC_CC_BANK_ONE; 773 } 774 775 ASC_SET_CHIP_CONTROL(iot, ioh, val); 776 return; 777 } 778 779 780 /******************************************************************************/ 781 /* Chip routines */ 782 /******************************************************************************/ 783 784 785 static int 786 AscStartChip(bus_space_tag_t iot, bus_space_handle_t ioh) 787 { 788 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 789 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 790 return (0); 791 792 return (1); 793 } 794 795 796 static int 797 AscStopChip(bus_space_tag_t iot, bus_space_handle_t ioh) 798 { 799 u_int8_t cc_val; 800 801 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 802 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 803 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 804 AscSetChipIH(iot, ioh, ASC_INS_HALT); 805 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 806 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 807 return (0); 808 809 return (1); 810 } 811 812 813 static u_int8_t 814 AscSetChipScsiID(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t new_id) 815 { 816 u_int16_t cfg_lsw; 817 818 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 819 return (new_id); 820 821 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 822 cfg_lsw &= 0xF8FF; 823 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 824 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 825 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 826 } 827 828 829 static u_int8_t 830 AscGetChipScsiCtrl(bus_space_tag_t iot, bus_space_handle_t ioh) 831 { 832 u_int8_t scsi_ctrl; 833 834 AscSetBank(iot, ioh, 1); 835 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 836 AscSetBank(iot, ioh, 0); 837 return (scsi_ctrl); 838 } 839 840 841 static int 842 AscSetRunChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh, 843 u_int8_t tid_no, u_int8_t sdtr_data) 844 { 845 int retval = FALSE; 846 847 if (AscHostReqRiscHalt(iot, ioh)) { 848 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 849 AscStartChip(iot, ioh); 850 } 851 return (retval); 852 } 853 854 855 static int 856 AscSetChipSynRegAtID(bus_space_tag_t iot, bus_space_handle_t ioh, 857 u_int8_t id, u_int8_t sdtr_data) 858 { 859 ASC_SCSI_BIT_ID_TYPE org_id; 860 int i; 861 int stax = TRUE; 862 863 AscSetBank(iot, ioh, 1); 864 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 865 for (i = 0; i <= ASC_MAX_TID; i++) 866 if (org_id == (0x01 << i)) 867 break; 868 869 org_id = i; 870 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 871 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 872 AscSetBank(iot, ioh, 0); 873 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 874 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 875 stax = FALSE; 876 } else 877 stax = FALSE; 878 879 AscSetBank(iot, ioh, 1); 880 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 881 AscSetBank(iot, ioh, 0); 882 return (stax); 883 } 884 885 886 static int 887 AscHostReqRiscHalt(bus_space_tag_t iot, bus_space_handle_t ioh) 888 { 889 int count = 0; 890 int retval = 0; 891 u_int8_t saved_stop_code; 892 893 894 if (AscIsChipHalted(iot, ioh)) 895 return (1); 896 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 897 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 898 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 899 900 do { 901 if (AscIsChipHalted(iot, ioh)) { 902 retval = 1; 903 break; 904 } 905 DvcSleepMilliSecond(100); 906 } while (count++ < 20); 907 908 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 909 910 return (retval); 911 } 912 913 914 static int 915 AscIsChipHalted(bus_space_tag_t iot, bus_space_handle_t ioh) 916 { 917 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 918 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 919 return (1); 920 921 return (0); 922 } 923 924 925 static void 926 AscSetChipIH(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t ins_code) 927 { 928 AscSetBank(iot, ioh, 1); 929 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 930 AscSetBank(iot, ioh, 0); 931 932 return; 933 } 934 935 936 /******************************************************************************/ 937 /* Lram routines */ 938 /******************************************************************************/ 939 940 941 static u_int8_t 942 AscReadLramByte(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr) 943 { 944 u_int8_t byte_data; 945 u_int16_t word_data; 946 947 948 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 949 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 950 951 if (addr & 1) { 952 /* odd address */ 953 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 954 } else { 955 /* even address */ 956 byte_data = (u_int8_t) (word_data & 0xFF); 957 } 958 959 return (byte_data); 960 } 961 962 963 static void 964 AscWriteLramByte(bus_space_tag_t iot, bus_space_handle_t ioh, 965 u_int16_t addr, u_int8_t data) 966 { 967 u_int16_t word_data; 968 969 970 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 971 972 if (addr & 1) { 973 /* odd address */ 974 word_data &= 0x00FF; 975 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 976 } else { 977 /* even address */ 978 word_data &= 0xFF00; 979 word_data |= ((u_int16_t) data) & 0x00FF; 980 } 981 982 AscWriteLramWord(iot, ioh, addr & 0xFFFE, word_data); 983 } 984 985 986 static u_int16_t 987 AscReadLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr) 988 { 989 990 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 991 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 992 } 993 994 995 static void 996 AscWriteLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, 997 u_int16_t addr, u_int16_t data) 998 { 999 1000 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1001 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1002 } 1003 1004 1005 static u_int32_t 1006 AscReadLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t addr) 1007 { 1008 u_int16_t low_word, hi_word; 1009 1010 1011 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1012 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1013 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1014 1015 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1016 } 1017 1018 1019 static void 1020 AscWriteLramDWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1021 u_int16_t addr, u_int32_t data) 1022 { 1023 1024 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1025 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1026 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1027 } 1028 1029 1030 static void 1031 AscMemWordSetLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1032 u_int16_t s_addr, u_int16_t s_words, int count) 1033 { 1034 int i; 1035 1036 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1037 for (i = 0; i < count; i++) 1038 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1039 } 1040 1041 1042 static void 1043 AscMemWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1044 u_int16_t s_addr, const u_int16_t *s_buffer, int words) 1045 { 1046 int i; 1047 1048 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1049 for (i = 0; i < words; i++, s_buffer++) 1050 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1051 } 1052 1053 1054 static void 1055 AscMemWordCopyFromLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1056 u_int16_t s_addr, u_int16_t *s_buffer, int words) 1057 { 1058 int i; 1059 1060 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1061 for (i = 0; i < words; i++, s_buffer++) 1062 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1063 } 1064 1065 1066 static void 1067 AscMemDWordCopyToLram(bus_space_tag_t iot, bus_space_handle_t ioh, 1068 u_int16_t s_addr, u_int32_t *s_buffer, int dwords) 1069 { 1070 int i; 1071 u_int32_t *pw; 1072 1073 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1074 1075 pw = s_buffer; 1076 for (i = 0; i < dwords; i++, pw++) { 1077 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1078 DELAY(1); 1079 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1080 } 1081 } 1082 1083 1084 static u_int32_t 1085 AscMemSumLramWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1086 u_int16_t s_addr, int words) 1087 { 1088 u_int32_t sum = 0L; 1089 u_int16_t i; 1090 1091 1092 for (i = 0; i < words; i++, s_addr += 2) 1093 sum += AscReadLramWord(iot, ioh, s_addr); 1094 1095 return (sum); 1096 } 1097 1098 1099 static int 1100 AscTestExternalLram(bus_space_tag_t iot, bus_space_handle_t ioh) 1101 { 1102 u_int16_t q_addr; 1103 u_int16_t saved_word; 1104 int retval; 1105 1106 1107 retval = 0; 1108 q_addr = ASC_QNO_TO_QADDR(241); 1109 saved_word = AscReadLramWord(iot, ioh, q_addr); 1110 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1111 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1112 DvcSleepMilliSecond(10); 1113 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1114 1115 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1116 retval = 1; 1117 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1118 } 1119 return (retval); 1120 } 1121 1122 1123 /******************************************************************************/ 1124 /* MicroCode routines */ 1125 /******************************************************************************/ 1126 1127 1128 static u_int16_t 1129 AscInitMicroCodeVar(ASC_SOFTC *sc) 1130 { 1131 bus_space_tag_t iot = sc->sc_iot; 1132 bus_space_handle_t ioh = sc->sc_ioh; 1133 u_int32_t phy_addr; 1134 int i; 1135 1136 1137 for (i = 0; i <= ASC_MAX_TID; i++) 1138 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1139 sc->sdtr_period_offset[i]); 1140 1141 AscInitQLinkVar(sc); 1142 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1143 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1144 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1145 1146 phy_addr = (sc->overrun_buf & 0xfffffff8) + 8; 1147 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1148 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1149 ASC_OVERRUN_BSIZE - 8); 1150 1151 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1152 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1153 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1154 1155 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1156 return (0); 1157 } 1158 if (AscStartChip(iot, ioh) != 1) { 1159 return (0); 1160 } 1161 return (1); 1162 } 1163 1164 1165 static u_int32_t 1166 AscLoadMicroCode(bus_space_tag_t iot, bus_space_handle_t ioh, 1167 u_int16_t s_addr, const u_int16_t *mcode_buf, u_int16_t mcode_size) 1168 { 1169 u_int32_t chksum; 1170 u_int16_t mcode_word_size; 1171 u_int16_t mcode_chksum; 1172 1173 mcode_word_size = mcode_size >> 1; 1174 /* clear board memory */ 1175 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1176 /* copy uCode to board memory */ 1177 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1178 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1179 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1180 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1181 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1182 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1183 1184 return (chksum); 1185 } 1186 1187 1188 /******************************************************************************/ 1189 /* EEProm routines */ 1190 /******************************************************************************/ 1191 1192 1193 static int 1194 AscWriteEEPCmdReg(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t cmd_reg) 1195 { 1196 u_int8_t read_back; 1197 int retry; 1198 1199 retry = 0; 1200 1201 while (TRUE) { 1202 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1203 DvcSleepMilliSecond(1); 1204 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1205 if (read_back == cmd_reg) 1206 return (1); 1207 1208 if (retry++ > ASC_EEP_MAX_RETRY) 1209 return (0); 1210 } 1211 } 1212 1213 1214 static int 1215 AscWriteEEPDataReg(bus_space_tag_t iot, bus_space_handle_t ioh, 1216 u_int16_t data_reg) 1217 { 1218 u_int16_t read_back; 1219 int retry; 1220 1221 retry = 0; 1222 while (TRUE) { 1223 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1224 DvcSleepMilliSecond(1); 1225 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1226 if (read_back == data_reg) 1227 return (1); 1228 1229 if (retry++ > ASC_EEP_MAX_RETRY) 1230 return (0); 1231 } 1232 } 1233 1234 1235 static void 1236 AscWaitEEPRead(void) 1237 { 1238 1239 DvcSleepMilliSecond(1); 1240 } 1241 1242 1243 static void 1244 AscWaitEEPWrite(void) 1245 { 1246 1247 DvcSleepMilliSecond(1); 1248 } 1249 1250 1251 static u_int16_t 1252 AscReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t addr) 1253 { 1254 u_int16_t read_wval; 1255 u_int8_t cmd_reg; 1256 1257 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1258 AscWaitEEPRead(); 1259 cmd_reg = addr | ASC_EEP_CMD_READ; 1260 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1261 AscWaitEEPRead(); 1262 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1263 AscWaitEEPRead(); 1264 1265 return (read_wval); 1266 } 1267 1268 1269 static u_int16_t 1270 AscWriteEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, 1271 u_int8_t addr, u_int16_t word_val) 1272 { 1273 u_int16_t read_wval; 1274 1275 read_wval = AscReadEEPWord(iot, ioh, addr); 1276 if (read_wval != word_val) { 1277 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1278 AscWaitEEPRead(); 1279 AscWriteEEPDataReg(iot, ioh, word_val); 1280 AscWaitEEPRead(); 1281 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1282 AscWaitEEPWrite(); 1283 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1284 AscWaitEEPRead(); 1285 return (AscReadEEPWord(iot, ioh, addr)); 1286 } 1287 return (read_wval); 1288 } 1289 1290 1291 static u_int16_t 1292 AscGetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh, 1293 ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type) 1294 { 1295 u_int16_t wval; 1296 u_int16_t sum; 1297 u_int16_t *wbuf; 1298 int cfg_beg; 1299 int cfg_end; 1300 int s_addr; 1301 int isa_pnp_wsize; 1302 1303 1304 wbuf = (u_int16_t *) cfg_buf; 1305 sum = 0; 1306 isa_pnp_wsize = 0; 1307 1308 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1309 wval = AscReadEEPWord(iot, ioh, s_addr); 1310 sum += wval; 1311 *wbuf = wval; 1312 } 1313 1314 if (bus_type & ASC_IS_VL) { 1315 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1316 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1317 } else { 1318 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1319 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1320 } 1321 1322 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1323 wval = AscReadEEPWord(iot, ioh, s_addr); 1324 sum += wval; 1325 *wbuf = wval; 1326 } 1327 1328 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1329 1330 return (sum); 1331 } 1332 1333 1334 static int 1335 AscSetEEPConfig(bus_space_tag_t iot, bus_space_handle_t ioh, 1336 ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type) 1337 { 1338 int retry; 1339 int n_error; 1340 1341 retry = 0; 1342 while (TRUE) { 1343 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1344 break; 1345 1346 if (++retry > ASC_EEP_MAX_RETRY) 1347 break; 1348 } 1349 1350 return (n_error); 1351 } 1352 1353 1354 static int 1355 AscSetEEPConfigOnce(bus_space_tag_t iot, bus_space_handle_t ioh, 1356 ASCEEP_CONFIG *cfg_buf, u_int16_t bus_type) 1357 { 1358 int n_error; 1359 u_int16_t *wbuf; 1360 u_int16_t sum; 1361 int s_addr; 1362 int cfg_beg; 1363 int cfg_end; 1364 1365 wbuf = (u_int16_t *) cfg_buf; 1366 n_error = 0; 1367 sum = 0; 1368 1369 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1370 sum += *wbuf; 1371 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1372 n_error++; 1373 } 1374 1375 if (bus_type & ASC_IS_VL) { 1376 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1377 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1378 } else { 1379 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1380 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1381 } 1382 1383 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1384 sum += *wbuf; 1385 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1386 n_error++; 1387 } 1388 1389 *wbuf = sum; 1390 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1391 n_error++; 1392 1393 wbuf = (u_int16_t *) cfg_buf; 1394 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1395 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1396 n_error++; 1397 } 1398 1399 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1400 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1401 n_error++; 1402 } 1403 1404 return (n_error); 1405 } 1406 1407 1408 #ifdef ASC_DEBUG 1409 static void 1410 AscPrintEEPConfig(ASCEEP_CONFIG *eep_config, u_int16_t chksum) 1411 { 1412 printf("---- ASC EEprom settings ----\n"); 1413 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1414 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1415 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1416 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1417 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1418 printf("start_motor = 0x%x\n", eep_config->start_motor); 1419 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1420 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1421 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1422 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1423 printf("no_scam = %d\n", eep_config->no_scam); 1424 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1425 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1426 printf("cntl = 0x%x\n", eep_config->cntl); 1427 #if BYTE_ORDER == BIG_ENDIAN 1428 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1429 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1430 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1431 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1432 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1433 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1434 #else 1435 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1436 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1437 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1438 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1439 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1440 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1441 #endif 1442 printf("checksum = 0x%x\n", eep_config->chksum); 1443 printf("calculated checksum = 0x%x\n", chksum); 1444 printf("-----------------------------\n"); 1445 } 1446 #endif 1447 1448 1449 /******************************************************************************/ 1450 /* Interrupt routines */ 1451 /******************************************************************************/ 1452 1453 1454 int 1455 AscISR(ASC_SOFTC *sc) 1456 { 1457 bus_space_tag_t iot = sc->sc_iot; 1458 bus_space_handle_t ioh = sc->sc_ioh; 1459 u_int16_t chipstat; 1460 u_int16_t saved_ram_addr; 1461 u_int8_t ctrl_reg; 1462 u_int8_t saved_ctrl_reg; 1463 int int_pending; 1464 int status; 1465 u_int8_t host_flag; 1466 1467 1468 int_pending = FALSE; 1469 1470 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1471 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1472 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1473 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1474 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1475 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1476 int_pending = TRUE; 1477 sc->sdtr_done = 0; 1478 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1479 1480 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1481 1482 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1483 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1484 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1485 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1486 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1487 } 1488 } 1489 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1490 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1491 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1492 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1493 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1494 1495 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1496 AscAckInterrupt(iot, ioh); 1497 int_pending = TRUE; 1498 1499 if ((chipstat & ASC_CSW_HALTED) && 1500 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1501 AscIsrChipHalted(sc); 1502 saved_ctrl_reg &= ~ASC_CC_HALT; 1503 } else { 1504 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1505 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1506 } else { 1507 do { 1508 if ((status = AscIsrQDone(sc)) == 1) 1509 break; 1510 } while (status == 0x11); 1511 } 1512 1513 if (status & 0x80) 1514 int_pending = -1; 1515 } 1516 } 1517 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1518 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1519 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1520 1521 return (1); 1522 /* return(int_pending); */ 1523 } 1524 1525 1526 static int 1527 AscIsrQDone(ASC_SOFTC *sc) 1528 { 1529 u_int8_t next_qp; 1530 u_int8_t n_q_used; 1531 u_int8_t sg_list_qp; 1532 u_int8_t sg_queue_cnt; 1533 u_int8_t q_cnt; 1534 u_int8_t done_q_tail; 1535 u_int8_t tid_no; 1536 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1537 ASC_SCSI_BIT_ID_TYPE target_id; 1538 bus_space_tag_t iot = sc->sc_iot; 1539 bus_space_handle_t ioh = sc->sc_ioh; 1540 u_int16_t q_addr; 1541 u_int16_t sg_q_addr; 1542 u_int8_t cur_target_qng; 1543 ASC_QDONE_INFO scsiq_buf; 1544 ASC_QDONE_INFO *scsiq; 1545 ASC_ISR_CALLBACK asc_isr_callback; 1546 1547 1548 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1549 n_q_used = 1; 1550 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1551 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1552 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1553 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1554 1555 if (next_qp != ASC_QLINK_END) { 1556 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1557 q_addr = ASC_QNO_TO_QADDR(next_qp); 1558 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1559 sc->max_dma_count); 1560 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1561 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1562 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1563 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1564 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1565 sg_q_addr = q_addr; 1566 sg_list_qp = next_qp; 1567 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1568 sg_list_qp = AscReadLramByte(iot, ioh, 1569 sg_q_addr + ASC_SCSIQ_B_FWD); 1570 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1571 if (sg_list_qp == ASC_QLINK_END) { 1572 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1573 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1574 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1575 panic("AscIsrQDone: Corrupted SG list encountered"); 1576 } 1577 AscWriteLramByte(iot, ioh, 1578 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1579 } 1580 n_q_used = sg_queue_cnt + 1; 1581 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1582 } 1583 if (sc->queue_full_or_busy & target_id) { 1584 cur_target_qng = AscReadLramByte(iot, ioh, 1585 ASC_QADR_BEG + scsiq->d2.target_ix); 1586 1587 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1588 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1589 scsi_busy &= ~target_id; 1590 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1591 sc->queue_full_or_busy &= ~target_id; 1592 } 1593 } 1594 if (sc->cur_total_qng >= n_q_used) { 1595 sc->cur_total_qng -= n_q_used; 1596 if (sc->cur_dvc_qng[tid_no] != 0) { 1597 sc->cur_dvc_qng[tid_no]--; 1598 } 1599 } else { 1600 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1601 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1602 panic("AscIsrQDone: Attempting to free more queues than are active"); 1603 } 1604 1605 if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) || 1606 ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1607 return (0x11); 1608 } else if (scsiq->q_status == ASC_QS_DONE) { 1609 scsiq->remain_bytes += scsiq->extra_bytes; 1610 1611 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1612 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1613 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1614 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1615 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1616 } 1617 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1618 AscStopChip(iot, ioh); 1619 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1620 DvcDelayNanoSecond(60000); 1621 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1622 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1623 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1624 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1625 } 1626 } 1627 (*asc_isr_callback) (sc, scsiq); 1628 1629 return (1); 1630 } else { 1631 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1632 panic("AscIsrQDone: completed scsiq with unknown status"); 1633 1634 return (0x80); 1635 } 1636 } 1637 return (0); 1638 } 1639 1640 1641 /* 1642 * handle all the conditions that may halt the board 1643 * waiting us to intervene 1644 */ 1645 static void 1646 AscIsrChipHalted(ASC_SOFTC *sc) 1647 { 1648 bus_space_tag_t iot = sc->sc_iot; 1649 bus_space_handle_t ioh = sc->sc_ioh; 1650 EXT_MSG out_msg; 1651 u_int16_t int_halt_code; 1652 u_int16_t halt_q_addr; 1653 u_int8_t halt_qp; 1654 u_int8_t target_ix; 1655 u_int8_t tag_code; 1656 u_int8_t q_status; 1657 u_int8_t q_cntl; 1658 u_int8_t tid_no; 1659 u_int8_t cur_dvc_qng; 1660 u_int8_t asyn_sdtr; 1661 u_int8_t scsi_status; 1662 u_int8_t sdtr_data; 1663 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1664 ASC_SCSI_BIT_ID_TYPE target_id; 1665 1666 1667 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1668 1669 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1670 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1671 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1672 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1673 tid_no = ASC_TIX_TO_TID(target_ix); 1674 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1675 1676 if (sc->pci_fix_asyn_xfer & target_id) { 1677 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1678 } else { 1679 asyn_sdtr = 0; 1680 } 1681 1682 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1683 if (sc->pci_fix_asyn_xfer & target_id) { 1684 AscSetChipSDTR(iot, ioh, 0, tid_no); 1685 sc->sdtr_data[tid_no] = 0; 1686 } 1687 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1688 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1689 if (sc->pci_fix_asyn_xfer & target_id) { 1690 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1691 sc->sdtr_data[tid_no] = asyn_sdtr; 1692 } 1693 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1694 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1695 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1696 tid_no, asyn_sdtr); 1697 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1698 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1699 q_cntl |= ASC_QC_REQ_SENSE; 1700 1701 if (sc->init_sdtr & target_id) { 1702 sc->sdtr_done &= ~target_id; 1703 1704 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1705 q_cntl |= ASC_QC_MSG_OUT; 1706 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1707 (sc->max_sdtr_index - 1)], 1708 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1709 } 1710 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1711 1712 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1713 tag_code &= 0xDC; 1714 1715 if ((sc->pci_fix_asyn_xfer & target_id) && 1716 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1717 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1718 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1719 } 1720 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1721 1722 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1723 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1724 1725 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1726 1727 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1728 scsi_busy &= ~target_id; 1729 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1730 1731 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1732 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1733 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1734 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1735 1736 if ((out_msg.msg_type == MS_EXTEND) && 1737 (out_msg.msg_len == MS_SDTR_LEN) && 1738 (out_msg.msg_req == MS_SDTR_CODE)) { 1739 sc->init_sdtr &= ~target_id; 1740 sc->sdtr_done &= ~target_id; 1741 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1742 sc->sdtr_data[tid_no] = asyn_sdtr; 1743 } 1744 q_cntl &= ~ASC_QC_MSG_OUT; 1745 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1746 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1747 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1748 scsi_status = AscReadLramByte(iot, ioh, 1749 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1750 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1751 1752 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1753 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1754 scsi_busy |= target_id; 1755 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1756 sc->queue_full_or_busy |= target_id; 1757 1758 if (scsi_status == SS_QUEUE_FULL) { 1759 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1760 cur_dvc_qng -= 1; 1761 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1762 1763 AscWriteLramByte(iot, ioh, 1764 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1765 1766 #if ASC_QUEUE_FLOW_CONTROL 1767 if ((sc->device[tid_no] != NULL) && 1768 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1769 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1770 } 1771 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1772 } 1773 } 1774 } 1775 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1776 } 1777 return; 1778 } 1779 1780 1781 static int 1782 AscWaitTixISRDone(ASC_SOFTC *sc, u_int8_t target_ix) 1783 { 1784 u_int8_t cur_req; 1785 u_int8_t tid_no; 1786 int i = 0; 1787 1788 tid_no = ASC_TIX_TO_TID(target_ix); 1789 while (i++ < 10) { 1790 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1791 break; 1792 1793 DvcSleepMilliSecond(1000L); 1794 if (sc->cur_dvc_qng[tid_no] == cur_req) 1795 break; 1796 } 1797 return (1); 1798 } 1799 1800 static int 1801 AscWaitISRDone(ASC_SOFTC *sc) 1802 { 1803 int tid; 1804 1805 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1806 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1807 1808 return (1); 1809 } 1810 1811 1812 static u_int8_t 1813 _AscCopyLramScsiDoneQ(bus_space_tag_t iot, bus_space_handle_t ioh, 1814 u_int16_t q_addr, ASC_QDONE_INFO *scsiq, u_int32_t max_dma_count) 1815 { 1816 u_int16_t _val; 1817 u_int8_t sg_queue_cnt; 1818 1819 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 1820 1821 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1822 scsiq->q_status = LO_BYTE(_val); 1823 scsiq->q_no = HI_BYTE(_val); 1824 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1825 scsiq->cntl = LO_BYTE(_val); 1826 sg_queue_cnt = HI_BYTE(_val); 1827 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 1828 scsiq->sense_len = LO_BYTE(_val); 1829 scsiq->extra_bytes = HI_BYTE(_val); 1830 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 1831 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 1832 scsiq->remain_bytes &= max_dma_count; 1833 1834 return (sg_queue_cnt); 1835 } 1836 1837 1838 static void 1839 AscGetQDoneInfo(bus_space_tag_t iot, bus_space_handle_t ioh, 1840 u_int16_t addr, ASC_QDONE_INFO *scsiq) 1841 { 1842 u_int16_t val; 1843 1844 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1845 1846 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1847 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1848 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1849 scsiq->d2.target_ix = LO_BYTE(val); 1850 scsiq->d2.flag = HI_BYTE(val); 1851 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1852 scsiq->d2.cdb_len = LO_BYTE(val); 1853 scsiq->d2.tag_code = HI_BYTE(val); 1854 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1855 1856 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1857 scsiq->d3.done_stat = LO_BYTE(val); 1858 scsiq->d3.host_stat = HI_BYTE(val); 1859 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1860 scsiq->d3.scsi_stat = LO_BYTE(val); 1861 scsiq->d3.scsi_msg = HI_BYTE(val); 1862 } 1863 1864 1865 static void 1866 AscToggleIRQAct(bus_space_tag_t iot, bus_space_handle_t ioh) 1867 { 1868 1869 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 1870 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1871 } 1872 1873 1874 static void 1875 AscDisableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh) 1876 { 1877 u_int16_t cfg; 1878 1879 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1880 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 1881 } 1882 1883 1884 static void 1885 AscEnableInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh) 1886 { 1887 u_int16_t cfg; 1888 1889 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1890 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 1891 } 1892 1893 1894 u_int8_t 1895 AscGetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t bus_type) 1896 { 1897 u_int16_t cfg_lsw; 1898 u_int8_t chip_irq; 1899 1900 1901 #if 0 1902 if (bus_type & ASC_IS_EISA) { 1903 cfg_lsw = AscGetEisaChipCfg(iot, ioh); 1904 chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 1905 if((chip_irq == 13) || (chip_irq > 15)) 1906 return (0); 1907 return(chip_irq); 1908 } 1909 #endif 1910 if ((bus_type & ASC_IS_VL) != 0) { 1911 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1912 chip_irq = (cfg_lsw >> 2) & 0x07; 1913 if ((chip_irq == 0) || 1914 (chip_irq == 4) || 1915 (chip_irq == 7)) { 1916 return (0); 1917 } 1918 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 1919 } 1920 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1921 chip_irq = (cfg_lsw >> 2) & 0x03; 1922 if (chip_irq == 3) 1923 chip_irq += 2; 1924 return (chip_irq + ASC_MIN_IRQ_NO); 1925 } 1926 1927 1928 static u_int8_t 1929 AscSetChipIRQ(bus_space_tag_t iot, bus_space_handle_t ioh, 1930 u_int8_t irq_no, u_int16_t bus_type) 1931 { 1932 u_int16_t cfg_lsw; 1933 1934 1935 if (bus_type & ASC_IS_VL) { 1936 if (irq_no) { 1937 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 1938 irq_no = 0; 1939 else 1940 irq_no -= ASC_MIN_IRQ_NO - 1; 1941 } 1942 1943 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 1944 cfg_lsw |= 0x0010; 1945 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 1946 AscToggleIRQAct(iot, ioh); 1947 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 1948 cfg_lsw |= (irq_no & 0x07) << 2; 1949 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 1950 AscToggleIRQAct(iot, ioh); 1951 1952 return (AscGetChipIRQ(iot, ioh, bus_type)); 1953 } 1954 if (bus_type & ASC_IS_ISA) { 1955 if (irq_no == 15) 1956 irq_no -= 2; 1957 irq_no -= ASC_MIN_IRQ_NO; 1958 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 1959 cfg_lsw |= (irq_no & 0x03) << 2; 1960 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 1961 1962 return (AscGetChipIRQ(iot, ioh, bus_type)); 1963 } 1964 return (0); 1965 } 1966 1967 1968 static void 1969 AscAckInterrupt(bus_space_tag_t iot, bus_space_handle_t ioh) 1970 { 1971 u_int8_t host_flag; 1972 u_int8_t risc_flag; 1973 u_int16_t loop; 1974 1975 1976 loop = 0; 1977 do { 1978 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 1979 if (loop++ > 0x7FFF) 1980 break; 1981 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 1982 1983 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1984 (~ASC_HOST_FLAG_ACK_INT); 1985 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1986 host_flag | ASC_HOST_FLAG_ACK_INT); 1987 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 1988 1989 loop = 0; 1990 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 1991 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 1992 if (loop++ > 3) 1993 break; 1994 } 1995 1996 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1997 } 1998 1999 2000 static u_int32_t 2001 AscGetMaxDmaCount(u_int16_t bus_type) 2002 { 2003 if (bus_type & ASC_IS_ISA) 2004 return (ASC_MAX_ISA_DMA_COUNT); 2005 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2006 return (ASC_MAX_VL_DMA_COUNT); 2007 return (ASC_MAX_PCI_DMA_COUNT); 2008 } 2009 2010 2011 u_int16_t 2012 AscGetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh) 2013 { 2014 u_int16_t channel; 2015 2016 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2017 if (channel == 0x03) 2018 return (0); 2019 else if (channel == 0x00) 2020 return (7); 2021 return (channel + 4); 2022 } 2023 2024 2025 static u_int16_t 2026 AscSetIsaDmaChannel(bus_space_tag_t iot, bus_space_handle_t ioh, 2027 u_int16_t dma_channel) 2028 { 2029 u_int16_t cfg_lsw; 2030 u_int8_t value; 2031 2032 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2033 if (dma_channel == 7) 2034 value = 0x00; 2035 else 2036 value = dma_channel - 4; 2037 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2038 cfg_lsw |= value; 2039 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2040 return (AscGetIsaDmaChannel(iot, ioh)); 2041 } 2042 return (0); 2043 } 2044 2045 2046 static u_int8_t 2047 AscGetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh) 2048 { 2049 u_int8_t speed_value; 2050 2051 AscSetBank(iot, ioh, 1); 2052 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2053 speed_value &= 0x07; 2054 AscSetBank(iot, ioh, 0); 2055 return (speed_value); 2056 } 2057 2058 2059 static u_int8_t 2060 AscSetIsaDmaSpeed(bus_space_tag_t iot, bus_space_handle_t ioh, 2061 u_int8_t speed_value) 2062 { 2063 speed_value &= 0x07; 2064 AscSetBank(iot, ioh, 1); 2065 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2066 AscSetBank(iot, ioh, 0); 2067 return (AscGetIsaDmaSpeed(iot, ioh)); 2068 } 2069 2070 2071 /******************************************************************************/ 2072 /* Messages routines */ 2073 /******************************************************************************/ 2074 2075 2076 static void 2077 AscHandleExtMsgIn(ASC_SOFTC *sc, u_int16_t halt_q_addr, u_int8_t q_cntl, 2078 ASC_SCSI_BIT_ID_TYPE target_id, int tid_no, u_int8_t asyn_sdtr) 2079 { 2080 bus_space_tag_t iot = sc->sc_iot; 2081 bus_space_handle_t ioh = sc->sc_ioh; 2082 EXT_MSG ext_msg; 2083 u_int8_t sdtr_data; 2084 int sdtr_accept; 2085 2086 2087 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2088 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2089 2090 if (ext_msg.msg_type == MS_EXTEND && 2091 ext_msg.msg_req == MS_SDTR_CODE && 2092 ext_msg.msg_len == MS_SDTR_LEN) { 2093 sdtr_accept = TRUE; 2094 2095 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2096 sdtr_accept = FALSE; 2097 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2098 } 2099 if ((ext_msg.xfer_period < 2100 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2101 (ext_msg.xfer_period > 2102 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2103 sdtr_accept = FALSE; 2104 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2105 } 2106 if (sdtr_accept) { 2107 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2108 ext_msg.req_ack_offset); 2109 if (sdtr_data == 0xFF) { 2110 q_cntl |= ASC_QC_MSG_OUT; 2111 sc->init_sdtr &= ~target_id; 2112 sc->sdtr_done &= ~target_id; 2113 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2114 sc->sdtr_data[tid_no] = asyn_sdtr; 2115 } 2116 } 2117 if (ext_msg.req_ack_offset == 0) { 2118 q_cntl &= ~ASC_QC_MSG_OUT; 2119 sc->init_sdtr &= ~target_id; 2120 sc->sdtr_done &= ~target_id; 2121 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2122 } else { 2123 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2124 q_cntl &= ~ASC_QC_MSG_OUT; 2125 sc->sdtr_done |= target_id; 2126 sc->init_sdtr |= target_id; 2127 sc->pci_fix_asyn_xfer &= ~target_id; 2128 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2129 ext_msg.req_ack_offset); 2130 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2131 sc->sdtr_data[tid_no] = sdtr_data; 2132 } else { 2133 q_cntl |= ASC_QC_MSG_OUT; 2134 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2135 ext_msg.req_ack_offset); 2136 sc->pci_fix_asyn_xfer &= ~target_id; 2137 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2138 ext_msg.req_ack_offset); 2139 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2140 sc->sdtr_data[tid_no] = sdtr_data; 2141 sc->sdtr_done |= target_id; 2142 sc->init_sdtr |= target_id; 2143 } 2144 } 2145 } else if (ext_msg.msg_type == MS_EXTEND && 2146 ext_msg.msg_req == MS_WDTR_CODE && 2147 ext_msg.msg_len == MS_WDTR_LEN) { 2148 ext_msg.wdtr_width = 0; 2149 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2150 (const u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2151 q_cntl |= ASC_QC_MSG_OUT; 2152 } else { 2153 ext_msg.msg_type = M1_MSG_REJECT; 2154 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2155 (const u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2156 q_cntl |= ASC_QC_MSG_OUT; 2157 } 2158 2159 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2160 } 2161 2162 2163 static u_int8_t 2164 AscMsgOutSDTR(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t sdtr_offset) 2165 { 2166 bus_space_tag_t iot = sc->sc_iot; 2167 bus_space_handle_t ioh = sc->sc_ioh; 2168 EXT_MSG sdtr_buf; 2169 u_int8_t sdtr_period_index; 2170 2171 2172 sdtr_buf.msg_type = MS_EXTEND; 2173 sdtr_buf.msg_len = MS_SDTR_LEN; 2174 sdtr_buf.msg_req = MS_SDTR_CODE; 2175 sdtr_buf.xfer_period = sdtr_period; 2176 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2177 sdtr_buf.req_ack_offset = sdtr_offset; 2178 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2179 sc->max_sdtr_index) { 2180 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2181 (const u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2182 return ((sdtr_period_index << 4) | sdtr_offset); 2183 } else { 2184 sdtr_buf.req_ack_offset = 0; 2185 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2186 (const u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2187 return (0); 2188 } 2189 } 2190 2191 2192 /******************************************************************************/ 2193 /* SDTR routines */ 2194 /******************************************************************************/ 2195 2196 2197 static void 2198 AscSetChipSDTR(bus_space_tag_t iot, bus_space_handle_t ioh, 2199 u_int8_t sdtr_data, u_int8_t tid_no) 2200 { 2201 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2202 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2203 } 2204 2205 2206 static u_int8_t 2207 AscCalSDTRData(ASC_SOFTC *sc, u_int8_t sdtr_period, u_int8_t syn_offset) 2208 { 2209 u_int8_t byte; 2210 u_int8_t sdtr_period_ix; 2211 2212 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2213 if (sdtr_period_ix > sc->max_sdtr_index) 2214 return (0xFF); 2215 2216 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2217 return (byte); 2218 } 2219 2220 2221 static u_int8_t 2222 AscGetSynPeriodIndex(ASC_SOFTC *sc, u_int8_t syn_time) 2223 { 2224 u_int8_t *period_table; 2225 int max_index; 2226 int min_index; 2227 int i; 2228 2229 period_table = sc->sdtr_period_tbl; 2230 max_index = sc->max_sdtr_index; 2231 min_index = sc->host_init_sdtr_index; 2232 if ((syn_time <= period_table[max_index])) { 2233 for (i = min_index; i < (max_index - 1); i++) { 2234 if (syn_time <= period_table[i]) 2235 return (i); 2236 } 2237 2238 return (max_index); 2239 } else 2240 return (max_index + 1); 2241 } 2242 2243 2244 /******************************************************************************/ 2245 /* Queue routines */ 2246 /******************************************************************************/ 2247 2248 /* 2249 * Send a command to the board 2250 */ 2251 int 2252 AscExeScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq) 2253 { 2254 bus_space_tag_t iot = sc->sc_iot; 2255 bus_space_handle_t ioh = sc->sc_ioh; 2256 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2257 int retval; 2258 int n_q_required; 2259 int disable_syn_offset_one_fix; 2260 int i; 2261 u_int32_t addr; 2262 u_int16_t sg_entry_cnt = 0; 2263 u_int16_t sg_entry_cnt_minus_one = 0; 2264 u_int8_t target_ix; 2265 u_int8_t tid_no; 2266 u_int8_t sdtr_data; 2267 u_int8_t extra_bytes; 2268 u_int8_t scsi_cmd; 2269 u_int32_t data_cnt; 2270 2271 2272 scsiq->q1.q_no = 0; 2273 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2274 scsiq->q1.extra_bytes = 0; 2275 2276 retval = ASC_BUSY; 2277 target_ix = scsiq->q2.target_ix; 2278 tid_no = ASC_TIX_TO_TID(target_ix); 2279 n_q_required = 1; 2280 2281 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2282 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2283 sc->sdtr_done &= ~scsiq->q1.target_id; 2284 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2285 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2286 (sc->max_sdtr_index - 1)], 2287 sdtr_data & ASC_SYN_MAX_OFFSET); 2288 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2289 } 2290 /* 2291 * if there is just one segment into S/G list then 2292 * map it as it was a single request, filling 2293 * data_addr and data_cnt of ASC_SCSIQ structure. 2294 */ 2295 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2296 sg_entry_cnt = sg_head->entry_cnt; 2297 2298 if (sg_entry_cnt < 1) 2299 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2300 sg_entry_cnt); 2301 2302 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2303 panic("AscExeScsiQueue: Queue with too many segs."); 2304 2305 if (sg_entry_cnt == 1) { 2306 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2307 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2308 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2309 } 2310 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2311 } 2312 scsi_cmd = scsiq->cdbptr[0]; 2313 disable_syn_offset_one_fix = FALSE; 2314 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2315 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2316 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2317 data_cnt = 0; 2318 for (i = 0; i < sg_entry_cnt; i++) 2319 data_cnt += sg_head->sg_list[i].bytes; 2320 } else { 2321 data_cnt = scsiq->q1.data_cnt; 2322 } 2323 2324 if (data_cnt != 0ul) { 2325 if (data_cnt < 512ul) { 2326 disable_syn_offset_one_fix = TRUE; 2327 } else { 2328 if (scsi_cmd == SCSICMD_Inquiry || 2329 scsi_cmd == SCSICMD_RequestSense || 2330 scsi_cmd == SCSICMD_ReadCapacity || 2331 scsi_cmd == SCSICMD_ReadTOC || 2332 scsi_cmd == SCSICMD_ModeSelect6 || 2333 scsi_cmd == SCSICMD_ModeSense6 || 2334 scsi_cmd == SCSICMD_ModeSelect10 || 2335 scsi_cmd == SCSICMD_ModeSense10) { 2336 disable_syn_offset_one_fix = TRUE; 2337 } 2338 } 2339 } 2340 } 2341 if (disable_syn_offset_one_fix) { 2342 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2343 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2344 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2345 } else { 2346 scsiq->q2.tag_code &= 0x23; 2347 } 2348 2349 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2350 if (sc->bug_fix_cntl) { 2351 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2352 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2353 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2354 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2355 extra_bytes = addr & 0x0003; 2356 if ((extra_bytes != 0) && 2357 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2358 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2359 scsiq->q1.extra_bytes = extra_bytes; 2360 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2361 extra_bytes; 2362 } 2363 } 2364 } 2365 } 2366 sg_head->entry_to_copy = sg_head->entry_cnt; 2367 n_q_required = AscSgListToQueue(sg_entry_cnt); 2368 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2369 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2370 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2371 } 2372 } else { 2373 if (sc->bug_fix_cntl) { 2374 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2375 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2376 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2377 extra_bytes = addr & 0x0003; 2378 if ((extra_bytes != 0) && 2379 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2380 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2381 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2382 scsiq->q1.data_cnt -= extra_bytes; 2383 scsiq->q1.extra_bytes = extra_bytes; 2384 } 2385 } 2386 } 2387 } 2388 } 2389 n_q_required = 1; 2390 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2391 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2392 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2393 } 2394 } 2395 2396 return (retval); 2397 } 2398 2399 2400 static int 2401 AscSendScsiQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t n_q_required) 2402 { 2403 bus_space_tag_t iot = sc->sc_iot; 2404 bus_space_handle_t ioh = sc->sc_ioh; 2405 u_int8_t free_q_head; 2406 u_int8_t next_qp; 2407 u_int8_t tid_no; 2408 u_int8_t target_ix; 2409 int retval; 2410 2411 2412 target_ix = scsiq->q2.target_ix; 2413 tid_no = ASC_TIX_TO_TID(target_ix); 2414 retval = ASC_BUSY; 2415 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2416 2417 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2418 != ASC_QLINK_END) { 2419 if (n_q_required > 1) { 2420 sc->last_q_shortage = 0; 2421 scsiq->sg_head->queue_cnt = n_q_required - 1; 2422 } 2423 scsiq->q1.q_no = free_q_head; 2424 2425 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2426 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2427 sc->cur_total_qng += n_q_required; 2428 sc->cur_dvc_qng[tid_no]++; 2429 } 2430 } 2431 return (retval); 2432 } 2433 2434 2435 static int 2436 AscPutReadySgListQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no) 2437 { 2438 bus_space_tag_t iot = sc->sc_iot; 2439 bus_space_handle_t ioh = sc->sc_ioh; 2440 int retval; 2441 int i; 2442 ASC_SG_HEAD *sg_head; 2443 ASC_SG_LIST_Q scsi_sg_q; 2444 u_int32_t saved_data_addr; 2445 u_int32_t saved_data_cnt; 2446 u_int16_t sg_list_dwords; 2447 u_int16_t sg_index; 2448 u_int16_t sg_entry_cnt; 2449 u_int16_t q_addr; 2450 u_int8_t next_qp; 2451 2452 2453 saved_data_addr = scsiq->q1.data_addr; 2454 saved_data_cnt = scsiq->q1.data_cnt; 2455 2456 if ((sg_head = scsiq->sg_head) != 0) { 2457 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2458 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2459 sg_entry_cnt = sg_head->entry_cnt - 1; 2460 if (sg_entry_cnt != 0) { 2461 q_addr = ASC_QNO_TO_QADDR(q_no); 2462 sg_index = 1; 2463 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2464 scsi_sg_q.sg_head_qp = q_no; 2465 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2466 2467 for (i = 0; i < sg_head->queue_cnt; i++) { 2468 scsi_sg_q.seq_no = i + 1; 2469 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2470 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2471 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2472 if (i == 0) { 2473 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2474 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2475 } else { 2476 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2477 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2478 } 2479 } else { 2480 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2481 sg_list_dwords = sg_entry_cnt << 1; 2482 if (i == 0) { 2483 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2484 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2485 } else { 2486 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2487 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2488 } 2489 2490 sg_entry_cnt = 0; 2491 } 2492 2493 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2494 scsi_sg_q.q_no = next_qp; 2495 q_addr = ASC_QNO_TO_QADDR(next_qp); 2496 2497 /* 2498 * Tell the board how many entries are in the S/G list 2499 */ 2500 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2501 (const u_int16_t *) & scsi_sg_q, 2502 sizeof(ASC_SG_LIST_Q) >> 1); 2503 /* 2504 * Tell the board the addresses of the S/G list segments 2505 */ 2506 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2507 (u_int32_t *) & sg_head->sg_list[sg_index], 2508 sg_list_dwords); 2509 sg_index += ASC_SG_LIST_PER_Q; 2510 } 2511 } 2512 } 2513 retval = AscPutReadyQueue(sc, scsiq, q_no); 2514 scsiq->q1.data_addr = saved_data_addr; 2515 scsiq->q1.data_cnt = saved_data_cnt; 2516 return (retval); 2517 } 2518 2519 2520 static int 2521 AscPutReadyQueue(ASC_SOFTC *sc, ASC_SCSI_Q *scsiq, u_int8_t q_no) 2522 { 2523 bus_space_tag_t iot = sc->sc_iot; 2524 bus_space_handle_t ioh = sc->sc_ioh; 2525 u_int16_t q_addr; 2526 u_int8_t tid_no; 2527 u_int8_t sdtr_data; 2528 u_int8_t syn_period_ix; 2529 u_int8_t syn_offset; 2530 2531 2532 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2533 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2534 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2535 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2536 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2537 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2538 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2539 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2540 } 2541 q_addr = ASC_QNO_TO_QADDR(q_no); 2542 2543 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2544 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2545 } 2546 scsiq->q1.status = ASC_QS_FREE; 2547 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2548 (const u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2549 2550 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2551 2552 /* 2553 * Let's start the command 2554 */ 2555 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2556 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2557 2558 return (ASC_NOERROR); 2559 } 2560 2561 2562 static void 2563 AscPutSCSIQ(bus_space_tag_t iot, bus_space_handle_t ioh, 2564 u_int16_t addr, ASC_SCSI_Q *scsiq) 2565 { 2566 u_int16_t val; 2567 2568 2569 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2570 2571 /* ASC_SCSIQ_1 */ 2572 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2573 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2574 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2575 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2576 val = LO_WORD(scsiq->q1.data_addr); 2577 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2578 val = HI_WORD(scsiq->q1.data_addr); 2579 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2580 val = LO_WORD(scsiq->q1.data_cnt); 2581 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2582 val = HI_WORD(scsiq->q1.data_cnt); 2583 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2584 val = LO_WORD(scsiq->q1.sense_addr); 2585 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2586 val = HI_WORD(scsiq->q1.sense_addr); 2587 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2588 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2589 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2590 2591 /* ASC_SCSIQ_2 */ 2592 val = LO_WORD(scsiq->q2.ccb_ptr); 2593 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2594 val = HI_WORD(scsiq->q2.ccb_ptr); 2595 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2596 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2597 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2598 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2599 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2600 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2601 } 2602 2603 2604 static int 2605 AscSgListToQueue(int sg_list) 2606 { 2607 int n_sg_list_qs; 2608 2609 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2610 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2611 n_sg_list_qs++; 2612 2613 return (n_sg_list_qs + 1); 2614 } 2615 2616 2617 static u_int 2618 AscGetNumOfFreeQueue(ASC_SOFTC *sc, u_int8_t target_ix, u_int8_t n_qs) 2619 { 2620 u_int cur_used_qs; 2621 u_int cur_free_qs; 2622 2623 2624 if (n_qs == 1) { 2625 cur_used_qs = sc->cur_total_qng + 2626 sc->last_q_shortage + 2627 ASC_MIN_FREE_Q; 2628 } else { 2629 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2630 } 2631 2632 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2633 cur_free_qs = sc->max_total_qng - cur_used_qs; 2634 return (cur_free_qs); 2635 } 2636 if (n_qs > 1) 2637 if ((n_qs > sc->last_q_shortage) && 2638 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2639 sc->last_q_shortage = n_qs; 2640 } 2641 return (0); 2642 } 2643 2644 2645 static u_int8_t 2646 AscAllocFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh, 2647 u_int8_t free_q_head) 2648 { 2649 u_int16_t q_addr; 2650 u_int8_t next_qp; 2651 u_int8_t q_status; 2652 2653 2654 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2655 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2656 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2657 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2658 return (next_qp); 2659 2660 return (ASC_QLINK_END); 2661 } 2662 2663 2664 static u_int8_t 2665 AscAllocMultipleFreeQueue(bus_space_tag_t iot, bus_space_handle_t ioh, 2666 u_int8_t free_q_head, u_int8_t n_free_q) 2667 { 2668 u_int8_t i; 2669 2670 for (i = 0; i < n_free_q; i++) { 2671 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2672 if (free_q_head == ASC_QLINK_END) 2673 break; 2674 } 2675 2676 return (free_q_head); 2677 } 2678 2679 2680 static int 2681 AscStopQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh) 2682 { 2683 int count = 0; 2684 2685 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2686 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2687 do { 2688 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2689 ASC_STOP_ACK_RISC_STOP) 2690 return (1); 2691 2692 DvcSleepMilliSecond(100); 2693 } while (count++ < 20); 2694 } 2695 return (0); 2696 } 2697 2698 2699 static void 2700 AscStartQueueExe(bus_space_tag_t iot, bus_space_handle_t ioh) 2701 { 2702 2703 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2704 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2705 } 2706 2707 2708 static void 2709 AscCleanUpBusyQueue(bus_space_tag_t iot, bus_space_handle_t ioh) 2710 { 2711 int count = 0; 2712 u_int8_t stop_code; 2713 2714 2715 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2716 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2717 do { 2718 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2719 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2720 break; 2721 2722 DvcSleepMilliSecond(100); 2723 } while (count++ < 20); 2724 } 2725 } 2726 2727 2728 static int 2729 _AscWaitQDone(bus_space_tag_t iot, bus_space_handle_t ioh, ASC_SCSI_Q *scsiq) 2730 { 2731 u_int16_t q_addr; 2732 u_int8_t q_status; 2733 int count = 0; 2734 2735 while (scsiq->q1.q_no == 0); 2736 2737 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2738 do { 2739 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2740 DvcSleepMilliSecond(100L); 2741 if (count++ > 30) 2742 return (0); 2743 2744 } while ((q_status & ASC_QS_READY) != 0); 2745 2746 return (1); 2747 } 2748 2749 2750 static int 2751 AscCleanUpDiscQueue(bus_space_tag_t iot, bus_space_handle_t ioh) 2752 { 2753 int count; 2754 u_int8_t stop_code; 2755 2756 count = 0; 2757 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2758 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 2759 do { 2760 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2761 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 2762 break; 2763 2764 DvcSleepMilliSecond(100); 2765 } while (count++ < 20); 2766 } 2767 return (1); 2768 } 2769 2770 2771 /******************************************************************************/ 2772 /* Abort and Reset CCB routines */ 2773 /******************************************************************************/ 2774 2775 2776 int 2777 AscAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb) 2778 { 2779 bus_space_tag_t iot = sc->sc_iot; 2780 bus_space_handle_t ioh = sc->sc_ioh; 2781 int retval; 2782 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2783 2784 2785 retval = -1; 2786 saved_unit_not_ready = sc->unit_not_ready; 2787 sc->unit_not_ready = 0xFF; 2788 AscWaitISRDone(sc); 2789 if (AscStopQueueExe(iot, ioh) == 1) { 2790 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 2791 retval = 1; 2792 AscCleanUpBusyQueue(iot, ioh); 2793 AscStartQueueExe(iot, ioh); 2794 } else { 2795 retval = 0; 2796 AscStartQueueExe(iot, ioh); 2797 } 2798 } 2799 sc->unit_not_ready = saved_unit_not_ready; 2800 2801 return (retval); 2802 } 2803 2804 2805 static int 2806 AscRiscHaltedAbortCCB(ASC_SOFTC *sc, ADV_CCB *ccb) 2807 { 2808 bus_space_tag_t iot = sc->sc_iot; 2809 bus_space_handle_t ioh = sc->sc_ioh; 2810 u_int16_t q_addr; 2811 u_int8_t q_no; 2812 ASC_QDONE_INFO scsiq_buf; 2813 ASC_QDONE_INFO *scsiq; 2814 ASC_ISR_CALLBACK asc_isr_callback; 2815 int last_int_level; 2816 2817 2818 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2819 last_int_level = DvcEnterCritical(); 2820 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2821 2822 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2823 q_addr = ASC_QNO_TO_QADDR(q_no); 2824 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 2825 q_addr + ASC_SCSIQ_D_CCBPTR); 2826 if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) { 2827 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2828 if (((scsiq->q_status & ASC_QS_READY) != 0) 2829 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 2830 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2831 scsiq->q_status |= ASC_QS_ABORTED; 2832 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2833 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2834 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2835 scsiq->q_status); 2836 (*asc_isr_callback) (sc, scsiq); 2837 return (1); 2838 } 2839 } 2840 } 2841 2842 DvcLeaveCritical(last_int_level); 2843 return (0); 2844 } 2845 2846 2847 static int 2848 AscRiscHaltedAbortTIX(ASC_SOFTC *sc, u_int8_t target_ix) 2849 { 2850 bus_space_tag_t iot = sc->sc_iot; 2851 bus_space_handle_t ioh = sc->sc_ioh; 2852 u_int16_t q_addr; 2853 u_int8_t q_no; 2854 ASC_QDONE_INFO scsiq_buf; 2855 ASC_QDONE_INFO *scsiq; 2856 ASC_ISR_CALLBACK asc_isr_callback; 2857 int last_int_level; 2858 2859 2860 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2861 last_int_level = DvcEnterCritical(); 2862 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2863 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2864 q_addr = ASC_QNO_TO_QADDR(q_no); 2865 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2866 if (((scsiq->q_status & ASC_QS_READY) != 0) && 2867 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 2868 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2869 if (scsiq->d2.target_ix == target_ix) { 2870 scsiq->q_status |= ASC_QS_ABORTED; 2871 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2872 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2873 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2874 scsiq->q_status); 2875 (*asc_isr_callback) (sc, scsiq); 2876 } 2877 } 2878 } 2879 DvcLeaveCritical(last_int_level); 2880 return (1); 2881 } 2882 2883 2884 /* 2885 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 2886 * so we cannot use this function with the actual NetBSD SCSI layer 2887 * because at boot time interrupts are disabled. 2888 */ 2889 int 2890 AscResetDevice(ASC_SOFTC *sc, u_char target_ix) 2891 { 2892 bus_space_tag_t iot = sc->sc_iot; 2893 bus_space_handle_t ioh = sc->sc_ioh; 2894 int retval; 2895 u_int8_t tid_no; 2896 ASC_SCSI_BIT_ID_TYPE target_id; 2897 int i; 2898 ASC_SCSI_REQ_Q scsiq_buf; 2899 ASC_SCSI_REQ_Q *scsiq; 2900 u_int8_t *buf; 2901 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2902 2903 2904 tid_no = ASC_TIX_TO_TID(target_ix); 2905 target_id = ASC_TID_TO_TARGET_ID(tid_no); 2906 saved_unit_not_ready = sc->unit_not_ready; 2907 sc->unit_not_ready = target_id; 2908 retval = ASC_ERROR; 2909 2910 AscWaitTixISRDone(sc, target_ix); 2911 2912 if (AscStopQueueExe(iot, ioh) == 1) { 2913 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 2914 AscCleanUpBusyQueue(iot, ioh); 2915 AscStartQueueExe(iot, ioh); 2916 AscWaitTixISRDone(sc, target_ix); 2917 retval = ASC_NOERROR; 2918 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 2919 buf = (u_char *) & scsiq_buf; 2920 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 2921 *buf++ = 0x00; 2922 scsiq->q1.status = (u_char) ASC_QS_READY; 2923 scsiq->q2.cdb_len = 6; 2924 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 2925 scsiq->q1.target_id = target_id; 2926 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 2927 scsiq->cdbptr = scsiq->cdb; 2928 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 2929 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 2930 sc->unit_not_ready &= ~target_id; 2931 sc->sdtr_done |= target_id; 2932 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 2933 sc->unit_not_ready = target_id; 2934 DvcSleepMilliSecond(1000); 2935 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 2936 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 2937 AscCleanUpDiscQueue(iot, ioh); 2938 AscStartQueueExe(iot, ioh); 2939 if (sc->pci_fix_asyn_xfer & target_id) 2940 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 2941 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 2942 AscWaitTixISRDone(sc, target_ix); 2943 } 2944 } else 2945 retval = ASC_BUSY; 2946 sc->sdtr_done &= ~target_id; 2947 } else { 2948 retval = ASC_ERROR; 2949 AscStartQueueExe(iot, ioh); 2950 } 2951 } 2952 sc->unit_not_ready = saved_unit_not_ready; 2953 return (retval); 2954 } 2955 2956 2957 int 2958 AscResetBus(ASC_SOFTC *sc) 2959 { 2960 bus_space_tag_t iot = sc->sc_iot; 2961 bus_space_handle_t ioh = sc->sc_ioh; 2962 int retval; 2963 int i; 2964 2965 2966 sc->unit_not_ready = 0xFF; 2967 retval = ASC_NOERROR; 2968 2969 AscWaitISRDone(sc); 2970 AscStopQueueExe(iot, ioh); 2971 sc->sdtr_done = 0; 2972 AscResetChipAndScsiBus(iot, ioh); 2973 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 2974 AscReInitLram(sc); 2975 for (i = 0; i <= ASC_MAX_TID; i++) { 2976 sc->cur_dvc_qng[i] = 0; 2977 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 2978 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 2979 } 2980 2981 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 2982 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 2983 retval = ASC_ERROR; 2984 2985 if (AscStartChip(iot, ioh) == 0) 2986 retval = ASC_ERROR; 2987 2988 AscStartQueueExe(iot, ioh); 2989 sc->unit_not_ready = 0; 2990 sc->queue_full_or_busy = 0; 2991 return (retval); 2992 } 2993 2994 2995 /******************************************************************************/ 2996 /* Error Handling routines */ 2997 /******************************************************************************/ 2998 2999 3000 static int 3001 AscSetLibErrorCode(ASC_SOFTC *sc, u_int16_t err_code) 3002 { 3003 /* 3004 * if(sc->err_code == 0) { sc->err_code = err_code; 3005 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3006 err_code); 3007 /* 3008 * } 3009 */ 3010 return (err_code); 3011 } 3012 3013 3014 /******************************************************************************/ 3015 /* Handle bugged borads routines */ 3016 /******************************************************************************/ 3017 3018 3019 void 3020 AscInquiryHandling(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq) 3021 { 3022 bus_space_tag_t iot = sc->sc_iot; 3023 bus_space_handle_t ioh = sc->sc_ioh; 3024 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3025 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3026 3027 orig_init_sdtr = sc->init_sdtr; 3028 orig_use_tagged_qng = sc->use_tagged_qng; 3029 3030 sc->init_sdtr &= ~tid_bit; 3031 sc->can_tagged_qng &= ~tid_bit; 3032 sc->use_tagged_qng &= ~tid_bit; 3033 3034 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3035 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3036 sc->init_sdtr |= tid_bit; 3037 3038 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3039 if (AscTagQueuingSafe(inq)) { 3040 sc->use_tagged_qng |= tid_bit; 3041 sc->can_tagged_qng |= tid_bit; 3042 } 3043 } 3044 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3045 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3046 sc->disc_enable); 3047 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3048 sc->use_tagged_qng); 3049 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3050 sc->can_tagged_qng); 3051 3052 sc->max_dvc_qng[tid_no] = 3053 sc->max_tag_qng[tid_no]; 3054 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3055 sc->max_dvc_qng[tid_no]); 3056 } 3057 if (orig_init_sdtr != sc->init_sdtr) 3058 AscAsyncFix(sc, tid_no, inq); 3059 } 3060 3061 3062 static int 3063 AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq) 3064 { 3065 if ((inq->add_len >= 32) && 3066 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3067 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3068 return 0; 3069 } 3070 return 1; 3071 } 3072 3073 3074 static void 3075 AscAsyncFix(ASC_SOFTC *sc, u_int8_t tid_no, ASC_SCSI_INQUIRY *inq) 3076 { 3077 u_int8_t dvc_type; 3078 ASC_SCSI_BIT_ID_TYPE tid_bits; 3079 3080 3081 dvc_type = inq->byte0.peri_dvc_type; 3082 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3083 3084 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3085 if (!(sc->init_sdtr & tid_bits)) { 3086 if ((dvc_type == SCSI_TYPE_CDROM) && 3087 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3088 sc->pci_fix_asyn_xfer_always |= tid_bits; 3089 } 3090 sc->pci_fix_asyn_xfer |= tid_bits; 3091 if ((dvc_type == SCSI_TYPE_PROC) || 3092 (dvc_type == SCSI_TYPE_SCANNER)) { 3093 sc->pci_fix_asyn_xfer &= ~tid_bits; 3094 } 3095 if ((dvc_type == SCSI_TYPE_SASD) && 3096 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3097 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3098 sc->pci_fix_asyn_xfer &= ~tid_bits; 3099 } 3100 if ((dvc_type == SCSI_TYPE_SASD) && 3101 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3102 sc->pci_fix_asyn_xfer &= ~tid_bits; 3103 } 3104 if ((dvc_type == SCSI_TYPE_CDROM) && 3105 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3106 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3107 sc->pci_fix_asyn_xfer &= ~tid_bits; 3108 } 3109 if ((dvc_type == SCSI_TYPE_CDROM) && 3110 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3111 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3112 sc->pci_fix_asyn_xfer &= ~tid_bits; 3113 } 3114 if (sc->pci_fix_asyn_xfer & tid_bits) { 3115 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3116 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3117 } 3118 } 3119 } 3120 } 3121 3122 3123 /******************************************************************************/ 3124 /* Miscellaneous routines */ 3125 /******************************************************************************/ 3126 3127 3128 static int 3129 AscCompareString(const u_char *str1, const u_char *str2, int len) 3130 { 3131 int i; 3132 int diff; 3133 3134 for (i = 0; i < len; i++) { 3135 diff = (int) (str1[i] - str2[i]); 3136 if (diff != 0) 3137 return (diff); 3138 } 3139 3140 return (0); 3141 } 3142 3143 3144 /******************************************************************************/ 3145 /* Device oriented routines */ 3146 /******************************************************************************/ 3147 3148 3149 static int 3150 DvcEnterCritical(void) 3151 { 3152 int s; 3153 3154 s = splbio(); 3155 return (s); 3156 } 3157 3158 3159 static void 3160 DvcLeaveCritical(int s) 3161 { 3162 3163 splx(s); 3164 } 3165 3166 3167 static void 3168 DvcSleepMilliSecond(u_int32_t n) 3169 { 3170 3171 DELAY(n * 1000); 3172 } 3173 3174 #ifdef UNUSED 3175 static void 3176 DvcDelayMicroSecond(u_int32_t n) 3177 { 3178 3179 DELAY(n); 3180 } 3181 #endif 3182 3183 static void 3184 DvcDelayNanoSecond(u_int32_t n) 3185 { 3186 3187 DELAY((n + 999) / 1000); 3188 } 3189
Indexes created Thu Oct 02 07:10:07 GMT 2025