advlib.c revision 1.4
1 /* $NetBSD: advlib.c,v 1.4 1998/09/26 16:02:56 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/scsipi/scsi_all.h> 67 #include <dev/scsipi/scsipi_all.h> 68 #include <dev/scsipi/scsiconf.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_param.h> 72 #include <vm/pmap.h> 73 74 #include <dev/ic/adv.h> 75 #include <dev/ic/advlib.h> 76 #include <dev/ic/advmcode.h> 77 78 79 /******************************************************************************/ 80 /* Static functions */ 81 /******************************************************************************/ 82 83 /* Initializzation routines */ 84 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 85 u_int16_t, u_int16_t *, u_int16_t)); 86 static void AscInitLram __P((ASC_SOFTC *)); 87 static void AscInitQLinkVar __P((ASC_SOFTC *)); 88 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 89 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 90 91 /* Chip register routines */ 92 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 93 94 /* RISC Chip routines */ 95 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 96 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 97 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 98 u_int8_t)); 99 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 100 static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t, 101 u_int16_t)); 102 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 103 u_int8_t, u_int8_t)); 104 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 105 u_int8_t, u_int8_t)); 106 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 107 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 108 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 109 110 /* Lram routines */ 111 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 112 u_int16_t)); 113 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t, u_int8_t)); 115 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t)); 117 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t, u_int16_t)); 119 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t)); 121 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t, u_int32_t)); 123 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int16_t, int)); 125 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t *, int)); 127 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int)); 129 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int32_t *, int)); 131 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, int)); 133 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 134 135 /* MicroCode routines */ 136 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 137 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 138 139 /* EEProm routines */ 140 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 141 u_int8_t)); 142 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 143 u_int16_t)); 144 static void AscWaitEEPRead __P((void)); 145 static void AscWaitEEPWrite __P((void)); 146 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 147 u_int8_t)); 148 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 149 u_int8_t, u_int16_t)); 150 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 151 ASCEEP_CONFIG *, u_int16_t)); 152 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 153 ASCEEP_CONFIG *, u_int16_t)); 154 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 155 ASCEEP_CONFIG *, u_int16_t)); 156 157 /* Interrupt routines */ 158 static void AscIsrChipHalted __P((ASC_SOFTC *)); 159 static int AscIsrQDone __P((ASC_SOFTC *)); 160 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 161 static int AscWaitISRDone __P((ASC_SOFTC *)); 162 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 163 u_int16_t, ASC_QDONE_INFO *, 164 u_int32_t)); 165 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 166 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 167 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 168 static u_int8_t AscGetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 169 u_int16_t)); 170 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 171 u_int8_t, u_int16_t)); 172 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 173 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 174 static u_int16_t AscGetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t)); 175 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 176 u_int16_t)); 177 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 178 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 179 u_int8_t)); 180 181 /* Messages routines */ 182 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 183 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 184 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 185 186 /* SDTR routines */ 187 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 188 u_int8_t, u_int8_t)); 189 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 190 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 191 192 /* Queue routines */ 193 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 194 static int AscSgListToQueue __P((int)); 195 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 196 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 197 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 198 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 199 u_int8_t)); 200 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 201 bus_space_handle_t, 202 u_int8_t, u_int8_t)); 203 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 204 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 205 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 206 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 207 ASC_SCSI_Q *)); 208 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 209 210 /* Abort and Reset CCB routines */ 211 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, u_int32_t)); 212 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 213 214 /* Error Handling routines */ 215 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 216 217 /* Handle bugged borads routines */ 218 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 219 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 220 221 /* Miscellaneous routines */ 222 static int AscCompareString __P((u_char *, u_char *, int)); 223 224 /* Device oriented routines */ 225 static int DvcEnterCritical __P((void)); 226 static void DvcLeaveCritical __P((int)); 227 static void DvcSleepMilliSecond __P((u_int32_t)); 228 //static void DvcDelayMicroSecond __P((u_int32_t)); 229 static void DvcDelayNanoSecond __P((u_int32_t)); 230 static u_int32_t DvcGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 231 ASC_SG_HEAD *)); 232 static void DvcPutScsiQ __P((bus_space_tag_t, bus_space_handle_t, 233 u_int16_t, u_int16_t *, int)); 234 static void DvcGetQinfo __P((bus_space_tag_t, bus_space_handle_t, 235 u_int16_t, u_int16_t *, int words)); 236 237 238 /******************************************************************************/ 239 /* Initializzation routines */ 240 /******************************************************************************/ 241 242 /* 243 * This function perform the following steps: 244 * - initialize ASC_SOFTC structure with defaults values. 245 * - inquire board registers to know what kind of board it is. 246 * - keep track of bugged borads. 247 */ 248 void 249 AscInitASC_SOFTC(sc) 250 ASC_SOFTC *sc; 251 { 252 bus_space_tag_t iot = sc->sc_iot; 253 bus_space_handle_t ioh = sc->sc_ioh; 254 int i; 255 u_int8_t chip_version; 256 257 258 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 259 ASC_SET_CHIP_STATUS(iot, ioh, 0); 260 261 sc->bug_fix_cntl = 0; 262 sc->pci_fix_asyn_xfer = 0; 263 sc->pci_fix_asyn_xfer_always = 0; 264 sc->sdtr_done = 0; 265 sc->cur_total_qng = 0; 266 sc->last_q_shortage = 0; 267 sc->use_tagged_qng = 0; 268 sc->unit_not_ready = 0; 269 sc->queue_full_or_busy = 0; 270 sc->host_init_sdtr_index = 0; 271 sc->can_tagged_qng = 0; 272 sc->cmd_qng_enabled = 0; 273 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 274 sc->init_sdtr = 0; 275 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 276 sc->scsi_reset_wait = 3; 277 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 278 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 279 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 280 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 281 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 282 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 283 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 284 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 285 sc->chip_version = chip_version; 286 if ((sc->bus_type & ASC_IS_PCI) && 287 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 288 sc->bus_type = ASC_IS_PCI_ULTRA; 289 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 290 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 291 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 292 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 293 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 294 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 295 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 296 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 297 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 298 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 299 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 300 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 301 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 302 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 303 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 304 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 305 sc->max_sdtr_index = 15; 306 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 307 ASC_SET_EXTRA_CONTROL(iot, ioh, 308 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 309 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 310 ASC_SET_EXTRA_CONTROL(iot, ioh, 311 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 312 } else { 313 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 314 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 315 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 316 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 317 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 318 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 319 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 320 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 321 sc->max_sdtr_index = 7; 322 } 323 324 if (sc->bus_type == ASC_IS_PCI) 325 ASC_SET_EXTRA_CONTROL(iot, ioh, 326 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 327 328 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 329 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 330 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 331 sc->bus_type = ASC_IS_ISAPNP; 332 } 333 if ((sc->bus_type & ASC_IS_ISA) != 0) 334 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 335 336 for (i = 0; i <= ASC_MAX_TID; i++) { 337 sc->cur_dvc_qng[i] = 0; 338 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 339 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 340 } 341 } 342 343 344 /* 345 * This function initialize some ASC_SOFTC fields with values read from 346 * on-board EEProm. 347 */ 348 u_int16_t 349 AscInitFromEEP(sc) 350 ASC_SOFTC *sc; 351 { 352 bus_space_tag_t iot = sc->sc_iot; 353 bus_space_handle_t ioh = sc->sc_ioh; 354 ASCEEP_CONFIG eep_config_buf; 355 ASCEEP_CONFIG *eep_config; 356 u_int16_t chksum; 357 u_int16_t warn_code; 358 u_int16_t cfg_msw, cfg_lsw; 359 int i; 360 int write_eep = 0; 361 362 363 warn_code = 0; 364 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 365 AscStopQueueExe(iot, ioh); 366 if ((AscStopChip(iot, ioh) == FALSE) || 367 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 368 AscResetChipAndScsiBus(iot, ioh); 369 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 370 } 371 if (AscIsChipHalted(iot, ioh) == FALSE) 372 return (-1); 373 374 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 375 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 376 return (-2); 377 378 eep_config = (ASCEEP_CONFIG *) & eep_config_buf; 379 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 380 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 381 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 382 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 383 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 384 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 385 } 386 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 387 if (chksum == 0) 388 chksum = 0xAA55; 389 390 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 391 warn_code |= ASC_WARN_AUTO_CONFIG; 392 if (sc->chip_version == 3) { 393 if (eep_config->cfg_lsw != cfg_lsw) { 394 warn_code |= ASC_WARN_EEPROM_RECOVER; 395 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 396 } 397 if (eep_config->cfg_msw != cfg_msw) { 398 warn_code |= ASC_WARN_EEPROM_RECOVER; 399 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 400 } 401 } 402 } 403 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 404 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 405 406 if (chksum != eep_config->chksum) { 407 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 408 ASC_CHIP_VER_PCI_ULTRA_3050) { 409 eep_config->init_sdtr = 0xFF; 410 eep_config->disc_enable = 0xFF; 411 eep_config->start_motor = 0xFF; 412 eep_config->use_cmd_qng = 0; 413 eep_config->max_total_qng = 0xF0; 414 eep_config->max_tag_qng = 0x20; 415 eep_config->cntl = 0xBFFF; 416 eep_config->chip_scsi_id = 7; 417 eep_config->no_scam = 0; 418 eep_config->adapter_info[0] = 0; 419 eep_config->adapter_info[1] = 0; 420 eep_config->adapter_info[2] = 0; 421 eep_config->adapter_info[3] = 0; 422 eep_config->adapter_info[4] = 0; 423 /* Indicate EEPROM-less board. */ 424 eep_config->adapter_info[5] = 0xBB; 425 } else { 426 write_eep = 1; 427 warn_code |= ASC_WARN_EEPROM_CHKSUM; 428 } 429 } 430 sc->sdtr_enable = eep_config->init_sdtr; 431 sc->disc_enable = eep_config->disc_enable; 432 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 433 sc->isa_dma_speed = eep_config->isa_dma_speed; 434 sc->start_motor = eep_config->start_motor; 435 sc->dvc_cntl = eep_config->cntl; 436 sc->adapter_info[0] = eep_config->adapter_info[0]; 437 sc->adapter_info[1] = eep_config->adapter_info[1]; 438 sc->adapter_info[2] = eep_config->adapter_info[2]; 439 sc->adapter_info[3] = eep_config->adapter_info[3]; 440 sc->adapter_info[4] = eep_config->adapter_info[4]; 441 sc->adapter_info[5] = eep_config->adapter_info[5]; 442 443 if (!AscTestExternalLram(iot, ioh)) { 444 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 445 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 446 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 447 } else { 448 eep_config->cfg_msw |= 0x0800; 449 cfg_msw |= 0x0800; 450 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 451 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 452 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 453 } 454 } 455 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 456 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 457 458 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 459 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 460 461 if (eep_config->max_tag_qng > eep_config->max_total_qng) 462 eep_config->max_tag_qng = eep_config->max_total_qng; 463 464 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 465 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 466 467 sc->max_total_qng = eep_config->max_total_qng; 468 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 469 eep_config->use_cmd_qng) { 470 eep_config->disc_enable = eep_config->use_cmd_qng; 471 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 472 } 473 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 474 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 475 476 eep_config->chip_scsi_id &= ASC_MAX_TID; 477 sc->chip_scsi_id = eep_config->chip_scsi_id; 478 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 479 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 480 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 481 } 482 for (i = 0; i <= ASC_MAX_TID; i++) { 483 sc->max_tag_qng[i] = eep_config->max_tag_qng; 484 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 485 (sc->host_init_sdtr_index << 4); 486 } 487 488 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 489 if (write_eep) 490 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 491 492 return (warn_code); 493 } 494 495 496 u_int16_t 497 AscInitFromASC_SOFTC(sc) 498 ASC_SOFTC *sc; 499 { 500 bus_space_tag_t iot = sc->sc_iot; 501 bus_space_handle_t ioh = sc->sc_ioh; 502 u_int16_t cfg_msw; 503 u_int16_t warn_code; 504 u_int16_t pci_device_id = sc->pci_device_id; 505 506 507 warn_code = 0; 508 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 509 510 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 511 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 512 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 513 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 514 } 515 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 516 sc->disc_enable = sc->cmd_qng_enabled; 517 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 518 } 519 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 520 warn_code |= ASC_WARN_AUTO_CONFIG; 521 } 522 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 523 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 524 } 525 if (sc->bus_type & ASC_IS_PCI) { 526 cfg_msw &= 0xFFC0; 527 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 528 529 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 530 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 531 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 532 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 533 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 534 } 535 } 536 } else if (sc->bus_type == ASC_IS_ISAPNP) { 537 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 538 ASC_CHIP_VER_ASYN_BUG) { 539 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 540 } 541 } 542 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 543 544 if (sc->bus_type & ASC_IS_ISA) { 545 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 546 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 547 } 548 return (warn_code); 549 } 550 551 552 /* 553 * - Initialize RISC chip 554 * - Intialize Lram 555 * - Load uCode into Lram 556 * - Enable Interrupts 557 */ 558 int 559 AscInitDriver(sc) 560 ASC_SOFTC *sc; 561 { 562 bus_space_tag_t iot = sc->sc_iot; 563 bus_space_handle_t ioh = sc->sc_ioh; 564 u_int32_t chksum; 565 566 567 if (!AscFindSignature(iot, ioh)) 568 return (1); 569 570 AscDisableInterrupt(iot, ioh); 571 572 AscInitLram(sc); 573 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 574 asc_mcode_size); 575 if (chksum != asc_mcode_chksum) 576 return (2); 577 578 if (AscInitMicroCodeVar(sc) == 0) 579 return (3); 580 581 AscEnableInterrupt(iot, ioh); 582 583 return (0); 584 } 585 586 587 int 588 AscFindSignature(iot, ioh) 589 bus_space_tag_t iot; 590 bus_space_handle_t ioh; 591 { 592 u_int16_t sig_word; 593 594 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 595 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 596 if (sig_word == ASC_1000_ID0W || 597 sig_word == ASC_1000_ID0W_FIX) 598 return (1); 599 } 600 return (0); 601 } 602 603 604 static u_int32_t 605 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 606 bus_space_tag_t iot; 607 bus_space_handle_t ioh; 608 u_int16_t s_addr; 609 u_int16_t *mcode_buf; 610 u_int16_t mcode_size; 611 { 612 u_int32_t chksum; 613 u_int16_t mcode_word_size; 614 u_int16_t mcode_chksum; 615 616 mcode_word_size = mcode_size >> 1; 617 /* clear board memory */ 618 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 619 /* copy uCode to board memory */ 620 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 621 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 622 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 623 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 624 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 625 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 626 627 return (chksum); 628 } 629 630 631 static void 632 AscInitLram(sc) 633 ASC_SOFTC *sc; 634 { 635 bus_space_tag_t iot = sc->sc_iot; 636 bus_space_handle_t ioh = sc->sc_ioh; 637 u_int8_t i; 638 u_int16_t s_addr; 639 640 641 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 642 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 643 644 i = ASC_MIN_ACTIVE_QNO; 645 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 647 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 648 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 649 i++; 650 s_addr += ASC_QBLK_SIZE; 651 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 652 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 653 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 655 } 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 657 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 658 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 659 i++; 660 s_addr += ASC_QBLK_SIZE; 661 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 662 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 663 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 664 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 665 } 666 } 667 668 669 void 670 AscReInitLram(sc) 671 ASC_SOFTC *sc; 672 { 673 674 AscInitLram(sc); 675 AscInitQLinkVar(sc); 676 } 677 678 679 static void 680 AscInitQLinkVar(sc) 681 ASC_SOFTC *sc; 682 { 683 bus_space_tag_t iot = sc->sc_iot; 684 bus_space_handle_t ioh = sc->sc_ioh; 685 u_int8_t i; 686 u_int16_t lram_addr; 687 688 689 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 690 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 691 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 692 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 693 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 694 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 695 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 696 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 697 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 698 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 699 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 700 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 701 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 702 lram_addr = ASC_QADR_BEG; 703 for (i = 0; i < 32; i++, lram_addr += 2) 704 AscWriteLramWord(iot, ioh, lram_addr, 0); 705 } 706 707 708 static int 709 AscResetChipAndScsiBus(bus_space_tag_t iot, 710 bus_space_handle_t ioh) 711 { 712 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 713 714 AscStopChip(iot, ioh); 715 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 716 717 DvcDelayNanoSecond(60000); 718 719 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 720 AscSetChipIH(iot, ioh, ASC_INS_HALT); 721 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 722 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 723 724 DvcSleepMilliSecond(200); 725 726 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 727 AscStartChip(iot, ioh); 728 729 DvcSleepMilliSecond(200); 730 731 return (AscIsChipHalted(iot, ioh)); 732 } 733 734 735 static u_int16_t 736 AscGetChipBusType(iot, ioh) 737 bus_space_tag_t iot; 738 bus_space_handle_t ioh; 739 { 740 u_int16_t chip_ver; 741 742 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 743 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 744 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 745 /* 746 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50) 747 * == 0x0C50)) return (ASC_IS_EISA); 748 */ 749 return (ASC_IS_VL); 750 } 751 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 752 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 753 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 754 return (ASC_IS_ISAPNP); 755 756 return (ASC_IS_ISA); 757 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 758 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 759 return (ASC_IS_PCI); 760 761 return (0); 762 } 763 764 765 /******************************************************************************/ 766 /* Chip register routines */ 767 /******************************************************************************/ 768 769 770 static void 771 AscSetBank(iot, ioh, bank) 772 bus_space_tag_t iot; 773 bus_space_handle_t ioh; 774 u_int8_t bank; 775 { 776 u_int8_t val; 777 778 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 779 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 780 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 781 ASC_CC_CHIP_RESET)); 782 783 switch (bank) { 784 case 1: 785 val |= ASC_CC_BANK_ONE; 786 break; 787 788 case 2: 789 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 790 break; 791 792 default: 793 val &= ~ASC_CC_BANK_ONE; 794 } 795 796 ASC_SET_CHIP_CONTROL(iot, ioh, val); 797 return; 798 } 799 800 801 /******************************************************************************/ 802 /* Chip routines */ 803 /******************************************************************************/ 804 805 806 static int 807 AscStartChip(iot, ioh) 808 bus_space_tag_t iot; 809 bus_space_handle_t ioh; 810 { 811 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 812 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 813 return (0); 814 815 return (1); 816 } 817 818 819 static int 820 AscStopChip(iot, ioh) 821 bus_space_tag_t iot; 822 bus_space_handle_t ioh; 823 { 824 u_int8_t cc_val; 825 826 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 827 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 828 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 829 AscSetChipIH(iot, ioh, ASC_INS_HALT); 830 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 831 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 832 return (0); 833 834 return (1); 835 } 836 837 838 static u_int8_t 839 AscGetChipVersion(iot, ioh, bus_type) 840 bus_space_tag_t iot; 841 bus_space_handle_t ioh; 842 u_int16_t bus_type; 843 { 844 if (bus_type & ASC_IS_EISA) { 845 /* 846 * u_int16_t eisa_iop; u_int8_t revision; 847 * 848 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) | 849 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop); 850 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 851 */ 852 } 853 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 854 } 855 856 857 static u_int8_t 858 AscSetChipScsiID(iot, ioh, new_id) 859 bus_space_tag_t iot; 860 bus_space_handle_t ioh; 861 u_int8_t new_id; 862 { 863 u_int16_t cfg_lsw; 864 865 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 866 return (new_id); 867 868 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 869 cfg_lsw &= 0xF8FF; 870 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 871 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 872 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 873 } 874 875 876 static u_int8_t 877 AscGetChipScsiCtrl(iot, ioh) 878 bus_space_tag_t iot; 879 bus_space_handle_t ioh; 880 { 881 u_int8_t scsi_ctrl; 882 883 AscSetBank(iot, ioh, 1); 884 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 885 AscSetBank(iot, ioh, 0); 886 return (scsi_ctrl); 887 } 888 889 890 static int 891 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 892 bus_space_tag_t iot; 893 bus_space_handle_t ioh; 894 u_int8_t tid_no; 895 u_int8_t sdtr_data; 896 { 897 int retval = FALSE; 898 899 if (AscHostReqRiscHalt(iot, ioh)) { 900 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 901 AscStartChip(iot, ioh); 902 } 903 return (retval); 904 } 905 906 907 static int 908 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 909 bus_space_tag_t iot; 910 bus_space_handle_t ioh; 911 u_int8_t id; 912 u_int8_t sdtr_data; 913 { 914 ASC_SCSI_BIT_ID_TYPE org_id; 915 int i; 916 int sta = TRUE; 917 918 AscSetBank(iot, ioh, 1); 919 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 920 for (i = 0; i <= ASC_MAX_TID; i++) 921 if (org_id == (0x01 << i)) 922 break; 923 924 org_id = i; 925 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 926 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 927 AscSetBank(iot, ioh, 0); 928 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 929 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 930 sta = FALSE; 931 } else 932 sta = FALSE; 933 934 AscSetBank(iot, ioh, 1); 935 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 936 AscSetBank(iot, ioh, 0); 937 return (sta); 938 } 939 940 941 static int 942 AscHostReqRiscHalt(iot, ioh) 943 bus_space_tag_t iot; 944 bus_space_handle_t ioh; 945 { 946 int count = 0; 947 int retval = 0; 948 u_int8_t saved_stop_code; 949 950 951 if (AscIsChipHalted(iot, ioh)) 952 return (1); 953 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 954 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 955 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 956 957 do { 958 if (AscIsChipHalted(iot, ioh)) { 959 retval = 1; 960 break; 961 } 962 DvcSleepMilliSecond(100); 963 } while (count++ < 20); 964 965 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 966 967 return (retval); 968 } 969 970 971 static int 972 AscIsChipHalted(iot, ioh) 973 bus_space_tag_t iot; 974 bus_space_handle_t ioh; 975 { 976 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 977 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 978 return (1); 979 980 return (0); 981 } 982 983 984 static void 985 AscSetChipIH(iot, ioh, ins_code) 986 bus_space_tag_t iot; 987 bus_space_handle_t ioh; 988 u_int16_t ins_code; 989 { 990 AscSetBank(iot, ioh, 1); 991 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 992 AscSetBank(iot, ioh, 0); 993 994 return; 995 } 996 997 998 /******************************************************************************/ 999 /* Lram routines */ 1000 /******************************************************************************/ 1001 1002 1003 static u_int8_t 1004 AscReadLramByte(iot, ioh, addr) 1005 bus_space_tag_t iot; 1006 bus_space_handle_t ioh; 1007 u_int16_t addr; 1008 { 1009 u_int8_t byte_data; 1010 u_int16_t word_data; 1011 1012 1013 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1014 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1015 #if BYTE_ORDER == BIG_ENDIAN 1016 if (addr & 1) 1017 //odd address 1018 byte_data = (u_int8_t) (word_data & 0xFF); 1019 else 1020 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1021 #else 1022 if (addr & 1) 1023 //odd address 1024 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1025 else 1026 byte_data = (u_int8_t) (word_data & 0xFF); 1027 #endif 1028 return (byte_data); 1029 } 1030 1031 1032 static void 1033 AscWriteLramByte(iot, ioh, addr, data) 1034 bus_space_tag_t iot; 1035 bus_space_handle_t ioh; 1036 u_int16_t addr; 1037 u_int8_t data; 1038 { 1039 u_int16_t word_data; 1040 1041 1042 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1043 #if BYTE_ORDER == BIG_ENDIAN 1044 if (addr & 1) 1045 //odd address 1046 { 1047 word_data &= 0xFF00; 1048 word_data |= ((u_int16_t) data) & 0x00FF; 1049 } else { 1050 word_data &= 0xFF00; 1051 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1052 } 1053 #else 1054 if (addr & 1) 1055 //odd address 1056 { 1057 word_data &= 0x00FF; 1058 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1059 } else { 1060 word_data &= 0xFF00; 1061 word_data |= ((u_int16_t) data) & 0x00FF; 1062 } 1063 #endif 1064 AscWriteLramWord(iot, ioh, addr, word_data); 1065 } 1066 1067 1068 static u_int16_t 1069 AscReadLramWord(iot, ioh, addr) 1070 bus_space_tag_t iot; 1071 bus_space_handle_t ioh; 1072 u_int16_t addr; 1073 { 1074 1075 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1076 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1077 } 1078 1079 1080 static void 1081 AscWriteLramWord(iot, ioh, addr, data) 1082 bus_space_tag_t iot; 1083 bus_space_handle_t ioh; 1084 u_int16_t addr; 1085 u_int16_t data; 1086 { 1087 1088 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1089 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1090 } 1091 1092 1093 static u_int32_t 1094 AscReadLramDWord(iot, ioh, addr) 1095 bus_space_tag_t iot; 1096 bus_space_handle_t ioh; 1097 u_int16_t addr; 1098 { 1099 u_int16_t low_word, hi_word; 1100 1101 1102 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1103 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1104 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1105 1106 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1107 } 1108 1109 1110 static void 1111 AscWriteLramDWord(iot, ioh, addr, data) 1112 bus_space_tag_t iot; 1113 bus_space_handle_t ioh; 1114 u_int16_t addr; 1115 u_int32_t data; 1116 { 1117 1118 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1119 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1120 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1121 } 1122 1123 1124 static void 1125 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1126 bus_space_tag_t iot; 1127 bus_space_handle_t ioh; 1128 u_int16_t s_addr; 1129 u_int16_t s_words; 1130 int count; 1131 { 1132 int i; 1133 1134 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1135 for (i = 0; i < count; i++) 1136 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1137 } 1138 1139 1140 static void 1141 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1142 bus_space_tag_t iot; 1143 bus_space_handle_t ioh; 1144 u_int16_t s_addr; 1145 u_int16_t *s_buffer; 1146 int words; 1147 { 1148 int i; 1149 1150 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1151 for (i = 0; i < words; i++, s_buffer++) 1152 ASC_SET_CHIP_LRAM_DATA(iot, ioh, *s_buffer); 1153 } 1154 1155 1156 static void 1157 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1158 bus_space_tag_t iot; 1159 bus_space_handle_t ioh; 1160 u_int16_t s_addr; 1161 u_int16_t *s_buffer; 1162 int words; 1163 { 1164 int i; 1165 1166 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1167 for (i = 0; i < words; i++, s_buffer++) 1168 *s_buffer = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1169 } 1170 1171 1172 static void 1173 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1174 bus_space_tag_t iot; 1175 bus_space_handle_t ioh; 1176 u_int16_t s_addr; 1177 u_int32_t *s_buffer; 1178 int dwords; 1179 { 1180 int i; 1181 int words; 1182 u_int16_t *pw; 1183 1184 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1185 1186 pw = (u_int16_t *) s_buffer; 1187 words = dwords << 1; 1188 for (i = 0; i < words; i++, pw++) 1189 ASC_SET_CHIP_LRAM_DATA(iot, ioh, *pw); 1190 } 1191 1192 1193 static u_int32_t 1194 AscMemSumLramWord(iot, ioh, s_addr, words) 1195 bus_space_tag_t iot; 1196 bus_space_handle_t ioh; 1197 u_int16_t s_addr; 1198 int words; 1199 { 1200 u_int32_t sum = 0L; 1201 u_int16_t i; 1202 1203 1204 for (i = 0; i < words; i++, s_addr += 2) 1205 sum += AscReadLramWord(iot, ioh, s_addr); 1206 1207 return (sum); 1208 } 1209 1210 1211 static int 1212 AscTestExternalLram(iot, ioh) 1213 bus_space_tag_t iot; 1214 bus_space_handle_t ioh; 1215 { 1216 u_int16_t q_addr; 1217 u_int16_t saved_word; 1218 int retval; 1219 1220 1221 retval = 0; 1222 q_addr = ASC_QNO_TO_QADDR(241); 1223 saved_word = AscReadLramWord(iot, ioh, q_addr); 1224 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1225 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1226 DvcSleepMilliSecond(10); 1227 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1228 1229 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1230 retval = 1; 1231 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1232 } 1233 return (retval); 1234 } 1235 1236 1237 /******************************************************************************/ 1238 /* MicroCode routines */ 1239 /******************************************************************************/ 1240 1241 1242 static u_int16_t 1243 AscInitMicroCodeVar(sc) 1244 ASC_SOFTC *sc; 1245 { 1246 bus_space_tag_t iot = sc->sc_iot; 1247 bus_space_handle_t ioh = sc->sc_ioh; 1248 u_int32_t phy_addr; 1249 int i; 1250 1251 1252 for (i = 0; i <= ASC_MAX_TID; i++) 1253 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1254 sc->sdtr_period_offset[i]); 1255 1256 AscInitQLinkVar(sc); 1257 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1258 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1259 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1260 1261 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1262 ASC_OVERRUN_BSIZE)) == 0L) { 1263 return (0); 1264 } else { 1265 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1266 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1267 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1268 ASC_OVERRUN_BSIZE - 8); 1269 } 1270 1271 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1272 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1273 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1274 1275 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1276 return (0); 1277 } 1278 if (AscStartChip(iot, ioh) != 1) { 1279 return (0); 1280 } 1281 return (1); 1282 } 1283 1284 1285 static u_int32_t 1286 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1287 ASC_SOFTC *sc; 1288 u_int8_t *buf_addr; 1289 u_int32_t buf_size; 1290 { 1291 ASC_MIN_SG_HEAD sg_head; 1292 1293 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1294 if (DvcGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1295 buf_size) { 1296 return (0L); 1297 } 1298 if (sg_head.entry_cnt > 1) { 1299 return (0L); 1300 } 1301 return (sg_head.sg_list[0].addr); 1302 } 1303 /******************************************************************************/ 1304 /* EEProm routines */ 1305 /******************************************************************************/ 1306 1307 1308 static int 1309 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1310 bus_space_tag_t iot; 1311 bus_space_handle_t ioh; 1312 u_int8_t cmd_reg; 1313 { 1314 u_int8_t read_back; 1315 int retry; 1316 1317 retry = 0; 1318 1319 while (TRUE) { 1320 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1321 DvcSleepMilliSecond(1); 1322 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1323 if (read_back == cmd_reg) 1324 return (1); 1325 1326 if (retry++ > ASC_EEP_MAX_RETRY) 1327 return (0); 1328 } 1329 } 1330 1331 1332 static int 1333 AscWriteEEPDataReg(iot, ioh, data_reg) 1334 bus_space_tag_t iot; 1335 bus_space_handle_t ioh; 1336 u_int16_t data_reg; 1337 { 1338 u_int16_t read_back; 1339 int retry; 1340 1341 retry = 0; 1342 while (TRUE) { 1343 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1344 DvcSleepMilliSecond(1); 1345 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1346 if (read_back == data_reg) 1347 return (1); 1348 1349 if (retry++ > ASC_EEP_MAX_RETRY) 1350 return (0); 1351 } 1352 } 1353 1354 1355 static void 1356 AscWaitEEPRead(void) 1357 { 1358 1359 DvcSleepMilliSecond(1); 1360 } 1361 1362 1363 static void 1364 AscWaitEEPWrite(void) 1365 { 1366 1367 DvcSleepMilliSecond(1); 1368 } 1369 1370 1371 static u_int16_t 1372 AscReadEEPWord(iot, ioh, addr) 1373 bus_space_tag_t iot; 1374 bus_space_handle_t ioh; 1375 u_int8_t addr; 1376 { 1377 u_int16_t read_wval; 1378 u_int8_t cmd_reg; 1379 1380 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1381 AscWaitEEPRead(); 1382 cmd_reg = addr | ASC_EEP_CMD_READ; 1383 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1384 AscWaitEEPRead(); 1385 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1386 AscWaitEEPRead(); 1387 1388 return (read_wval); 1389 } 1390 1391 1392 static u_int16_t 1393 AscWriteEEPWord(iot, ioh, addr, word_val) 1394 bus_space_tag_t iot; 1395 bus_space_handle_t ioh; 1396 u_int8_t addr; 1397 u_int16_t word_val; 1398 { 1399 u_int16_t read_wval; 1400 1401 read_wval = AscReadEEPWord(iot, ioh, addr); 1402 if (read_wval != word_val) { 1403 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1404 AscWaitEEPRead(); 1405 AscWriteEEPDataReg(iot, ioh, word_val); 1406 AscWaitEEPRead(); 1407 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1408 AscWaitEEPWrite(); 1409 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1410 AscWaitEEPRead(); 1411 return (AscReadEEPWord(iot, ioh, addr)); 1412 } 1413 return (read_wval); 1414 } 1415 1416 1417 static u_int16_t 1418 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1419 bus_space_tag_t iot; 1420 bus_space_handle_t ioh; 1421 ASCEEP_CONFIG *cfg_buf; 1422 u_int16_t bus_type; 1423 { 1424 u_int16_t wval; 1425 u_int16_t sum; 1426 u_int16_t *wbuf; 1427 int cfg_beg; 1428 int cfg_end; 1429 int s_addr; 1430 int isa_pnp_wsize; 1431 1432 1433 wbuf = (u_int16_t *) cfg_buf; 1434 sum = 0; 1435 isa_pnp_wsize = 0; 1436 1437 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1438 wval = AscReadEEPWord(iot, ioh, s_addr); 1439 sum += wval; 1440 *wbuf = wval; 1441 } 1442 1443 if (bus_type & ASC_IS_VL) { 1444 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1445 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1446 } else { 1447 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1448 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1449 } 1450 1451 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1452 wval = AscReadEEPWord(iot, ioh, s_addr); 1453 sum += wval; 1454 *wbuf = wval; 1455 } 1456 1457 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1458 1459 return (sum); 1460 } 1461 1462 1463 static int 1464 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1465 bus_space_tag_t iot; 1466 bus_space_handle_t ioh; 1467 ASCEEP_CONFIG *cfg_buf; 1468 u_int16_t bus_type; 1469 { 1470 int retry; 1471 int n_error; 1472 1473 retry = 0; 1474 while (TRUE) { 1475 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1476 break; 1477 1478 if (++retry > ASC_EEP_MAX_RETRY) 1479 break; 1480 } 1481 1482 return (n_error); 1483 } 1484 1485 1486 static int 1487 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1488 bus_space_tag_t iot; 1489 bus_space_handle_t ioh; 1490 ASCEEP_CONFIG *cfg_buf; 1491 u_int16_t bus_type; 1492 { 1493 int n_error; 1494 u_int16_t *wbuf; 1495 u_int16_t sum; 1496 int s_addr; 1497 int cfg_beg; 1498 int cfg_end; 1499 1500 wbuf = (u_int16_t *) cfg_buf; 1501 n_error = 0; 1502 sum = 0; 1503 1504 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1505 sum += *wbuf; 1506 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1507 n_error++; 1508 } 1509 1510 if (bus_type & ASC_IS_VL) { 1511 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1512 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1513 } else { 1514 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1515 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1516 } 1517 1518 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1519 sum += *wbuf; 1520 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1521 n_error++; 1522 } 1523 1524 *wbuf = sum; 1525 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1526 n_error++; 1527 1528 wbuf = (u_int16_t *) cfg_buf; 1529 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) 1530 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1531 n_error++; 1532 1533 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) 1534 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1535 n_error++; 1536 1537 return (n_error); 1538 } 1539 1540 1541 /******************************************************************************/ 1542 /* Interrupt routines */ 1543 /******************************************************************************/ 1544 1545 1546 int 1547 AscISR(sc) 1548 ASC_SOFTC *sc; 1549 { 1550 bus_space_tag_t iot = sc->sc_iot; 1551 bus_space_handle_t ioh = sc->sc_ioh; 1552 u_int16_t chipstat; 1553 u_int16_t saved_ram_addr; 1554 u_int8_t ctrl_reg; 1555 u_int8_t saved_ctrl_reg; 1556 int int_pending; 1557 int status; 1558 u_int8_t host_flag; 1559 1560 1561 int_pending = FALSE; 1562 1563 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1564 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1565 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1566 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1567 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) 1568 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1569 int_pending = TRUE; 1570 sc->sdtr_done = 0; 1571 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1572 1573 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1574 1575 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1576 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1577 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1578 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1579 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1580 } 1581 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1582 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1583 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1584 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1585 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1586 1587 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1588 AscAckInterrupt(iot, ioh); 1589 int_pending = TRUE; 1590 1591 if ((chipstat & ASC_CSW_HALTED) && 1592 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1593 AscIsrChipHalted(sc); 1594 saved_ctrl_reg &= ~ASC_CC_HALT; 1595 } else { 1596 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1597 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1598 } else { 1599 do { 1600 if ((status = AscIsrQDone(sc)) == 1) 1601 break; 1602 } while (status == 0x11); 1603 } 1604 1605 if (status & 0x80) 1606 int_pending = -1; 1607 } 1608 } 1609 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1610 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1611 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1612 1613 return (1); 1614 /* return(int_pending); */ 1615 } 1616 1617 1618 static int 1619 AscIsrQDone(sc) 1620 ASC_SOFTC *sc; 1621 { 1622 u_int8_t next_qp; 1623 u_int8_t n_q_used; 1624 u_int8_t sg_list_qp; 1625 u_int8_t sg_queue_cnt; 1626 u_int8_t q_cnt; 1627 u_int8_t done_q_tail; 1628 u_int8_t tid_no; 1629 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1630 ASC_SCSI_BIT_ID_TYPE target_id; 1631 bus_space_tag_t iot = sc->sc_iot; 1632 bus_space_handle_t ioh = sc->sc_ioh; 1633 u_int16_t q_addr; 1634 u_int16_t sg_q_addr; 1635 u_int8_t cur_target_qng; 1636 ASC_QDONE_INFO scsiq_buf; 1637 ASC_QDONE_INFO *scsiq; 1638 ASC_ISR_CALLBACK asc_isr_callback; 1639 1640 1641 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1642 n_q_used = 1; 1643 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1644 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1645 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1646 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1647 1648 if (next_qp != ASC_QLINK_END) { 1649 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1650 q_addr = ASC_QNO_TO_QADDR(next_qp); 1651 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1652 sc->max_dma_count); 1653 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1654 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1655 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1656 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1657 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1658 sg_q_addr = q_addr; 1659 sg_list_qp = next_qp; 1660 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1661 sg_list_qp = AscReadLramByte(iot, ioh, 1662 sg_q_addr + ASC_SCSIQ_B_FWD); 1663 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1664 if (sg_list_qp == ASC_QLINK_END) { 1665 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1666 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1667 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1668 panic("AscIsrQDone: Corrupted SG list encountered"); 1669 } 1670 AscWriteLramByte(iot, ioh, 1671 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1672 } 1673 n_q_used = sg_queue_cnt + 1; 1674 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1675 } 1676 if (sc->queue_full_or_busy & target_id) { 1677 cur_target_qng = AscReadLramByte(iot, ioh, 1678 ASC_QADR_BEG + scsiq->d2.target_ix); 1679 1680 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1681 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1682 scsi_busy &= ~target_id; 1683 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1684 sc->queue_full_or_busy &= ~target_id; 1685 } 1686 } 1687 if (sc->cur_total_qng >= n_q_used) { 1688 sc->cur_total_qng -= n_q_used; 1689 if (sc->cur_dvc_qng[tid_no] != 0) 1690 sc->cur_dvc_qng[tid_no]--; 1691 } else { 1692 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1693 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1694 panic("AscIsrQDone: Attempting to free more queues than are active"); 1695 } 1696 1697 if ((scsiq->d2.ccb_ptr == 0UL) || ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1698 return (0x11); 1699 } else if (scsiq->q_status == ASC_QS_DONE) { 1700 scsiq->remain_bytes += scsiq->extra_bytes; 1701 1702 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1703 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1704 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1705 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1706 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1707 } 1708 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1709 AscStopChip(iot, ioh); 1710 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1711 DvcDelayNanoSecond(60000); 1712 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1713 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1714 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1715 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1716 } 1717 } 1718 (*asc_isr_callback) (sc, scsiq); 1719 1720 return (1); 1721 } else { 1722 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1723 panic("AscIsrQDone: completed scsiq with unknown status"); 1724 1725 return (0x80); 1726 } 1727 } 1728 return (0); 1729 } 1730 1731 1732 /* 1733 * handle all the conditions that may halt the board 1734 * waiting us to intervene 1735 */ 1736 static void 1737 AscIsrChipHalted(sc) 1738 ASC_SOFTC *sc; 1739 { 1740 bus_space_tag_t iot = sc->sc_iot; 1741 bus_space_handle_t ioh = sc->sc_ioh; 1742 EXT_MSG out_msg; 1743 u_int16_t int_halt_code; 1744 u_int16_t halt_q_addr; 1745 u_int8_t halt_qp; 1746 u_int8_t target_ix; 1747 u_int8_t tag_code; 1748 u_int8_t q_status; 1749 u_int8_t q_cntl; 1750 u_int8_t tid_no; 1751 u_int8_t cur_dvc_qng; 1752 u_int8_t asyn_sdtr; 1753 u_int8_t scsi_status; 1754 u_int8_t sdtr_data; 1755 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1756 ASC_SCSI_BIT_ID_TYPE target_id; 1757 1758 1759 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1760 1761 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1762 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1763 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1764 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1765 tid_no = ASC_TIX_TO_TID(target_ix); 1766 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1767 1768 if (sc->pci_fix_asyn_xfer & target_id) 1769 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1770 else 1771 asyn_sdtr = 0; 1772 1773 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1774 if (sc->pci_fix_asyn_xfer & target_id) { 1775 AscSetChipSDTR(iot, ioh, 0, tid_no); 1776 sc->sdtr_data[tid_no] = 0; 1777 } 1778 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1779 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1780 if (sc->pci_fix_asyn_xfer & target_id) { 1781 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1782 sc->sdtr_data[tid_no] = asyn_sdtr; 1783 } 1784 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1785 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1786 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1787 tid_no, asyn_sdtr); 1788 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1789 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1790 q_cntl |= ASC_QC_REQ_SENSE; 1791 1792 if (sc->init_sdtr & target_id) { 1793 sc->sdtr_done &= ~target_id; 1794 1795 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1796 q_cntl |= ASC_QC_MSG_OUT; 1797 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1798 (sc->max_sdtr_index - 1)], 1799 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1800 } 1801 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1802 1803 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1804 tag_code &= 0xDC; 1805 1806 if ((sc->pci_fix_asyn_xfer & target_id) && 1807 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1808 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1809 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1810 } 1811 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1812 1813 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1814 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1815 1816 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1817 1818 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1819 scsi_busy &= ~target_id; 1820 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1821 1822 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1823 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1824 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1825 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1826 1827 if ((out_msg.msg_type == MS_EXTEND) && 1828 (out_msg.msg_len == MS_SDTR_LEN) && 1829 (out_msg.msg_req == MS_SDTR_CODE)) { 1830 1831 sc->init_sdtr &= ~target_id; 1832 sc->sdtr_done &= ~target_id; 1833 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1834 sc->sdtr_data[tid_no] = asyn_sdtr; 1835 } 1836 q_cntl &= ~ASC_QC_MSG_OUT; 1837 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1838 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1839 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1840 scsi_status = AscReadLramByte(iot, ioh, 1841 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1842 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1843 1844 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1845 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1846 scsi_busy |= target_id; 1847 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1848 sc->queue_full_or_busy |= target_id; 1849 1850 if (scsi_status == SS_QUEUE_FULL) { 1851 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1852 cur_dvc_qng -= 1; 1853 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1854 1855 AscWriteLramByte(iot, ioh, 1856 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1857 1858 #if ASC_QUEUE_FLOW_CONTROL 1859 if ((sc->device[tid_no] != NULL) && 1860 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1861 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1862 } 1863 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1864 } 1865 } 1866 } 1867 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1868 } 1869 return; 1870 } 1871 1872 1873 static int 1874 AscWaitTixISRDone(sc, target_ix) 1875 ASC_SOFTC *sc; 1876 u_int8_t target_ix; 1877 { 1878 u_int8_t cur_req; 1879 u_int8_t tid_no; 1880 int i = 0; 1881 1882 tid_no = ASC_TIX_TO_TID(target_ix); 1883 while (i++ < 10) { 1884 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1885 break; 1886 1887 DvcSleepMilliSecond(1000L); 1888 if (sc->cur_dvc_qng[tid_no] == cur_req) 1889 break; 1890 } 1891 return (1); 1892 } 1893 1894 static int 1895 AscWaitISRDone(sc) 1896 ASC_SOFTC *sc; 1897 { 1898 int tid; 1899 1900 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1901 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1902 1903 return (1); 1904 } 1905 1906 1907 static u_int8_t 1908 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1909 bus_space_tag_t iot; 1910 bus_space_handle_t ioh; 1911 u_int16_t q_addr; 1912 ASC_QDONE_INFO *scsiq; 1913 u_int32_t max_dma_count; 1914 { 1915 u_int16_t _val; 1916 u_int8_t sg_queue_cnt; 1917 1918 DvcGetQinfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, (u_int16_t *) scsiq, 1919 ((sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2)); 1920 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1921 scsiq->q_status = _val; 1922 scsiq->q_no = (_val >> 8); 1923 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1924 scsiq->cntl = _val; 1925 sg_queue_cnt = (_val >> 8); 1926 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 1927 scsiq->sense_len = _val; 1928 scsiq->extra_bytes = (_val >> 8); 1929 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 1930 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 1931 scsiq->remain_bytes &= max_dma_count; 1932 1933 return (sg_queue_cnt); 1934 } 1935 1936 1937 static void 1938 AscToggleIRQAct(iot, ioh) 1939 bus_space_tag_t iot; 1940 bus_space_handle_t ioh; 1941 { 1942 1943 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 1944 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1945 } 1946 1947 1948 static void 1949 AscDisableInterrupt(iot, ioh) 1950 bus_space_tag_t iot; 1951 bus_space_handle_t ioh; 1952 { 1953 u_int16_t cfg; 1954 1955 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1956 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 1957 } 1958 1959 1960 static void 1961 AscEnableInterrupt(iot, ioh) 1962 bus_space_tag_t iot; 1963 bus_space_handle_t ioh; 1964 { 1965 u_int16_t cfg; 1966 1967 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1968 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 1969 } 1970 1971 1972 static u_int8_t 1973 AscGetChipIRQ(iot, ioh, bus_type) 1974 bus_space_tag_t iot; 1975 bus_space_handle_t ioh; 1976 u_int16_t bus_type; 1977 { 1978 u_int16_t cfg_lsw; 1979 u_int8_t chip_irq; 1980 1981 1982 if (bus_type & ASC_IS_EISA) { 1983 /* 1984 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq = 1985 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) || 1986 * (chip_irq > 15)) return (0); return(chip_irq); 1987 */ 1988 } 1989 if ((bus_type & ASC_IS_VL) != 0) { 1990 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1991 chip_irq = (cfg_lsw >> 2) & 0x07; 1992 if ((chip_irq == 0) || 1993 (chip_irq == 4) || 1994 (chip_irq == 7)) { 1995 return (0); 1996 } 1997 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 1998 } 1999 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2000 chip_irq = (cfg_lsw >> 2) & 0x03; 2001 if (chip_irq == 3) 2002 chip_irq += 2; 2003 return (chip_irq + ASC_MIN_IRQ_NO); 2004 } 2005 2006 2007 static u_int8_t 2008 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2009 bus_space_tag_t iot; 2010 bus_space_handle_t ioh; 2011 u_int8_t irq_no; 2012 u_int16_t bus_type; 2013 { 2014 u_int16_t cfg_lsw; 2015 2016 2017 if (bus_type & ASC_IS_VL) { 2018 if (irq_no) { 2019 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2020 irq_no = 0; 2021 else 2022 irq_no -= ASC_MIN_IRQ_NO - 1; 2023 } 2024 2025 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2026 cfg_lsw |= 0x0010; 2027 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2028 AscToggleIRQAct(iot, ioh); 2029 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2030 cfg_lsw |= (irq_no & 0x07) << 2; 2031 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2032 AscToggleIRQAct(iot, ioh); 2033 2034 return (AscGetChipIRQ(iot, ioh, bus_type)); 2035 } 2036 if (bus_type & ASC_IS_ISA) { 2037 if (irq_no == 15) 2038 irq_no -= 2; 2039 irq_no -= ASC_MIN_IRQ_NO; 2040 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2041 cfg_lsw |= (irq_no & 0x03) << 2; 2042 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2043 2044 return (AscGetChipIRQ(iot, ioh, bus_type)); 2045 } 2046 return (0); 2047 } 2048 2049 2050 static void 2051 AscAckInterrupt(iot, ioh) 2052 bus_space_tag_t iot; 2053 bus_space_handle_t ioh; 2054 { 2055 u_int8_t host_flag; 2056 u_int8_t risc_flag; 2057 u_int16_t loop; 2058 2059 2060 loop = 0; 2061 do { 2062 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2063 if (loop++ > 0x7FFF) 2064 break; 2065 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2066 2067 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2068 (~ASC_HOST_FLAG_ACK_INT); 2069 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2070 host_flag | ASC_HOST_FLAG_ACK_INT); 2071 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2072 2073 loop = 0; 2074 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2075 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2076 if (loop++ > 3) 2077 break; 2078 } 2079 2080 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2081 } 2082 2083 2084 static u_int32_t 2085 AscGetMaxDmaCount(bus_type) 2086 u_int16_t bus_type; 2087 { 2088 if (bus_type & ASC_IS_ISA) 2089 return (ASC_MAX_ISA_DMA_COUNT); 2090 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2091 return (ASC_MAX_VL_DMA_COUNT); 2092 return (ASC_MAX_PCI_DMA_COUNT); 2093 } 2094 2095 2096 static u_int16_t 2097 AscGetIsaDmaChannel(iot, ioh) 2098 bus_space_tag_t iot; 2099 bus_space_handle_t ioh; 2100 { 2101 u_int16_t channel; 2102 2103 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2104 if (channel == 0x03) 2105 return (0); 2106 else if (channel == 0x00) 2107 return (7); 2108 return (channel + 4); 2109 } 2110 2111 2112 static u_int16_t 2113 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2114 bus_space_tag_t iot; 2115 bus_space_handle_t ioh; 2116 u_int16_t dma_channel; 2117 { 2118 u_int16_t cfg_lsw; 2119 u_int8_t value; 2120 2121 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2122 if (dma_channel == 7) 2123 value = 0x00; 2124 else 2125 value = dma_channel - 4; 2126 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2127 cfg_lsw |= value; 2128 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2129 return (AscGetIsaDmaChannel(iot, ioh)); 2130 } 2131 return (0); 2132 } 2133 2134 2135 static u_int8_t 2136 AscGetIsaDmaSpeed(iot, ioh) 2137 bus_space_tag_t iot; 2138 bus_space_handle_t ioh; 2139 { 2140 u_int8_t speed_value; 2141 2142 AscSetBank(iot, ioh, 1); 2143 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2144 speed_value &= 0x07; 2145 AscSetBank(iot, ioh, 0); 2146 return (speed_value); 2147 } 2148 2149 2150 static u_int8_t 2151 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2152 bus_space_tag_t iot; 2153 bus_space_handle_t ioh; 2154 u_int8_t speed_value; 2155 { 2156 speed_value &= 0x07; 2157 AscSetBank(iot, ioh, 1); 2158 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2159 AscSetBank(iot, ioh, 0); 2160 return (AscGetIsaDmaSpeed(iot, ioh)); 2161 } 2162 2163 2164 /******************************************************************************/ 2165 /* Messages routines */ 2166 /******************************************************************************/ 2167 2168 2169 static void 2170 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2171 ASC_SOFTC *sc; 2172 u_int16_t halt_q_addr; 2173 u_int8_t q_cntl; 2174 ASC_SCSI_BIT_ID_TYPE target_id; 2175 int tid_no; 2176 u_int8_t asyn_sdtr; 2177 { 2178 bus_space_tag_t iot = sc->sc_iot; 2179 bus_space_handle_t ioh = sc->sc_ioh; 2180 EXT_MSG ext_msg; 2181 u_int8_t sdtr_data; 2182 int sdtr_accept; 2183 2184 2185 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2186 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2187 2188 if (ext_msg.msg_type == MS_EXTEND && 2189 ext_msg.msg_req == MS_SDTR_CODE && 2190 ext_msg.msg_len == MS_SDTR_LEN) { 2191 sdtr_accept = TRUE; 2192 2193 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2194 sdtr_accept = FALSE; 2195 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2196 } 2197 if ((ext_msg.xfer_period < 2198 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2199 (ext_msg.xfer_period > 2200 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2201 sdtr_accept = FALSE; 2202 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2203 } 2204 if (sdtr_accept) { 2205 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2206 ext_msg.req_ack_offset); 2207 if (sdtr_data == 0xFF) { 2208 q_cntl |= ASC_QC_MSG_OUT; 2209 sc->init_sdtr &= ~target_id; 2210 sc->sdtr_done &= ~target_id; 2211 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2212 sc->sdtr_data[tid_no] = asyn_sdtr; 2213 } 2214 } 2215 if (ext_msg.req_ack_offset == 0) { 2216 q_cntl &= ~ASC_QC_MSG_OUT; 2217 sc->init_sdtr &= ~target_id; 2218 sc->sdtr_done &= ~target_id; 2219 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2220 } else { 2221 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2222 q_cntl &= ~ASC_QC_MSG_OUT; 2223 sc->sdtr_done |= target_id; 2224 sc->init_sdtr |= target_id; 2225 sc->pci_fix_asyn_xfer &= ~target_id; 2226 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2227 ext_msg.req_ack_offset); 2228 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2229 sc->sdtr_data[tid_no] = sdtr_data; 2230 } else { 2231 q_cntl |= ASC_QC_MSG_OUT; 2232 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2233 ext_msg.req_ack_offset); 2234 sc->pci_fix_asyn_xfer &= ~target_id; 2235 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2236 ext_msg.req_ack_offset); 2237 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2238 sc->sdtr_data[tid_no] = sdtr_data; 2239 sc->sdtr_done |= target_id; 2240 sc->init_sdtr |= target_id; 2241 } 2242 } 2243 } else if (ext_msg.msg_type == MS_EXTEND && 2244 ext_msg.msg_req == MS_WDTR_CODE && 2245 ext_msg.msg_len == MS_WDTR_LEN) { 2246 ext_msg.wdtr_width = 0; 2247 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2248 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2249 q_cntl |= ASC_QC_MSG_OUT; 2250 } else { 2251 ext_msg.msg_type = M1_MSG_REJECT; 2252 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2253 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2254 q_cntl |= ASC_QC_MSG_OUT; 2255 } 2256 2257 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2258 } 2259 2260 2261 static u_int8_t 2262 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2263 ASC_SOFTC *sc; 2264 u_int8_t sdtr_period; 2265 u_int8_t sdtr_offset; 2266 { 2267 bus_space_tag_t iot = sc->sc_iot; 2268 bus_space_handle_t ioh = sc->sc_ioh; 2269 EXT_MSG sdtr_buf; 2270 u_int8_t sdtr_period_index; 2271 2272 2273 sdtr_buf.msg_type = MS_EXTEND; 2274 sdtr_buf.msg_len = MS_SDTR_LEN; 2275 sdtr_buf.msg_req = MS_SDTR_CODE; 2276 sdtr_buf.xfer_period = sdtr_period; 2277 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2278 sdtr_buf.req_ack_offset = sdtr_offset; 2279 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2280 sc->max_sdtr_index) { 2281 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2282 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2283 return ((sdtr_period_index << 4) | sdtr_offset); 2284 } else { 2285 sdtr_buf.req_ack_offset = 0; 2286 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2287 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2288 return (0); 2289 } 2290 } 2291 2292 2293 /******************************************************************************/ 2294 /* SDTR routines */ 2295 /******************************************************************************/ 2296 2297 2298 static void 2299 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2300 bus_space_tag_t iot; 2301 bus_space_handle_t ioh; 2302 u_int8_t sdtr_data; 2303 u_int8_t tid_no; 2304 { 2305 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2306 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2307 } 2308 2309 2310 static u_int8_t 2311 AscCalSDTRData(sc, sdtr_period, syn_offset) 2312 ASC_SOFTC *sc; 2313 u_int8_t sdtr_period; 2314 u_int8_t syn_offset; 2315 { 2316 u_int8_t byte; 2317 u_int8_t sdtr_period_ix; 2318 2319 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2320 if (sdtr_period_ix > sc->max_sdtr_index) 2321 return (0xFF); 2322 2323 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2324 return (byte); 2325 } 2326 2327 2328 static u_int8_t 2329 AscGetSynPeriodIndex(sc, syn_time) 2330 ASC_SOFTC *sc; 2331 u_int8_t syn_time; 2332 { 2333 u_int8_t *period_table; 2334 int max_index; 2335 int min_index; 2336 int i; 2337 2338 period_table = sc->sdtr_period_tbl; 2339 max_index = sc->max_sdtr_index; 2340 min_index = sc->host_init_sdtr_index; 2341 if ((syn_time <= period_table[max_index])) { 2342 for (i = min_index; i < (max_index - 1); i++) { 2343 if (syn_time <= period_table[i]) 2344 return (i); 2345 } 2346 2347 return (max_index); 2348 } else 2349 return (max_index + 1); 2350 } 2351 2352 2353 /******************************************************************************/ 2354 /* Queue routines */ 2355 /******************************************************************************/ 2356 2357 /* 2358 * Send a command to the board 2359 */ 2360 int 2361 AscExeScsiQueue(sc, scsiq) 2362 ASC_SOFTC *sc; 2363 ASC_SCSI_Q *scsiq; 2364 { 2365 bus_space_tag_t iot = sc->sc_iot; 2366 bus_space_handle_t ioh = sc->sc_ioh; 2367 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2368 int retval; 2369 int n_q_required; 2370 int disable_syn_offset_one_fix; 2371 int i; 2372 u_int32_t addr; 2373 u_int16_t sg_entry_cnt = 0; 2374 u_int16_t sg_entry_cnt_minus_one = 0; 2375 u_int8_t target_ix; 2376 u_int8_t tid_no; 2377 u_int8_t sdtr_data; 2378 u_int8_t extra_bytes; 2379 u_int8_t scsi_cmd; 2380 u_int32_t data_cnt; 2381 2382 2383 scsiq->q1.q_no = 0; 2384 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2385 scsiq->q1.extra_bytes = 0; 2386 2387 retval = ASC_BUSY; 2388 target_ix = scsiq->q2.target_ix; 2389 tid_no = ASC_TIX_TO_TID(target_ix); 2390 n_q_required = 1; 2391 2392 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2393 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2394 sc->sdtr_done &= ~scsiq->q1.target_id; 2395 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2396 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2397 (sc->max_sdtr_index - 1)], 2398 sdtr_data & ASC_SYN_MAX_OFFSET); 2399 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2400 } 2401 /* 2402 * if there is just one segment into S/G list then 2403 * map it as it was a single request, filling 2404 * data_addr and data_cnt of ASC_SCSIQ structure. 2405 */ 2406 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2407 sg_entry_cnt = sg_head->entry_cnt; 2408 2409 if (sg_entry_cnt < 1) 2410 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2411 sg_entry_cnt); 2412 2413 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2414 panic("AscExeScsiQueue: Queue with too many segs."); 2415 2416 if (sg_entry_cnt == 1) { 2417 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2418 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2419 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2420 } 2421 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2422 } 2423 scsi_cmd = scsiq->cdbptr[0]; 2424 disable_syn_offset_one_fix = FALSE; 2425 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2426 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2427 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2428 data_cnt = 0; 2429 for (i = 0; i < sg_entry_cnt; i++) 2430 data_cnt += sg_head->sg_list[i].bytes; 2431 } else { 2432 data_cnt = scsiq->q1.data_cnt; 2433 } 2434 2435 if (data_cnt != 0ul) { 2436 if (data_cnt < 512ul) { 2437 disable_syn_offset_one_fix = TRUE; 2438 } else { 2439 if (scsi_cmd == SCSICMD_Inquiry || 2440 scsi_cmd == SCSICMD_RequestSense || 2441 scsi_cmd == SCSICMD_ReadCapacity || 2442 scsi_cmd == SCSICMD_ReadTOC || 2443 scsi_cmd == SCSICMD_ModeSelect6 || 2444 scsi_cmd == SCSICMD_ModeSense6 || 2445 scsi_cmd == SCSICMD_ModeSelect10 || 2446 scsi_cmd == SCSICMD_ModeSense10) { 2447 disable_syn_offset_one_fix = TRUE; 2448 } 2449 } 2450 } 2451 } 2452 if (disable_syn_offset_one_fix) { 2453 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2454 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2455 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2456 } else { 2457 scsiq->q2.tag_code &= 0x23; 2458 } 2459 2460 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2461 if (sc->bug_fix_cntl) { 2462 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2463 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2464 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2465 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2466 extra_bytes = addr & 0x0003; 2467 if ((extra_bytes != 0) && 2468 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2469 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2470 scsiq->q1.extra_bytes = extra_bytes; 2471 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2472 extra_bytes; 2473 } 2474 } 2475 } 2476 } 2477 sg_head->entry_to_copy = sg_head->entry_cnt; 2478 n_q_required = AscSgListToQueue(sg_entry_cnt); 2479 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2480 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2481 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2482 } 2483 } else { 2484 if (sc->bug_fix_cntl) { 2485 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2486 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2487 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2488 extra_bytes = addr & 0x0003; 2489 if ((extra_bytes != 0) && 2490 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2491 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2492 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2493 scsiq->q1.data_cnt -= extra_bytes; 2494 scsiq->q1.extra_bytes = extra_bytes; 2495 } 2496 } 2497 } 2498 } 2499 } 2500 n_q_required = 1; 2501 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2502 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2503 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2504 } 2505 } 2506 2507 return (retval); 2508 } 2509 2510 2511 static int 2512 AscSendScsiQueue(sc, scsiq, n_q_required) 2513 ASC_SOFTC *sc; 2514 ASC_SCSI_Q *scsiq; 2515 u_int8_t n_q_required; 2516 { 2517 bus_space_tag_t iot = sc->sc_iot; 2518 bus_space_handle_t ioh = sc->sc_ioh; 2519 u_int8_t free_q_head; 2520 u_int8_t next_qp; 2521 u_int8_t tid_no; 2522 u_int8_t target_ix; 2523 int retval; 2524 2525 2526 target_ix = scsiq->q2.target_ix; 2527 tid_no = ASC_TIX_TO_TID(target_ix); 2528 retval = ASC_BUSY; 2529 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2530 2531 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2532 != ASC_QLINK_END) { 2533 if (n_q_required > 1) { 2534 sc->last_q_shortage = 0; 2535 scsiq->sg_head->queue_cnt = n_q_required - 1; 2536 } 2537 scsiq->q1.q_no = free_q_head; 2538 2539 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2540 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2541 sc->cur_total_qng += n_q_required; 2542 sc->cur_dvc_qng[tid_no]++; 2543 } 2544 } 2545 return (retval); 2546 } 2547 2548 2549 static int 2550 AscPutReadySgListQueue(sc, scsiq, q_no) 2551 ASC_SOFTC *sc; 2552 ASC_SCSI_Q *scsiq; 2553 u_int8_t q_no; 2554 { 2555 bus_space_tag_t iot = sc->sc_iot; 2556 bus_space_handle_t ioh = sc->sc_ioh; 2557 int retval; 2558 int i; 2559 ASC_SG_HEAD *sg_head; 2560 ASC_SG_LIST_Q scsi_sg_q; 2561 u_int32_t saved_data_addr; 2562 u_int32_t saved_data_cnt; 2563 u_int16_t sg_list_dwords; 2564 u_int16_t sg_index; 2565 u_int16_t sg_entry_cnt; 2566 u_int16_t q_addr; 2567 u_int8_t next_qp; 2568 2569 2570 saved_data_addr = scsiq->q1.data_addr; 2571 saved_data_cnt = scsiq->q1.data_cnt; 2572 2573 if ((sg_head = scsiq->sg_head) != 0) { 2574 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2575 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2576 sg_entry_cnt = sg_head->entry_cnt - 1; 2577 if (sg_entry_cnt != 0) { 2578 q_addr = ASC_QNO_TO_QADDR(q_no); 2579 sg_index = 1; 2580 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2581 scsi_sg_q.sg_head_qp = q_no; 2582 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2583 2584 for (i = 0; i < sg_head->queue_cnt; i++) { 2585 scsi_sg_q.seq_no = i + 1; 2586 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2587 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2588 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2589 if (i == 0) { 2590 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2591 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2592 } else { 2593 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2594 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2595 } 2596 } else { 2597 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2598 sg_list_dwords = sg_entry_cnt << 1; 2599 if (i == 0) { 2600 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2601 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2602 } else { 2603 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2604 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2605 } 2606 2607 sg_entry_cnt = 0; 2608 } 2609 2610 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2611 scsi_sg_q.q_no = next_qp; 2612 q_addr = ASC_QNO_TO_QADDR(next_qp); 2613 2614 /* 2615 * Tell the board how many entries are in the S/G list 2616 */ 2617 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2618 (u_int16_t *) & scsi_sg_q, sizeof(ASC_SG_LIST_Q) >> 1); 2619 /* 2620 * Tell the board the addresses of the S/G list segments 2621 */ 2622 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2623 (u_int32_t *) & sg_head->sg_list[sg_index], sg_list_dwords); 2624 sg_index += ASC_SG_LIST_PER_Q; 2625 } 2626 } 2627 } 2628 retval = AscPutReadyQueue(sc, scsiq, q_no); 2629 scsiq->q1.data_addr = saved_data_addr; 2630 scsiq->q1.data_cnt = saved_data_cnt; 2631 return (retval); 2632 } 2633 2634 2635 static int 2636 AscPutReadyQueue(sc, scsiq, q_no) 2637 ASC_SOFTC *sc; 2638 ASC_SCSI_Q *scsiq; 2639 u_int8_t q_no; 2640 { 2641 bus_space_tag_t iot = sc->sc_iot; 2642 bus_space_handle_t ioh = sc->sc_ioh; 2643 u_int16_t q_addr; 2644 u_int8_t tid_no; 2645 u_int8_t sdtr_data; 2646 u_int8_t syn_period_ix; 2647 u_int8_t syn_offset; 2648 2649 2650 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2651 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2652 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2653 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2654 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2655 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2656 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2657 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2658 } 2659 q_addr = ASC_QNO_TO_QADDR(q_no); 2660 2661 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2662 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2663 } 2664 scsiq->q1.status = ASC_QS_FREE; 2665 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2666 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2667 2668 DvcPutScsiQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, 2669 (u_int16_t *) & scsiq->q1.cntl, 2670 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 2671 2672 /* 2673 * Let's start the command 2674 */ 2675 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2676 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2677 2678 return (ASC_NOERROR); 2679 } 2680 2681 2682 static int 2683 AscSgListToQueue(sg_list) 2684 int sg_list; 2685 { 2686 int n_sg_list_qs; 2687 2688 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2689 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2690 n_sg_list_qs++; 2691 2692 return (n_sg_list_qs + 1); 2693 } 2694 2695 2696 static u_int 2697 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2698 ASC_SOFTC *sc; 2699 u_int8_t target_ix; 2700 u_int8_t n_qs; 2701 { 2702 u_int cur_used_qs; 2703 u_int cur_free_qs; 2704 2705 2706 if (n_qs == 1) { 2707 cur_used_qs = sc->cur_total_qng + 2708 sc->last_q_shortage + 2709 ASC_MIN_FREE_Q; 2710 } else { 2711 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2712 } 2713 2714 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2715 cur_free_qs = sc->max_total_qng - cur_used_qs; 2716 return (cur_free_qs); 2717 } 2718 if (n_qs > 1) 2719 if ((n_qs > sc->last_q_shortage) && 2720 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2721 sc->last_q_shortage = n_qs; 2722 } 2723 return (0); 2724 } 2725 2726 2727 static u_int8_t 2728 AscAllocFreeQueue(iot, ioh, free_q_head) 2729 bus_space_tag_t iot; 2730 bus_space_handle_t ioh; 2731 u_int8_t free_q_head; 2732 { 2733 u_int16_t q_addr; 2734 u_int8_t next_qp; 2735 u_int8_t q_status; 2736 2737 2738 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2739 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2740 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2741 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2742 return (next_qp); 2743 2744 return (ASC_QLINK_END); 2745 } 2746 2747 2748 static u_int8_t 2749 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2750 bus_space_tag_t iot; 2751 bus_space_handle_t ioh; 2752 u_int8_t free_q_head; 2753 u_int8_t n_free_q; 2754 { 2755 u_int8_t i; 2756 2757 for (i = 0; i < n_free_q; i++) { 2758 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2759 if (free_q_head == ASC_QLINK_END) 2760 break; 2761 } 2762 2763 return (free_q_head); 2764 } 2765 2766 2767 static int 2768 AscStopQueueExe(iot, ioh) 2769 bus_space_tag_t iot; 2770 bus_space_handle_t ioh; 2771 { 2772 int count = 0; 2773 2774 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2775 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2776 do { 2777 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2778 ASC_STOP_ACK_RISC_STOP) 2779 return (1); 2780 2781 DvcSleepMilliSecond(100); 2782 } while (count++ < 20); 2783 } 2784 return (0); 2785 } 2786 2787 2788 static void 2789 AscStartQueueExe(iot, ioh) 2790 bus_space_tag_t iot; 2791 bus_space_handle_t ioh; 2792 { 2793 2794 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2795 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2796 } 2797 2798 2799 static void 2800 AscCleanUpBusyQueue(iot, ioh) 2801 bus_space_tag_t iot; 2802 bus_space_handle_t ioh; 2803 { 2804 int count = 0; 2805 u_int8_t stop_code; 2806 2807 2808 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2809 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2810 do { 2811 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2812 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2813 break; 2814 2815 DvcSleepMilliSecond(100); 2816 } while (count++ < 20); 2817 } 2818 } 2819 2820 2821 static int 2822 _AscWaitQDone(iot, ioh, scsiq) 2823 bus_space_tag_t iot; 2824 bus_space_handle_t ioh; 2825 ASC_SCSI_Q *scsiq; 2826 { 2827 u_int16_t q_addr; 2828 u_int8_t q_status; 2829 int count = 0; 2830 2831 while (scsiq->q1.q_no == 0); 2832 2833 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2834 do { 2835 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2836 DvcSleepMilliSecond(100L); 2837 if (count++ > 30) 2838 return (0); 2839 2840 } while ((q_status & ASC_QS_READY) != 0); 2841 2842 return (1); 2843 } 2844 2845 2846 static int 2847 AscCleanUpDiscQueue(iot, ioh) 2848 bus_space_tag_t iot; 2849 bus_space_handle_t ioh; 2850 { 2851 int count; 2852 u_int8_t stop_code; 2853 2854 count = 0; 2855 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2856 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 2857 do { 2858 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2859 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 2860 break; 2861 2862 DvcSleepMilliSecond(100); 2863 } while (count++ < 20); 2864 } 2865 return (1); 2866 } 2867 2868 2869 /******************************************************************************/ 2870 /* Abort and Reset CCB routines */ 2871 /******************************************************************************/ 2872 2873 2874 int 2875 AscAbortCCB(sc, ccb) 2876 ASC_SOFTC *sc; 2877 u_int32_t ccb; 2878 { 2879 bus_space_tag_t iot = sc->sc_iot; 2880 bus_space_handle_t ioh = sc->sc_ioh; 2881 int retval; 2882 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2883 2884 2885 retval = -1; 2886 saved_unit_not_ready = sc->unit_not_ready; 2887 sc->unit_not_ready = 0xFF; 2888 AscWaitISRDone(sc); 2889 if (AscStopQueueExe(iot, ioh) == 1) { 2890 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 2891 retval = 1; 2892 AscCleanUpBusyQueue(iot, ioh); 2893 AscStartQueueExe(iot, ioh); 2894 } else { 2895 retval = 0; 2896 AscStartQueueExe(iot, ioh); 2897 } 2898 } 2899 sc->unit_not_ready = saved_unit_not_ready; 2900 2901 return (retval); 2902 } 2903 2904 2905 static int 2906 AscRiscHaltedAbortCCB(sc, ccb) 2907 ASC_SOFTC *sc; 2908 u_int32_t ccb; 2909 { 2910 bus_space_tag_t iot = sc->sc_iot; 2911 bus_space_handle_t ioh = sc->sc_ioh; 2912 u_int16_t q_addr; 2913 u_int8_t q_no; 2914 ASC_QDONE_INFO scsiq_buf; 2915 ASC_QDONE_INFO *scsiq; 2916 ASC_ISR_CALLBACK asc_isr_callback; 2917 int last_int_level; 2918 2919 2920 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2921 last_int_level = DvcEnterCritical(); 2922 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2923 2924 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2925 q_addr = ASC_QNO_TO_QADDR(q_no); 2926 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 2927 q_addr + ASC_SCSIQ_D_CCBPTR); 2928 if (scsiq->d2.ccb_ptr == ccb) { 2929 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2930 if (((scsiq->q_status & ASC_QS_READY) != 0) 2931 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 2932 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2933 scsiq->q_status |= ASC_QS_ABORTED; 2934 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2935 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2936 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2937 scsiq->q_status); 2938 (*asc_isr_callback) (sc, scsiq); 2939 return (1); 2940 } 2941 } 2942 } 2943 2944 DvcLeaveCritical(last_int_level); 2945 return (0); 2946 } 2947 2948 2949 static int 2950 AscRiscHaltedAbortTIX(sc, target_ix) 2951 ASC_SOFTC *sc; 2952 u_int8_t target_ix; 2953 { 2954 bus_space_tag_t iot = sc->sc_iot; 2955 bus_space_handle_t ioh = sc->sc_ioh; 2956 u_int16_t q_addr; 2957 u_int8_t q_no; 2958 ASC_QDONE_INFO scsiq_buf; 2959 ASC_QDONE_INFO *scsiq; 2960 ASC_ISR_CALLBACK asc_isr_callback; 2961 int last_int_level; 2962 2963 2964 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2965 last_int_level = DvcEnterCritical(); 2966 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2967 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2968 q_addr = ASC_QNO_TO_QADDR(q_no); 2969 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2970 if (((scsiq->q_status & ASC_QS_READY) != 0) && 2971 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 2972 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2973 if (scsiq->d2.target_ix == target_ix) { 2974 scsiq->q_status |= ASC_QS_ABORTED; 2975 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2976 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2977 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2978 scsiq->q_status); 2979 (*asc_isr_callback) (sc, scsiq); 2980 } 2981 } 2982 } 2983 DvcLeaveCritical(last_int_level); 2984 return (1); 2985 } 2986 2987 2988 /* 2989 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 2990 * so we cannot use this function with the actual NetBSD SCSI layer 2991 * because at boot time interrupts are disabled. 2992 */ 2993 int 2994 AscResetDevice(sc, target_ix) 2995 ASC_SOFTC *sc; 2996 u_char target_ix; 2997 { 2998 bus_space_tag_t iot = sc->sc_iot; 2999 bus_space_handle_t ioh = sc->sc_ioh; 3000 int retval; 3001 u_int8_t tid_no; 3002 ASC_SCSI_BIT_ID_TYPE target_id; 3003 int i; 3004 ASC_SCSI_REQ_Q scsiq_buf; 3005 ASC_SCSI_REQ_Q *scsiq; 3006 u_int8_t *buf; 3007 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3008 3009 3010 tid_no = ASC_TIX_TO_TID(target_ix); 3011 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3012 saved_unit_not_ready = sc->unit_not_ready; 3013 sc->unit_not_ready = target_id; 3014 retval = ASC_ERROR; 3015 3016 AscWaitTixISRDone(sc, target_ix); 3017 3018 if (AscStopQueueExe(iot, ioh) == 1) { 3019 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3020 AscCleanUpBusyQueue(iot, ioh); 3021 AscStartQueueExe(iot, ioh); 3022 AscWaitTixISRDone(sc, target_ix); 3023 retval = ASC_NOERROR; 3024 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3025 buf = (u_char *) & scsiq_buf; 3026 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3027 *buf++ = 0x00; 3028 scsiq->q1.status = (u_char) ASC_QS_READY; 3029 scsiq->q2.cdb_len = 6; 3030 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3031 scsiq->q1.target_id = target_id; 3032 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3033 scsiq->cdbptr = (u_int8_t *) scsiq->cdb; 3034 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3035 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3036 sc->unit_not_ready &= ~target_id; 3037 sc->sdtr_done |= target_id; 3038 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3039 sc->unit_not_ready = target_id; 3040 DvcSleepMilliSecond(1000); 3041 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3042 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3043 AscCleanUpDiscQueue(iot, ioh); 3044 AscStartQueueExe(iot, ioh); 3045 if (sc->pci_fix_asyn_xfer & target_id) 3046 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3047 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3048 AscWaitTixISRDone(sc, target_ix); 3049 } 3050 } else 3051 retval = ASC_BUSY; 3052 sc->sdtr_done &= ~target_id; 3053 } else { 3054 retval = ASC_ERROR; 3055 AscStartQueueExe(iot, ioh); 3056 } 3057 } 3058 sc->unit_not_ready = saved_unit_not_ready; 3059 return (retval); 3060 } 3061 3062 3063 int 3064 AscResetBus(sc) 3065 ASC_SOFTC *sc; 3066 { 3067 bus_space_tag_t iot = sc->sc_iot; 3068 bus_space_handle_t ioh = sc->sc_ioh; 3069 int retval; 3070 int i; 3071 3072 3073 sc->unit_not_ready = 0xFF; 3074 retval = ASC_NOERROR; 3075 3076 AscWaitISRDone(sc); 3077 AscStopQueueExe(iot, ioh); 3078 sc->sdtr_done = 0; 3079 AscResetChipAndScsiBus(iot, ioh); 3080 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3081 AscReInitLram(sc); 3082 for (i = 0; i <= ASC_MAX_TID; i++) { 3083 sc->cur_dvc_qng[i] = 0; 3084 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3085 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3086 } 3087 3088 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3089 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3090 retval = ASC_ERROR; 3091 3092 if (AscStartChip(iot, ioh) == 0) 3093 retval = ASC_ERROR; 3094 3095 AscStartQueueExe(iot, ioh); 3096 sc->unit_not_ready = 0; 3097 sc->queue_full_or_busy = 0; 3098 return (retval); 3099 } 3100 3101 3102 /******************************************************************************/ 3103 /* Error Handling routines */ 3104 /******************************************************************************/ 3105 3106 3107 static int 3108 AscSetLibErrorCode(sc, err_code) 3109 ASC_SOFTC *sc; 3110 u_int16_t err_code; 3111 { 3112 /* 3113 * if(sc->err_code == 0) { sc->err_code = err_code; 3114 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3115 err_code); 3116 /* 3117 * } 3118 */ 3119 return (err_code); 3120 } 3121 3122 3123 /******************************************************************************/ 3124 /* Handle bugged borads routines */ 3125 /******************************************************************************/ 3126 3127 3128 void 3129 AscInquiryHandling(sc, tid_no, inq) 3130 ASC_SOFTC *sc; 3131 u_int8_t tid_no; 3132 ASC_SCSI_INQUIRY *inq; 3133 { 3134 bus_space_tag_t iot = sc->sc_iot; 3135 bus_space_handle_t ioh = sc->sc_ioh; 3136 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3137 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3138 3139 3140 orig_init_sdtr = sc->init_sdtr; 3141 orig_use_tagged_qng = sc->use_tagged_qng; 3142 3143 sc->init_sdtr &= ~tid_bit; 3144 sc->can_tagged_qng &= ~tid_bit; 3145 sc->use_tagged_qng &= ~tid_bit; 3146 3147 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3148 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3149 sc->init_sdtr |= tid_bit; 3150 3151 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3152 if (AscTagQueuingSafe(inq)) { 3153 sc->use_tagged_qng |= tid_bit; 3154 sc->can_tagged_qng |= tid_bit; 3155 } 3156 } 3157 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3158 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3159 sc->disc_enable); 3160 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3161 sc->use_tagged_qng); 3162 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3163 sc->can_tagged_qng); 3164 3165 sc->max_dvc_qng[tid_no] = 3166 sc->max_tag_qng[tid_no]; 3167 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3168 sc->max_dvc_qng[tid_no]); 3169 } 3170 if (orig_init_sdtr != sc->init_sdtr) 3171 AscAsyncFix(sc, tid_no, inq); 3172 } 3173 3174 3175 static int 3176 AscTagQueuingSafe(inq) 3177 ASC_SCSI_INQUIRY *inq; 3178 { 3179 if ((inq->add_len >= 32) && 3180 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3181 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3182 return 0; 3183 } 3184 return 1; 3185 } 3186 3187 3188 static void 3189 AscAsyncFix(sc, tid_no, inq) 3190 ASC_SOFTC *sc; 3191 u_int8_t tid_no; 3192 ASC_SCSI_INQUIRY *inq; 3193 { 3194 u_int8_t dvc_type; 3195 ASC_SCSI_BIT_ID_TYPE tid_bits; 3196 3197 3198 dvc_type = inq->byte0.peri_dvc_type; 3199 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3200 3201 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3202 if (!(sc->init_sdtr & tid_bits)) { 3203 if ((dvc_type == SCSI_TYPE_CDROM) && 3204 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3205 sc->pci_fix_asyn_xfer_always |= tid_bits; 3206 } 3207 sc->pci_fix_asyn_xfer |= tid_bits; 3208 if ((dvc_type == SCSI_TYPE_PROC) || 3209 (dvc_type == SCSI_TYPE_SCANNER)) { 3210 sc->pci_fix_asyn_xfer &= ~tid_bits; 3211 } 3212 if ((dvc_type == SCSI_TYPE_SASD) && 3213 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3214 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3215 sc->pci_fix_asyn_xfer &= ~tid_bits; 3216 } 3217 if ((dvc_type == SCSI_TYPE_SASD) && 3218 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3219 sc->pci_fix_asyn_xfer &= ~tid_bits; 3220 } 3221 if ((dvc_type == SCSI_TYPE_CDROM) && 3222 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3223 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3224 sc->pci_fix_asyn_xfer &= ~tid_bits; 3225 } 3226 if ((dvc_type == SCSI_TYPE_CDROM) && 3227 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3228 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3229 sc->pci_fix_asyn_xfer &= ~tid_bits; 3230 } 3231 if (sc->pci_fix_asyn_xfer & tid_bits) { 3232 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3233 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3234 } 3235 } 3236 } 3237 } 3238 3239 3240 /******************************************************************************/ 3241 /* Miscellaneous routines */ 3242 /******************************************************************************/ 3243 3244 3245 static int 3246 AscCompareString(str1, str2, len) 3247 u_char *str1; 3248 u_char *str2; 3249 int len; 3250 { 3251 int i; 3252 int diff; 3253 3254 for (i = 0; i < len; i++) { 3255 diff = (int) (str1[i] - str2[i]); 3256 if (diff != 0) 3257 return (diff); 3258 } 3259 3260 return (0); 3261 } 3262 3263 3264 /******************************************************************************/ 3265 /* Device oriented routines */ 3266 /******************************************************************************/ 3267 3268 3269 static int 3270 DvcEnterCritical(void) 3271 { 3272 int s; 3273 3274 s = splbio(); 3275 return (s); 3276 } 3277 3278 3279 static void 3280 DvcLeaveCritical(s) 3281 int s; 3282 { 3283 3284 splx(s); 3285 } 3286 3287 3288 static void 3289 DvcSleepMilliSecond(n) 3290 u_int32_t n; 3291 { 3292 3293 DELAY(n * 1000); 3294 } 3295 3296 #ifdef UNUSED 3297 static void 3298 DvcDelayMicroSecond(n) 3299 u_int32_t n; 3300 { 3301 3302 DELAY(n); 3303 } 3304 #endif 3305 3306 static void 3307 DvcDelayNanoSecond(n) 3308 u_int32_t n; 3309 { 3310 3311 DELAY((n + 999) / 1000); 3312 } 3313 3314 3315 static u_int32_t 3316 DvcGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 3317 ASC_SOFTC *sc; 3318 u_int8_t *buf_addr; 3319 u_int32_t buf_len; 3320 ASC_SG_HEAD *asc_sg_head_ptr; 3321 { 3322 u_int32_t buf_size; 3323 3324 buf_size = buf_len; 3325 asc_sg_head_ptr->entry_cnt = 1; 3326 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 3327 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 3328 3329 return (buf_size); 3330 } 3331 3332 3333 static void 3334 DvcPutScsiQ(iot, ioh, s_addr, outbuf, words) 3335 bus_space_tag_t iot; 3336 bus_space_handle_t ioh; 3337 u_int16_t s_addr; 3338 u_int16_t *outbuf; 3339 int words; 3340 { 3341 int i; 3342 3343 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 3344 for (i = 0; i < words; i++, outbuf++) { 3345 if (i == 2 || i == 10) 3346 continue; 3347 3348 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *outbuf); 3349 } 3350 } 3351 3352 3353 static void 3354 DvcGetQinfo(iot, ioh, s_addr, inbuf, words) 3355 bus_space_tag_t iot; 3356 bus_space_handle_t ioh; 3357 u_int16_t s_addr; 3358 u_int16_t *inbuf; 3359 int words; 3360 { 3361 int i; 3362 3363 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 3364 for (i = 0; i < words; i++, inbuf++) { 3365 if (i == 5) 3366 continue; 3367 3368 *inbuf = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 3369 } 3370 } 3371
Indexes created Thu Oct 02 10:09:58 GMT 2025