advlib.c revision 1.5
1 /* $NetBSD: advlib.c,v 1.5 1998/10/13 22:57:26 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/scsipi/scsi_all.h> 67 #include <dev/scsipi/scsipi_all.h> 68 #include <dev/scsipi/scsiconf.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_param.h> 72 #include <vm/pmap.h> 73 74 #include <dev/ic/adv.h> 75 #include <dev/ic/advlib.h> 76 #include <dev/ic/advmcode.h> 77 78 79 /******************************************************************************/ 80 /* Static functions */ 81 /******************************************************************************/ 82 83 /* Initializzation routines */ 84 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 85 u_int16_t, u_int16_t *, u_int16_t)); 86 static void AscInitLram __P((ASC_SOFTC *)); 87 static void AscInitQLinkVar __P((ASC_SOFTC *)); 88 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 89 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 90 91 /* Chip register routines */ 92 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 93 94 /* RISC Chip routines */ 95 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 96 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 97 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 98 u_int8_t)); 99 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 100 static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t, 101 u_int16_t)); 102 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 103 u_int8_t, u_int8_t)); 104 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 105 u_int8_t, u_int8_t)); 106 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 107 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 108 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 109 110 /* Lram routines */ 111 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 112 u_int16_t)); 113 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t, u_int8_t)); 115 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t)); 117 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t, u_int16_t)); 119 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t)); 121 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t, u_int32_t)); 123 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int16_t, int)); 125 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t *, int)); 127 static void AscMCodeCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int)); 129 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int16_t *, int)); 131 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, u_int32_t *, int)); 133 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 134 u_int16_t, int)); 135 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 136 137 /* MicroCode routines */ 138 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 139 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 140 141 /* EEProm routines */ 142 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 143 u_int8_t)); 144 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 145 u_int16_t)); 146 static void AscWaitEEPRead __P((void)); 147 static void AscWaitEEPWrite __P((void)); 148 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 149 u_int8_t)); 150 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 151 u_int8_t, u_int16_t)); 152 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 153 ASCEEP_CONFIG *, u_int16_t)); 154 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 155 ASCEEP_CONFIG *, u_int16_t)); 156 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 157 ASCEEP_CONFIG *, u_int16_t)); 158 159 /* Interrupt routines */ 160 static void AscIsrChipHalted __P((ASC_SOFTC *)); 161 static int AscIsrQDone __P((ASC_SOFTC *)); 162 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 163 static int AscWaitISRDone __P((ASC_SOFTC *)); 164 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 165 u_int16_t, ASC_QDONE_INFO *, 166 u_int32_t)); 167 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 168 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 169 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 170 static u_int8_t AscGetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 171 u_int16_t)); 172 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 173 u_int8_t, u_int16_t)); 174 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 175 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 176 static u_int16_t AscGetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t)); 177 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 178 u_int16_t)); 179 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 180 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 181 u_int8_t)); 182 183 /* Messages routines */ 184 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 185 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 186 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 187 188 /* SDTR routines */ 189 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 190 u_int8_t, u_int8_t)); 191 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 192 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 193 194 /* Queue routines */ 195 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 196 static int AscSgListToQueue __P((int)); 197 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 198 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 199 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 200 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 201 u_int8_t)); 202 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 203 bus_space_handle_t, 204 u_int8_t, u_int8_t)); 205 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 206 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 207 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 208 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 209 ASC_SCSI_Q *)); 210 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 211 212 /* Abort and Reset CCB routines */ 213 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, u_int32_t)); 214 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 215 216 /* Error Handling routines */ 217 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 218 219 /* Handle bugged borads routines */ 220 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 221 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 222 223 /* Miscellaneous routines */ 224 static int AscCompareString __P((u_char *, u_char *, int)); 225 226 /* Device oriented routines */ 227 static int DvcEnterCritical __P((void)); 228 static void DvcLeaveCritical __P((int)); 229 static void DvcSleepMilliSecond __P((u_int32_t)); 230 //static void DvcDelayMicroSecond __P((u_int32_t)); 231 static void DvcDelayNanoSecond __P((u_int32_t)); 232 static u_int32_t DvcGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 233 ASC_SG_HEAD *)); 234 static void DvcPutScsiQ __P((bus_space_tag_t, bus_space_handle_t, 235 u_int16_t, u_int16_t *, int)); 236 static void DvcGetQinfo __P((bus_space_tag_t, bus_space_handle_t, 237 u_int16_t, u_int16_t *, int words)); 238 239 240 /******************************************************************************/ 241 /* Initializzation routines */ 242 /******************************************************************************/ 243 244 /* 245 * This function perform the following steps: 246 * - initialize ASC_SOFTC structure with defaults values. 247 * - inquire board registers to know what kind of board it is. 248 * - keep track of bugged borads. 249 */ 250 void 251 AscInitASC_SOFTC(sc) 252 ASC_SOFTC *sc; 253 { 254 bus_space_tag_t iot = sc->sc_iot; 255 bus_space_handle_t ioh = sc->sc_ioh; 256 int i; 257 u_int8_t chip_version; 258 259 260 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 261 ASC_SET_CHIP_STATUS(iot, ioh, 0); 262 263 sc->bug_fix_cntl = 0; 264 sc->pci_fix_asyn_xfer = 0; 265 sc->pci_fix_asyn_xfer_always = 0; 266 sc->sdtr_done = 0; 267 sc->cur_total_qng = 0; 268 sc->last_q_shortage = 0; 269 sc->use_tagged_qng = 0; 270 sc->unit_not_ready = 0; 271 sc->queue_full_or_busy = 0; 272 sc->host_init_sdtr_index = 0; 273 sc->can_tagged_qng = 0; 274 sc->cmd_qng_enabled = 0; 275 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 276 sc->init_sdtr = 0; 277 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 278 sc->scsi_reset_wait = 3; 279 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 280 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 281 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 282 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 283 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 284 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 285 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 286 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 287 sc->chip_version = chip_version; 288 if ((sc->bus_type & ASC_IS_PCI) && 289 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 290 sc->bus_type = ASC_IS_PCI_ULTRA; 291 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 292 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 293 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 294 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 295 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 296 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 297 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 298 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 299 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 300 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 301 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 302 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 303 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 304 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 305 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 306 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 307 sc->max_sdtr_index = 15; 308 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 309 ASC_SET_EXTRA_CONTROL(iot, ioh, 310 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 311 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 312 ASC_SET_EXTRA_CONTROL(iot, ioh, 313 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 314 } else { 315 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 316 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 317 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 318 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 319 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 320 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 321 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 322 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 323 sc->max_sdtr_index = 7; 324 } 325 326 if (sc->bus_type == ASC_IS_PCI) 327 ASC_SET_EXTRA_CONTROL(iot, ioh, 328 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 329 330 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 331 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 332 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 333 sc->bus_type = ASC_IS_ISAPNP; 334 } 335 if ((sc->bus_type & ASC_IS_ISA) != 0) 336 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 337 338 for (i = 0; i <= ASC_MAX_TID; i++) { 339 sc->cur_dvc_qng[i] = 0; 340 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 341 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 342 } 343 } 344 345 346 /* 347 * This function initialize some ASC_SOFTC fields with values read from 348 * on-board EEProm. 349 */ 350 u_int16_t 351 AscInitFromEEP(sc) 352 ASC_SOFTC *sc; 353 { 354 bus_space_tag_t iot = sc->sc_iot; 355 bus_space_handle_t ioh = sc->sc_ioh; 356 ASCEEP_CONFIG eep_config_buf; 357 ASCEEP_CONFIG *eep_config; 358 u_int16_t chksum; 359 u_int16_t warn_code; 360 u_int16_t cfg_msw, cfg_lsw; 361 int i; 362 int write_eep = 0; 363 364 365 warn_code = 0; 366 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 367 AscStopQueueExe(iot, ioh); 368 if ((AscStopChip(iot, ioh) == FALSE) || 369 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 370 AscResetChipAndScsiBus(iot, ioh); 371 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 372 } 373 if (AscIsChipHalted(iot, ioh) == FALSE) 374 return (-1); 375 376 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 377 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 378 return (-2); 379 380 eep_config = (ASCEEP_CONFIG *) & eep_config_buf; 381 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 382 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 383 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 384 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 385 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 386 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 387 } 388 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 389 if (chksum == 0) 390 chksum = 0xAA55; 391 392 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 393 warn_code |= ASC_WARN_AUTO_CONFIG; 394 if (sc->chip_version == 3) { 395 if (eep_config->cfg_lsw != cfg_lsw) { 396 warn_code |= ASC_WARN_EEPROM_RECOVER; 397 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 398 } 399 if (eep_config->cfg_msw != cfg_msw) { 400 warn_code |= ASC_WARN_EEPROM_RECOVER; 401 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 402 } 403 } 404 } 405 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 406 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 407 408 if (chksum != eep_config->chksum) { 409 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 410 ASC_CHIP_VER_PCI_ULTRA_3050) { 411 eep_config->init_sdtr = 0xFF; 412 eep_config->disc_enable = 0xFF; 413 eep_config->start_motor = 0xFF; 414 eep_config->use_cmd_qng = 0; 415 eep_config->max_total_qng = 0xF0; 416 eep_config->max_tag_qng = 0x20; 417 eep_config->cntl = 0xBFFF; 418 eep_config->chip_scsi_id = 7; 419 eep_config->no_scam = 0; 420 eep_config->adapter_info[0] = 0; 421 eep_config->adapter_info[1] = 0; 422 eep_config->adapter_info[2] = 0; 423 eep_config->adapter_info[3] = 0; 424 eep_config->adapter_info[4] = 0; 425 /* Indicate EEPROM-less board. */ 426 eep_config->adapter_info[5] = 0xBB; 427 } else { 428 write_eep = 1; 429 warn_code |= ASC_WARN_EEPROM_CHKSUM; 430 } 431 } 432 sc->sdtr_enable = eep_config->init_sdtr; 433 sc->disc_enable = eep_config->disc_enable; 434 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 435 sc->isa_dma_speed = eep_config->isa_dma_speed; 436 sc->start_motor = eep_config->start_motor; 437 sc->dvc_cntl = eep_config->cntl; 438 sc->adapter_info[0] = eep_config->adapter_info[0]; 439 sc->adapter_info[1] = eep_config->adapter_info[1]; 440 sc->adapter_info[2] = eep_config->adapter_info[2]; 441 sc->adapter_info[3] = eep_config->adapter_info[3]; 442 sc->adapter_info[4] = eep_config->adapter_info[4]; 443 sc->adapter_info[5] = eep_config->adapter_info[5]; 444 445 if (!AscTestExternalLram(iot, ioh)) { 446 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 447 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 448 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 449 } else { 450 eep_config->cfg_msw |= 0x0800; 451 cfg_msw |= 0x0800; 452 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 453 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 454 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 455 } 456 } 457 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 458 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 459 460 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 461 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 462 463 if (eep_config->max_tag_qng > eep_config->max_total_qng) 464 eep_config->max_tag_qng = eep_config->max_total_qng; 465 466 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 467 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 468 469 sc->max_total_qng = eep_config->max_total_qng; 470 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 471 eep_config->use_cmd_qng) { 472 eep_config->disc_enable = eep_config->use_cmd_qng; 473 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 474 } 475 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 476 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 477 478 eep_config->chip_scsi_id &= ASC_MAX_TID; 479 sc->chip_scsi_id = eep_config->chip_scsi_id; 480 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 481 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 482 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 483 } 484 for (i = 0; i <= ASC_MAX_TID; i++) { 485 sc->max_tag_qng[i] = eep_config->max_tag_qng; 486 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 487 (sc->host_init_sdtr_index << 4); 488 } 489 490 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 491 if (write_eep) 492 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 493 494 return (warn_code); 495 } 496 497 498 u_int16_t 499 AscInitFromASC_SOFTC(sc) 500 ASC_SOFTC *sc; 501 { 502 bus_space_tag_t iot = sc->sc_iot; 503 bus_space_handle_t ioh = sc->sc_ioh; 504 u_int16_t cfg_msw; 505 u_int16_t warn_code; 506 u_int16_t pci_device_id = sc->pci_device_id; 507 508 509 warn_code = 0; 510 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 511 512 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 513 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 514 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 515 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 516 } 517 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 518 sc->disc_enable = sc->cmd_qng_enabled; 519 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 520 } 521 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 522 warn_code |= ASC_WARN_AUTO_CONFIG; 523 } 524 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 525 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 526 } 527 if (sc->bus_type & ASC_IS_PCI) { 528 cfg_msw &= 0xFFC0; 529 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 530 531 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 532 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 533 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 534 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 535 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 536 } 537 } 538 } else if (sc->bus_type == ASC_IS_ISAPNP) { 539 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 540 ASC_CHIP_VER_ASYN_BUG) { 541 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 542 } 543 } 544 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 545 546 if (sc->bus_type & ASC_IS_ISA) { 547 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 548 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 549 } 550 return (warn_code); 551 } 552 553 554 /* 555 * - Initialize RISC chip 556 * - Intialize Lram 557 * - Load uCode into Lram 558 * - Enable Interrupts 559 */ 560 int 561 AscInitDriver(sc) 562 ASC_SOFTC *sc; 563 { 564 bus_space_tag_t iot = sc->sc_iot; 565 bus_space_handle_t ioh = sc->sc_ioh; 566 u_int32_t chksum; 567 568 569 if (!AscFindSignature(iot, ioh)) 570 return (1); 571 572 AscDisableInterrupt(iot, ioh); 573 574 AscInitLram(sc); 575 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 576 asc_mcode_size); 577 if (chksum != asc_mcode_chksum) 578 return (2); 579 580 if (AscInitMicroCodeVar(sc) == 0) 581 return (3); 582 583 AscEnableInterrupt(iot, ioh); 584 585 return (0); 586 } 587 588 589 int 590 AscFindSignature(iot, ioh) 591 bus_space_tag_t iot; 592 bus_space_handle_t ioh; 593 { 594 u_int16_t sig_word; 595 596 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 597 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 598 if (sig_word == ASC_1000_ID0W || 599 sig_word == ASC_1000_ID0W_FIX) 600 return (1); 601 } 602 return (0); 603 } 604 605 606 static u_int32_t 607 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 608 bus_space_tag_t iot; 609 bus_space_handle_t ioh; 610 u_int16_t s_addr; 611 u_int16_t *mcode_buf; 612 u_int16_t mcode_size; 613 { 614 u_int32_t chksum; 615 u_int16_t mcode_word_size; 616 u_int16_t mcode_chksum; 617 618 mcode_word_size = mcode_size >> 1; 619 /* clear board memory */ 620 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 621 /* copy uCode to board memory */ 622 AscMCodeCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 623 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 624 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 625 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 626 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 627 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 628 629 return (chksum); 630 } 631 632 633 static void 634 AscInitLram(sc) 635 ASC_SOFTC *sc; 636 { 637 bus_space_tag_t iot = sc->sc_iot; 638 bus_space_handle_t ioh = sc->sc_ioh; 639 u_int8_t i; 640 u_int16_t s_addr; 641 642 643 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 644 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 645 646 i = ASC_MIN_ACTIVE_QNO; 647 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 648 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 649 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 651 i++; 652 s_addr += ASC_QBLK_SIZE; 653 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 655 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 657 } 658 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 659 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 660 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 661 i++; 662 s_addr += ASC_QBLK_SIZE; 663 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 664 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 665 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 666 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 667 } 668 } 669 670 671 void 672 AscReInitLram(sc) 673 ASC_SOFTC *sc; 674 { 675 676 AscInitLram(sc); 677 AscInitQLinkVar(sc); 678 } 679 680 681 static void 682 AscInitQLinkVar(sc) 683 ASC_SOFTC *sc; 684 { 685 bus_space_tag_t iot = sc->sc_iot; 686 bus_space_handle_t ioh = sc->sc_ioh; 687 u_int8_t i; 688 u_int16_t lram_addr; 689 690 691 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 692 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 693 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 694 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 695 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 696 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 697 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 698 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 699 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 700 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 701 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 702 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 703 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 704 lram_addr = ASC_QADR_BEG; 705 for (i = 0; i < 32; i++, lram_addr += 2) 706 AscWriteLramWord(iot, ioh, lram_addr, 0); 707 } 708 709 710 static int 711 AscResetChipAndScsiBus(bus_space_tag_t iot, 712 bus_space_handle_t ioh) 713 { 714 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 715 716 AscStopChip(iot, ioh); 717 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 718 719 DvcDelayNanoSecond(60000); 720 721 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 722 AscSetChipIH(iot, ioh, ASC_INS_HALT); 723 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 724 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 725 726 DvcSleepMilliSecond(200); 727 728 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 729 AscStartChip(iot, ioh); 730 731 DvcSleepMilliSecond(200); 732 733 return (AscIsChipHalted(iot, ioh)); 734 } 735 736 737 static u_int16_t 738 AscGetChipBusType(iot, ioh) 739 bus_space_tag_t iot; 740 bus_space_handle_t ioh; 741 { 742 u_int16_t chip_ver; 743 744 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 745 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 746 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 747 /* 748 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50) 749 * == 0x0C50)) return (ASC_IS_EISA); 750 */ 751 return (ASC_IS_VL); 752 } 753 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 754 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 755 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 756 return (ASC_IS_ISAPNP); 757 758 return (ASC_IS_ISA); 759 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 760 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 761 return (ASC_IS_PCI); 762 763 return (0); 764 } 765 766 767 /******************************************************************************/ 768 /* Chip register routines */ 769 /******************************************************************************/ 770 771 772 static void 773 AscSetBank(iot, ioh, bank) 774 bus_space_tag_t iot; 775 bus_space_handle_t ioh; 776 u_int8_t bank; 777 { 778 u_int8_t val; 779 780 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 781 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 782 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 783 ASC_CC_CHIP_RESET)); 784 785 switch (bank) { 786 case 1: 787 val |= ASC_CC_BANK_ONE; 788 break; 789 790 case 2: 791 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 792 break; 793 794 default: 795 val &= ~ASC_CC_BANK_ONE; 796 } 797 798 ASC_SET_CHIP_CONTROL(iot, ioh, val); 799 return; 800 } 801 802 803 /******************************************************************************/ 804 /* Chip routines */ 805 /******************************************************************************/ 806 807 808 static int 809 AscStartChip(iot, ioh) 810 bus_space_tag_t iot; 811 bus_space_handle_t ioh; 812 { 813 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 814 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 815 return (0); 816 817 return (1); 818 } 819 820 821 static int 822 AscStopChip(iot, ioh) 823 bus_space_tag_t iot; 824 bus_space_handle_t ioh; 825 { 826 u_int8_t cc_val; 827 828 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 829 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 830 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 831 AscSetChipIH(iot, ioh, ASC_INS_HALT); 832 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 833 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 834 return (0); 835 836 return (1); 837 } 838 839 840 static u_int8_t 841 AscGetChipVersion(iot, ioh, bus_type) 842 bus_space_tag_t iot; 843 bus_space_handle_t ioh; 844 u_int16_t bus_type; 845 { 846 if (bus_type & ASC_IS_EISA) { 847 /* 848 * u_int16_t eisa_iop; u_int8_t revision; 849 * 850 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) | 851 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop); 852 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 853 */ 854 } 855 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 856 } 857 858 859 static u_int8_t 860 AscSetChipScsiID(iot, ioh, new_id) 861 bus_space_tag_t iot; 862 bus_space_handle_t ioh; 863 u_int8_t new_id; 864 { 865 u_int16_t cfg_lsw; 866 867 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 868 return (new_id); 869 870 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 871 cfg_lsw &= 0xF8FF; 872 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 873 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 874 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 875 } 876 877 878 static u_int8_t 879 AscGetChipScsiCtrl(iot, ioh) 880 bus_space_tag_t iot; 881 bus_space_handle_t ioh; 882 { 883 u_int8_t scsi_ctrl; 884 885 AscSetBank(iot, ioh, 1); 886 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 887 AscSetBank(iot, ioh, 0); 888 return (scsi_ctrl); 889 } 890 891 892 static int 893 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 894 bus_space_tag_t iot; 895 bus_space_handle_t ioh; 896 u_int8_t tid_no; 897 u_int8_t sdtr_data; 898 { 899 int retval = FALSE; 900 901 if (AscHostReqRiscHalt(iot, ioh)) { 902 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 903 AscStartChip(iot, ioh); 904 } 905 return (retval); 906 } 907 908 909 static int 910 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 911 bus_space_tag_t iot; 912 bus_space_handle_t ioh; 913 u_int8_t id; 914 u_int8_t sdtr_data; 915 { 916 ASC_SCSI_BIT_ID_TYPE org_id; 917 int i; 918 int sta = TRUE; 919 920 AscSetBank(iot, ioh, 1); 921 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 922 for (i = 0; i <= ASC_MAX_TID; i++) 923 if (org_id == (0x01 << i)) 924 break; 925 926 org_id = i; 927 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 928 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 929 AscSetBank(iot, ioh, 0); 930 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 931 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 932 sta = FALSE; 933 } else 934 sta = FALSE; 935 936 AscSetBank(iot, ioh, 1); 937 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 938 AscSetBank(iot, ioh, 0); 939 return (sta); 940 } 941 942 943 static int 944 AscHostReqRiscHalt(iot, ioh) 945 bus_space_tag_t iot; 946 bus_space_handle_t ioh; 947 { 948 int count = 0; 949 int retval = 0; 950 u_int8_t saved_stop_code; 951 952 953 if (AscIsChipHalted(iot, ioh)) 954 return (1); 955 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 956 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 957 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 958 959 do { 960 if (AscIsChipHalted(iot, ioh)) { 961 retval = 1; 962 break; 963 } 964 DvcSleepMilliSecond(100); 965 } while (count++ < 20); 966 967 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 968 969 return (retval); 970 } 971 972 973 static int 974 AscIsChipHalted(iot, ioh) 975 bus_space_tag_t iot; 976 bus_space_handle_t ioh; 977 { 978 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 979 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 980 return (1); 981 982 return (0); 983 } 984 985 986 static void 987 AscSetChipIH(iot, ioh, ins_code) 988 bus_space_tag_t iot; 989 bus_space_handle_t ioh; 990 u_int16_t ins_code; 991 { 992 AscSetBank(iot, ioh, 1); 993 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 994 AscSetBank(iot, ioh, 0); 995 996 return; 997 } 998 999 1000 /******************************************************************************/ 1001 /* Lram routines */ 1002 /******************************************************************************/ 1003 1004 1005 static u_int8_t 1006 AscReadLramByte(iot, ioh, addr) 1007 bus_space_tag_t iot; 1008 bus_space_handle_t ioh; 1009 u_int16_t addr; 1010 { 1011 u_int8_t byte_data; 1012 u_int16_t word_data; 1013 1014 1015 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1016 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1017 #if BYTE_ORDER == BIG_ENDIAN 1018 if (addr & 1) 1019 //odd address 1020 byte_data = (u_int8_t) (word_data & 0xFF); 1021 else 1022 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1023 #else 1024 if (addr & 1) 1025 //odd address 1026 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1027 else 1028 byte_data = (u_int8_t) (word_data & 0xFF); 1029 #endif 1030 return (byte_data); 1031 } 1032 1033 1034 static void 1035 AscWriteLramByte(iot, ioh, addr, data) 1036 bus_space_tag_t iot; 1037 bus_space_handle_t ioh; 1038 u_int16_t addr; 1039 u_int8_t data; 1040 { 1041 u_int16_t word_data; 1042 1043 1044 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1045 #if BYTE_ORDER == BIG_ENDIAN 1046 if (addr & 1) 1047 //odd address 1048 { 1049 word_data &= 0xFF00; 1050 word_data |= ((u_int16_t) data) & 0x00FF; 1051 } else { 1052 word_data &= 0xFF00; 1053 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1054 } 1055 #else 1056 if (addr & 1) 1057 //odd address 1058 { 1059 word_data &= 0x00FF; 1060 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1061 } else { 1062 word_data &= 0xFF00; 1063 word_data |= ((u_int16_t) data) & 0x00FF; 1064 } 1065 #endif 1066 AscWriteLramWord(iot, ioh, addr, word_data); 1067 } 1068 1069 1070 static u_int16_t 1071 AscReadLramWord(iot, ioh, addr) 1072 bus_space_tag_t iot; 1073 bus_space_handle_t ioh; 1074 u_int16_t addr; 1075 { 1076 1077 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1078 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1079 } 1080 1081 1082 static void 1083 AscWriteLramWord(iot, ioh, addr, data) 1084 bus_space_tag_t iot; 1085 bus_space_handle_t ioh; 1086 u_int16_t addr; 1087 u_int16_t data; 1088 { 1089 1090 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1091 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1092 } 1093 1094 1095 static u_int32_t 1096 AscReadLramDWord(iot, ioh, addr) 1097 bus_space_tag_t iot; 1098 bus_space_handle_t ioh; 1099 u_int16_t addr; 1100 { 1101 u_int16_t low_word, hi_word; 1102 1103 1104 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1105 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1106 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1107 1108 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1109 } 1110 1111 1112 static void 1113 AscWriteLramDWord(iot, ioh, addr, data) 1114 bus_space_tag_t iot; 1115 bus_space_handle_t ioh; 1116 u_int16_t addr; 1117 u_int32_t data; 1118 { 1119 1120 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1121 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1122 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1123 } 1124 1125 1126 static void 1127 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1128 bus_space_tag_t iot; 1129 bus_space_handle_t ioh; 1130 u_int16_t s_addr; 1131 u_int16_t s_words; 1132 int count; 1133 { 1134 int i; 1135 1136 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1137 for (i = 0; i < count; i++) 1138 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1139 } 1140 1141 1142 static void 1143 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1144 bus_space_tag_t iot; 1145 bus_space_handle_t ioh; 1146 u_int16_t s_addr; 1147 u_int16_t *s_buffer; 1148 int words; 1149 { 1150 int i; 1151 1152 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1153 for (i = 0; i < words; i++, s_buffer++) 1154 ASC_SET_CHIP_LRAM_DATA(iot, ioh, *s_buffer); 1155 } 1156 1157 1158 static void 1159 AscMCodeCopyToLram(iot, ioh, s_addr, s_buffer, words) 1160 bus_space_tag_t iot; 1161 bus_space_handle_t ioh; 1162 u_int16_t s_addr; 1163 u_int16_t *s_buffer; 1164 int words; 1165 { 1166 u_int16_t uCodeWord; 1167 int i; 1168 1169 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1170 for (i = 0; i < words; i++, s_buffer++) { 1171 #if BYTE_ORDER == BIG_ENDIAN 1172 uCodeWord = SWAPBYTES(*s_buffer); 1173 #else 1174 uCodeWord = *s_buffer; 1175 #endif 1176 ASC_SET_CHIP_LRAM_DATA(iot, ioh, uCodeWord); 1177 } 1178 } 1179 1180 1181 static void 1182 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1183 bus_space_tag_t iot; 1184 bus_space_handle_t ioh; 1185 u_int16_t s_addr; 1186 u_int16_t *s_buffer; 1187 int words; 1188 { 1189 int i; 1190 1191 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1192 for (i = 0; i < words; i++, s_buffer++) 1193 *s_buffer = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1194 } 1195 1196 1197 static void 1198 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1199 bus_space_tag_t iot; 1200 bus_space_handle_t ioh; 1201 u_int16_t s_addr; 1202 u_int32_t *s_buffer; 1203 int dwords; 1204 { 1205 int i; 1206 int words; 1207 u_int16_t *pw; 1208 1209 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1210 1211 pw = (u_int16_t *) s_buffer; 1212 words = dwords << 1; 1213 for (i = 0; i < words; i++, pw++) 1214 ASC_SET_CHIP_LRAM_DATA(iot, ioh, *pw); 1215 } 1216 1217 1218 static u_int32_t 1219 AscMemSumLramWord(iot, ioh, s_addr, words) 1220 bus_space_tag_t iot; 1221 bus_space_handle_t ioh; 1222 u_int16_t s_addr; 1223 int words; 1224 { 1225 u_int32_t sum = 0L; 1226 u_int16_t i; 1227 u_int16_t w; 1228 1229 1230 printf("\nreading\n"); 1231 for (i = 0; i < words; i++, s_addr += 2) { 1232 w = AscReadLramWord(iot, ioh, s_addr); 1233 if(i < 5) 1234 printf("0x%x ", w); 1235 sum += w; 1236 } 1237 printf("\n"); 1238 1239 return (sum); 1240 } 1241 1242 1243 static int 1244 AscTestExternalLram(iot, ioh) 1245 bus_space_tag_t iot; 1246 bus_space_handle_t ioh; 1247 { 1248 u_int16_t q_addr; 1249 u_int16_t saved_word; 1250 int retval; 1251 1252 1253 retval = 0; 1254 q_addr = ASC_QNO_TO_QADDR(241); 1255 saved_word = AscReadLramWord(iot, ioh, q_addr); 1256 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1257 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1258 DvcSleepMilliSecond(10); 1259 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1260 1261 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1262 retval = 1; 1263 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1264 } 1265 return (retval); 1266 } 1267 1268 1269 /******************************************************************************/ 1270 /* MicroCode routines */ 1271 /******************************************************************************/ 1272 1273 1274 static u_int16_t 1275 AscInitMicroCodeVar(sc) 1276 ASC_SOFTC *sc; 1277 { 1278 bus_space_tag_t iot = sc->sc_iot; 1279 bus_space_handle_t ioh = sc->sc_ioh; 1280 u_int32_t phy_addr; 1281 int i; 1282 1283 1284 for (i = 0; i <= ASC_MAX_TID; i++) 1285 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1286 sc->sdtr_period_offset[i]); 1287 1288 AscInitQLinkVar(sc); 1289 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1290 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1291 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1292 1293 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1294 ASC_OVERRUN_BSIZE)) == 0L) { 1295 return (0); 1296 } else { 1297 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1298 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1299 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1300 ASC_OVERRUN_BSIZE - 8); 1301 } 1302 1303 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1304 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1305 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1306 1307 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1308 return (0); 1309 } 1310 if (AscStartChip(iot, ioh) != 1) { 1311 return (0); 1312 } 1313 return (1); 1314 } 1315 1316 1317 static u_int32_t 1318 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1319 ASC_SOFTC *sc; 1320 u_int8_t *buf_addr; 1321 u_int32_t buf_size; 1322 { 1323 ASC_MIN_SG_HEAD sg_head; 1324 1325 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1326 if (DvcGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1327 buf_size) { 1328 return (0L); 1329 } 1330 if (sg_head.entry_cnt > 1) { 1331 return (0L); 1332 } 1333 return (sg_head.sg_list[0].addr); 1334 } 1335 /******************************************************************************/ 1336 /* EEProm routines */ 1337 /******************************************************************************/ 1338 1339 1340 static int 1341 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1342 bus_space_tag_t iot; 1343 bus_space_handle_t ioh; 1344 u_int8_t cmd_reg; 1345 { 1346 u_int8_t read_back; 1347 int retry; 1348 1349 retry = 0; 1350 1351 while (TRUE) { 1352 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1353 DvcSleepMilliSecond(1); 1354 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1355 if (read_back == cmd_reg) 1356 return (1); 1357 1358 if (retry++ > ASC_EEP_MAX_RETRY) 1359 return (0); 1360 } 1361 } 1362 1363 1364 static int 1365 AscWriteEEPDataReg(iot, ioh, data_reg) 1366 bus_space_tag_t iot; 1367 bus_space_handle_t ioh; 1368 u_int16_t data_reg; 1369 { 1370 u_int16_t read_back; 1371 int retry; 1372 1373 retry = 0; 1374 while (TRUE) { 1375 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1376 DvcSleepMilliSecond(1); 1377 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1378 if (read_back == data_reg) 1379 return (1); 1380 1381 if (retry++ > ASC_EEP_MAX_RETRY) 1382 return (0); 1383 } 1384 } 1385 1386 1387 static void 1388 AscWaitEEPRead(void) 1389 { 1390 1391 DvcSleepMilliSecond(1); 1392 } 1393 1394 1395 static void 1396 AscWaitEEPWrite(void) 1397 { 1398 1399 DvcSleepMilliSecond(1); 1400 } 1401 1402 1403 static u_int16_t 1404 AscReadEEPWord(iot, ioh, addr) 1405 bus_space_tag_t iot; 1406 bus_space_handle_t ioh; 1407 u_int8_t addr; 1408 { 1409 u_int16_t read_wval; 1410 u_int8_t cmd_reg; 1411 1412 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1413 AscWaitEEPRead(); 1414 cmd_reg = addr | ASC_EEP_CMD_READ; 1415 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1416 AscWaitEEPRead(); 1417 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1418 AscWaitEEPRead(); 1419 1420 return (read_wval); 1421 } 1422 1423 1424 static u_int16_t 1425 AscWriteEEPWord(iot, ioh, addr, word_val) 1426 bus_space_tag_t iot; 1427 bus_space_handle_t ioh; 1428 u_int8_t addr; 1429 u_int16_t word_val; 1430 { 1431 u_int16_t read_wval; 1432 1433 read_wval = AscReadEEPWord(iot, ioh, addr); 1434 if (read_wval != word_val) { 1435 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1436 AscWaitEEPRead(); 1437 AscWriteEEPDataReg(iot, ioh, word_val); 1438 AscWaitEEPRead(); 1439 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1440 AscWaitEEPWrite(); 1441 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1442 AscWaitEEPRead(); 1443 return (AscReadEEPWord(iot, ioh, addr)); 1444 } 1445 return (read_wval); 1446 } 1447 1448 1449 static u_int16_t 1450 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1451 bus_space_tag_t iot; 1452 bus_space_handle_t ioh; 1453 ASCEEP_CONFIG *cfg_buf; 1454 u_int16_t bus_type; 1455 { 1456 u_int16_t wval; 1457 u_int16_t sum; 1458 u_int16_t *wbuf; 1459 int cfg_beg; 1460 int cfg_end; 1461 int s_addr; 1462 int isa_pnp_wsize; 1463 1464 1465 wbuf = (u_int16_t *) cfg_buf; 1466 sum = 0; 1467 isa_pnp_wsize = 0; 1468 1469 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1470 wval = AscReadEEPWord(iot, ioh, s_addr); 1471 sum += wval; 1472 *wbuf = wval; 1473 } 1474 1475 if (bus_type & ASC_IS_VL) { 1476 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1477 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1478 } else { 1479 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1480 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1481 } 1482 1483 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1484 wval = AscReadEEPWord(iot, ioh, s_addr); 1485 sum += wval; 1486 *wbuf = wval; 1487 } 1488 1489 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1490 1491 return (sum); 1492 } 1493 1494 1495 static int 1496 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1497 bus_space_tag_t iot; 1498 bus_space_handle_t ioh; 1499 ASCEEP_CONFIG *cfg_buf; 1500 u_int16_t bus_type; 1501 { 1502 int retry; 1503 int n_error; 1504 1505 retry = 0; 1506 while (TRUE) { 1507 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1508 break; 1509 1510 if (++retry > ASC_EEP_MAX_RETRY) 1511 break; 1512 } 1513 1514 return (n_error); 1515 } 1516 1517 1518 static int 1519 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1520 bus_space_tag_t iot; 1521 bus_space_handle_t ioh; 1522 ASCEEP_CONFIG *cfg_buf; 1523 u_int16_t bus_type; 1524 { 1525 int n_error; 1526 u_int16_t *wbuf; 1527 u_int16_t sum; 1528 int s_addr; 1529 int cfg_beg; 1530 int cfg_end; 1531 1532 wbuf = (u_int16_t *) cfg_buf; 1533 n_error = 0; 1534 sum = 0; 1535 1536 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1537 sum += *wbuf; 1538 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1539 n_error++; 1540 } 1541 1542 if (bus_type & ASC_IS_VL) { 1543 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1544 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1545 } else { 1546 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1547 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1548 } 1549 1550 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1551 sum += *wbuf; 1552 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1553 n_error++; 1554 } 1555 1556 *wbuf = sum; 1557 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1558 n_error++; 1559 1560 wbuf = (u_int16_t *) cfg_buf; 1561 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) 1562 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1563 n_error++; 1564 1565 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) 1566 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1567 n_error++; 1568 1569 return (n_error); 1570 } 1571 1572 1573 /******************************************************************************/ 1574 /* Interrupt routines */ 1575 /******************************************************************************/ 1576 1577 1578 int 1579 AscISR(sc) 1580 ASC_SOFTC *sc; 1581 { 1582 bus_space_tag_t iot = sc->sc_iot; 1583 bus_space_handle_t ioh = sc->sc_ioh; 1584 u_int16_t chipstat; 1585 u_int16_t saved_ram_addr; 1586 u_int8_t ctrl_reg; 1587 u_int8_t saved_ctrl_reg; 1588 int int_pending; 1589 int status; 1590 u_int8_t host_flag; 1591 1592 1593 int_pending = FALSE; 1594 1595 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1596 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1597 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1598 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1599 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) 1600 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1601 int_pending = TRUE; 1602 sc->sdtr_done = 0; 1603 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1604 1605 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1606 1607 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1608 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1609 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1610 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1611 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1612 } 1613 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1614 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1615 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1616 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1617 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1618 1619 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1620 AscAckInterrupt(iot, ioh); 1621 int_pending = TRUE; 1622 1623 if ((chipstat & ASC_CSW_HALTED) && 1624 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1625 AscIsrChipHalted(sc); 1626 saved_ctrl_reg &= ~ASC_CC_HALT; 1627 } else { 1628 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1629 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1630 } else { 1631 do { 1632 if ((status = AscIsrQDone(sc)) == 1) 1633 break; 1634 } while (status == 0x11); 1635 } 1636 1637 if (status & 0x80) 1638 int_pending = -1; 1639 } 1640 } 1641 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1642 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1643 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1644 1645 return (1); 1646 /* return(int_pending); */ 1647 } 1648 1649 1650 static int 1651 AscIsrQDone(sc) 1652 ASC_SOFTC *sc; 1653 { 1654 u_int8_t next_qp; 1655 u_int8_t n_q_used; 1656 u_int8_t sg_list_qp; 1657 u_int8_t sg_queue_cnt; 1658 u_int8_t q_cnt; 1659 u_int8_t done_q_tail; 1660 u_int8_t tid_no; 1661 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1662 ASC_SCSI_BIT_ID_TYPE target_id; 1663 bus_space_tag_t iot = sc->sc_iot; 1664 bus_space_handle_t ioh = sc->sc_ioh; 1665 u_int16_t q_addr; 1666 u_int16_t sg_q_addr; 1667 u_int8_t cur_target_qng; 1668 ASC_QDONE_INFO scsiq_buf; 1669 ASC_QDONE_INFO *scsiq; 1670 ASC_ISR_CALLBACK asc_isr_callback; 1671 1672 1673 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1674 n_q_used = 1; 1675 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1676 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1677 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1678 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1679 1680 if (next_qp != ASC_QLINK_END) { 1681 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1682 q_addr = ASC_QNO_TO_QADDR(next_qp); 1683 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1684 sc->max_dma_count); 1685 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1686 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1687 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1688 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1689 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1690 sg_q_addr = q_addr; 1691 sg_list_qp = next_qp; 1692 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1693 sg_list_qp = AscReadLramByte(iot, ioh, 1694 sg_q_addr + ASC_SCSIQ_B_FWD); 1695 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1696 if (sg_list_qp == ASC_QLINK_END) { 1697 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1698 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1699 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1700 panic("AscIsrQDone: Corrupted SG list encountered"); 1701 } 1702 AscWriteLramByte(iot, ioh, 1703 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1704 } 1705 n_q_used = sg_queue_cnt + 1; 1706 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1707 } 1708 if (sc->queue_full_or_busy & target_id) { 1709 cur_target_qng = AscReadLramByte(iot, ioh, 1710 ASC_QADR_BEG + scsiq->d2.target_ix); 1711 1712 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1713 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1714 scsi_busy &= ~target_id; 1715 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1716 sc->queue_full_or_busy &= ~target_id; 1717 } 1718 } 1719 if (sc->cur_total_qng >= n_q_used) { 1720 sc->cur_total_qng -= n_q_used; 1721 if (sc->cur_dvc_qng[tid_no] != 0) 1722 sc->cur_dvc_qng[tid_no]--; 1723 } else { 1724 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1725 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1726 panic("AscIsrQDone: Attempting to free more queues than are active"); 1727 } 1728 1729 if ((scsiq->d2.ccb_ptr == 0UL) || ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1730 return (0x11); 1731 } else if (scsiq->q_status == ASC_QS_DONE) { 1732 scsiq->remain_bytes += scsiq->extra_bytes; 1733 1734 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1735 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1736 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1737 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1738 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1739 } 1740 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1741 AscStopChip(iot, ioh); 1742 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1743 DvcDelayNanoSecond(60000); 1744 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1745 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1746 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1747 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1748 } 1749 } 1750 (*asc_isr_callback) (sc, scsiq); 1751 1752 return (1); 1753 } else { 1754 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1755 panic("AscIsrQDone: completed scsiq with unknown status"); 1756 1757 return (0x80); 1758 } 1759 } 1760 return (0); 1761 } 1762 1763 1764 /* 1765 * handle all the conditions that may halt the board 1766 * waiting us to intervene 1767 */ 1768 static void 1769 AscIsrChipHalted(sc) 1770 ASC_SOFTC *sc; 1771 { 1772 bus_space_tag_t iot = sc->sc_iot; 1773 bus_space_handle_t ioh = sc->sc_ioh; 1774 EXT_MSG out_msg; 1775 u_int16_t int_halt_code; 1776 u_int16_t halt_q_addr; 1777 u_int8_t halt_qp; 1778 u_int8_t target_ix; 1779 u_int8_t tag_code; 1780 u_int8_t q_status; 1781 u_int8_t q_cntl; 1782 u_int8_t tid_no; 1783 u_int8_t cur_dvc_qng; 1784 u_int8_t asyn_sdtr; 1785 u_int8_t scsi_status; 1786 u_int8_t sdtr_data; 1787 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1788 ASC_SCSI_BIT_ID_TYPE target_id; 1789 1790 1791 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1792 1793 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1794 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1795 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1796 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1797 tid_no = ASC_TIX_TO_TID(target_ix); 1798 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1799 1800 if (sc->pci_fix_asyn_xfer & target_id) 1801 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1802 else 1803 asyn_sdtr = 0; 1804 1805 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1806 if (sc->pci_fix_asyn_xfer & target_id) { 1807 AscSetChipSDTR(iot, ioh, 0, tid_no); 1808 sc->sdtr_data[tid_no] = 0; 1809 } 1810 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1811 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1812 if (sc->pci_fix_asyn_xfer & target_id) { 1813 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1814 sc->sdtr_data[tid_no] = asyn_sdtr; 1815 } 1816 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1817 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1818 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1819 tid_no, asyn_sdtr); 1820 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1821 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1822 q_cntl |= ASC_QC_REQ_SENSE; 1823 1824 if (sc->init_sdtr & target_id) { 1825 sc->sdtr_done &= ~target_id; 1826 1827 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1828 q_cntl |= ASC_QC_MSG_OUT; 1829 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1830 (sc->max_sdtr_index - 1)], 1831 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1832 } 1833 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1834 1835 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1836 tag_code &= 0xDC; 1837 1838 if ((sc->pci_fix_asyn_xfer & target_id) && 1839 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1840 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1841 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1842 } 1843 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1844 1845 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1846 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1847 1848 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1849 1850 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1851 scsi_busy &= ~target_id; 1852 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1853 1854 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1855 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1856 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1857 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1858 1859 if ((out_msg.msg_type == MS_EXTEND) && 1860 (out_msg.msg_len == MS_SDTR_LEN) && 1861 (out_msg.msg_req == MS_SDTR_CODE)) { 1862 1863 sc->init_sdtr &= ~target_id; 1864 sc->sdtr_done &= ~target_id; 1865 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1866 sc->sdtr_data[tid_no] = asyn_sdtr; 1867 } 1868 q_cntl &= ~ASC_QC_MSG_OUT; 1869 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1870 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1871 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1872 scsi_status = AscReadLramByte(iot, ioh, 1873 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1874 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1875 1876 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1877 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1878 scsi_busy |= target_id; 1879 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1880 sc->queue_full_or_busy |= target_id; 1881 1882 if (scsi_status == SS_QUEUE_FULL) { 1883 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1884 cur_dvc_qng -= 1; 1885 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1886 1887 AscWriteLramByte(iot, ioh, 1888 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1889 1890 #if ASC_QUEUE_FLOW_CONTROL 1891 if ((sc->device[tid_no] != NULL) && 1892 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1893 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1894 } 1895 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1896 } 1897 } 1898 } 1899 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1900 } 1901 return; 1902 } 1903 1904 1905 static int 1906 AscWaitTixISRDone(sc, target_ix) 1907 ASC_SOFTC *sc; 1908 u_int8_t target_ix; 1909 { 1910 u_int8_t cur_req; 1911 u_int8_t tid_no; 1912 int i = 0; 1913 1914 tid_no = ASC_TIX_TO_TID(target_ix); 1915 while (i++ < 10) { 1916 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1917 break; 1918 1919 DvcSleepMilliSecond(1000L); 1920 if (sc->cur_dvc_qng[tid_no] == cur_req) 1921 break; 1922 } 1923 return (1); 1924 } 1925 1926 static int 1927 AscWaitISRDone(sc) 1928 ASC_SOFTC *sc; 1929 { 1930 int tid; 1931 1932 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1933 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1934 1935 return (1); 1936 } 1937 1938 1939 static u_int8_t 1940 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1941 bus_space_tag_t iot; 1942 bus_space_handle_t ioh; 1943 u_int16_t q_addr; 1944 ASC_QDONE_INFO *scsiq; 1945 u_int32_t max_dma_count; 1946 { 1947 u_int16_t _val; 1948 u_int8_t sg_queue_cnt; 1949 1950 DvcGetQinfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, (u_int16_t *) scsiq, 1951 ((sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2)); 1952 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1953 scsiq->q_status = _val; 1954 scsiq->q_no = (_val >> 8); 1955 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1956 scsiq->cntl = _val; 1957 sg_queue_cnt = (_val >> 8); 1958 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 1959 scsiq->sense_len = _val; 1960 scsiq->extra_bytes = (_val >> 8); 1961 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 1962 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 1963 scsiq->remain_bytes &= max_dma_count; 1964 1965 return (sg_queue_cnt); 1966 } 1967 1968 1969 static void 1970 AscToggleIRQAct(iot, ioh) 1971 bus_space_tag_t iot; 1972 bus_space_handle_t ioh; 1973 { 1974 1975 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 1976 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1977 } 1978 1979 1980 static void 1981 AscDisableInterrupt(iot, ioh) 1982 bus_space_tag_t iot; 1983 bus_space_handle_t ioh; 1984 { 1985 u_int16_t cfg; 1986 1987 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 1988 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 1989 } 1990 1991 1992 static void 1993 AscEnableInterrupt(iot, ioh) 1994 bus_space_tag_t iot; 1995 bus_space_handle_t ioh; 1996 { 1997 u_int16_t cfg; 1998 1999 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2000 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2001 } 2002 2003 2004 static u_int8_t 2005 AscGetChipIRQ(iot, ioh, bus_type) 2006 bus_space_tag_t iot; 2007 bus_space_handle_t ioh; 2008 u_int16_t bus_type; 2009 { 2010 u_int16_t cfg_lsw; 2011 u_int8_t chip_irq; 2012 2013 2014 if (bus_type & ASC_IS_EISA) { 2015 /* 2016 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq = 2017 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) || 2018 * (chip_irq > 15)) return (0); return(chip_irq); 2019 */ 2020 } 2021 if ((bus_type & ASC_IS_VL) != 0) { 2022 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2023 chip_irq = (cfg_lsw >> 2) & 0x07; 2024 if ((chip_irq == 0) || 2025 (chip_irq == 4) || 2026 (chip_irq == 7)) { 2027 return (0); 2028 } 2029 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2030 } 2031 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2032 chip_irq = (cfg_lsw >> 2) & 0x03; 2033 if (chip_irq == 3) 2034 chip_irq += 2; 2035 return (chip_irq + ASC_MIN_IRQ_NO); 2036 } 2037 2038 2039 static u_int8_t 2040 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2041 bus_space_tag_t iot; 2042 bus_space_handle_t ioh; 2043 u_int8_t irq_no; 2044 u_int16_t bus_type; 2045 { 2046 u_int16_t cfg_lsw; 2047 2048 2049 if (bus_type & ASC_IS_VL) { 2050 if (irq_no) { 2051 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2052 irq_no = 0; 2053 else 2054 irq_no -= ASC_MIN_IRQ_NO - 1; 2055 } 2056 2057 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2058 cfg_lsw |= 0x0010; 2059 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2060 AscToggleIRQAct(iot, ioh); 2061 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2062 cfg_lsw |= (irq_no & 0x07) << 2; 2063 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2064 AscToggleIRQAct(iot, ioh); 2065 2066 return (AscGetChipIRQ(iot, ioh, bus_type)); 2067 } 2068 if (bus_type & ASC_IS_ISA) { 2069 if (irq_no == 15) 2070 irq_no -= 2; 2071 irq_no -= ASC_MIN_IRQ_NO; 2072 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2073 cfg_lsw |= (irq_no & 0x03) << 2; 2074 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2075 2076 return (AscGetChipIRQ(iot, ioh, bus_type)); 2077 } 2078 return (0); 2079 } 2080 2081 2082 static void 2083 AscAckInterrupt(iot, ioh) 2084 bus_space_tag_t iot; 2085 bus_space_handle_t ioh; 2086 { 2087 u_int8_t host_flag; 2088 u_int8_t risc_flag; 2089 u_int16_t loop; 2090 2091 2092 loop = 0; 2093 do { 2094 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2095 if (loop++ > 0x7FFF) 2096 break; 2097 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2098 2099 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2100 (~ASC_HOST_FLAG_ACK_INT); 2101 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2102 host_flag | ASC_HOST_FLAG_ACK_INT); 2103 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2104 2105 loop = 0; 2106 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2107 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2108 if (loop++ > 3) 2109 break; 2110 } 2111 2112 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2113 } 2114 2115 2116 static u_int32_t 2117 AscGetMaxDmaCount(bus_type) 2118 u_int16_t bus_type; 2119 { 2120 if (bus_type & ASC_IS_ISA) 2121 return (ASC_MAX_ISA_DMA_COUNT); 2122 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2123 return (ASC_MAX_VL_DMA_COUNT); 2124 return (ASC_MAX_PCI_DMA_COUNT); 2125 } 2126 2127 2128 static u_int16_t 2129 AscGetIsaDmaChannel(iot, ioh) 2130 bus_space_tag_t iot; 2131 bus_space_handle_t ioh; 2132 { 2133 u_int16_t channel; 2134 2135 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2136 if (channel == 0x03) 2137 return (0); 2138 else if (channel == 0x00) 2139 return (7); 2140 return (channel + 4); 2141 } 2142 2143 2144 static u_int16_t 2145 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2146 bus_space_tag_t iot; 2147 bus_space_handle_t ioh; 2148 u_int16_t dma_channel; 2149 { 2150 u_int16_t cfg_lsw; 2151 u_int8_t value; 2152 2153 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2154 if (dma_channel == 7) 2155 value = 0x00; 2156 else 2157 value = dma_channel - 4; 2158 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2159 cfg_lsw |= value; 2160 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2161 return (AscGetIsaDmaChannel(iot, ioh)); 2162 } 2163 return (0); 2164 } 2165 2166 2167 static u_int8_t 2168 AscGetIsaDmaSpeed(iot, ioh) 2169 bus_space_tag_t iot; 2170 bus_space_handle_t ioh; 2171 { 2172 u_int8_t speed_value; 2173 2174 AscSetBank(iot, ioh, 1); 2175 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2176 speed_value &= 0x07; 2177 AscSetBank(iot, ioh, 0); 2178 return (speed_value); 2179 } 2180 2181 2182 static u_int8_t 2183 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2184 bus_space_tag_t iot; 2185 bus_space_handle_t ioh; 2186 u_int8_t speed_value; 2187 { 2188 speed_value &= 0x07; 2189 AscSetBank(iot, ioh, 1); 2190 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2191 AscSetBank(iot, ioh, 0); 2192 return (AscGetIsaDmaSpeed(iot, ioh)); 2193 } 2194 2195 2196 /******************************************************************************/ 2197 /* Messages routines */ 2198 /******************************************************************************/ 2199 2200 2201 static void 2202 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2203 ASC_SOFTC *sc; 2204 u_int16_t halt_q_addr; 2205 u_int8_t q_cntl; 2206 ASC_SCSI_BIT_ID_TYPE target_id; 2207 int tid_no; 2208 u_int8_t asyn_sdtr; 2209 { 2210 bus_space_tag_t iot = sc->sc_iot; 2211 bus_space_handle_t ioh = sc->sc_ioh; 2212 EXT_MSG ext_msg; 2213 u_int8_t sdtr_data; 2214 int sdtr_accept; 2215 2216 2217 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2218 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2219 2220 if (ext_msg.msg_type == MS_EXTEND && 2221 ext_msg.msg_req == MS_SDTR_CODE && 2222 ext_msg.msg_len == MS_SDTR_LEN) { 2223 sdtr_accept = TRUE; 2224 2225 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2226 sdtr_accept = FALSE; 2227 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2228 } 2229 if ((ext_msg.xfer_period < 2230 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2231 (ext_msg.xfer_period > 2232 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2233 sdtr_accept = FALSE; 2234 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2235 } 2236 if (sdtr_accept) { 2237 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2238 ext_msg.req_ack_offset); 2239 if (sdtr_data == 0xFF) { 2240 q_cntl |= ASC_QC_MSG_OUT; 2241 sc->init_sdtr &= ~target_id; 2242 sc->sdtr_done &= ~target_id; 2243 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2244 sc->sdtr_data[tid_no] = asyn_sdtr; 2245 } 2246 } 2247 if (ext_msg.req_ack_offset == 0) { 2248 q_cntl &= ~ASC_QC_MSG_OUT; 2249 sc->init_sdtr &= ~target_id; 2250 sc->sdtr_done &= ~target_id; 2251 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2252 } else { 2253 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2254 q_cntl &= ~ASC_QC_MSG_OUT; 2255 sc->sdtr_done |= target_id; 2256 sc->init_sdtr |= target_id; 2257 sc->pci_fix_asyn_xfer &= ~target_id; 2258 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2259 ext_msg.req_ack_offset); 2260 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2261 sc->sdtr_data[tid_no] = sdtr_data; 2262 } else { 2263 q_cntl |= ASC_QC_MSG_OUT; 2264 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2265 ext_msg.req_ack_offset); 2266 sc->pci_fix_asyn_xfer &= ~target_id; 2267 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2268 ext_msg.req_ack_offset); 2269 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2270 sc->sdtr_data[tid_no] = sdtr_data; 2271 sc->sdtr_done |= target_id; 2272 sc->init_sdtr |= target_id; 2273 } 2274 } 2275 } else if (ext_msg.msg_type == MS_EXTEND && 2276 ext_msg.msg_req == MS_WDTR_CODE && 2277 ext_msg.msg_len == MS_WDTR_LEN) { 2278 ext_msg.wdtr_width = 0; 2279 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2280 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2281 q_cntl |= ASC_QC_MSG_OUT; 2282 } else { 2283 ext_msg.msg_type = M1_MSG_REJECT; 2284 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2285 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2286 q_cntl |= ASC_QC_MSG_OUT; 2287 } 2288 2289 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2290 } 2291 2292 2293 static u_int8_t 2294 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2295 ASC_SOFTC *sc; 2296 u_int8_t sdtr_period; 2297 u_int8_t sdtr_offset; 2298 { 2299 bus_space_tag_t iot = sc->sc_iot; 2300 bus_space_handle_t ioh = sc->sc_ioh; 2301 EXT_MSG sdtr_buf; 2302 u_int8_t sdtr_period_index; 2303 2304 2305 sdtr_buf.msg_type = MS_EXTEND; 2306 sdtr_buf.msg_len = MS_SDTR_LEN; 2307 sdtr_buf.msg_req = MS_SDTR_CODE; 2308 sdtr_buf.xfer_period = sdtr_period; 2309 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2310 sdtr_buf.req_ack_offset = sdtr_offset; 2311 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2312 sc->max_sdtr_index) { 2313 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2314 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2315 return ((sdtr_period_index << 4) | sdtr_offset); 2316 } else { 2317 sdtr_buf.req_ack_offset = 0; 2318 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2319 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2320 return (0); 2321 } 2322 } 2323 2324 2325 /******************************************************************************/ 2326 /* SDTR routines */ 2327 /******************************************************************************/ 2328 2329 2330 static void 2331 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2332 bus_space_tag_t iot; 2333 bus_space_handle_t ioh; 2334 u_int8_t sdtr_data; 2335 u_int8_t tid_no; 2336 { 2337 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2338 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2339 } 2340 2341 2342 static u_int8_t 2343 AscCalSDTRData(sc, sdtr_period, syn_offset) 2344 ASC_SOFTC *sc; 2345 u_int8_t sdtr_period; 2346 u_int8_t syn_offset; 2347 { 2348 u_int8_t byte; 2349 u_int8_t sdtr_period_ix; 2350 2351 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2352 if (sdtr_period_ix > sc->max_sdtr_index) 2353 return (0xFF); 2354 2355 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2356 return (byte); 2357 } 2358 2359 2360 static u_int8_t 2361 AscGetSynPeriodIndex(sc, syn_time) 2362 ASC_SOFTC *sc; 2363 u_int8_t syn_time; 2364 { 2365 u_int8_t *period_table; 2366 int max_index; 2367 int min_index; 2368 int i; 2369 2370 period_table = sc->sdtr_period_tbl; 2371 max_index = sc->max_sdtr_index; 2372 min_index = sc->host_init_sdtr_index; 2373 if ((syn_time <= period_table[max_index])) { 2374 for (i = min_index; i < (max_index - 1); i++) { 2375 if (syn_time <= period_table[i]) 2376 return (i); 2377 } 2378 2379 return (max_index); 2380 } else 2381 return (max_index + 1); 2382 } 2383 2384 2385 /******************************************************************************/ 2386 /* Queue routines */ 2387 /******************************************************************************/ 2388 2389 /* 2390 * Send a command to the board 2391 */ 2392 int 2393 AscExeScsiQueue(sc, scsiq) 2394 ASC_SOFTC *sc; 2395 ASC_SCSI_Q *scsiq; 2396 { 2397 bus_space_tag_t iot = sc->sc_iot; 2398 bus_space_handle_t ioh = sc->sc_ioh; 2399 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2400 int retval; 2401 int n_q_required; 2402 int disable_syn_offset_one_fix; 2403 int i; 2404 u_int32_t addr; 2405 u_int16_t sg_entry_cnt = 0; 2406 u_int16_t sg_entry_cnt_minus_one = 0; 2407 u_int8_t target_ix; 2408 u_int8_t tid_no; 2409 u_int8_t sdtr_data; 2410 u_int8_t extra_bytes; 2411 u_int8_t scsi_cmd; 2412 u_int32_t data_cnt; 2413 2414 2415 scsiq->q1.q_no = 0; 2416 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2417 scsiq->q1.extra_bytes = 0; 2418 2419 retval = ASC_BUSY; 2420 target_ix = scsiq->q2.target_ix; 2421 tid_no = ASC_TIX_TO_TID(target_ix); 2422 n_q_required = 1; 2423 2424 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2425 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2426 sc->sdtr_done &= ~scsiq->q1.target_id; 2427 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2428 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2429 (sc->max_sdtr_index - 1)], 2430 sdtr_data & ASC_SYN_MAX_OFFSET); 2431 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2432 } 2433 /* 2434 * if there is just one segment into S/G list then 2435 * map it as it was a single request, filling 2436 * data_addr and data_cnt of ASC_SCSIQ structure. 2437 */ 2438 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2439 sg_entry_cnt = sg_head->entry_cnt; 2440 2441 if (sg_entry_cnt < 1) 2442 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2443 sg_entry_cnt); 2444 2445 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2446 panic("AscExeScsiQueue: Queue with too many segs."); 2447 2448 if (sg_entry_cnt == 1) { 2449 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2450 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2451 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2452 } 2453 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2454 } 2455 scsi_cmd = scsiq->cdbptr[0]; 2456 disable_syn_offset_one_fix = FALSE; 2457 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2458 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2459 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2460 data_cnt = 0; 2461 for (i = 0; i < sg_entry_cnt; i++) 2462 data_cnt += sg_head->sg_list[i].bytes; 2463 } else { 2464 data_cnt = scsiq->q1.data_cnt; 2465 } 2466 2467 if (data_cnt != 0ul) { 2468 if (data_cnt < 512ul) { 2469 disable_syn_offset_one_fix = TRUE; 2470 } else { 2471 if (scsi_cmd == SCSICMD_Inquiry || 2472 scsi_cmd == SCSICMD_RequestSense || 2473 scsi_cmd == SCSICMD_ReadCapacity || 2474 scsi_cmd == SCSICMD_ReadTOC || 2475 scsi_cmd == SCSICMD_ModeSelect6 || 2476 scsi_cmd == SCSICMD_ModeSense6 || 2477 scsi_cmd == SCSICMD_ModeSelect10 || 2478 scsi_cmd == SCSICMD_ModeSense10) { 2479 disable_syn_offset_one_fix = TRUE; 2480 } 2481 } 2482 } 2483 } 2484 if (disable_syn_offset_one_fix) { 2485 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2486 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2487 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2488 } else { 2489 scsiq->q2.tag_code &= 0x23; 2490 } 2491 2492 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2493 if (sc->bug_fix_cntl) { 2494 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2495 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2496 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2497 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2498 extra_bytes = addr & 0x0003; 2499 if ((extra_bytes != 0) && 2500 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2501 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2502 scsiq->q1.extra_bytes = extra_bytes; 2503 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2504 extra_bytes; 2505 } 2506 } 2507 } 2508 } 2509 sg_head->entry_to_copy = sg_head->entry_cnt; 2510 n_q_required = AscSgListToQueue(sg_entry_cnt); 2511 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2512 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2513 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2514 } 2515 } else { 2516 if (sc->bug_fix_cntl) { 2517 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2518 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2519 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2520 extra_bytes = addr & 0x0003; 2521 if ((extra_bytes != 0) && 2522 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2523 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2524 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2525 scsiq->q1.data_cnt -= extra_bytes; 2526 scsiq->q1.extra_bytes = extra_bytes; 2527 } 2528 } 2529 } 2530 } 2531 } 2532 n_q_required = 1; 2533 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2534 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2535 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2536 } 2537 } 2538 2539 return (retval); 2540 } 2541 2542 2543 static int 2544 AscSendScsiQueue(sc, scsiq, n_q_required) 2545 ASC_SOFTC *sc; 2546 ASC_SCSI_Q *scsiq; 2547 u_int8_t n_q_required; 2548 { 2549 bus_space_tag_t iot = sc->sc_iot; 2550 bus_space_handle_t ioh = sc->sc_ioh; 2551 u_int8_t free_q_head; 2552 u_int8_t next_qp; 2553 u_int8_t tid_no; 2554 u_int8_t target_ix; 2555 int retval; 2556 2557 2558 target_ix = scsiq->q2.target_ix; 2559 tid_no = ASC_TIX_TO_TID(target_ix); 2560 retval = ASC_BUSY; 2561 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2562 2563 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2564 != ASC_QLINK_END) { 2565 if (n_q_required > 1) { 2566 sc->last_q_shortage = 0; 2567 scsiq->sg_head->queue_cnt = n_q_required - 1; 2568 } 2569 scsiq->q1.q_no = free_q_head; 2570 2571 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2572 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2573 sc->cur_total_qng += n_q_required; 2574 sc->cur_dvc_qng[tid_no]++; 2575 } 2576 } 2577 return (retval); 2578 } 2579 2580 2581 static int 2582 AscPutReadySgListQueue(sc, scsiq, q_no) 2583 ASC_SOFTC *sc; 2584 ASC_SCSI_Q *scsiq; 2585 u_int8_t q_no; 2586 { 2587 bus_space_tag_t iot = sc->sc_iot; 2588 bus_space_handle_t ioh = sc->sc_ioh; 2589 int retval; 2590 int i; 2591 ASC_SG_HEAD *sg_head; 2592 ASC_SG_LIST_Q scsi_sg_q; 2593 u_int32_t saved_data_addr; 2594 u_int32_t saved_data_cnt; 2595 u_int16_t sg_list_dwords; 2596 u_int16_t sg_index; 2597 u_int16_t sg_entry_cnt; 2598 u_int16_t q_addr; 2599 u_int8_t next_qp; 2600 2601 2602 saved_data_addr = scsiq->q1.data_addr; 2603 saved_data_cnt = scsiq->q1.data_cnt; 2604 2605 if ((sg_head = scsiq->sg_head) != 0) { 2606 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2607 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2608 sg_entry_cnt = sg_head->entry_cnt - 1; 2609 if (sg_entry_cnt != 0) { 2610 q_addr = ASC_QNO_TO_QADDR(q_no); 2611 sg_index = 1; 2612 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2613 scsi_sg_q.sg_head_qp = q_no; 2614 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2615 2616 for (i = 0; i < sg_head->queue_cnt; i++) { 2617 scsi_sg_q.seq_no = i + 1; 2618 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2619 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2620 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2621 if (i == 0) { 2622 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2623 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2624 } else { 2625 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2626 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2627 } 2628 } else { 2629 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2630 sg_list_dwords = sg_entry_cnt << 1; 2631 if (i == 0) { 2632 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2633 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2634 } else { 2635 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2636 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2637 } 2638 2639 sg_entry_cnt = 0; 2640 } 2641 2642 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2643 scsi_sg_q.q_no = next_qp; 2644 q_addr = ASC_QNO_TO_QADDR(next_qp); 2645 2646 /* 2647 * Tell the board how many entries are in the S/G list 2648 */ 2649 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2650 (u_int16_t *) & scsi_sg_q, sizeof(ASC_SG_LIST_Q) >> 1); 2651 /* 2652 * Tell the board the addresses of the S/G list segments 2653 */ 2654 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2655 (u_int32_t *) & sg_head->sg_list[sg_index], sg_list_dwords); 2656 sg_index += ASC_SG_LIST_PER_Q; 2657 } 2658 } 2659 } 2660 retval = AscPutReadyQueue(sc, scsiq, q_no); 2661 scsiq->q1.data_addr = saved_data_addr; 2662 scsiq->q1.data_cnt = saved_data_cnt; 2663 return (retval); 2664 } 2665 2666 2667 static int 2668 AscPutReadyQueue(sc, scsiq, q_no) 2669 ASC_SOFTC *sc; 2670 ASC_SCSI_Q *scsiq; 2671 u_int8_t q_no; 2672 { 2673 bus_space_tag_t iot = sc->sc_iot; 2674 bus_space_handle_t ioh = sc->sc_ioh; 2675 u_int16_t q_addr; 2676 u_int8_t tid_no; 2677 u_int8_t sdtr_data; 2678 u_int8_t syn_period_ix; 2679 u_int8_t syn_offset; 2680 2681 2682 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2683 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2684 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2685 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2686 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2687 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2688 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2689 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2690 } 2691 q_addr = ASC_QNO_TO_QADDR(q_no); 2692 2693 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2694 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2695 } 2696 scsiq->q1.status = ASC_QS_FREE; 2697 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2698 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2699 2700 DvcPutScsiQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, 2701 (u_int16_t *) & scsiq->q1.cntl, 2702 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 2703 2704 /* 2705 * Let's start the command 2706 */ 2707 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2708 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2709 2710 return (ASC_NOERROR); 2711 } 2712 2713 2714 static int 2715 AscSgListToQueue(sg_list) 2716 int sg_list; 2717 { 2718 int n_sg_list_qs; 2719 2720 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2721 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2722 n_sg_list_qs++; 2723 2724 return (n_sg_list_qs + 1); 2725 } 2726 2727 2728 static u_int 2729 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2730 ASC_SOFTC *sc; 2731 u_int8_t target_ix; 2732 u_int8_t n_qs; 2733 { 2734 u_int cur_used_qs; 2735 u_int cur_free_qs; 2736 2737 2738 if (n_qs == 1) { 2739 cur_used_qs = sc->cur_total_qng + 2740 sc->last_q_shortage + 2741 ASC_MIN_FREE_Q; 2742 } else { 2743 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2744 } 2745 2746 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2747 cur_free_qs = sc->max_total_qng - cur_used_qs; 2748 return (cur_free_qs); 2749 } 2750 if (n_qs > 1) 2751 if ((n_qs > sc->last_q_shortage) && 2752 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2753 sc->last_q_shortage = n_qs; 2754 } 2755 return (0); 2756 } 2757 2758 2759 static u_int8_t 2760 AscAllocFreeQueue(iot, ioh, free_q_head) 2761 bus_space_tag_t iot; 2762 bus_space_handle_t ioh; 2763 u_int8_t free_q_head; 2764 { 2765 u_int16_t q_addr; 2766 u_int8_t next_qp; 2767 u_int8_t q_status; 2768 2769 2770 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2771 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2772 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2773 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2774 return (next_qp); 2775 2776 return (ASC_QLINK_END); 2777 } 2778 2779 2780 static u_int8_t 2781 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2782 bus_space_tag_t iot; 2783 bus_space_handle_t ioh; 2784 u_int8_t free_q_head; 2785 u_int8_t n_free_q; 2786 { 2787 u_int8_t i; 2788 2789 for (i = 0; i < n_free_q; i++) { 2790 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2791 if (free_q_head == ASC_QLINK_END) 2792 break; 2793 } 2794 2795 return (free_q_head); 2796 } 2797 2798 2799 static int 2800 AscStopQueueExe(iot, ioh) 2801 bus_space_tag_t iot; 2802 bus_space_handle_t ioh; 2803 { 2804 int count = 0; 2805 2806 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2807 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2808 do { 2809 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2810 ASC_STOP_ACK_RISC_STOP) 2811 return (1); 2812 2813 DvcSleepMilliSecond(100); 2814 } while (count++ < 20); 2815 } 2816 return (0); 2817 } 2818 2819 2820 static void 2821 AscStartQueueExe(iot, ioh) 2822 bus_space_tag_t iot; 2823 bus_space_handle_t ioh; 2824 { 2825 2826 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2827 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2828 } 2829 2830 2831 static void 2832 AscCleanUpBusyQueue(iot, ioh) 2833 bus_space_tag_t iot; 2834 bus_space_handle_t ioh; 2835 { 2836 int count = 0; 2837 u_int8_t stop_code; 2838 2839 2840 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2841 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2842 do { 2843 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2844 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2845 break; 2846 2847 DvcSleepMilliSecond(100); 2848 } while (count++ < 20); 2849 } 2850 } 2851 2852 2853 static int 2854 _AscWaitQDone(iot, ioh, scsiq) 2855 bus_space_tag_t iot; 2856 bus_space_handle_t ioh; 2857 ASC_SCSI_Q *scsiq; 2858 { 2859 u_int16_t q_addr; 2860 u_int8_t q_status; 2861 int count = 0; 2862 2863 while (scsiq->q1.q_no == 0); 2864 2865 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2866 do { 2867 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2868 DvcSleepMilliSecond(100L); 2869 if (count++ > 30) 2870 return (0); 2871 2872 } while ((q_status & ASC_QS_READY) != 0); 2873 2874 return (1); 2875 } 2876 2877 2878 static int 2879 AscCleanUpDiscQueue(iot, ioh) 2880 bus_space_tag_t iot; 2881 bus_space_handle_t ioh; 2882 { 2883 int count; 2884 u_int8_t stop_code; 2885 2886 count = 0; 2887 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2888 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 2889 do { 2890 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2891 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 2892 break; 2893 2894 DvcSleepMilliSecond(100); 2895 } while (count++ < 20); 2896 } 2897 return (1); 2898 } 2899 2900 2901 /******************************************************************************/ 2902 /* Abort and Reset CCB routines */ 2903 /******************************************************************************/ 2904 2905 2906 int 2907 AscAbortCCB(sc, ccb) 2908 ASC_SOFTC *sc; 2909 u_int32_t ccb; 2910 { 2911 bus_space_tag_t iot = sc->sc_iot; 2912 bus_space_handle_t ioh = sc->sc_ioh; 2913 int retval; 2914 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 2915 2916 2917 retval = -1; 2918 saved_unit_not_ready = sc->unit_not_ready; 2919 sc->unit_not_ready = 0xFF; 2920 AscWaitISRDone(sc); 2921 if (AscStopQueueExe(iot, ioh) == 1) { 2922 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 2923 retval = 1; 2924 AscCleanUpBusyQueue(iot, ioh); 2925 AscStartQueueExe(iot, ioh); 2926 } else { 2927 retval = 0; 2928 AscStartQueueExe(iot, ioh); 2929 } 2930 } 2931 sc->unit_not_ready = saved_unit_not_ready; 2932 2933 return (retval); 2934 } 2935 2936 2937 static int 2938 AscRiscHaltedAbortCCB(sc, ccb) 2939 ASC_SOFTC *sc; 2940 u_int32_t ccb; 2941 { 2942 bus_space_tag_t iot = sc->sc_iot; 2943 bus_space_handle_t ioh = sc->sc_ioh; 2944 u_int16_t q_addr; 2945 u_int8_t q_no; 2946 ASC_QDONE_INFO scsiq_buf; 2947 ASC_QDONE_INFO *scsiq; 2948 ASC_ISR_CALLBACK asc_isr_callback; 2949 int last_int_level; 2950 2951 2952 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2953 last_int_level = DvcEnterCritical(); 2954 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2955 2956 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 2957 q_addr = ASC_QNO_TO_QADDR(q_no); 2958 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 2959 q_addr + ASC_SCSIQ_D_CCBPTR); 2960 if (scsiq->d2.ccb_ptr == ccb) { 2961 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 2962 if (((scsiq->q_status & ASC_QS_READY) != 0) 2963 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 2964 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 2965 scsiq->q_status |= ASC_QS_ABORTED; 2966 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 2967 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 2968 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2969 scsiq->q_status); 2970 (*asc_isr_callback) (sc, scsiq); 2971 return (1); 2972 } 2973 } 2974 } 2975 2976 DvcLeaveCritical(last_int_level); 2977 return (0); 2978 } 2979 2980 2981 static int 2982 AscRiscHaltedAbortTIX(sc, target_ix) 2983 ASC_SOFTC *sc; 2984 u_int8_t target_ix; 2985 { 2986 bus_space_tag_t iot = sc->sc_iot; 2987 bus_space_handle_t ioh = sc->sc_ioh; 2988 u_int16_t q_addr; 2989 u_int8_t q_no; 2990 ASC_QDONE_INFO scsiq_buf; 2991 ASC_QDONE_INFO *scsiq; 2992 ASC_ISR_CALLBACK asc_isr_callback; 2993 int last_int_level; 2994 2995 2996 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 2997 last_int_level = DvcEnterCritical(); 2998 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 2999 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3000 q_addr = ASC_QNO_TO_QADDR(q_no); 3001 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3002 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3003 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3004 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3005 if (scsiq->d2.target_ix == target_ix) { 3006 scsiq->q_status |= ASC_QS_ABORTED; 3007 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3008 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3009 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3010 scsiq->q_status); 3011 (*asc_isr_callback) (sc, scsiq); 3012 } 3013 } 3014 } 3015 DvcLeaveCritical(last_int_level); 3016 return (1); 3017 } 3018 3019 3020 /* 3021 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3022 * so we cannot use this function with the actual NetBSD SCSI layer 3023 * because at boot time interrupts are disabled. 3024 */ 3025 int 3026 AscResetDevice(sc, target_ix) 3027 ASC_SOFTC *sc; 3028 u_char target_ix; 3029 { 3030 bus_space_tag_t iot = sc->sc_iot; 3031 bus_space_handle_t ioh = sc->sc_ioh; 3032 int retval; 3033 u_int8_t tid_no; 3034 ASC_SCSI_BIT_ID_TYPE target_id; 3035 int i; 3036 ASC_SCSI_REQ_Q scsiq_buf; 3037 ASC_SCSI_REQ_Q *scsiq; 3038 u_int8_t *buf; 3039 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3040 3041 3042 tid_no = ASC_TIX_TO_TID(target_ix); 3043 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3044 saved_unit_not_ready = sc->unit_not_ready; 3045 sc->unit_not_ready = target_id; 3046 retval = ASC_ERROR; 3047 3048 AscWaitTixISRDone(sc, target_ix); 3049 3050 if (AscStopQueueExe(iot, ioh) == 1) { 3051 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3052 AscCleanUpBusyQueue(iot, ioh); 3053 AscStartQueueExe(iot, ioh); 3054 AscWaitTixISRDone(sc, target_ix); 3055 retval = ASC_NOERROR; 3056 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3057 buf = (u_char *) & scsiq_buf; 3058 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3059 *buf++ = 0x00; 3060 scsiq->q1.status = (u_char) ASC_QS_READY; 3061 scsiq->q2.cdb_len = 6; 3062 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3063 scsiq->q1.target_id = target_id; 3064 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3065 scsiq->cdbptr = (u_int8_t *) scsiq->cdb; 3066 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3067 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3068 sc->unit_not_ready &= ~target_id; 3069 sc->sdtr_done |= target_id; 3070 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3071 sc->unit_not_ready = target_id; 3072 DvcSleepMilliSecond(1000); 3073 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3074 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3075 AscCleanUpDiscQueue(iot, ioh); 3076 AscStartQueueExe(iot, ioh); 3077 if (sc->pci_fix_asyn_xfer & target_id) 3078 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3079 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3080 AscWaitTixISRDone(sc, target_ix); 3081 } 3082 } else 3083 retval = ASC_BUSY; 3084 sc->sdtr_done &= ~target_id; 3085 } else { 3086 retval = ASC_ERROR; 3087 AscStartQueueExe(iot, ioh); 3088 } 3089 } 3090 sc->unit_not_ready = saved_unit_not_ready; 3091 return (retval); 3092 } 3093 3094 3095 int 3096 AscResetBus(sc) 3097 ASC_SOFTC *sc; 3098 { 3099 bus_space_tag_t iot = sc->sc_iot; 3100 bus_space_handle_t ioh = sc->sc_ioh; 3101 int retval; 3102 int i; 3103 3104 3105 sc->unit_not_ready = 0xFF; 3106 retval = ASC_NOERROR; 3107 3108 AscWaitISRDone(sc); 3109 AscStopQueueExe(iot, ioh); 3110 sc->sdtr_done = 0; 3111 AscResetChipAndScsiBus(iot, ioh); 3112 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3113 AscReInitLram(sc); 3114 for (i = 0; i <= ASC_MAX_TID; i++) { 3115 sc->cur_dvc_qng[i] = 0; 3116 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3117 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3118 } 3119 3120 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3121 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3122 retval = ASC_ERROR; 3123 3124 if (AscStartChip(iot, ioh) == 0) 3125 retval = ASC_ERROR; 3126 3127 AscStartQueueExe(iot, ioh); 3128 sc->unit_not_ready = 0; 3129 sc->queue_full_or_busy = 0; 3130 return (retval); 3131 } 3132 3133 3134 /******************************************************************************/ 3135 /* Error Handling routines */ 3136 /******************************************************************************/ 3137 3138 3139 static int 3140 AscSetLibErrorCode(sc, err_code) 3141 ASC_SOFTC *sc; 3142 u_int16_t err_code; 3143 { 3144 /* 3145 * if(sc->err_code == 0) { sc->err_code = err_code; 3146 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3147 err_code); 3148 /* 3149 * } 3150 */ 3151 return (err_code); 3152 } 3153 3154 3155 /******************************************************************************/ 3156 /* Handle bugged borads routines */ 3157 /******************************************************************************/ 3158 3159 3160 void 3161 AscInquiryHandling(sc, tid_no, inq) 3162 ASC_SOFTC *sc; 3163 u_int8_t tid_no; 3164 ASC_SCSI_INQUIRY *inq; 3165 { 3166 bus_space_tag_t iot = sc->sc_iot; 3167 bus_space_handle_t ioh = sc->sc_ioh; 3168 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3169 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3170 3171 3172 orig_init_sdtr = sc->init_sdtr; 3173 orig_use_tagged_qng = sc->use_tagged_qng; 3174 3175 sc->init_sdtr &= ~tid_bit; 3176 sc->can_tagged_qng &= ~tid_bit; 3177 sc->use_tagged_qng &= ~tid_bit; 3178 3179 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3180 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3181 sc->init_sdtr |= tid_bit; 3182 3183 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3184 if (AscTagQueuingSafe(inq)) { 3185 sc->use_tagged_qng |= tid_bit; 3186 sc->can_tagged_qng |= tid_bit; 3187 } 3188 } 3189 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3190 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3191 sc->disc_enable); 3192 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3193 sc->use_tagged_qng); 3194 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3195 sc->can_tagged_qng); 3196 3197 sc->max_dvc_qng[tid_no] = 3198 sc->max_tag_qng[tid_no]; 3199 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3200 sc->max_dvc_qng[tid_no]); 3201 } 3202 if (orig_init_sdtr != sc->init_sdtr) 3203 AscAsyncFix(sc, tid_no, inq); 3204 } 3205 3206 3207 static int 3208 AscTagQueuingSafe(inq) 3209 ASC_SCSI_INQUIRY *inq; 3210 { 3211 if ((inq->add_len >= 32) && 3212 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3213 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3214 return 0; 3215 } 3216 return 1; 3217 } 3218 3219 3220 static void 3221 AscAsyncFix(sc, tid_no, inq) 3222 ASC_SOFTC *sc; 3223 u_int8_t tid_no; 3224 ASC_SCSI_INQUIRY *inq; 3225 { 3226 u_int8_t dvc_type; 3227 ASC_SCSI_BIT_ID_TYPE tid_bits; 3228 3229 3230 dvc_type = inq->byte0.peri_dvc_type; 3231 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3232 3233 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3234 if (!(sc->init_sdtr & tid_bits)) { 3235 if ((dvc_type == SCSI_TYPE_CDROM) && 3236 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3237 sc->pci_fix_asyn_xfer_always |= tid_bits; 3238 } 3239 sc->pci_fix_asyn_xfer |= tid_bits; 3240 if ((dvc_type == SCSI_TYPE_PROC) || 3241 (dvc_type == SCSI_TYPE_SCANNER)) { 3242 sc->pci_fix_asyn_xfer &= ~tid_bits; 3243 } 3244 if ((dvc_type == SCSI_TYPE_SASD) && 3245 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3246 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3247 sc->pci_fix_asyn_xfer &= ~tid_bits; 3248 } 3249 if ((dvc_type == SCSI_TYPE_SASD) && 3250 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3251 sc->pci_fix_asyn_xfer &= ~tid_bits; 3252 } 3253 if ((dvc_type == SCSI_TYPE_CDROM) && 3254 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3255 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3256 sc->pci_fix_asyn_xfer &= ~tid_bits; 3257 } 3258 if ((dvc_type == SCSI_TYPE_CDROM) && 3259 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3260 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3261 sc->pci_fix_asyn_xfer &= ~tid_bits; 3262 } 3263 if (sc->pci_fix_asyn_xfer & tid_bits) { 3264 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3265 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3266 } 3267 } 3268 } 3269 } 3270 3271 3272 /******************************************************************************/ 3273 /* Miscellaneous routines */ 3274 /******************************************************************************/ 3275 3276 3277 static int 3278 AscCompareString(str1, str2, len) 3279 u_char *str1; 3280 u_char *str2; 3281 int len; 3282 { 3283 int i; 3284 int diff; 3285 3286 for (i = 0; i < len; i++) { 3287 diff = (int) (str1[i] - str2[i]); 3288 if (diff != 0) 3289 return (diff); 3290 } 3291 3292 return (0); 3293 } 3294 3295 3296 /******************************************************************************/ 3297 /* Device oriented routines */ 3298 /******************************************************************************/ 3299 3300 3301 static int 3302 DvcEnterCritical(void) 3303 { 3304 int s; 3305 3306 s = splbio(); 3307 return (s); 3308 } 3309 3310 3311 static void 3312 DvcLeaveCritical(s) 3313 int s; 3314 { 3315 3316 splx(s); 3317 } 3318 3319 3320 static void 3321 DvcSleepMilliSecond(n) 3322 u_int32_t n; 3323 { 3324 3325 DELAY(n * 1000); 3326 } 3327 3328 #ifdef UNUSED 3329 static void 3330 DvcDelayMicroSecond(n) 3331 u_int32_t n; 3332 { 3333 3334 DELAY(n); 3335 } 3336 #endif 3337 3338 static void 3339 DvcDelayNanoSecond(n) 3340 u_int32_t n; 3341 { 3342 3343 DELAY((n + 999) / 1000); 3344 } 3345 3346 3347 static u_int32_t 3348 DvcGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 3349 ASC_SOFTC *sc; 3350 u_int8_t *buf_addr; 3351 u_int32_t buf_len; 3352 ASC_SG_HEAD *asc_sg_head_ptr; 3353 { 3354 u_int32_t buf_size; 3355 3356 buf_size = buf_len; 3357 asc_sg_head_ptr->entry_cnt = 1; 3358 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 3359 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 3360 3361 return (buf_size); 3362 } 3363 3364 3365 static void 3366 DvcPutScsiQ(iot, ioh, s_addr, outbuf, words) 3367 bus_space_tag_t iot; 3368 bus_space_handle_t ioh; 3369 u_int16_t s_addr; 3370 u_int16_t *outbuf; 3371 int words; 3372 { 3373 int i; 3374 3375 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 3376 for (i = 0; i < words; i++, outbuf++) { 3377 if (i == 2 || i == 10) 3378 continue; 3379 3380 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *outbuf); 3381 } 3382 } 3383 3384 3385 static void 3386 DvcGetQinfo(iot, ioh, s_addr, inbuf, words) 3387 bus_space_tag_t iot; 3388 bus_space_handle_t ioh; 3389 u_int16_t s_addr; 3390 u_int16_t *inbuf; 3391 int words; 3392 { 3393 int i; 3394 3395 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 3396 for (i = 0; i < words; i++, inbuf++) { 3397 if (i == 5) 3398 continue; 3399 3400 *inbuf = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 3401 } 3402 } 3403
Indexes created Tue Sep 23 23:09:58 GMT 2025