advlib.c revision 1.8.4.1
1 /* $NetBSD: advlib.c,v 1.8.4.1 1999/06/21 01:17:39 thorpej Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/scsipi/scsi_all.h> 67 #include <dev/scsipi/scsipi_all.h> 68 #include <dev/scsipi/scsiconf.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_param.h> 72 #include <vm/pmap.h> 73 74 #include <dev/ic/advlib.h> 75 #include <dev/ic/adv.h> 76 #include <dev/ic/advmcode.h> 77 78 79 /* #define ASC_DEBUG */ 80 81 /******************************************************************************/ 82 /* Static functions */ 83 /******************************************************************************/ 84 85 /* Initializzation routines */ 86 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 87 u_int16_t, u_int16_t *, u_int16_t)); 88 static void AscInitLram __P((ASC_SOFTC *)); 89 static void AscInitQLinkVar __P((ASC_SOFTC *)); 90 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 91 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 92 /* 93 static u_int16_t AscGetEisaChipCfg __P((bus_space_tag_t, bus_space_handle_t)); 94 */ 95 /* Chip register routines */ 96 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 97 98 /* RISC Chip routines */ 99 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 100 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 101 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 102 u_int8_t)); 103 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 104 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 105 u_int8_t, u_int8_t)); 106 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 107 u_int8_t, u_int8_t)); 108 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 109 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 110 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 111 112 /* Lram routines */ 113 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t)); 115 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int8_t)); 117 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t)); 119 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int16_t)); 121 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t)); 123 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int32_t)); 125 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t, int)); 127 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int)); 129 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int16_t *, int)); 131 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, u_int32_t *, int)); 133 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 134 u_int16_t, int)); 135 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 136 137 /* MicroCode routines */ 138 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 139 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 140 static u_int32_t AscGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 141 ASC_SG_HEAD *)); 142 143 /* EEProm routines */ 144 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 145 u_int8_t)); 146 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 147 u_int16_t)); 148 static void AscWaitEEPRead __P((void)); 149 static void AscWaitEEPWrite __P((void)); 150 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 151 u_int8_t)); 152 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 153 u_int8_t, u_int16_t)); 154 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 155 ASCEEP_CONFIG *, u_int16_t)); 156 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 157 ASCEEP_CONFIG *, u_int16_t)); 158 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 159 ASCEEP_CONFIG *, u_int16_t)); 160 #ifdef ASC_DEBUG 161 static void AscPrintEEPConfig __P((ASCEEP_CONFIG *, u_int16_t)); 162 #endif 163 164 /* Interrupt routines */ 165 static void AscIsrChipHalted __P((ASC_SOFTC *)); 166 static int AscIsrQDone __P((ASC_SOFTC *)); 167 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 168 static int AscWaitISRDone __P((ASC_SOFTC *)); 169 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 170 u_int16_t, ASC_QDONE_INFO *, 171 u_int32_t)); 172 static void AscGetQDoneInfo __P((bus_space_tag_t, bus_space_handle_t, u_int16_t, 173 ASC_QDONE_INFO *)); 174 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 175 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 176 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 177 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 178 u_int8_t, u_int16_t)); 179 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 180 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 181 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 182 u_int16_t)); 183 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 184 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 185 u_int8_t)); 186 187 /* Messages routines */ 188 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 189 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 190 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 191 192 /* SDTR routines */ 193 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 194 u_int8_t, u_int8_t)); 195 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 196 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 197 198 /* Queue routines */ 199 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 200 static int AscSgListToQueue __P((int)); 201 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 202 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 203 static void AscPutSCSIQ __P((bus_space_tag_t, bus_space_handle_t, 204 u_int16_t, ASC_SCSI_Q *)); 205 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 206 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 207 u_int8_t)); 208 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 209 bus_space_handle_t, 210 u_int8_t, u_int8_t)); 211 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 212 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 213 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 214 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 215 ASC_SCSI_Q *)); 216 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 217 218 /* Abort and Reset CCB routines */ 219 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, ADV_CCB *)); 220 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 221 222 /* Error Handling routines */ 223 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 224 225 /* Handle bugged borads routines */ 226 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 227 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 228 229 /* Miscellaneous routines */ 230 static int AscCompareString __P((u_char *, u_char *, int)); 231 232 /* Device oriented routines */ 233 static int DvcEnterCritical __P((void)); 234 static void DvcLeaveCritical __P((int)); 235 static void DvcSleepMilliSecond __P((u_int32_t)); 236 //static void DvcDelayMicroSecond __P((u_int32_t)); 237 static void DvcDelayNanoSecond __P((u_int32_t)); 238 239 240 /******************************************************************************/ 241 /* Initializzation routines */ 242 /******************************************************************************/ 243 244 /* 245 * This function perform the following steps: 246 * - initialize ASC_SOFTC structure with defaults values. 247 * - inquire board registers to know what kind of board it is. 248 * - keep track of bugged borads. 249 */ 250 void 251 AscInitASC_SOFTC(sc) 252 ASC_SOFTC *sc; 253 { 254 bus_space_tag_t iot = sc->sc_iot; 255 bus_space_handle_t ioh = sc->sc_ioh; 256 int i; 257 258 259 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 260 ASC_SET_CHIP_STATUS(iot, ioh, 0); 261 262 sc->bug_fix_cntl = 0; 263 sc->pci_fix_asyn_xfer = 0; 264 sc->pci_fix_asyn_xfer_always = 0; 265 sc->sdtr_done = 0; 266 sc->cur_total_qng = 0; 267 sc->last_q_shortage = 0; 268 sc->use_tagged_qng = 0; 269 sc->unit_not_ready = 0; 270 sc->queue_full_or_busy = 0; 271 sc->host_init_sdtr_index = 0; 272 sc->can_tagged_qng = 0; 273 sc->cmd_qng_enabled = 0; 274 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 275 sc->init_sdtr = 0; 276 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 277 sc->scsi_reset_wait = 3; 278 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 279 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 280 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 281 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 282 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 283 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 284 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 285 if ((sc->bus_type & ASC_IS_PCI) && 286 (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 287 sc->bus_type = ASC_IS_PCI_ULTRA; 288 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 289 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 290 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 291 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 292 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 293 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 294 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 295 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 296 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 297 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 298 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 299 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 300 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 301 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 302 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 303 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 304 sc->max_sdtr_index = 15; 305 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 306 ASC_SET_EXTRA_CONTROL(iot, ioh, 307 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 308 else if (sc->chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 309 ASC_SET_EXTRA_CONTROL(iot, ioh, 310 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 311 } else { 312 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 313 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 314 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 315 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 316 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 317 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 318 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 319 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 320 sc->max_sdtr_index = 7; 321 } 322 323 if (sc->bus_type == ASC_IS_PCI) 324 ASC_SET_EXTRA_CONTROL(iot, ioh, 325 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 326 327 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 328 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 329 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 330 sc->bus_type = ASC_IS_ISAPNP; 331 } 332 if ((sc->bus_type & ASC_IS_ISA) != 0) 333 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 334 335 for (i = 0; i <= ASC_MAX_TID; i++) { 336 sc->cur_dvc_qng[i] = 0; 337 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 338 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 339 } 340 } 341 342 343 /* 344 * This function initialize some ASC_SOFTC fields with values read from 345 * on-board EEProm. 346 */ 347 int16_t 348 AscInitFromEEP(sc) 349 ASC_SOFTC *sc; 350 { 351 bus_space_tag_t iot = sc->sc_iot; 352 bus_space_handle_t ioh = sc->sc_ioh; 353 ASCEEP_CONFIG eep_config_buf; 354 ASCEEP_CONFIG *eep_config; 355 u_int16_t chksum; 356 u_int16_t warn_code; 357 u_int16_t cfg_msw, cfg_lsw; 358 int i; 359 int write_eep = 0; 360 361 362 warn_code = 0; 363 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 364 AscStopQueueExe(iot, ioh); 365 366 AscStopChip(iot, ioh); 367 AscResetChipAndScsiBus(iot, ioh); 368 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 369 370 if ((AscStopChip(iot, ioh) == FALSE) || 371 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 372 AscResetChipAndScsiBus(iot, ioh); 373 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 374 } 375 if (AscIsChipHalted(iot, ioh) == FALSE) 376 return (-1); 377 378 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 379 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 380 return (-2); 381 382 eep_config = &eep_config_buf; 383 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 384 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 385 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 386 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 387 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 388 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 389 } 390 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 391 #ifdef ASC_DEBUG 392 AscPrintEEPConfig(eep_config, chksum); 393 #endif 394 if (chksum == 0) 395 chksum = 0xAA55; 396 397 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 398 warn_code |= ASC_WARN_AUTO_CONFIG; 399 if (sc->chip_version == 3) { 400 if (eep_config->cfg_lsw != cfg_lsw) { 401 warn_code |= ASC_WARN_EEPROM_RECOVER; 402 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 403 } 404 if (eep_config->cfg_msw != cfg_msw) { 405 warn_code |= ASC_WARN_EEPROM_RECOVER; 406 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 407 } 408 } 409 } 410 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 411 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 412 413 if (chksum != eep_config->chksum) { 414 if (sc->chip_version == ASC_CHIP_VER_PCI_ULTRA_3050) { 415 eep_config->init_sdtr = 0xFF; 416 eep_config->disc_enable = 0xFF; 417 eep_config->start_motor = 0xFF; 418 eep_config->use_cmd_qng = 0; 419 eep_config->max_total_qng = 0xF0; 420 eep_config->max_tag_qng = 0x20; 421 eep_config->cntl = 0xBFFF; 422 eep_config->chip_scsi_id = 7; 423 eep_config->no_scam = 0; 424 eep_config->adapter_info[0] = 0; 425 eep_config->adapter_info[1] = 0; 426 eep_config->adapter_info[2] = 0; 427 eep_config->adapter_info[3] = 0; 428 #if BYTE_ORDER == BIG_ENDIAN 429 eep_config->adapter_info[5] = 0; 430 /* Indicate EEPROM-less board. */ 431 eep_config->adapter_info[4] = 0xBB; 432 #else 433 eep_config->adapter_info[4] = 0; 434 /* Indicate EEPROM-less board. */ 435 eep_config->adapter_info[5] = 0xBB; 436 #endif 437 } else { 438 write_eep = 1; 439 warn_code |= ASC_WARN_EEPROM_CHKSUM; 440 } 441 } 442 sc->sdtr_enable = eep_config->init_sdtr; 443 sc->disc_enable = eep_config->disc_enable; 444 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 445 sc->isa_dma_speed = eep_config->isa_dma_speed; 446 sc->start_motor = eep_config->start_motor; 447 sc->dvc_cntl = eep_config->cntl; 448 #if BYTE_ORDER == BIG_ENDIAN 449 sc->adapter_info[0] = eep_config->adapter_info[1]; 450 sc->adapter_info[1] = eep_config->adapter_info[0]; 451 sc->adapter_info[2] = eep_config->adapter_info[3]; 452 sc->adapter_info[3] = eep_config->adapter_info[2]; 453 sc->adapter_info[4] = eep_config->adapter_info[5]; 454 sc->adapter_info[5] = eep_config->adapter_info[4]; 455 #else 456 sc->adapter_info[0] = eep_config->adapter_info[0]; 457 sc->adapter_info[1] = eep_config->adapter_info[1]; 458 sc->adapter_info[2] = eep_config->adapter_info[2]; 459 sc->adapter_info[3] = eep_config->adapter_info[3]; 460 sc->adapter_info[4] = eep_config->adapter_info[4]; 461 sc->adapter_info[5] = eep_config->adapter_info[5]; 462 #endif 463 464 if (!AscTestExternalLram(iot, ioh)) { 465 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 466 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 467 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 468 } else { 469 eep_config->cfg_msw |= 0x0800; 470 cfg_msw |= 0x0800; 471 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 472 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 473 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 474 } 475 } 476 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 477 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 478 479 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 480 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 481 482 if (eep_config->max_tag_qng > eep_config->max_total_qng) 483 eep_config->max_tag_qng = eep_config->max_total_qng; 484 485 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 486 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 487 488 sc->max_total_qng = eep_config->max_total_qng; 489 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 490 eep_config->use_cmd_qng) { 491 eep_config->disc_enable = eep_config->use_cmd_qng; 492 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 493 } 494 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 495 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 496 497 eep_config->chip_scsi_id &= ASC_MAX_TID; 498 sc->chip_scsi_id = eep_config->chip_scsi_id; 499 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 500 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 501 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 502 } 503 for (i = 0; i <= ASC_MAX_TID; i++) { 504 sc->max_tag_qng[i] = eep_config->max_tag_qng; 505 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 506 (sc->host_init_sdtr_index << 4); 507 } 508 509 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 510 if (write_eep) { 511 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 512 #ifdef ASC_DEBUG 513 AscPrintEEPConfig(eep_config, 0); 514 #endif 515 } 516 517 return (warn_code); 518 } 519 520 521 u_int16_t 522 AscInitFromASC_SOFTC(sc) 523 ASC_SOFTC *sc; 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 u_int16_t cfg_msw; 528 u_int16_t warn_code; 529 u_int16_t pci_device_id = sc->pci_device_id; 530 531 532 warn_code = 0; 533 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 534 535 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 536 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 537 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 538 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 539 } 540 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 541 sc->disc_enable = sc->cmd_qng_enabled; 542 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 543 } 544 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 545 warn_code |= ASC_WARN_AUTO_CONFIG; 546 } 547 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 548 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 549 } 550 if (sc->bus_type & ASC_IS_PCI) { 551 cfg_msw &= 0xFFC0; 552 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 553 554 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 555 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 556 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 557 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 558 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 559 } 560 } 561 } else if (sc->bus_type == ASC_IS_ISAPNP) { 562 if (sc->chip_version == ASC_CHIP_VER_ASYN_BUG) { 563 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 564 } 565 } 566 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 567 568 if (sc->bus_type & ASC_IS_ISA) { 569 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 570 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 571 } 572 return (warn_code); 573 } 574 575 576 /* 577 * - Initialize RISC chip 578 * - Intialize Lram 579 * - Load uCode into Lram 580 * - Enable Interrupts 581 */ 582 int 583 AscInitDriver(sc) 584 ASC_SOFTC *sc; 585 { 586 bus_space_tag_t iot = sc->sc_iot; 587 bus_space_handle_t ioh = sc->sc_ioh; 588 u_int32_t chksum; 589 590 591 if (!AscFindSignature(iot, ioh)) 592 return (1); 593 594 AscDisableInterrupt(iot, ioh); 595 596 AscInitLram(sc); 597 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 598 asc_mcode_size); 599 if (chksum != asc_mcode_chksum) 600 return (2); 601 602 if (AscInitMicroCodeVar(sc) == 0) 603 return (3); 604 605 AscEnableInterrupt(iot, ioh); 606 607 return (0); 608 } 609 610 611 int 612 AscFindSignature(iot, ioh) 613 bus_space_tag_t iot; 614 bus_space_handle_t ioh; 615 { 616 u_int16_t sig_word; 617 618 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 619 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 620 if (sig_word == ASC_1000_ID0W || 621 sig_word == ASC_1000_ID0W_FIX) 622 return (1); 623 } 624 return (0); 625 } 626 627 628 static void 629 AscInitLram(sc) 630 ASC_SOFTC *sc; 631 { 632 bus_space_tag_t iot = sc->sc_iot; 633 bus_space_handle_t ioh = sc->sc_ioh; 634 u_int8_t i; 635 u_int16_t s_addr; 636 637 638 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 639 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 640 641 i = ASC_MIN_ACTIVE_QNO; 642 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 643 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 644 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 645 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 646 i++; 647 s_addr += ASC_QBLK_SIZE; 648 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 649 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 651 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 652 } 653 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 655 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 656 i++; 657 s_addr += ASC_QBLK_SIZE; 658 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 659 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 660 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 661 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 662 } 663 } 664 665 666 void 667 AscReInitLram(sc) 668 ASC_SOFTC *sc; 669 { 670 671 AscInitLram(sc); 672 AscInitQLinkVar(sc); 673 } 674 675 676 static void 677 AscInitQLinkVar(sc) 678 ASC_SOFTC *sc; 679 { 680 bus_space_tag_t iot = sc->sc_iot; 681 bus_space_handle_t ioh = sc->sc_ioh; 682 u_int8_t i; 683 u_int16_t lram_addr; 684 685 686 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 687 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 688 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 689 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 690 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 691 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 692 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 693 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 694 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 695 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 696 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 697 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 698 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 699 lram_addr = ASC_QADR_BEG; 700 for (i = 0; i < 32; i++, lram_addr += 2) 701 AscWriteLramWord(iot, ioh, lram_addr, 0); 702 } 703 704 705 static int 706 AscResetChipAndScsiBus(bus_space_tag_t iot, 707 bus_space_handle_t ioh) 708 { 709 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 710 711 AscStopChip(iot, ioh); 712 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 713 714 DvcDelayNanoSecond(60000); 715 716 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 717 AscSetChipIH(iot, ioh, ASC_INS_HALT); 718 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 719 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 720 721 DvcSleepMilliSecond(200); 722 723 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 724 AscStartChip(iot, ioh); 725 726 DvcSleepMilliSecond(200); 727 728 return (AscIsChipHalted(iot, ioh)); 729 } 730 731 732 static u_int16_t 733 AscGetChipBusType(iot, ioh) 734 bus_space_tag_t iot; 735 bus_space_handle_t ioh; 736 { 737 u_int16_t chip_ver; 738 739 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 740 /* if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 741 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 742 if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) { 743 return (ASC_IS_EISA); 744 } 745 else { 746 return (ASC_IS_VL); 747 } 748 } 749 */ if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 750 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 751 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 752 return (ASC_IS_ISAPNP); 753 754 return (ASC_IS_ISA); 755 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 756 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 757 return (ASC_IS_PCI); 758 759 return (0); 760 } 761 762 /* 763 static u_int16_t 764 AscGetEisaChipCfg(iot, ioh) 765 bus_space_tag_t iot; 766 bus_space_handle_t ioh; 767 { 768 int eisa_cfg_iop; 769 770 eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK); 771 return (inw(eisa_cfg_iop)); 772 } 773 */ 774 775 /******************************************************************************/ 776 /* Chip register routines */ 777 /******************************************************************************/ 778 779 780 static void 781 AscSetBank(iot, ioh, bank) 782 bus_space_tag_t iot; 783 bus_space_handle_t ioh; 784 u_int8_t bank; 785 { 786 u_int8_t val; 787 788 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 789 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 790 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 791 ASC_CC_CHIP_RESET)); 792 793 switch (bank) { 794 case 1: 795 val |= ASC_CC_BANK_ONE; 796 break; 797 798 case 2: 799 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 800 break; 801 802 default: 803 val &= ~ASC_CC_BANK_ONE; 804 } 805 806 ASC_SET_CHIP_CONTROL(iot, ioh, val); 807 return; 808 } 809 810 811 /******************************************************************************/ 812 /* Chip routines */ 813 /******************************************************************************/ 814 815 816 static int 817 AscStartChip(iot, ioh) 818 bus_space_tag_t iot; 819 bus_space_handle_t ioh; 820 { 821 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 822 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 823 return (0); 824 825 return (1); 826 } 827 828 829 static int 830 AscStopChip(iot, ioh) 831 bus_space_tag_t iot; 832 bus_space_handle_t ioh; 833 { 834 u_int8_t cc_val; 835 836 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 837 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 838 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 839 AscSetChipIH(iot, ioh, ASC_INS_HALT); 840 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 841 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 842 return (0); 843 844 return (1); 845 } 846 847 848 static u_int8_t 849 AscSetChipScsiID(iot, ioh, new_id) 850 bus_space_tag_t iot; 851 bus_space_handle_t ioh; 852 u_int8_t new_id; 853 { 854 u_int16_t cfg_lsw; 855 856 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 857 return (new_id); 858 859 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 860 cfg_lsw &= 0xF8FF; 861 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 862 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 863 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 864 } 865 866 867 static u_int8_t 868 AscGetChipScsiCtrl(iot, ioh) 869 bus_space_tag_t iot; 870 bus_space_handle_t ioh; 871 { 872 u_int8_t scsi_ctrl; 873 874 AscSetBank(iot, ioh, 1); 875 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 876 AscSetBank(iot, ioh, 0); 877 return (scsi_ctrl); 878 } 879 880 881 static int 882 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 883 bus_space_tag_t iot; 884 bus_space_handle_t ioh; 885 u_int8_t tid_no; 886 u_int8_t sdtr_data; 887 { 888 int retval = FALSE; 889 890 if (AscHostReqRiscHalt(iot, ioh)) { 891 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 892 AscStartChip(iot, ioh); 893 } 894 return (retval); 895 } 896 897 898 static int 899 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 900 bus_space_tag_t iot; 901 bus_space_handle_t ioh; 902 u_int8_t id; 903 u_int8_t sdtr_data; 904 { 905 ASC_SCSI_BIT_ID_TYPE org_id; 906 int i; 907 int sta = TRUE; 908 909 AscSetBank(iot, ioh, 1); 910 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 911 for (i = 0; i <= ASC_MAX_TID; i++) 912 if (org_id == (0x01 << i)) 913 break; 914 915 org_id = i; 916 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 917 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 918 AscSetBank(iot, ioh, 0); 919 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 920 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 921 sta = FALSE; 922 } else 923 sta = FALSE; 924 925 AscSetBank(iot, ioh, 1); 926 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 927 AscSetBank(iot, ioh, 0); 928 return (sta); 929 } 930 931 932 static int 933 AscHostReqRiscHalt(iot, ioh) 934 bus_space_tag_t iot; 935 bus_space_handle_t ioh; 936 { 937 int count = 0; 938 int retval = 0; 939 u_int8_t saved_stop_code; 940 941 942 if (AscIsChipHalted(iot, ioh)) 943 return (1); 944 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 945 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 946 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 947 948 do { 949 if (AscIsChipHalted(iot, ioh)) { 950 retval = 1; 951 break; 952 } 953 DvcSleepMilliSecond(100); 954 } while (count++ < 20); 955 956 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 957 958 return (retval); 959 } 960 961 962 static int 963 AscIsChipHalted(iot, ioh) 964 bus_space_tag_t iot; 965 bus_space_handle_t ioh; 966 { 967 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 968 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 969 return (1); 970 971 return (0); 972 } 973 974 975 static void 976 AscSetChipIH(iot, ioh, ins_code) 977 bus_space_tag_t iot; 978 bus_space_handle_t ioh; 979 u_int16_t ins_code; 980 { 981 AscSetBank(iot, ioh, 1); 982 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 983 AscSetBank(iot, ioh, 0); 984 985 return; 986 } 987 988 989 /******************************************************************************/ 990 /* Lram routines */ 991 /******************************************************************************/ 992 993 994 static u_int8_t 995 AscReadLramByte(iot, ioh, addr) 996 bus_space_tag_t iot; 997 bus_space_handle_t ioh; 998 u_int16_t addr; 999 { 1000 u_int8_t byte_data; 1001 u_int16_t word_data; 1002 1003 1004 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1005 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1006 1007 if (addr & 1) { 1008 /* odd address */ 1009 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1010 } else { 1011 /* even address */ 1012 byte_data = (u_int8_t) (word_data & 0xFF); 1013 } 1014 1015 return (byte_data); 1016 } 1017 1018 1019 static void 1020 AscWriteLramByte(iot, ioh, addr, data) 1021 bus_space_tag_t iot; 1022 bus_space_handle_t ioh; 1023 u_int16_t addr; 1024 u_int8_t data; 1025 { 1026 u_int16_t word_data; 1027 1028 1029 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1030 1031 if (addr & 1) { 1032 /* odd address */ 1033 word_data &= 0x00FF; 1034 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1035 } else { 1036 /* even address */ 1037 word_data &= 0xFF00; 1038 word_data |= ((u_int16_t) data) & 0x00FF; 1039 } 1040 1041 AscWriteLramWord(iot, ioh, addr, word_data); 1042 } 1043 1044 1045 static u_int16_t 1046 AscReadLramWord(iot, ioh, addr) 1047 bus_space_tag_t iot; 1048 bus_space_handle_t ioh; 1049 u_int16_t addr; 1050 { 1051 1052 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1053 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1054 } 1055 1056 1057 static void 1058 AscWriteLramWord(iot, ioh, addr, data) 1059 bus_space_tag_t iot; 1060 bus_space_handle_t ioh; 1061 u_int16_t addr; 1062 u_int16_t data; 1063 { 1064 1065 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1066 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1067 } 1068 1069 1070 static u_int32_t 1071 AscReadLramDWord(iot, ioh, addr) 1072 bus_space_tag_t iot; 1073 bus_space_handle_t ioh; 1074 u_int16_t addr; 1075 { 1076 u_int16_t low_word, hi_word; 1077 1078 1079 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1080 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1081 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1082 1083 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1084 } 1085 1086 1087 static void 1088 AscWriteLramDWord(iot, ioh, addr, data) 1089 bus_space_tag_t iot; 1090 bus_space_handle_t ioh; 1091 u_int16_t addr; 1092 u_int32_t data; 1093 { 1094 1095 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1096 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1097 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1098 } 1099 1100 1101 static void 1102 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1103 bus_space_tag_t iot; 1104 bus_space_handle_t ioh; 1105 u_int16_t s_addr; 1106 u_int16_t s_words; 1107 int count; 1108 { 1109 int i; 1110 1111 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1112 for (i = 0; i < count; i++) 1113 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1114 } 1115 1116 1117 static void 1118 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1119 bus_space_tag_t iot; 1120 bus_space_handle_t ioh; 1121 u_int16_t s_addr; 1122 u_int16_t *s_buffer; 1123 int words; 1124 { 1125 int i; 1126 1127 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1128 for (i = 0; i < words; i++, s_buffer++) 1129 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1130 } 1131 1132 1133 static void 1134 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1135 bus_space_tag_t iot; 1136 bus_space_handle_t ioh; 1137 u_int16_t s_addr; 1138 u_int16_t *s_buffer; 1139 int words; 1140 { 1141 int i; 1142 1143 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1144 for (i = 0; i < words; i++, s_buffer++) 1145 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1146 } 1147 1148 1149 static void 1150 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1151 bus_space_tag_t iot; 1152 bus_space_handle_t ioh; 1153 u_int16_t s_addr; 1154 u_int32_t *s_buffer; 1155 int dwords; 1156 { 1157 int i; 1158 u_int32_t *pw; 1159 1160 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1161 1162 pw = s_buffer; 1163 for (i = 0; i < dwords; i++, pw++) { 1164 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1165 DELAY(1); 1166 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1167 } 1168 } 1169 1170 1171 static u_int32_t 1172 AscMemSumLramWord(iot, ioh, s_addr, words) 1173 bus_space_tag_t iot; 1174 bus_space_handle_t ioh; 1175 u_int16_t s_addr; 1176 int words; 1177 { 1178 u_int32_t sum = 0L; 1179 u_int16_t i; 1180 1181 1182 for (i = 0; i < words; i++, s_addr += 2) 1183 sum += AscReadLramWord(iot, ioh, s_addr); 1184 1185 return (sum); 1186 } 1187 1188 1189 static int 1190 AscTestExternalLram(iot, ioh) 1191 bus_space_tag_t iot; 1192 bus_space_handle_t ioh; 1193 { 1194 u_int16_t q_addr; 1195 u_int16_t saved_word; 1196 int retval; 1197 1198 1199 retval = 0; 1200 q_addr = ASC_QNO_TO_QADDR(241); 1201 saved_word = AscReadLramWord(iot, ioh, q_addr); 1202 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1203 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1204 DvcSleepMilliSecond(10); 1205 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1206 1207 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1208 retval = 1; 1209 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1210 } 1211 return (retval); 1212 } 1213 1214 1215 /******************************************************************************/ 1216 /* MicroCode routines */ 1217 /******************************************************************************/ 1218 1219 1220 static u_int16_t 1221 AscInitMicroCodeVar(sc) 1222 ASC_SOFTC *sc; 1223 { 1224 bus_space_tag_t iot = sc->sc_iot; 1225 bus_space_handle_t ioh = sc->sc_ioh; 1226 u_int32_t phy_addr; 1227 int i; 1228 1229 1230 for (i = 0; i <= ASC_MAX_TID; i++) 1231 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1232 sc->sdtr_period_offset[i]); 1233 1234 AscInitQLinkVar(sc); 1235 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1236 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1237 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1238 1239 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1240 ASC_OVERRUN_BSIZE)) == 0L) { 1241 return (0); 1242 } else { 1243 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1244 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1245 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1246 ASC_OVERRUN_BSIZE - 8); 1247 } 1248 1249 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1250 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1251 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1252 1253 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1254 return (0); 1255 } 1256 if (AscStartChip(iot, ioh) != 1) { 1257 return (0); 1258 } 1259 return (1); 1260 } 1261 1262 1263 static u_int32_t 1264 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 1265 bus_space_tag_t iot; 1266 bus_space_handle_t ioh; 1267 u_int16_t s_addr; 1268 u_int16_t *mcode_buf; 1269 u_int16_t mcode_size; 1270 { 1271 u_int32_t chksum; 1272 u_int16_t mcode_word_size; 1273 u_int16_t mcode_chksum; 1274 1275 mcode_word_size = mcode_size >> 1; 1276 /* clear board memory */ 1277 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1278 /* copy uCode to board memory */ 1279 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1280 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1281 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1282 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1283 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1284 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1285 1286 return (chksum); 1287 } 1288 1289 1290 static u_int32_t 1291 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1292 ASC_SOFTC *sc; 1293 u_int8_t *buf_addr; 1294 u_int32_t buf_size; 1295 { 1296 ASC_MIN_SG_HEAD sg_head; 1297 1298 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1299 if (AscGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1300 buf_size) { 1301 return (0L); 1302 } 1303 if (sg_head.entry_cnt > 1) { 1304 return (0L); 1305 } 1306 return (sg_head.sg_list[0].addr); 1307 } 1308 1309 1310 static u_int32_t 1311 AscGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 1312 ASC_SOFTC *sc; 1313 u_int8_t *buf_addr; 1314 u_int32_t buf_len; 1315 ASC_SG_HEAD *asc_sg_head_ptr; 1316 { 1317 u_int32_t buf_size; 1318 1319 buf_size = buf_len; 1320 asc_sg_head_ptr->entry_cnt = 1; 1321 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 1322 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 1323 1324 return (buf_size); 1325 } 1326 1327 1328 /******************************************************************************/ 1329 /* EEProm routines */ 1330 /******************************************************************************/ 1331 1332 1333 static int 1334 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1335 bus_space_tag_t iot; 1336 bus_space_handle_t ioh; 1337 u_int8_t cmd_reg; 1338 { 1339 u_int8_t read_back; 1340 int retry; 1341 1342 retry = 0; 1343 1344 while (TRUE) { 1345 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1346 DvcSleepMilliSecond(1); 1347 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1348 if (read_back == cmd_reg) 1349 return (1); 1350 1351 if (retry++ > ASC_EEP_MAX_RETRY) 1352 return (0); 1353 } 1354 } 1355 1356 1357 static int 1358 AscWriteEEPDataReg(iot, ioh, data_reg) 1359 bus_space_tag_t iot; 1360 bus_space_handle_t ioh; 1361 u_int16_t data_reg; 1362 { 1363 u_int16_t read_back; 1364 int retry; 1365 1366 retry = 0; 1367 while (TRUE) { 1368 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1369 DvcSleepMilliSecond(1); 1370 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1371 if (read_back == data_reg) 1372 return (1); 1373 1374 if (retry++ > ASC_EEP_MAX_RETRY) 1375 return (0); 1376 } 1377 } 1378 1379 1380 static void 1381 AscWaitEEPRead(void) 1382 { 1383 1384 DvcSleepMilliSecond(1); 1385 } 1386 1387 1388 static void 1389 AscWaitEEPWrite(void) 1390 { 1391 1392 DvcSleepMilliSecond(1); 1393 } 1394 1395 1396 static u_int16_t 1397 AscReadEEPWord(iot, ioh, addr) 1398 bus_space_tag_t iot; 1399 bus_space_handle_t ioh; 1400 u_int8_t addr; 1401 { 1402 u_int16_t read_wval; 1403 u_int8_t cmd_reg; 1404 1405 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1406 AscWaitEEPRead(); 1407 cmd_reg = addr | ASC_EEP_CMD_READ; 1408 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1409 AscWaitEEPRead(); 1410 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1411 AscWaitEEPRead(); 1412 1413 return (read_wval); 1414 } 1415 1416 1417 static u_int16_t 1418 AscWriteEEPWord(iot, ioh, addr, word_val) 1419 bus_space_tag_t iot; 1420 bus_space_handle_t ioh; 1421 u_int8_t addr; 1422 u_int16_t word_val; 1423 { 1424 u_int16_t read_wval; 1425 1426 read_wval = AscReadEEPWord(iot, ioh, addr); 1427 if (read_wval != word_val) { 1428 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1429 AscWaitEEPRead(); 1430 AscWriteEEPDataReg(iot, ioh, word_val); 1431 AscWaitEEPRead(); 1432 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1433 AscWaitEEPWrite(); 1434 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1435 AscWaitEEPRead(); 1436 return (AscReadEEPWord(iot, ioh, addr)); 1437 } 1438 return (read_wval); 1439 } 1440 1441 1442 static u_int16_t 1443 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1444 bus_space_tag_t iot; 1445 bus_space_handle_t ioh; 1446 ASCEEP_CONFIG *cfg_buf; 1447 u_int16_t bus_type; 1448 { 1449 u_int16_t wval; 1450 u_int16_t sum; 1451 u_int16_t *wbuf; 1452 int cfg_beg; 1453 int cfg_end; 1454 int s_addr; 1455 int isa_pnp_wsize; 1456 1457 1458 wbuf = (u_int16_t *) cfg_buf; 1459 sum = 0; 1460 isa_pnp_wsize = 0; 1461 1462 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1463 wval = AscReadEEPWord(iot, ioh, s_addr); 1464 sum += wval; 1465 *wbuf = wval; 1466 } 1467 1468 if (bus_type & ASC_IS_VL) { 1469 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1470 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1471 } else { 1472 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1473 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1474 } 1475 1476 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1477 wval = AscReadEEPWord(iot, ioh, s_addr); 1478 sum += wval; 1479 *wbuf = wval; 1480 } 1481 1482 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1483 1484 return (sum); 1485 } 1486 1487 1488 static int 1489 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1490 bus_space_tag_t iot; 1491 bus_space_handle_t ioh; 1492 ASCEEP_CONFIG *cfg_buf; 1493 u_int16_t bus_type; 1494 { 1495 int retry; 1496 int n_error; 1497 1498 retry = 0; 1499 while (TRUE) { 1500 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1501 break; 1502 1503 if (++retry > ASC_EEP_MAX_RETRY) 1504 break; 1505 } 1506 1507 return (n_error); 1508 } 1509 1510 1511 static int 1512 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1513 bus_space_tag_t iot; 1514 bus_space_handle_t ioh; 1515 ASCEEP_CONFIG *cfg_buf; 1516 u_int16_t bus_type; 1517 { 1518 int n_error; 1519 u_int16_t *wbuf; 1520 u_int16_t sum; 1521 int s_addr; 1522 int cfg_beg; 1523 int cfg_end; 1524 1525 wbuf = (u_int16_t *) cfg_buf; 1526 n_error = 0; 1527 sum = 0; 1528 1529 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1530 sum += *wbuf; 1531 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1532 n_error++; 1533 } 1534 1535 if (bus_type & ASC_IS_VL) { 1536 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1537 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1538 } else { 1539 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1540 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1541 } 1542 1543 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1544 sum += *wbuf; 1545 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1546 n_error++; 1547 } 1548 1549 *wbuf = sum; 1550 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1551 n_error++; 1552 1553 wbuf = (u_int16_t *) cfg_buf; 1554 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1555 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1556 n_error++; 1557 } 1558 1559 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1560 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1561 n_error++; 1562 } 1563 1564 return (n_error); 1565 } 1566 1567 1568 #ifdef ASC_DEBUG 1569 static void 1570 AscPrintEEPConfig(eep_config, chksum) 1571 ASCEEP_CONFIG *eep_config; 1572 u_int16_t chksum; 1573 { 1574 printf("---- ASC EEprom settings ----\n"); 1575 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1576 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1577 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1578 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1579 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1580 printf("start_motor = 0x%x\n", eep_config->start_motor); 1581 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1582 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1583 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1584 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1585 printf("no_scam = %d\n", eep_config->no_scam); 1586 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1587 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1588 printf("cntl = 0x%x\n", eep_config->cntl); 1589 #if BYTE_ORDER == BIG_ENDIAN 1590 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1591 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1592 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1593 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1594 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1595 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1596 #else 1597 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1598 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1599 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1600 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1601 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1602 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1603 #endif 1604 printf("checksum = 0x%x\n", eep_config->chksum); 1605 printf("calculated checksum = 0x%x\n", chksum); 1606 printf("-----------------------------\n"); 1607 } 1608 #endif 1609 1610 1611 /******************************************************************************/ 1612 /* Interrupt routines */ 1613 /******************************************************************************/ 1614 1615 1616 int 1617 AscISR(sc) 1618 ASC_SOFTC *sc; 1619 { 1620 bus_space_tag_t iot = sc->sc_iot; 1621 bus_space_handle_t ioh = sc->sc_ioh; 1622 u_int16_t chipstat; 1623 u_int16_t saved_ram_addr; 1624 u_int8_t ctrl_reg; 1625 u_int8_t saved_ctrl_reg; 1626 int int_pending; 1627 int status; 1628 u_int8_t host_flag; 1629 1630 1631 int_pending = FALSE; 1632 1633 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1634 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1635 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1636 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1637 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1638 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1639 int_pending = TRUE; 1640 sc->sdtr_done = 0; 1641 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1642 1643 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1644 1645 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1646 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1647 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1648 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1649 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1650 } 1651 } 1652 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1653 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1654 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1655 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1656 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1657 1658 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1659 AscAckInterrupt(iot, ioh); 1660 int_pending = TRUE; 1661 1662 if ((chipstat & ASC_CSW_HALTED) && 1663 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1664 AscIsrChipHalted(sc); 1665 saved_ctrl_reg &= ~ASC_CC_HALT; 1666 } else { 1667 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1668 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1669 } else { 1670 do { 1671 if ((status = AscIsrQDone(sc)) == 1) 1672 break; 1673 } while (status == 0x11); 1674 } 1675 1676 if (status & 0x80) 1677 int_pending = -1; 1678 } 1679 } 1680 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1681 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1682 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1683 1684 return (1); 1685 /* return(int_pending); */ 1686 } 1687 1688 1689 static int 1690 AscIsrQDone(sc) 1691 ASC_SOFTC *sc; 1692 { 1693 u_int8_t next_qp; 1694 u_int8_t n_q_used; 1695 u_int8_t sg_list_qp; 1696 u_int8_t sg_queue_cnt; 1697 u_int8_t q_cnt; 1698 u_int8_t done_q_tail; 1699 u_int8_t tid_no; 1700 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1701 ASC_SCSI_BIT_ID_TYPE target_id; 1702 bus_space_tag_t iot = sc->sc_iot; 1703 bus_space_handle_t ioh = sc->sc_ioh; 1704 u_int16_t q_addr; 1705 u_int16_t sg_q_addr; 1706 u_int8_t cur_target_qng; 1707 ASC_QDONE_INFO scsiq_buf; 1708 ASC_QDONE_INFO *scsiq; 1709 ASC_ISR_CALLBACK asc_isr_callback; 1710 1711 1712 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1713 n_q_used = 1; 1714 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1715 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1716 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1717 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1718 1719 if (next_qp != ASC_QLINK_END) { 1720 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1721 q_addr = ASC_QNO_TO_QADDR(next_qp); 1722 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1723 sc->max_dma_count); 1724 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1725 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1726 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1727 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1728 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1729 sg_q_addr = q_addr; 1730 sg_list_qp = next_qp; 1731 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1732 sg_list_qp = AscReadLramByte(iot, ioh, 1733 sg_q_addr + ASC_SCSIQ_B_FWD); 1734 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1735 if (sg_list_qp == ASC_QLINK_END) { 1736 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1737 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1738 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1739 panic("AscIsrQDone: Corrupted SG list encountered"); 1740 } 1741 AscWriteLramByte(iot, ioh, 1742 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1743 } 1744 n_q_used = sg_queue_cnt + 1; 1745 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1746 } 1747 if (sc->queue_full_or_busy & target_id) { 1748 cur_target_qng = AscReadLramByte(iot, ioh, 1749 ASC_QADR_BEG + scsiq->d2.target_ix); 1750 1751 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1752 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1753 scsi_busy &= ~target_id; 1754 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1755 sc->queue_full_or_busy &= ~target_id; 1756 } 1757 } 1758 if (sc->cur_total_qng >= n_q_used) { 1759 sc->cur_total_qng -= n_q_used; 1760 if (sc->cur_dvc_qng[tid_no] != 0) { 1761 sc->cur_dvc_qng[tid_no]--; 1762 } 1763 } else { 1764 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1765 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1766 panic("AscIsrQDone: Attempting to free more queues than are active"); 1767 } 1768 1769 if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) || 1770 ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1771 return (0x11); 1772 } else if (scsiq->q_status == ASC_QS_DONE) { 1773 scsiq->remain_bytes += scsiq->extra_bytes; 1774 1775 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1776 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1777 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1778 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1779 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1780 } 1781 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1782 AscStopChip(iot, ioh); 1783 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1784 DvcDelayNanoSecond(60000); 1785 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1786 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1787 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1788 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1789 } 1790 } 1791 (*asc_isr_callback) (sc, scsiq); 1792 1793 return (1); 1794 } else { 1795 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1796 panic("AscIsrQDone: completed scsiq with unknown status"); 1797 1798 return (0x80); 1799 } 1800 } 1801 return (0); 1802 } 1803 1804 1805 /* 1806 * handle all the conditions that may halt the board 1807 * waiting us to intervene 1808 */ 1809 static void 1810 AscIsrChipHalted(sc) 1811 ASC_SOFTC *sc; 1812 { 1813 bus_space_tag_t iot = sc->sc_iot; 1814 bus_space_handle_t ioh = sc->sc_ioh; 1815 EXT_MSG out_msg; 1816 u_int16_t int_halt_code; 1817 u_int16_t halt_q_addr; 1818 u_int8_t halt_qp; 1819 u_int8_t target_ix; 1820 u_int8_t tag_code; 1821 u_int8_t q_status; 1822 u_int8_t q_cntl; 1823 u_int8_t tid_no; 1824 u_int8_t cur_dvc_qng; 1825 u_int8_t asyn_sdtr; 1826 u_int8_t scsi_status; 1827 u_int8_t sdtr_data; 1828 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1829 ASC_SCSI_BIT_ID_TYPE target_id; 1830 1831 1832 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1833 1834 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1835 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1836 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1837 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1838 tid_no = ASC_TIX_TO_TID(target_ix); 1839 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1840 1841 if (sc->pci_fix_asyn_xfer & target_id) { 1842 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1843 } else { 1844 asyn_sdtr = 0; 1845 } 1846 1847 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1848 if (sc->pci_fix_asyn_xfer & target_id) { 1849 AscSetChipSDTR(iot, ioh, 0, tid_no); 1850 sc->sdtr_data[tid_no] = 0; 1851 } 1852 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1853 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1854 if (sc->pci_fix_asyn_xfer & target_id) { 1855 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1856 sc->sdtr_data[tid_no] = asyn_sdtr; 1857 } 1858 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1859 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1860 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1861 tid_no, asyn_sdtr); 1862 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1863 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1864 q_cntl |= ASC_QC_REQ_SENSE; 1865 1866 if (sc->init_sdtr & target_id) { 1867 sc->sdtr_done &= ~target_id; 1868 1869 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1870 q_cntl |= ASC_QC_MSG_OUT; 1871 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1872 (sc->max_sdtr_index - 1)], 1873 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1874 } 1875 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1876 1877 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1878 tag_code &= 0xDC; 1879 1880 if ((sc->pci_fix_asyn_xfer & target_id) && 1881 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1882 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1883 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1884 } 1885 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1886 1887 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1888 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1889 1890 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1891 1892 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1893 scsi_busy &= ~target_id; 1894 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1895 1896 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1897 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1898 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1899 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1900 1901 if ((out_msg.msg_type == MS_EXTEND) && 1902 (out_msg.msg_len == MS_SDTR_LEN) && 1903 (out_msg.msg_req == MS_SDTR_CODE)) { 1904 sc->init_sdtr &= ~target_id; 1905 sc->sdtr_done &= ~target_id; 1906 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1907 sc->sdtr_data[tid_no] = asyn_sdtr; 1908 } 1909 q_cntl &= ~ASC_QC_MSG_OUT; 1910 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1911 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1912 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1913 scsi_status = AscReadLramByte(iot, ioh, 1914 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1915 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1916 1917 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1918 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1919 scsi_busy |= target_id; 1920 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1921 sc->queue_full_or_busy |= target_id; 1922 1923 if (scsi_status == SS_QUEUE_FULL) { 1924 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1925 cur_dvc_qng -= 1; 1926 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1927 1928 AscWriteLramByte(iot, ioh, 1929 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1930 1931 #if ASC_QUEUE_FLOW_CONTROL 1932 if ((sc->device[tid_no] != NULL) && 1933 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1934 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1935 } 1936 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1937 } 1938 } 1939 } 1940 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1941 } 1942 return; 1943 } 1944 1945 1946 static int 1947 AscWaitTixISRDone(sc, target_ix) 1948 ASC_SOFTC *sc; 1949 u_int8_t target_ix; 1950 { 1951 u_int8_t cur_req; 1952 u_int8_t tid_no; 1953 int i = 0; 1954 1955 tid_no = ASC_TIX_TO_TID(target_ix); 1956 while (i++ < 10) { 1957 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1958 break; 1959 1960 DvcSleepMilliSecond(1000L); 1961 if (sc->cur_dvc_qng[tid_no] == cur_req) 1962 break; 1963 } 1964 return (1); 1965 } 1966 1967 static int 1968 AscWaitISRDone(sc) 1969 ASC_SOFTC *sc; 1970 { 1971 int tid; 1972 1973 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1974 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1975 1976 return (1); 1977 } 1978 1979 1980 static u_int8_t 1981 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1982 bus_space_tag_t iot; 1983 bus_space_handle_t ioh; 1984 u_int16_t q_addr; 1985 ASC_QDONE_INFO *scsiq; 1986 u_int32_t max_dma_count; 1987 { 1988 u_int16_t _val; 1989 u_int8_t sg_queue_cnt; 1990 1991 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 1992 1993 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1994 scsiq->q_status = LO_BYTE(_val); 1995 scsiq->q_no = HI_BYTE(_val); 1996 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1997 scsiq->cntl = LO_BYTE(_val); 1998 sg_queue_cnt = HI_BYTE(_val); 1999 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 2000 scsiq->sense_len = LO_BYTE(_val); 2001 scsiq->extra_bytes = HI_BYTE(_val); 2002 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 2003 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 2004 scsiq->remain_bytes &= max_dma_count; 2005 2006 return (sg_queue_cnt); 2007 } 2008 2009 2010 static void 2011 AscGetQDoneInfo(iot, ioh, addr, scsiq) 2012 bus_space_tag_t iot; 2013 bus_space_handle_t ioh; 2014 u_int16_t addr; 2015 ASC_QDONE_INFO *scsiq; 2016 { 2017 u_int16_t val; 2018 2019 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2020 2021 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2022 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 2023 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2024 scsiq->d2.target_ix = LO_BYTE(val); 2025 scsiq->d2.flag = HI_BYTE(val); 2026 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2027 scsiq->d2.cdb_len = LO_BYTE(val); 2028 scsiq->d2.tag_code = HI_BYTE(val); 2029 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2030 2031 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2032 scsiq->d3.done_stat = LO_BYTE(val); 2033 scsiq->d3.host_stat = HI_BYTE(val); 2034 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2035 scsiq->d3.scsi_stat = LO_BYTE(val); 2036 scsiq->d3.scsi_msg = HI_BYTE(val); 2037 } 2038 2039 2040 static void 2041 AscToggleIRQAct(iot, ioh) 2042 bus_space_tag_t iot; 2043 bus_space_handle_t ioh; 2044 { 2045 2046 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 2047 ASC_SET_CHIP_STATUS(iot, ioh, 0); 2048 } 2049 2050 2051 static void 2052 AscDisableInterrupt(iot, ioh) 2053 bus_space_tag_t iot; 2054 bus_space_handle_t ioh; 2055 { 2056 u_int16_t cfg; 2057 2058 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2059 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 2060 } 2061 2062 2063 static void 2064 AscEnableInterrupt(iot, ioh) 2065 bus_space_tag_t iot; 2066 bus_space_handle_t ioh; 2067 { 2068 u_int16_t cfg; 2069 2070 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2071 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2072 } 2073 2074 2075 u_int8_t 2076 AscGetChipIRQ(iot, ioh, bus_type) 2077 bus_space_tag_t iot; 2078 bus_space_handle_t ioh; 2079 u_int16_t bus_type; 2080 { 2081 u_int16_t cfg_lsw; 2082 u_int8_t chip_irq; 2083 2084 2085 /* if (bus_type & ASC_IS_EISA) { 2086 cfg_lsw = AscGetEisaChipCfg(iot, ioh); 2087 chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 2088 if((chip_irq == 13) || (chip_irq > 15)) 2089 return (0); 2090 return(chip_irq); 2091 } 2092 */ if ((bus_type & ASC_IS_VL) != 0) { 2093 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2094 chip_irq = (cfg_lsw >> 2) & 0x07; 2095 if ((chip_irq == 0) || 2096 (chip_irq == 4) || 2097 (chip_irq == 7)) { 2098 return (0); 2099 } 2100 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2101 } 2102 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2103 chip_irq = (cfg_lsw >> 2) & 0x03; 2104 if (chip_irq == 3) 2105 chip_irq += 2; 2106 return (chip_irq + ASC_MIN_IRQ_NO); 2107 } 2108 2109 2110 static u_int8_t 2111 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2112 bus_space_tag_t iot; 2113 bus_space_handle_t ioh; 2114 u_int8_t irq_no; 2115 u_int16_t bus_type; 2116 { 2117 u_int16_t cfg_lsw; 2118 2119 2120 if (bus_type & ASC_IS_VL) { 2121 if (irq_no) { 2122 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2123 irq_no = 0; 2124 else 2125 irq_no -= ASC_MIN_IRQ_NO - 1; 2126 } 2127 2128 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2129 cfg_lsw |= 0x0010; 2130 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2131 AscToggleIRQAct(iot, ioh); 2132 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2133 cfg_lsw |= (irq_no & 0x07) << 2; 2134 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2135 AscToggleIRQAct(iot, ioh); 2136 2137 return (AscGetChipIRQ(iot, ioh, bus_type)); 2138 } 2139 if (bus_type & ASC_IS_ISA) { 2140 if (irq_no == 15) 2141 irq_no -= 2; 2142 irq_no -= ASC_MIN_IRQ_NO; 2143 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2144 cfg_lsw |= (irq_no & 0x03) << 2; 2145 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2146 2147 return (AscGetChipIRQ(iot, ioh, bus_type)); 2148 } 2149 return (0); 2150 } 2151 2152 2153 static void 2154 AscAckInterrupt(iot, ioh) 2155 bus_space_tag_t iot; 2156 bus_space_handle_t ioh; 2157 { 2158 u_int8_t host_flag; 2159 u_int8_t risc_flag; 2160 u_int16_t loop; 2161 2162 2163 loop = 0; 2164 do { 2165 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2166 if (loop++ > 0x7FFF) 2167 break; 2168 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2169 2170 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2171 (~ASC_HOST_FLAG_ACK_INT); 2172 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2173 host_flag | ASC_HOST_FLAG_ACK_INT); 2174 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2175 2176 loop = 0; 2177 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2178 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2179 if (loop++ > 3) 2180 break; 2181 } 2182 2183 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2184 } 2185 2186 2187 static u_int32_t 2188 AscGetMaxDmaCount(bus_type) 2189 u_int16_t bus_type; 2190 { 2191 if (bus_type & ASC_IS_ISA) 2192 return (ASC_MAX_ISA_DMA_COUNT); 2193 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2194 return (ASC_MAX_VL_DMA_COUNT); 2195 return (ASC_MAX_PCI_DMA_COUNT); 2196 } 2197 2198 2199 u_int16_t 2200 AscGetIsaDmaChannel(iot, ioh) 2201 bus_space_tag_t iot; 2202 bus_space_handle_t ioh; 2203 { 2204 u_int16_t channel; 2205 2206 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2207 if (channel == 0x03) 2208 return (0); 2209 else if (channel == 0x00) 2210 return (7); 2211 return (channel + 4); 2212 } 2213 2214 2215 static u_int16_t 2216 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2217 bus_space_tag_t iot; 2218 bus_space_handle_t ioh; 2219 u_int16_t dma_channel; 2220 { 2221 u_int16_t cfg_lsw; 2222 u_int8_t value; 2223 2224 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2225 if (dma_channel == 7) 2226 value = 0x00; 2227 else 2228 value = dma_channel - 4; 2229 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2230 cfg_lsw |= value; 2231 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2232 return (AscGetIsaDmaChannel(iot, ioh)); 2233 } 2234 return (0); 2235 } 2236 2237 2238 static u_int8_t 2239 AscGetIsaDmaSpeed(iot, ioh) 2240 bus_space_tag_t iot; 2241 bus_space_handle_t ioh; 2242 { 2243 u_int8_t speed_value; 2244 2245 AscSetBank(iot, ioh, 1); 2246 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2247 speed_value &= 0x07; 2248 AscSetBank(iot, ioh, 0); 2249 return (speed_value); 2250 } 2251 2252 2253 static u_int8_t 2254 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2255 bus_space_tag_t iot; 2256 bus_space_handle_t ioh; 2257 u_int8_t speed_value; 2258 { 2259 speed_value &= 0x07; 2260 AscSetBank(iot, ioh, 1); 2261 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2262 AscSetBank(iot, ioh, 0); 2263 return (AscGetIsaDmaSpeed(iot, ioh)); 2264 } 2265 2266 2267 /******************************************************************************/ 2268 /* Messages routines */ 2269 /******************************************************************************/ 2270 2271 2272 static void 2273 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2274 ASC_SOFTC *sc; 2275 u_int16_t halt_q_addr; 2276 u_int8_t q_cntl; 2277 ASC_SCSI_BIT_ID_TYPE target_id; 2278 int tid_no; 2279 u_int8_t asyn_sdtr; 2280 { 2281 bus_space_tag_t iot = sc->sc_iot; 2282 bus_space_handle_t ioh = sc->sc_ioh; 2283 EXT_MSG ext_msg; 2284 u_int8_t sdtr_data; 2285 int sdtr_accept; 2286 2287 2288 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2289 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2290 2291 if (ext_msg.msg_type == MS_EXTEND && 2292 ext_msg.msg_req == MS_SDTR_CODE && 2293 ext_msg.msg_len == MS_SDTR_LEN) { 2294 sdtr_accept = TRUE; 2295 2296 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2297 sdtr_accept = FALSE; 2298 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2299 } 2300 if ((ext_msg.xfer_period < 2301 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2302 (ext_msg.xfer_period > 2303 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2304 sdtr_accept = FALSE; 2305 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2306 } 2307 if (sdtr_accept) { 2308 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2309 ext_msg.req_ack_offset); 2310 if (sdtr_data == 0xFF) { 2311 q_cntl |= ASC_QC_MSG_OUT; 2312 sc->init_sdtr &= ~target_id; 2313 sc->sdtr_done &= ~target_id; 2314 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2315 sc->sdtr_data[tid_no] = asyn_sdtr; 2316 } 2317 } 2318 if (ext_msg.req_ack_offset == 0) { 2319 q_cntl &= ~ASC_QC_MSG_OUT; 2320 sc->init_sdtr &= ~target_id; 2321 sc->sdtr_done &= ~target_id; 2322 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2323 } else { 2324 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2325 q_cntl &= ~ASC_QC_MSG_OUT; 2326 sc->sdtr_done |= target_id; 2327 sc->init_sdtr |= target_id; 2328 sc->pci_fix_asyn_xfer &= ~target_id; 2329 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2330 ext_msg.req_ack_offset); 2331 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2332 sc->sdtr_data[tid_no] = sdtr_data; 2333 } else { 2334 q_cntl |= ASC_QC_MSG_OUT; 2335 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2336 ext_msg.req_ack_offset); 2337 sc->pci_fix_asyn_xfer &= ~target_id; 2338 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2339 ext_msg.req_ack_offset); 2340 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2341 sc->sdtr_data[tid_no] = sdtr_data; 2342 sc->sdtr_done |= target_id; 2343 sc->init_sdtr |= target_id; 2344 } 2345 } 2346 } else if (ext_msg.msg_type == MS_EXTEND && 2347 ext_msg.msg_req == MS_WDTR_CODE && 2348 ext_msg.msg_len == MS_WDTR_LEN) { 2349 ext_msg.wdtr_width = 0; 2350 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2351 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2352 q_cntl |= ASC_QC_MSG_OUT; 2353 } else { 2354 ext_msg.msg_type = M1_MSG_REJECT; 2355 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2356 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2357 q_cntl |= ASC_QC_MSG_OUT; 2358 } 2359 2360 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2361 } 2362 2363 2364 static u_int8_t 2365 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2366 ASC_SOFTC *sc; 2367 u_int8_t sdtr_period; 2368 u_int8_t sdtr_offset; 2369 { 2370 bus_space_tag_t iot = sc->sc_iot; 2371 bus_space_handle_t ioh = sc->sc_ioh; 2372 EXT_MSG sdtr_buf; 2373 u_int8_t sdtr_period_index; 2374 2375 2376 sdtr_buf.msg_type = MS_EXTEND; 2377 sdtr_buf.msg_len = MS_SDTR_LEN; 2378 sdtr_buf.msg_req = MS_SDTR_CODE; 2379 sdtr_buf.xfer_period = sdtr_period; 2380 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2381 sdtr_buf.req_ack_offset = sdtr_offset; 2382 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2383 sc->max_sdtr_index) { 2384 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2385 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2386 return ((sdtr_period_index << 4) | sdtr_offset); 2387 } else { 2388 sdtr_buf.req_ack_offset = 0; 2389 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2390 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2391 return (0); 2392 } 2393 } 2394 2395 2396 /******************************************************************************/ 2397 /* SDTR routines */ 2398 /******************************************************************************/ 2399 2400 2401 static void 2402 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2403 bus_space_tag_t iot; 2404 bus_space_handle_t ioh; 2405 u_int8_t sdtr_data; 2406 u_int8_t tid_no; 2407 { 2408 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2409 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2410 } 2411 2412 2413 static u_int8_t 2414 AscCalSDTRData(sc, sdtr_period, syn_offset) 2415 ASC_SOFTC *sc; 2416 u_int8_t sdtr_period; 2417 u_int8_t syn_offset; 2418 { 2419 u_int8_t byte; 2420 u_int8_t sdtr_period_ix; 2421 2422 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2423 if (sdtr_period_ix > sc->max_sdtr_index) 2424 return (0xFF); 2425 2426 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2427 return (byte); 2428 } 2429 2430 2431 static u_int8_t 2432 AscGetSynPeriodIndex(sc, syn_time) 2433 ASC_SOFTC *sc; 2434 u_int8_t syn_time; 2435 { 2436 u_int8_t *period_table; 2437 int max_index; 2438 int min_index; 2439 int i; 2440 2441 period_table = sc->sdtr_period_tbl; 2442 max_index = sc->max_sdtr_index; 2443 min_index = sc->host_init_sdtr_index; 2444 if ((syn_time <= period_table[max_index])) { 2445 for (i = min_index; i < (max_index - 1); i++) { 2446 if (syn_time <= period_table[i]) 2447 return (i); 2448 } 2449 2450 return (max_index); 2451 } else 2452 return (max_index + 1); 2453 } 2454 2455 2456 /******************************************************************************/ 2457 /* Queue routines */ 2458 /******************************************************************************/ 2459 2460 /* 2461 * Send a command to the board 2462 */ 2463 int 2464 AscExeScsiQueue(sc, scsiq) 2465 ASC_SOFTC *sc; 2466 ASC_SCSI_Q *scsiq; 2467 { 2468 bus_space_tag_t iot = sc->sc_iot; 2469 bus_space_handle_t ioh = sc->sc_ioh; 2470 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2471 int retval; 2472 int n_q_required; 2473 int disable_syn_offset_one_fix; 2474 int i; 2475 u_int32_t addr; 2476 u_int16_t sg_entry_cnt = 0; 2477 u_int16_t sg_entry_cnt_minus_one = 0; 2478 u_int8_t target_ix; 2479 u_int8_t tid_no; 2480 u_int8_t sdtr_data; 2481 u_int8_t extra_bytes; 2482 u_int8_t scsi_cmd; 2483 u_int32_t data_cnt; 2484 2485 2486 scsiq->q1.q_no = 0; 2487 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2488 scsiq->q1.extra_bytes = 0; 2489 2490 retval = ASC_BUSY; 2491 target_ix = scsiq->q2.target_ix; 2492 tid_no = ASC_TIX_TO_TID(target_ix); 2493 n_q_required = 1; 2494 2495 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2496 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2497 sc->sdtr_done &= ~scsiq->q1.target_id; 2498 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2499 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2500 (sc->max_sdtr_index - 1)], 2501 sdtr_data & ASC_SYN_MAX_OFFSET); 2502 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2503 } 2504 /* 2505 * if there is just one segment into S/G list then 2506 * map it as it was a single request, filling 2507 * data_addr and data_cnt of ASC_SCSIQ structure. 2508 */ 2509 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2510 sg_entry_cnt = sg_head->entry_cnt; 2511 2512 if (sg_entry_cnt < 1) 2513 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2514 sg_entry_cnt); 2515 2516 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2517 panic("AscExeScsiQueue: Queue with too many segs."); 2518 2519 if (sg_entry_cnt == 1) { 2520 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2521 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2522 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2523 } 2524 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2525 } 2526 scsi_cmd = scsiq->cdbptr[0]; 2527 disable_syn_offset_one_fix = FALSE; 2528 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2529 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2530 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2531 data_cnt = 0; 2532 for (i = 0; i < sg_entry_cnt; i++) 2533 data_cnt += sg_head->sg_list[i].bytes; 2534 } else { 2535 data_cnt = scsiq->q1.data_cnt; 2536 } 2537 2538 if (data_cnt != 0ul) { 2539 if (data_cnt < 512ul) { 2540 disable_syn_offset_one_fix = TRUE; 2541 } else { 2542 if (scsi_cmd == SCSICMD_Inquiry || 2543 scsi_cmd == SCSICMD_RequestSense || 2544 scsi_cmd == SCSICMD_ReadCapacity || 2545 scsi_cmd == SCSICMD_ReadTOC || 2546 scsi_cmd == SCSICMD_ModeSelect6 || 2547 scsi_cmd == SCSICMD_ModeSense6 || 2548 scsi_cmd == SCSICMD_ModeSelect10 || 2549 scsi_cmd == SCSICMD_ModeSense10) { 2550 disable_syn_offset_one_fix = TRUE; 2551 } 2552 } 2553 } 2554 } 2555 if (disable_syn_offset_one_fix) { 2556 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2557 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2558 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2559 } else { 2560 scsiq->q2.tag_code &= 0x23; 2561 } 2562 2563 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2564 if (sc->bug_fix_cntl) { 2565 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2566 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2567 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2568 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2569 extra_bytes = addr & 0x0003; 2570 if ((extra_bytes != 0) && 2571 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2572 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2573 scsiq->q1.extra_bytes = extra_bytes; 2574 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2575 extra_bytes; 2576 } 2577 } 2578 } 2579 } 2580 sg_head->entry_to_copy = sg_head->entry_cnt; 2581 n_q_required = AscSgListToQueue(sg_entry_cnt); 2582 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2583 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2584 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2585 } 2586 } else { 2587 if (sc->bug_fix_cntl) { 2588 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2589 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2590 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2591 extra_bytes = addr & 0x0003; 2592 if ((extra_bytes != 0) && 2593 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2594 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2595 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2596 scsiq->q1.data_cnt -= extra_bytes; 2597 scsiq->q1.extra_bytes = extra_bytes; 2598 } 2599 } 2600 } 2601 } 2602 } 2603 n_q_required = 1; 2604 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2605 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2606 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2607 } 2608 } 2609 2610 return (retval); 2611 } 2612 2613 2614 static int 2615 AscSendScsiQueue(sc, scsiq, n_q_required) 2616 ASC_SOFTC *sc; 2617 ASC_SCSI_Q *scsiq; 2618 u_int8_t n_q_required; 2619 { 2620 bus_space_tag_t iot = sc->sc_iot; 2621 bus_space_handle_t ioh = sc->sc_ioh; 2622 u_int8_t free_q_head; 2623 u_int8_t next_qp; 2624 u_int8_t tid_no; 2625 u_int8_t target_ix; 2626 int retval; 2627 2628 2629 target_ix = scsiq->q2.target_ix; 2630 tid_no = ASC_TIX_TO_TID(target_ix); 2631 retval = ASC_BUSY; 2632 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2633 2634 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2635 != ASC_QLINK_END) { 2636 if (n_q_required > 1) { 2637 sc->last_q_shortage = 0; 2638 scsiq->sg_head->queue_cnt = n_q_required - 1; 2639 } 2640 scsiq->q1.q_no = free_q_head; 2641 2642 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2643 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2644 sc->cur_total_qng += n_q_required; 2645 sc->cur_dvc_qng[tid_no]++; 2646 } 2647 } 2648 return (retval); 2649 } 2650 2651 2652 static int 2653 AscPutReadySgListQueue(sc, scsiq, q_no) 2654 ASC_SOFTC *sc; 2655 ASC_SCSI_Q *scsiq; 2656 u_int8_t q_no; 2657 { 2658 bus_space_tag_t iot = sc->sc_iot; 2659 bus_space_handle_t ioh = sc->sc_ioh; 2660 int retval; 2661 int i; 2662 ASC_SG_HEAD *sg_head; 2663 ASC_SG_LIST_Q scsi_sg_q; 2664 u_int32_t saved_data_addr; 2665 u_int32_t saved_data_cnt; 2666 u_int16_t sg_list_dwords; 2667 u_int16_t sg_index; 2668 u_int16_t sg_entry_cnt; 2669 u_int16_t q_addr; 2670 u_int8_t next_qp; 2671 2672 2673 saved_data_addr = scsiq->q1.data_addr; 2674 saved_data_cnt = scsiq->q1.data_cnt; 2675 2676 if ((sg_head = scsiq->sg_head) != 0) { 2677 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2678 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2679 sg_entry_cnt = sg_head->entry_cnt - 1; 2680 if (sg_entry_cnt != 0) { 2681 q_addr = ASC_QNO_TO_QADDR(q_no); 2682 sg_index = 1; 2683 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2684 scsi_sg_q.sg_head_qp = q_no; 2685 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2686 2687 for (i = 0; i < sg_head->queue_cnt; i++) { 2688 scsi_sg_q.seq_no = i + 1; 2689 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2690 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2691 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2692 if (i == 0) { 2693 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2694 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2695 } else { 2696 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2697 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2698 } 2699 } else { 2700 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2701 sg_list_dwords = sg_entry_cnt << 1; 2702 if (i == 0) { 2703 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2704 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2705 } else { 2706 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2707 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2708 } 2709 2710 sg_entry_cnt = 0; 2711 } 2712 2713 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2714 scsi_sg_q.q_no = next_qp; 2715 q_addr = ASC_QNO_TO_QADDR(next_qp); 2716 2717 /* 2718 * Tell the board how many entries are in the S/G list 2719 */ 2720 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2721 (u_int16_t *) & scsi_sg_q, 2722 sizeof(ASC_SG_LIST_Q) >> 1); 2723 /* 2724 * Tell the board the addresses of the S/G list segments 2725 */ 2726 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2727 (u_int32_t *) & sg_head->sg_list[sg_index], 2728 sg_list_dwords); 2729 sg_index += ASC_SG_LIST_PER_Q; 2730 } 2731 } 2732 } 2733 retval = AscPutReadyQueue(sc, scsiq, q_no); 2734 scsiq->q1.data_addr = saved_data_addr; 2735 scsiq->q1.data_cnt = saved_data_cnt; 2736 return (retval); 2737 } 2738 2739 2740 static int 2741 AscPutReadyQueue(sc, scsiq, q_no) 2742 ASC_SOFTC *sc; 2743 ASC_SCSI_Q *scsiq; 2744 u_int8_t q_no; 2745 { 2746 bus_space_tag_t iot = sc->sc_iot; 2747 bus_space_handle_t ioh = sc->sc_ioh; 2748 u_int16_t q_addr; 2749 u_int8_t tid_no; 2750 u_int8_t sdtr_data; 2751 u_int8_t syn_period_ix; 2752 u_int8_t syn_offset; 2753 2754 2755 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2756 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2757 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2758 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2759 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2760 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2761 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2762 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2763 } 2764 q_addr = ASC_QNO_TO_QADDR(q_no); 2765 2766 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2767 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2768 } 2769 scsiq->q1.status = ASC_QS_FREE; 2770 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2771 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2772 2773 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2774 2775 /* 2776 * Let's start the command 2777 */ 2778 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2779 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2780 2781 return (ASC_NOERROR); 2782 } 2783 2784 2785 static void 2786 AscPutSCSIQ(iot, ioh, addr, scsiq) 2787 bus_space_tag_t iot; 2788 bus_space_handle_t ioh; 2789 u_int16_t addr; 2790 ASC_SCSI_Q *scsiq; 2791 { 2792 u_int16_t val; 2793 2794 2795 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2796 2797 /* ASC_SCSIQ_1 */ 2798 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2799 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2800 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2801 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2802 val = LO_WORD(scsiq->q1.data_addr); 2803 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2804 val = HI_WORD(scsiq->q1.data_addr); 2805 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2806 val = LO_WORD(scsiq->q1.data_cnt); 2807 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2808 val = HI_WORD(scsiq->q1.data_cnt); 2809 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2810 val = LO_WORD(scsiq->q1.sense_addr); 2811 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2812 val = HI_WORD(scsiq->q1.sense_addr); 2813 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2814 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2815 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2816 2817 /* ASC_SCSIQ_2 */ 2818 val = LO_WORD(scsiq->q2.ccb_ptr); 2819 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2820 val = HI_WORD(scsiq->q2.ccb_ptr); 2821 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2822 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2823 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2824 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2825 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2826 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2827 } 2828 2829 2830 static int 2831 AscSgListToQueue(sg_list) 2832 int sg_list; 2833 { 2834 int n_sg_list_qs; 2835 2836 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2837 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2838 n_sg_list_qs++; 2839 2840 return (n_sg_list_qs + 1); 2841 } 2842 2843 2844 static u_int 2845 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2846 ASC_SOFTC *sc; 2847 u_int8_t target_ix; 2848 u_int8_t n_qs; 2849 { 2850 u_int cur_used_qs; 2851 u_int cur_free_qs; 2852 2853 2854 if (n_qs == 1) { 2855 cur_used_qs = sc->cur_total_qng + 2856 sc->last_q_shortage + 2857 ASC_MIN_FREE_Q; 2858 } else { 2859 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2860 } 2861 2862 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2863 cur_free_qs = sc->max_total_qng - cur_used_qs; 2864 return (cur_free_qs); 2865 } 2866 if (n_qs > 1) 2867 if ((n_qs > sc->last_q_shortage) && 2868 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2869 sc->last_q_shortage = n_qs; 2870 } 2871 return (0); 2872 } 2873 2874 2875 static u_int8_t 2876 AscAllocFreeQueue(iot, ioh, free_q_head) 2877 bus_space_tag_t iot; 2878 bus_space_handle_t ioh; 2879 u_int8_t free_q_head; 2880 { 2881 u_int16_t q_addr; 2882 u_int8_t next_qp; 2883 u_int8_t q_status; 2884 2885 2886 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2887 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2888 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2889 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2890 return (next_qp); 2891 2892 return (ASC_QLINK_END); 2893 } 2894 2895 2896 static u_int8_t 2897 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2898 bus_space_tag_t iot; 2899 bus_space_handle_t ioh; 2900 u_int8_t free_q_head; 2901 u_int8_t n_free_q; 2902 { 2903 u_int8_t i; 2904 2905 for (i = 0; i < n_free_q; i++) { 2906 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2907 if (free_q_head == ASC_QLINK_END) 2908 break; 2909 } 2910 2911 return (free_q_head); 2912 } 2913 2914 2915 static int 2916 AscStopQueueExe(iot, ioh) 2917 bus_space_tag_t iot; 2918 bus_space_handle_t ioh; 2919 { 2920 int count = 0; 2921 2922 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2923 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2924 do { 2925 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2926 ASC_STOP_ACK_RISC_STOP) 2927 return (1); 2928 2929 DvcSleepMilliSecond(100); 2930 } while (count++ < 20); 2931 } 2932 return (0); 2933 } 2934 2935 2936 static void 2937 AscStartQueueExe(iot, ioh) 2938 bus_space_tag_t iot; 2939 bus_space_handle_t ioh; 2940 { 2941 2942 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2943 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2944 } 2945 2946 2947 static void 2948 AscCleanUpBusyQueue(iot, ioh) 2949 bus_space_tag_t iot; 2950 bus_space_handle_t ioh; 2951 { 2952 int count = 0; 2953 u_int8_t stop_code; 2954 2955 2956 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2957 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2958 do { 2959 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2960 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2961 break; 2962 2963 DvcSleepMilliSecond(100); 2964 } while (count++ < 20); 2965 } 2966 } 2967 2968 2969 static int 2970 _AscWaitQDone(iot, ioh, scsiq) 2971 bus_space_tag_t iot; 2972 bus_space_handle_t ioh; 2973 ASC_SCSI_Q *scsiq; 2974 { 2975 u_int16_t q_addr; 2976 u_int8_t q_status; 2977 int count = 0; 2978 2979 while (scsiq->q1.q_no == 0); 2980 2981 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2982 do { 2983 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2984 DvcSleepMilliSecond(100L); 2985 if (count++ > 30) 2986 return (0); 2987 2988 } while ((q_status & ASC_QS_READY) != 0); 2989 2990 return (1); 2991 } 2992 2993 2994 static int 2995 AscCleanUpDiscQueue(iot, ioh) 2996 bus_space_tag_t iot; 2997 bus_space_handle_t ioh; 2998 { 2999 int count; 3000 u_int8_t stop_code; 3001 3002 count = 0; 3003 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 3004 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 3005 do { 3006 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 3007 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 3008 break; 3009 3010 DvcSleepMilliSecond(100); 3011 } while (count++ < 20); 3012 } 3013 return (1); 3014 } 3015 3016 3017 /******************************************************************************/ 3018 /* Abort and Reset CCB routines */ 3019 /******************************************************************************/ 3020 3021 3022 int 3023 AscAbortCCB(sc, ccb) 3024 ASC_SOFTC *sc; 3025 ADV_CCB *ccb; 3026 { 3027 bus_space_tag_t iot = sc->sc_iot; 3028 bus_space_handle_t ioh = sc->sc_ioh; 3029 int retval; 3030 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3031 3032 3033 retval = -1; 3034 saved_unit_not_ready = sc->unit_not_ready; 3035 sc->unit_not_ready = 0xFF; 3036 AscWaitISRDone(sc); 3037 if (AscStopQueueExe(iot, ioh) == 1) { 3038 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 3039 retval = 1; 3040 AscCleanUpBusyQueue(iot, ioh); 3041 AscStartQueueExe(iot, ioh); 3042 } else { 3043 retval = 0; 3044 AscStartQueueExe(iot, ioh); 3045 } 3046 } 3047 sc->unit_not_ready = saved_unit_not_ready; 3048 3049 return (retval); 3050 } 3051 3052 3053 static int 3054 AscRiscHaltedAbortCCB(sc, ccb) 3055 ASC_SOFTC *sc; 3056 ADV_CCB *ccb; 3057 { 3058 bus_space_tag_t iot = sc->sc_iot; 3059 bus_space_handle_t ioh = sc->sc_ioh; 3060 u_int16_t q_addr; 3061 u_int8_t q_no; 3062 ASC_QDONE_INFO scsiq_buf; 3063 ASC_QDONE_INFO *scsiq; 3064 ASC_ISR_CALLBACK asc_isr_callback; 3065 int last_int_level; 3066 3067 3068 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3069 last_int_level = DvcEnterCritical(); 3070 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3071 3072 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3073 q_addr = ASC_QNO_TO_QADDR(q_no); 3074 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 3075 q_addr + ASC_SCSIQ_D_CCBPTR); 3076 if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) { 3077 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3078 if (((scsiq->q_status & ASC_QS_READY) != 0) 3079 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 3080 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3081 scsiq->q_status |= ASC_QS_ABORTED; 3082 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3083 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3084 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3085 scsiq->q_status); 3086 (*asc_isr_callback) (sc, scsiq); 3087 return (1); 3088 } 3089 } 3090 } 3091 3092 DvcLeaveCritical(last_int_level); 3093 return (0); 3094 } 3095 3096 3097 static int 3098 AscRiscHaltedAbortTIX(sc, target_ix) 3099 ASC_SOFTC *sc; 3100 u_int8_t target_ix; 3101 { 3102 bus_space_tag_t iot = sc->sc_iot; 3103 bus_space_handle_t ioh = sc->sc_ioh; 3104 u_int16_t q_addr; 3105 u_int8_t q_no; 3106 ASC_QDONE_INFO scsiq_buf; 3107 ASC_QDONE_INFO *scsiq; 3108 ASC_ISR_CALLBACK asc_isr_callback; 3109 int last_int_level; 3110 3111 3112 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3113 last_int_level = DvcEnterCritical(); 3114 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3115 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3116 q_addr = ASC_QNO_TO_QADDR(q_no); 3117 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3118 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3119 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3120 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3121 if (scsiq->d2.target_ix == target_ix) { 3122 scsiq->q_status |= ASC_QS_ABORTED; 3123 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3124 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3125 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3126 scsiq->q_status); 3127 (*asc_isr_callback) (sc, scsiq); 3128 } 3129 } 3130 } 3131 DvcLeaveCritical(last_int_level); 3132 return (1); 3133 } 3134 3135 3136 /* 3137 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3138 * so we cannot use this function with the actual NetBSD SCSI layer 3139 * because at boot time interrupts are disabled. 3140 */ 3141 int 3142 AscResetDevice(sc, target_ix) 3143 ASC_SOFTC *sc; 3144 u_char target_ix; 3145 { 3146 bus_space_tag_t iot = sc->sc_iot; 3147 bus_space_handle_t ioh = sc->sc_ioh; 3148 int retval; 3149 u_int8_t tid_no; 3150 ASC_SCSI_BIT_ID_TYPE target_id; 3151 int i; 3152 ASC_SCSI_REQ_Q scsiq_buf; 3153 ASC_SCSI_REQ_Q *scsiq; 3154 u_int8_t *buf; 3155 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3156 3157 3158 tid_no = ASC_TIX_TO_TID(target_ix); 3159 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3160 saved_unit_not_ready = sc->unit_not_ready; 3161 sc->unit_not_ready = target_id; 3162 retval = ASC_ERROR; 3163 3164 AscWaitTixISRDone(sc, target_ix); 3165 3166 if (AscStopQueueExe(iot, ioh) == 1) { 3167 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3168 AscCleanUpBusyQueue(iot, ioh); 3169 AscStartQueueExe(iot, ioh); 3170 AscWaitTixISRDone(sc, target_ix); 3171 retval = ASC_NOERROR; 3172 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3173 buf = (u_char *) & scsiq_buf; 3174 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3175 *buf++ = 0x00; 3176 scsiq->q1.status = (u_char) ASC_QS_READY; 3177 scsiq->q2.cdb_len = 6; 3178 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3179 scsiq->q1.target_id = target_id; 3180 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3181 scsiq->cdbptr = scsiq->cdb; 3182 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3183 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3184 sc->unit_not_ready &= ~target_id; 3185 sc->sdtr_done |= target_id; 3186 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3187 sc->unit_not_ready = target_id; 3188 DvcSleepMilliSecond(1000); 3189 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3190 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3191 AscCleanUpDiscQueue(iot, ioh); 3192 AscStartQueueExe(iot, ioh); 3193 if (sc->pci_fix_asyn_xfer & target_id) 3194 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3195 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3196 AscWaitTixISRDone(sc, target_ix); 3197 } 3198 } else 3199 retval = ASC_BUSY; 3200 sc->sdtr_done &= ~target_id; 3201 } else { 3202 retval = ASC_ERROR; 3203 AscStartQueueExe(iot, ioh); 3204 } 3205 } 3206 sc->unit_not_ready = saved_unit_not_ready; 3207 return (retval); 3208 } 3209 3210 3211 int 3212 AscResetBus(sc) 3213 ASC_SOFTC *sc; 3214 { 3215 bus_space_tag_t iot = sc->sc_iot; 3216 bus_space_handle_t ioh = sc->sc_ioh; 3217 int retval; 3218 int i; 3219 3220 3221 sc->unit_not_ready = 0xFF; 3222 retval = ASC_NOERROR; 3223 3224 AscWaitISRDone(sc); 3225 AscStopQueueExe(iot, ioh); 3226 sc->sdtr_done = 0; 3227 AscResetChipAndScsiBus(iot, ioh); 3228 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3229 AscReInitLram(sc); 3230 for (i = 0; i <= ASC_MAX_TID; i++) { 3231 sc->cur_dvc_qng[i] = 0; 3232 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3233 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3234 } 3235 3236 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3237 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3238 retval = ASC_ERROR; 3239 3240 if (AscStartChip(iot, ioh) == 0) 3241 retval = ASC_ERROR; 3242 3243 AscStartQueueExe(iot, ioh); 3244 sc->unit_not_ready = 0; 3245 sc->queue_full_or_busy = 0; 3246 return (retval); 3247 } 3248 3249 3250 /******************************************************************************/ 3251 /* Error Handling routines */ 3252 /******************************************************************************/ 3253 3254 3255 static int 3256 AscSetLibErrorCode(sc, err_code) 3257 ASC_SOFTC *sc; 3258 u_int16_t err_code; 3259 { 3260 /* 3261 * if(sc->err_code == 0) { sc->err_code = err_code; 3262 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3263 err_code); 3264 /* 3265 * } 3266 */ 3267 return (err_code); 3268 } 3269 3270 3271 /******************************************************************************/ 3272 /* Handle bugged borads routines */ 3273 /******************************************************************************/ 3274 3275 3276 void 3277 AscInquiryHandling(sc, tid_no, inq) 3278 ASC_SOFTC *sc; 3279 u_int8_t tid_no; 3280 ASC_SCSI_INQUIRY *inq; 3281 { 3282 bus_space_tag_t iot = sc->sc_iot; 3283 bus_space_handle_t ioh = sc->sc_ioh; 3284 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3285 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3286 3287 3288 orig_init_sdtr = sc->init_sdtr; 3289 orig_use_tagged_qng = sc->use_tagged_qng; 3290 3291 sc->init_sdtr &= ~tid_bit; 3292 sc->can_tagged_qng &= ~tid_bit; 3293 sc->use_tagged_qng &= ~tid_bit; 3294 3295 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3296 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3297 sc->init_sdtr |= tid_bit; 3298 3299 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3300 if (AscTagQueuingSafe(inq)) { 3301 sc->use_tagged_qng |= tid_bit; 3302 sc->can_tagged_qng |= tid_bit; 3303 } 3304 } 3305 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3306 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3307 sc->disc_enable); 3308 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3309 sc->use_tagged_qng); 3310 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3311 sc->can_tagged_qng); 3312 3313 sc->max_dvc_qng[tid_no] = 3314 sc->max_tag_qng[tid_no]; 3315 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3316 sc->max_dvc_qng[tid_no]); 3317 } 3318 if (orig_init_sdtr != sc->init_sdtr) 3319 AscAsyncFix(sc, tid_no, inq); 3320 } 3321 3322 3323 static int 3324 AscTagQueuingSafe(inq) 3325 ASC_SCSI_INQUIRY *inq; 3326 { 3327 if ((inq->add_len >= 32) && 3328 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3329 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3330 return 0; 3331 } 3332 return 1; 3333 } 3334 3335 3336 static void 3337 AscAsyncFix(sc, tid_no, inq) 3338 ASC_SOFTC *sc; 3339 u_int8_t tid_no; 3340 ASC_SCSI_INQUIRY *inq; 3341 { 3342 u_int8_t dvc_type; 3343 ASC_SCSI_BIT_ID_TYPE tid_bits; 3344 3345 3346 dvc_type = inq->byte0.peri_dvc_type; 3347 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3348 3349 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3350 if (!(sc->init_sdtr & tid_bits)) { 3351 if ((dvc_type == SCSI_TYPE_CDROM) && 3352 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3353 sc->pci_fix_asyn_xfer_always |= tid_bits; 3354 } 3355 sc->pci_fix_asyn_xfer |= tid_bits; 3356 if ((dvc_type == SCSI_TYPE_PROC) || 3357 (dvc_type == SCSI_TYPE_SCANNER)) { 3358 sc->pci_fix_asyn_xfer &= ~tid_bits; 3359 } 3360 if ((dvc_type == SCSI_TYPE_SASD) && 3361 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3362 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3363 sc->pci_fix_asyn_xfer &= ~tid_bits; 3364 } 3365 if ((dvc_type == SCSI_TYPE_SASD) && 3366 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3367 sc->pci_fix_asyn_xfer &= ~tid_bits; 3368 } 3369 if ((dvc_type == SCSI_TYPE_CDROM) && 3370 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3371 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3372 sc->pci_fix_asyn_xfer &= ~tid_bits; 3373 } 3374 if ((dvc_type == SCSI_TYPE_CDROM) && 3375 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3376 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3377 sc->pci_fix_asyn_xfer &= ~tid_bits; 3378 } 3379 if (sc->pci_fix_asyn_xfer & tid_bits) { 3380 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3381 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3382 } 3383 } 3384 } 3385 } 3386 3387 3388 /******************************************************************************/ 3389 /* Miscellaneous routines */ 3390 /******************************************************************************/ 3391 3392 3393 static int 3394 AscCompareString(str1, str2, len) 3395 u_char *str1; 3396 u_char *str2; 3397 int len; 3398 { 3399 int i; 3400 int diff; 3401 3402 for (i = 0; i < len; i++) { 3403 diff = (int) (str1[i] - str2[i]); 3404 if (diff != 0) 3405 return (diff); 3406 } 3407 3408 return (0); 3409 } 3410 3411 3412 /******************************************************************************/ 3413 /* Device oriented routines */ 3414 /******************************************************************************/ 3415 3416 3417 static int 3418 DvcEnterCritical(void) 3419 { 3420 int s; 3421 3422 s = splbio(); 3423 return (s); 3424 } 3425 3426 3427 static void 3428 DvcLeaveCritical(s) 3429 int s; 3430 { 3431 3432 splx(s); 3433 } 3434 3435 3436 static void 3437 DvcSleepMilliSecond(n) 3438 u_int32_t n; 3439 { 3440 3441 DELAY(n * 1000); 3442 } 3443 3444 #ifdef UNUSED 3445 static void 3446 DvcDelayMicroSecond(n) 3447 u_int32_t n; 3448 { 3449 3450 DELAY(n); 3451 } 3452 #endif 3453 3454 static void 3455 DvcDelayNanoSecond(n) 3456 u_int32_t n; 3457 { 3458 3459 DELAY((n + 999) / 1000); 3460 } 3461
Indexes created Thu Oct 02 07:10:07 GMT 2025