advlib.c revision 1.9
1 /* $NetBSD: advlib.c,v 1.9 1999/06/06 17:33:18 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/scsipi/scsi_all.h> 67 #include <dev/scsipi/scsipi_all.h> 68 #include <dev/scsipi/scsiconf.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_param.h> 72 #include <vm/pmap.h> 73 74 #include <dev/ic/advlib.h> 75 #include <dev/ic/adv.h> 76 #include <dev/ic/advmcode.h> 77 78 79 /* #define ASC_DEBUG */ 80 81 /******************************************************************************/ 82 /* Static functions */ 83 /******************************************************************************/ 84 85 /* Initializzation routines */ 86 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 87 u_int16_t, u_int16_t *, u_int16_t)); 88 static void AscInitLram __P((ASC_SOFTC *)); 89 static void AscInitQLinkVar __P((ASC_SOFTC *)); 90 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 91 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 92 static u_int16_t AscGetEisaChipCfg __P((bus_space_tag_t, bus_space_handle_t)); 93 94 /* Chip register routines */ 95 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 96 97 /* RISC Chip routines */ 98 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 99 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 100 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 101 u_int8_t)); 102 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 103 static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t, 104 u_int16_t)); 105 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 106 u_int8_t, u_int8_t)); 107 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 108 u_int8_t, u_int8_t)); 109 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 110 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 111 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 112 113 /* Lram routines */ 114 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 115 u_int16_t)); 116 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 117 u_int16_t, u_int8_t)); 118 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 119 u_int16_t)); 120 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 121 u_int16_t, u_int16_t)); 122 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 123 u_int16_t)); 124 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 125 u_int16_t, u_int32_t)); 126 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 127 u_int16_t, u_int16_t, int)); 128 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 129 u_int16_t, u_int16_t *, int)); 130 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 131 u_int16_t, u_int16_t *, int)); 132 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 133 u_int16_t, u_int32_t *, int)); 134 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 135 u_int16_t, int)); 136 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 137 138 /* MicroCode routines */ 139 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 140 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 141 static u_int32_t AscGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 142 ASC_SG_HEAD *)); 143 144 /* EEProm routines */ 145 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 146 u_int8_t)); 147 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 148 u_int16_t)); 149 static void AscWaitEEPRead __P((void)); 150 static void AscWaitEEPWrite __P((void)); 151 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 152 u_int8_t)); 153 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 154 u_int8_t, u_int16_t)); 155 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 156 ASCEEP_CONFIG *, u_int16_t)); 157 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 158 ASCEEP_CONFIG *, u_int16_t)); 159 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 160 ASCEEP_CONFIG *, u_int16_t)); 161 #ifdef ASC_DEBUG 162 static void AscPrintEEPConfig __P((ASCEEP_CONFIG *, u_int16_t)); 163 #endif 164 165 /* Interrupt routines */ 166 static void AscIsrChipHalted __P((ASC_SOFTC *)); 167 static int AscIsrQDone __P((ASC_SOFTC *)); 168 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 169 static int AscWaitISRDone __P((ASC_SOFTC *)); 170 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 171 u_int16_t, ASC_QDONE_INFO *, 172 u_int32_t)); 173 static void AscGetQDoneInfo __P((bus_space_tag_t, bus_space_handle_t, u_int16_t, 174 ASC_QDONE_INFO *)); 175 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 176 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 177 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 178 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 179 u_int8_t, u_int16_t)); 180 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 181 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 182 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 183 u_int16_t)); 184 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 185 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 186 u_int8_t)); 187 188 /* Messages routines */ 189 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 190 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 191 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 192 193 /* SDTR routines */ 194 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 195 u_int8_t, u_int8_t)); 196 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 197 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 198 199 /* Queue routines */ 200 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 201 static int AscSgListToQueue __P((int)); 202 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 203 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 204 static void AscPutSCSIQ __P((bus_space_tag_t, bus_space_handle_t, 205 u_int16_t, ASC_SCSI_Q *)); 206 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 207 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 208 u_int8_t)); 209 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 210 bus_space_handle_t, 211 u_int8_t, u_int8_t)); 212 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 213 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 214 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 215 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 216 ASC_SCSI_Q *)); 217 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 218 219 /* Abort and Reset CCB routines */ 220 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, ADV_CCB *)); 221 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 222 223 /* Error Handling routines */ 224 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 225 226 /* Handle bugged borads routines */ 227 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 228 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 229 230 /* Miscellaneous routines */ 231 static int AscCompareString __P((u_char *, u_char *, int)); 232 233 /* Device oriented routines */ 234 static int DvcEnterCritical __P((void)); 235 static void DvcLeaveCritical __P((int)); 236 static void DvcSleepMilliSecond __P((u_int32_t)); 237 //static void DvcDelayMicroSecond __P((u_int32_t)); 238 static void DvcDelayNanoSecond __P((u_int32_t)); 239 240 241 /******************************************************************************/ 242 /* Initializzation routines */ 243 /******************************************************************************/ 244 245 /* 246 * This function perform the following steps: 247 * - initialize ASC_SOFTC structure with defaults values. 248 * - inquire board registers to know what kind of board it is. 249 * - keep track of bugged borads. 250 */ 251 void 252 AscInitASC_SOFTC(sc) 253 ASC_SOFTC *sc; 254 { 255 bus_space_tag_t iot = sc->sc_iot; 256 bus_space_handle_t ioh = sc->sc_ioh; 257 int i; 258 u_int8_t chip_version; 259 260 261 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 262 ASC_SET_CHIP_STATUS(iot, ioh, 0); 263 264 sc->bug_fix_cntl = 0; 265 sc->pci_fix_asyn_xfer = 0; 266 sc->pci_fix_asyn_xfer_always = 0; 267 sc->sdtr_done = 0; 268 sc->cur_total_qng = 0; 269 sc->last_q_shortage = 0; 270 sc->use_tagged_qng = 0; 271 sc->unit_not_ready = 0; 272 sc->queue_full_or_busy = 0; 273 sc->host_init_sdtr_index = 0; 274 sc->can_tagged_qng = 0; 275 sc->cmd_qng_enabled = 0; 276 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 277 sc->init_sdtr = 0; 278 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 279 sc->scsi_reset_wait = 3; 280 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 281 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 282 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 283 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 284 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 285 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 286 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 287 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 288 sc->chip_version = chip_version; 289 if ((sc->bus_type & ASC_IS_PCI) && 290 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 291 sc->bus_type = ASC_IS_PCI_ULTRA; 292 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 293 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 294 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 295 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 296 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 297 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 298 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 299 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 300 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 301 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 302 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 303 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 304 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 305 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 306 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 307 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 308 sc->max_sdtr_index = 15; 309 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 310 ASC_SET_EXTRA_CONTROL(iot, ioh, 311 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 312 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 313 ASC_SET_EXTRA_CONTROL(iot, ioh, 314 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 315 } else { 316 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 317 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 318 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 319 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 320 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 321 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 322 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 323 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 324 sc->max_sdtr_index = 7; 325 } 326 327 if (sc->bus_type == ASC_IS_PCI) 328 ASC_SET_EXTRA_CONTROL(iot, ioh, 329 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 330 331 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 332 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 333 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 334 sc->bus_type = ASC_IS_ISAPNP; 335 } 336 if ((sc->bus_type & ASC_IS_ISA) != 0) 337 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 338 339 for (i = 0; i <= ASC_MAX_TID; i++) { 340 sc->cur_dvc_qng[i] = 0; 341 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 342 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 343 } 344 } 345 346 347 /* 348 * This function initialize some ASC_SOFTC fields with values read from 349 * on-board EEProm. 350 */ 351 int16_t 352 AscInitFromEEP(sc) 353 ASC_SOFTC *sc; 354 { 355 bus_space_tag_t iot = sc->sc_iot; 356 bus_space_handle_t ioh = sc->sc_ioh; 357 ASCEEP_CONFIG eep_config_buf; 358 ASCEEP_CONFIG *eep_config; 359 u_int16_t chksum; 360 u_int16_t warn_code; 361 u_int16_t cfg_msw, cfg_lsw; 362 int i; 363 int write_eep = 0; 364 365 366 warn_code = 0; 367 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 368 AscStopQueueExe(iot, ioh); 369 370 AscStopChip(iot, ioh); 371 AscResetChipAndScsiBus(iot, ioh); 372 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 373 374 if ((AscStopChip(iot, ioh) == FALSE) || 375 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 376 AscResetChipAndScsiBus(iot, ioh); 377 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 378 } 379 if (AscIsChipHalted(iot, ioh) == FALSE) 380 return (-1); 381 382 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 383 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 384 return (-2); 385 386 eep_config = &eep_config_buf; 387 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 388 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 389 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 390 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 391 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 392 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 393 } 394 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 395 #ifdef ASC_DEBUG 396 AscPrintEEPConfig(eep_config, chksum); 397 #endif 398 if (chksum == 0) 399 chksum = 0xAA55; 400 401 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 402 warn_code |= ASC_WARN_AUTO_CONFIG; 403 if (sc->chip_version == 3) { 404 if (eep_config->cfg_lsw != cfg_lsw) { 405 warn_code |= ASC_WARN_EEPROM_RECOVER; 406 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 407 } 408 if (eep_config->cfg_msw != cfg_msw) { 409 warn_code |= ASC_WARN_EEPROM_RECOVER; 410 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 411 } 412 } 413 } 414 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 415 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 416 417 if (chksum != eep_config->chksum) { 418 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 419 ASC_CHIP_VER_PCI_ULTRA_3050) { 420 eep_config->init_sdtr = 0xFF; 421 eep_config->disc_enable = 0xFF; 422 eep_config->start_motor = 0xFF; 423 eep_config->use_cmd_qng = 0; 424 eep_config->max_total_qng = 0xF0; 425 eep_config->max_tag_qng = 0x20; 426 eep_config->cntl = 0xBFFF; 427 eep_config->chip_scsi_id = 7; 428 eep_config->no_scam = 0; 429 eep_config->adapter_info[0] = 0; 430 eep_config->adapter_info[1] = 0; 431 eep_config->adapter_info[2] = 0; 432 eep_config->adapter_info[3] = 0; 433 #if BYTE_ORDER == BIG_ENDIAN 434 eep_config->adapter_info[5] = 0; 435 /* Indicate EEPROM-less board. */ 436 eep_config->adapter_info[4] = 0xBB; 437 #else 438 eep_config->adapter_info[4] = 0; 439 /* Indicate EEPROM-less board. */ 440 eep_config->adapter_info[5] = 0xBB; 441 #endif 442 } else { 443 write_eep = 1; 444 warn_code |= ASC_WARN_EEPROM_CHKSUM; 445 } 446 } 447 sc->sdtr_enable = eep_config->init_sdtr; 448 sc->disc_enable = eep_config->disc_enable; 449 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 450 sc->isa_dma_speed = eep_config->isa_dma_speed; 451 sc->start_motor = eep_config->start_motor; 452 sc->dvc_cntl = eep_config->cntl; 453 #if BYTE_ORDER == BIG_ENDIAN 454 sc->adapter_info[0] = eep_config->adapter_info[1]; 455 sc->adapter_info[1] = eep_config->adapter_info[0]; 456 sc->adapter_info[2] = eep_config->adapter_info[3]; 457 sc->adapter_info[3] = eep_config->adapter_info[2]; 458 sc->adapter_info[4] = eep_config->adapter_info[5]; 459 sc->adapter_info[5] = eep_config->adapter_info[4]; 460 #else 461 sc->adapter_info[0] = eep_config->adapter_info[0]; 462 sc->adapter_info[1] = eep_config->adapter_info[1]; 463 sc->adapter_info[2] = eep_config->adapter_info[2]; 464 sc->adapter_info[3] = eep_config->adapter_info[3]; 465 sc->adapter_info[4] = eep_config->adapter_info[4]; 466 sc->adapter_info[5] = eep_config->adapter_info[5]; 467 #endif 468 469 if (!AscTestExternalLram(iot, ioh)) { 470 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 471 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 472 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 473 } else { 474 eep_config->cfg_msw |= 0x0800; 475 cfg_msw |= 0x0800; 476 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 477 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 478 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 479 } 480 } 481 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 482 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 483 484 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 485 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 486 487 if (eep_config->max_tag_qng > eep_config->max_total_qng) 488 eep_config->max_tag_qng = eep_config->max_total_qng; 489 490 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 491 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 492 493 sc->max_total_qng = eep_config->max_total_qng; 494 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 495 eep_config->use_cmd_qng) { 496 eep_config->disc_enable = eep_config->use_cmd_qng; 497 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 498 } 499 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 500 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 501 502 eep_config->chip_scsi_id &= ASC_MAX_TID; 503 sc->chip_scsi_id = eep_config->chip_scsi_id; 504 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 505 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 506 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 507 } 508 for (i = 0; i <= ASC_MAX_TID; i++) { 509 sc->max_tag_qng[i] = eep_config->max_tag_qng; 510 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 511 (sc->host_init_sdtr_index << 4); 512 } 513 514 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 515 if (write_eep) { 516 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 517 #ifdef ASC_DEBUG 518 AscPrintEEPConfig(eep_config, 0); 519 #endif 520 } 521 522 return (warn_code); 523 } 524 525 526 u_int16_t 527 AscInitFromASC_SOFTC(sc) 528 ASC_SOFTC *sc; 529 { 530 bus_space_tag_t iot = sc->sc_iot; 531 bus_space_handle_t ioh = sc->sc_ioh; 532 u_int16_t cfg_msw; 533 u_int16_t warn_code; 534 u_int16_t pci_device_id = sc->pci_device_id; 535 536 537 warn_code = 0; 538 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 539 540 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 541 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 542 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 543 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 544 } 545 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 546 sc->disc_enable = sc->cmd_qng_enabled; 547 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 548 } 549 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 550 warn_code |= ASC_WARN_AUTO_CONFIG; 551 } 552 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 553 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 554 } 555 if (sc->bus_type & ASC_IS_PCI) { 556 cfg_msw &= 0xFFC0; 557 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 558 559 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 560 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 561 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 562 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 563 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 564 } 565 } 566 } else if (sc->bus_type == ASC_IS_ISAPNP) { 567 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 568 ASC_CHIP_VER_ASYN_BUG) { 569 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 570 } 571 } 572 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 573 574 if (sc->bus_type & ASC_IS_ISA) { 575 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 576 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 577 } 578 return (warn_code); 579 } 580 581 582 /* 583 * - Initialize RISC chip 584 * - Intialize Lram 585 * - Load uCode into Lram 586 * - Enable Interrupts 587 */ 588 int 589 AscInitDriver(sc) 590 ASC_SOFTC *sc; 591 { 592 bus_space_tag_t iot = sc->sc_iot; 593 bus_space_handle_t ioh = sc->sc_ioh; 594 u_int32_t chksum; 595 596 597 if (!AscFindSignature(iot, ioh)) 598 return (1); 599 600 AscDisableInterrupt(iot, ioh); 601 602 AscInitLram(sc); 603 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 604 asc_mcode_size); 605 if (chksum != asc_mcode_chksum) 606 return (2); 607 608 if (AscInitMicroCodeVar(sc) == 0) 609 return (3); 610 611 AscEnableInterrupt(iot, ioh); 612 613 return (0); 614 } 615 616 617 int 618 AscFindSignature(iot, ioh) 619 bus_space_tag_t iot; 620 bus_space_handle_t ioh; 621 { 622 u_int16_t sig_word; 623 624 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 625 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 626 if (sig_word == ASC_1000_ID0W || 627 sig_word == ASC_1000_ID0W_FIX) 628 return (1); 629 } 630 return (0); 631 } 632 633 634 static void 635 AscInitLram(sc) 636 ASC_SOFTC *sc; 637 { 638 bus_space_tag_t iot = sc->sc_iot; 639 bus_space_handle_t ioh = sc->sc_ioh; 640 u_int8_t i; 641 u_int16_t s_addr; 642 643 644 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 645 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 646 647 i = ASC_MIN_ACTIVE_QNO; 648 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 649 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 651 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 652 i++; 653 s_addr += ASC_QBLK_SIZE; 654 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 655 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 657 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 658 } 659 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 660 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 661 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 662 i++; 663 s_addr += ASC_QBLK_SIZE; 664 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 665 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 666 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 667 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 668 } 669 } 670 671 672 void 673 AscReInitLram(sc) 674 ASC_SOFTC *sc; 675 { 676 677 AscInitLram(sc); 678 AscInitQLinkVar(sc); 679 } 680 681 682 static void 683 AscInitQLinkVar(sc) 684 ASC_SOFTC *sc; 685 { 686 bus_space_tag_t iot = sc->sc_iot; 687 bus_space_handle_t ioh = sc->sc_ioh; 688 u_int8_t i; 689 u_int16_t lram_addr; 690 691 692 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 693 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 694 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 695 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 696 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 697 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 698 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 699 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 700 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 701 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 702 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 703 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 704 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 705 lram_addr = ASC_QADR_BEG; 706 for (i = 0; i < 32; i++, lram_addr += 2) 707 AscWriteLramWord(iot, ioh, lram_addr, 0); 708 } 709 710 711 static int 712 AscResetChipAndScsiBus(bus_space_tag_t iot, 713 bus_space_handle_t ioh) 714 { 715 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 716 717 AscStopChip(iot, ioh); 718 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 719 720 DvcDelayNanoSecond(60000); 721 722 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 723 AscSetChipIH(iot, ioh, ASC_INS_HALT); 724 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 725 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 726 727 DvcSleepMilliSecond(200); 728 729 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 730 AscStartChip(iot, ioh); 731 732 DvcSleepMilliSecond(200); 733 734 return (AscIsChipHalted(iot, ioh)); 735 } 736 737 738 static u_int16_t 739 AscGetChipBusType(iot, ioh) 740 bus_space_tag_t iot; 741 bus_space_handle_t ioh; 742 { 743 u_int16_t chip_ver; 744 745 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 746 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 747 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 748 if(((ioh & 0x0C30) == 0x0C30) || ((ioh & 0x0C50) == 0x0C50)) { 749 return (ASC_IS_EISA); 750 } 751 else { 752 return (ASC_IS_VL); 753 } 754 } 755 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 756 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 757 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 758 return (ASC_IS_ISAPNP); 759 760 return (ASC_IS_ISA); 761 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 762 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 763 return (ASC_IS_PCI); 764 765 return (0); 766 } 767 768 769 static u_int16_t 770 AscGetEisaChipCfg(iot, ioh) 771 bus_space_tag_t iot; 772 bus_space_handle_t ioh; 773 { 774 int eisa_cfg_iop; 775 776 eisa_cfg_iop = ASC_GET_EISA_SLOT(ioh) | (ASC_EISA_CFG_IOP_MASK); 777 return (inw(eisa_cfg_iop)); 778 } 779 780 781 /******************************************************************************/ 782 /* Chip register routines */ 783 /******************************************************************************/ 784 785 786 static void 787 AscSetBank(iot, ioh, bank) 788 bus_space_tag_t iot; 789 bus_space_handle_t ioh; 790 u_int8_t bank; 791 { 792 u_int8_t val; 793 794 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 795 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 796 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 797 ASC_CC_CHIP_RESET)); 798 799 switch (bank) { 800 case 1: 801 val |= ASC_CC_BANK_ONE; 802 break; 803 804 case 2: 805 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 806 break; 807 808 default: 809 val &= ~ASC_CC_BANK_ONE; 810 } 811 812 ASC_SET_CHIP_CONTROL(iot, ioh, val); 813 return; 814 } 815 816 817 /******************************************************************************/ 818 /* Chip routines */ 819 /******************************************************************************/ 820 821 822 static int 823 AscStartChip(iot, ioh) 824 bus_space_tag_t iot; 825 bus_space_handle_t ioh; 826 { 827 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 828 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 829 return (0); 830 831 return (1); 832 } 833 834 835 static int 836 AscStopChip(iot, ioh) 837 bus_space_tag_t iot; 838 bus_space_handle_t ioh; 839 { 840 u_int8_t cc_val; 841 842 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 843 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 844 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 845 AscSetChipIH(iot, ioh, ASC_INS_HALT); 846 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 847 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 848 return (0); 849 850 return (1); 851 } 852 853 854 static u_int8_t 855 AscGetChipVersion(iot, ioh, bus_type) 856 bus_space_tag_t iot; 857 bus_space_handle_t ioh; 858 u_int16_t bus_type; 859 { 860 u_int16_t eisa_iop; 861 u_int8_t revision; 862 863 if (bus_type & ASC_IS_EISA) { 864 eisa_iop = ASC_GET_EISA_SLOT(ioh) | ASC_EISA_REV_IOP_MASK; 865 revision = inb(eisa_iop); 866 return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 867 } 868 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 869 } 870 871 872 static u_int8_t 873 AscSetChipScsiID(iot, ioh, new_id) 874 bus_space_tag_t iot; 875 bus_space_handle_t ioh; 876 u_int8_t new_id; 877 { 878 u_int16_t cfg_lsw; 879 880 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 881 return (new_id); 882 883 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 884 cfg_lsw &= 0xF8FF; 885 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 886 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 887 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 888 } 889 890 891 static u_int8_t 892 AscGetChipScsiCtrl(iot, ioh) 893 bus_space_tag_t iot; 894 bus_space_handle_t ioh; 895 { 896 u_int8_t scsi_ctrl; 897 898 AscSetBank(iot, ioh, 1); 899 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 900 AscSetBank(iot, ioh, 0); 901 return (scsi_ctrl); 902 } 903 904 905 static int 906 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 907 bus_space_tag_t iot; 908 bus_space_handle_t ioh; 909 u_int8_t tid_no; 910 u_int8_t sdtr_data; 911 { 912 int retval = FALSE; 913 914 if (AscHostReqRiscHalt(iot, ioh)) { 915 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 916 AscStartChip(iot, ioh); 917 } 918 return (retval); 919 } 920 921 922 static int 923 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 924 bus_space_tag_t iot; 925 bus_space_handle_t ioh; 926 u_int8_t id; 927 u_int8_t sdtr_data; 928 { 929 ASC_SCSI_BIT_ID_TYPE org_id; 930 int i; 931 int sta = TRUE; 932 933 AscSetBank(iot, ioh, 1); 934 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 935 for (i = 0; i <= ASC_MAX_TID; i++) 936 if (org_id == (0x01 << i)) 937 break; 938 939 org_id = i; 940 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 941 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 942 AscSetBank(iot, ioh, 0); 943 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 944 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 945 sta = FALSE; 946 } else 947 sta = FALSE; 948 949 AscSetBank(iot, ioh, 1); 950 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 951 AscSetBank(iot, ioh, 0); 952 return (sta); 953 } 954 955 956 static int 957 AscHostReqRiscHalt(iot, ioh) 958 bus_space_tag_t iot; 959 bus_space_handle_t ioh; 960 { 961 int count = 0; 962 int retval = 0; 963 u_int8_t saved_stop_code; 964 965 966 if (AscIsChipHalted(iot, ioh)) 967 return (1); 968 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 969 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 970 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 971 972 do { 973 if (AscIsChipHalted(iot, ioh)) { 974 retval = 1; 975 break; 976 } 977 DvcSleepMilliSecond(100); 978 } while (count++ < 20); 979 980 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 981 982 return (retval); 983 } 984 985 986 static int 987 AscIsChipHalted(iot, ioh) 988 bus_space_tag_t iot; 989 bus_space_handle_t ioh; 990 { 991 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 992 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 993 return (1); 994 995 return (0); 996 } 997 998 999 static void 1000 AscSetChipIH(iot, ioh, ins_code) 1001 bus_space_tag_t iot; 1002 bus_space_handle_t ioh; 1003 u_int16_t ins_code; 1004 { 1005 AscSetBank(iot, ioh, 1); 1006 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 1007 AscSetBank(iot, ioh, 0); 1008 1009 return; 1010 } 1011 1012 1013 /******************************************************************************/ 1014 /* Lram routines */ 1015 /******************************************************************************/ 1016 1017 1018 static u_int8_t 1019 AscReadLramByte(iot, ioh, addr) 1020 bus_space_tag_t iot; 1021 bus_space_handle_t ioh; 1022 u_int16_t addr; 1023 { 1024 u_int8_t byte_data; 1025 u_int16_t word_data; 1026 1027 1028 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1029 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1030 1031 if (addr & 1) { 1032 /* odd address */ 1033 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1034 } else { 1035 /* even address */ 1036 byte_data = (u_int8_t) (word_data & 0xFF); 1037 } 1038 1039 return (byte_data); 1040 } 1041 1042 1043 static void 1044 AscWriteLramByte(iot, ioh, addr, data) 1045 bus_space_tag_t iot; 1046 bus_space_handle_t ioh; 1047 u_int16_t addr; 1048 u_int8_t data; 1049 { 1050 u_int16_t word_data; 1051 1052 1053 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1054 1055 if (addr & 1) { 1056 /* odd address */ 1057 word_data &= 0x00FF; 1058 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1059 } else { 1060 /* even address */ 1061 word_data &= 0xFF00; 1062 word_data |= ((u_int16_t) data) & 0x00FF; 1063 } 1064 1065 AscWriteLramWord(iot, ioh, addr, word_data); 1066 } 1067 1068 1069 static u_int16_t 1070 AscReadLramWord(iot, ioh, addr) 1071 bus_space_tag_t iot; 1072 bus_space_handle_t ioh; 1073 u_int16_t addr; 1074 { 1075 1076 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1077 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1078 } 1079 1080 1081 static void 1082 AscWriteLramWord(iot, ioh, addr, data) 1083 bus_space_tag_t iot; 1084 bus_space_handle_t ioh; 1085 u_int16_t addr; 1086 u_int16_t data; 1087 { 1088 1089 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1090 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1091 } 1092 1093 1094 static u_int32_t 1095 AscReadLramDWord(iot, ioh, addr) 1096 bus_space_tag_t iot; 1097 bus_space_handle_t ioh; 1098 u_int16_t addr; 1099 { 1100 u_int16_t low_word, hi_word; 1101 1102 1103 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1104 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1105 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1106 1107 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1108 } 1109 1110 1111 static void 1112 AscWriteLramDWord(iot, ioh, addr, data) 1113 bus_space_tag_t iot; 1114 bus_space_handle_t ioh; 1115 u_int16_t addr; 1116 u_int32_t data; 1117 { 1118 1119 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1120 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1121 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1122 } 1123 1124 1125 static void 1126 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1127 bus_space_tag_t iot; 1128 bus_space_handle_t ioh; 1129 u_int16_t s_addr; 1130 u_int16_t s_words; 1131 int count; 1132 { 1133 int i; 1134 1135 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1136 for (i = 0; i < count; i++) 1137 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1138 } 1139 1140 1141 static void 1142 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1143 bus_space_tag_t iot; 1144 bus_space_handle_t ioh; 1145 u_int16_t s_addr; 1146 u_int16_t *s_buffer; 1147 int words; 1148 { 1149 int i; 1150 1151 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1152 for (i = 0; i < words; i++, s_buffer++) 1153 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1154 } 1155 1156 1157 static void 1158 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1159 bus_space_tag_t iot; 1160 bus_space_handle_t ioh; 1161 u_int16_t s_addr; 1162 u_int16_t *s_buffer; 1163 int words; 1164 { 1165 int i; 1166 1167 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1168 for (i = 0; i < words; i++, s_buffer++) 1169 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1170 } 1171 1172 1173 static void 1174 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1175 bus_space_tag_t iot; 1176 bus_space_handle_t ioh; 1177 u_int16_t s_addr; 1178 u_int32_t *s_buffer; 1179 int dwords; 1180 { 1181 int i; 1182 u_int32_t *pw; 1183 1184 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1185 1186 pw = s_buffer; 1187 for (i = 0; i < dwords; i++, pw++) { 1188 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1189 DELAY(1); 1190 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1191 } 1192 } 1193 1194 1195 static u_int32_t 1196 AscMemSumLramWord(iot, ioh, s_addr, words) 1197 bus_space_tag_t iot; 1198 bus_space_handle_t ioh; 1199 u_int16_t s_addr; 1200 int words; 1201 { 1202 u_int32_t sum = 0L; 1203 u_int16_t i; 1204 1205 1206 for (i = 0; i < words; i++, s_addr += 2) 1207 sum += AscReadLramWord(iot, ioh, s_addr); 1208 1209 return (sum); 1210 } 1211 1212 1213 static int 1214 AscTestExternalLram(iot, ioh) 1215 bus_space_tag_t iot; 1216 bus_space_handle_t ioh; 1217 { 1218 u_int16_t q_addr; 1219 u_int16_t saved_word; 1220 int retval; 1221 1222 1223 retval = 0; 1224 q_addr = ASC_QNO_TO_QADDR(241); 1225 saved_word = AscReadLramWord(iot, ioh, q_addr); 1226 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1227 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1228 DvcSleepMilliSecond(10); 1229 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1230 1231 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1232 retval = 1; 1233 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1234 } 1235 return (retval); 1236 } 1237 1238 1239 /******************************************************************************/ 1240 /* MicroCode routines */ 1241 /******************************************************************************/ 1242 1243 1244 static u_int16_t 1245 AscInitMicroCodeVar(sc) 1246 ASC_SOFTC *sc; 1247 { 1248 bus_space_tag_t iot = sc->sc_iot; 1249 bus_space_handle_t ioh = sc->sc_ioh; 1250 u_int32_t phy_addr; 1251 int i; 1252 1253 1254 for (i = 0; i <= ASC_MAX_TID; i++) 1255 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1256 sc->sdtr_period_offset[i]); 1257 1258 AscInitQLinkVar(sc); 1259 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1260 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1261 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1262 1263 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1264 ASC_OVERRUN_BSIZE)) == 0L) { 1265 return (0); 1266 } else { 1267 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1268 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1269 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1270 ASC_OVERRUN_BSIZE - 8); 1271 } 1272 1273 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1274 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1275 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1276 1277 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1278 return (0); 1279 } 1280 if (AscStartChip(iot, ioh) != 1) { 1281 return (0); 1282 } 1283 return (1); 1284 } 1285 1286 1287 static u_int32_t 1288 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 1289 bus_space_tag_t iot; 1290 bus_space_handle_t ioh; 1291 u_int16_t s_addr; 1292 u_int16_t *mcode_buf; 1293 u_int16_t mcode_size; 1294 { 1295 u_int32_t chksum; 1296 u_int16_t mcode_word_size; 1297 u_int16_t mcode_chksum; 1298 1299 mcode_word_size = mcode_size >> 1; 1300 /* clear board memory */ 1301 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1302 /* copy uCode to board memory */ 1303 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1304 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1305 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1306 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1307 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1308 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1309 1310 return (chksum); 1311 } 1312 1313 1314 static u_int32_t 1315 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1316 ASC_SOFTC *sc; 1317 u_int8_t *buf_addr; 1318 u_int32_t buf_size; 1319 { 1320 ASC_MIN_SG_HEAD sg_head; 1321 1322 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1323 if (AscGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1324 buf_size) { 1325 return (0L); 1326 } 1327 if (sg_head.entry_cnt > 1) { 1328 return (0L); 1329 } 1330 return (sg_head.sg_list[0].addr); 1331 } 1332 1333 1334 static u_int32_t 1335 AscGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 1336 ASC_SOFTC *sc; 1337 u_int8_t *buf_addr; 1338 u_int32_t buf_len; 1339 ASC_SG_HEAD *asc_sg_head_ptr; 1340 { 1341 u_int32_t buf_size; 1342 1343 buf_size = buf_len; 1344 asc_sg_head_ptr->entry_cnt = 1; 1345 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 1346 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 1347 1348 return (buf_size); 1349 } 1350 1351 1352 /******************************************************************************/ 1353 /* EEProm routines */ 1354 /******************************************************************************/ 1355 1356 1357 static int 1358 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1359 bus_space_tag_t iot; 1360 bus_space_handle_t ioh; 1361 u_int8_t cmd_reg; 1362 { 1363 u_int8_t read_back; 1364 int retry; 1365 1366 retry = 0; 1367 1368 while (TRUE) { 1369 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1370 DvcSleepMilliSecond(1); 1371 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1372 if (read_back == cmd_reg) 1373 return (1); 1374 1375 if (retry++ > ASC_EEP_MAX_RETRY) 1376 return (0); 1377 } 1378 } 1379 1380 1381 static int 1382 AscWriteEEPDataReg(iot, ioh, data_reg) 1383 bus_space_tag_t iot; 1384 bus_space_handle_t ioh; 1385 u_int16_t data_reg; 1386 { 1387 u_int16_t read_back; 1388 int retry; 1389 1390 retry = 0; 1391 while (TRUE) { 1392 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1393 DvcSleepMilliSecond(1); 1394 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1395 if (read_back == data_reg) 1396 return (1); 1397 1398 if (retry++ > ASC_EEP_MAX_RETRY) 1399 return (0); 1400 } 1401 } 1402 1403 1404 static void 1405 AscWaitEEPRead(void) 1406 { 1407 1408 DvcSleepMilliSecond(1); 1409 } 1410 1411 1412 static void 1413 AscWaitEEPWrite(void) 1414 { 1415 1416 DvcSleepMilliSecond(1); 1417 } 1418 1419 1420 static u_int16_t 1421 AscReadEEPWord(iot, ioh, addr) 1422 bus_space_tag_t iot; 1423 bus_space_handle_t ioh; 1424 u_int8_t addr; 1425 { 1426 u_int16_t read_wval; 1427 u_int8_t cmd_reg; 1428 1429 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1430 AscWaitEEPRead(); 1431 cmd_reg = addr | ASC_EEP_CMD_READ; 1432 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1433 AscWaitEEPRead(); 1434 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1435 AscWaitEEPRead(); 1436 1437 return (read_wval); 1438 } 1439 1440 1441 static u_int16_t 1442 AscWriteEEPWord(iot, ioh, addr, word_val) 1443 bus_space_tag_t iot; 1444 bus_space_handle_t ioh; 1445 u_int8_t addr; 1446 u_int16_t word_val; 1447 { 1448 u_int16_t read_wval; 1449 1450 read_wval = AscReadEEPWord(iot, ioh, addr); 1451 if (read_wval != word_val) { 1452 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1453 AscWaitEEPRead(); 1454 AscWriteEEPDataReg(iot, ioh, word_val); 1455 AscWaitEEPRead(); 1456 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1457 AscWaitEEPWrite(); 1458 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1459 AscWaitEEPRead(); 1460 return (AscReadEEPWord(iot, ioh, addr)); 1461 } 1462 return (read_wval); 1463 } 1464 1465 1466 static u_int16_t 1467 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1468 bus_space_tag_t iot; 1469 bus_space_handle_t ioh; 1470 ASCEEP_CONFIG *cfg_buf; 1471 u_int16_t bus_type; 1472 { 1473 u_int16_t wval; 1474 u_int16_t sum; 1475 u_int16_t *wbuf; 1476 int cfg_beg; 1477 int cfg_end; 1478 int s_addr; 1479 int isa_pnp_wsize; 1480 1481 1482 wbuf = (u_int16_t *) cfg_buf; 1483 sum = 0; 1484 isa_pnp_wsize = 0; 1485 1486 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1487 wval = AscReadEEPWord(iot, ioh, s_addr); 1488 sum += wval; 1489 *wbuf = wval; 1490 } 1491 1492 if (bus_type & ASC_IS_VL) { 1493 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1494 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1495 } else { 1496 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1497 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1498 } 1499 1500 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1501 wval = AscReadEEPWord(iot, ioh, s_addr); 1502 sum += wval; 1503 *wbuf = wval; 1504 } 1505 1506 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1507 1508 return (sum); 1509 } 1510 1511 1512 static int 1513 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1514 bus_space_tag_t iot; 1515 bus_space_handle_t ioh; 1516 ASCEEP_CONFIG *cfg_buf; 1517 u_int16_t bus_type; 1518 { 1519 int retry; 1520 int n_error; 1521 1522 retry = 0; 1523 while (TRUE) { 1524 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1525 break; 1526 1527 if (++retry > ASC_EEP_MAX_RETRY) 1528 break; 1529 } 1530 1531 return (n_error); 1532 } 1533 1534 1535 static int 1536 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1537 bus_space_tag_t iot; 1538 bus_space_handle_t ioh; 1539 ASCEEP_CONFIG *cfg_buf; 1540 u_int16_t bus_type; 1541 { 1542 int n_error; 1543 u_int16_t *wbuf; 1544 u_int16_t sum; 1545 int s_addr; 1546 int cfg_beg; 1547 int cfg_end; 1548 1549 wbuf = (u_int16_t *) cfg_buf; 1550 n_error = 0; 1551 sum = 0; 1552 1553 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1554 sum += *wbuf; 1555 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1556 n_error++; 1557 } 1558 1559 if (bus_type & ASC_IS_VL) { 1560 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1561 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1562 } else { 1563 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1564 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1565 } 1566 1567 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1568 sum += *wbuf; 1569 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1570 n_error++; 1571 } 1572 1573 *wbuf = sum; 1574 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1575 n_error++; 1576 1577 wbuf = (u_int16_t *) cfg_buf; 1578 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1579 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1580 n_error++; 1581 } 1582 1583 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1584 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1585 n_error++; 1586 } 1587 1588 return (n_error); 1589 } 1590 1591 1592 #ifdef ASC_DEBUG 1593 static void 1594 AscPrintEEPConfig(eep_config, chksum) 1595 ASCEEP_CONFIG *eep_config; 1596 u_int16_t chksum; 1597 { 1598 printf("---- ASC EEprom settings ----\n"); 1599 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1600 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1601 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1602 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1603 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1604 printf("start_motor = 0x%x\n", eep_config->start_motor); 1605 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1606 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1607 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1608 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1609 printf("no_scam = %d\n", eep_config->no_scam); 1610 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1611 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1612 printf("cntl = 0x%x\n", eep_config->cntl); 1613 #if BYTE_ORDER == BIG_ENDIAN 1614 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1615 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1616 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1617 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1618 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1619 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1620 #else 1621 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1622 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1623 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1624 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1625 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1626 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1627 #endif 1628 printf("checksum = 0x%x\n", eep_config->chksum); 1629 printf("calculated checksum = 0x%x\n", chksum); 1630 printf("-----------------------------\n"); 1631 } 1632 #endif 1633 1634 1635 /******************************************************************************/ 1636 /* Interrupt routines */ 1637 /******************************************************************************/ 1638 1639 1640 int 1641 AscISR(sc) 1642 ASC_SOFTC *sc; 1643 { 1644 bus_space_tag_t iot = sc->sc_iot; 1645 bus_space_handle_t ioh = sc->sc_ioh; 1646 u_int16_t chipstat; 1647 u_int16_t saved_ram_addr; 1648 u_int8_t ctrl_reg; 1649 u_int8_t saved_ctrl_reg; 1650 int int_pending; 1651 int status; 1652 u_int8_t host_flag; 1653 1654 1655 int_pending = FALSE; 1656 1657 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1658 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1659 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1660 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1661 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1662 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1663 int_pending = TRUE; 1664 sc->sdtr_done = 0; 1665 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1666 1667 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1668 1669 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1670 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1671 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1672 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1673 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1674 } 1675 } 1676 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1677 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1678 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1679 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1680 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1681 1682 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1683 AscAckInterrupt(iot, ioh); 1684 int_pending = TRUE; 1685 1686 if ((chipstat & ASC_CSW_HALTED) && 1687 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1688 AscIsrChipHalted(sc); 1689 saved_ctrl_reg &= ~ASC_CC_HALT; 1690 } else { 1691 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1692 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1693 } else { 1694 do { 1695 if ((status = AscIsrQDone(sc)) == 1) 1696 break; 1697 } while (status == 0x11); 1698 } 1699 1700 if (status & 0x80) 1701 int_pending = -1; 1702 } 1703 } 1704 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1705 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1706 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1707 1708 return (1); 1709 /* return(int_pending); */ 1710 } 1711 1712 1713 static int 1714 AscIsrQDone(sc) 1715 ASC_SOFTC *sc; 1716 { 1717 u_int8_t next_qp; 1718 u_int8_t n_q_used; 1719 u_int8_t sg_list_qp; 1720 u_int8_t sg_queue_cnt; 1721 u_int8_t q_cnt; 1722 u_int8_t done_q_tail; 1723 u_int8_t tid_no; 1724 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1725 ASC_SCSI_BIT_ID_TYPE target_id; 1726 bus_space_tag_t iot = sc->sc_iot; 1727 bus_space_handle_t ioh = sc->sc_ioh; 1728 u_int16_t q_addr; 1729 u_int16_t sg_q_addr; 1730 u_int8_t cur_target_qng; 1731 ASC_QDONE_INFO scsiq_buf; 1732 ASC_QDONE_INFO *scsiq; 1733 ASC_ISR_CALLBACK asc_isr_callback; 1734 1735 1736 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1737 n_q_used = 1; 1738 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1739 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1740 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1741 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1742 1743 if (next_qp != ASC_QLINK_END) { 1744 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1745 q_addr = ASC_QNO_TO_QADDR(next_qp); 1746 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1747 sc->max_dma_count); 1748 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1749 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1750 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1751 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1752 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1753 sg_q_addr = q_addr; 1754 sg_list_qp = next_qp; 1755 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1756 sg_list_qp = AscReadLramByte(iot, ioh, 1757 sg_q_addr + ASC_SCSIQ_B_FWD); 1758 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1759 if (sg_list_qp == ASC_QLINK_END) { 1760 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1761 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1762 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1763 panic("AscIsrQDone: Corrupted SG list encountered"); 1764 } 1765 AscWriteLramByte(iot, ioh, 1766 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1767 } 1768 n_q_used = sg_queue_cnt + 1; 1769 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1770 } 1771 if (sc->queue_full_or_busy & target_id) { 1772 cur_target_qng = AscReadLramByte(iot, ioh, 1773 ASC_QADR_BEG + scsiq->d2.target_ix); 1774 1775 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1776 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1777 scsi_busy &= ~target_id; 1778 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1779 sc->queue_full_or_busy &= ~target_id; 1780 } 1781 } 1782 if (sc->cur_total_qng >= n_q_used) { 1783 sc->cur_total_qng -= n_q_used; 1784 if (sc->cur_dvc_qng[tid_no] != 0) { 1785 sc->cur_dvc_qng[tid_no]--; 1786 } 1787 } else { 1788 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1789 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1790 panic("AscIsrQDone: Attempting to free more queues than are active"); 1791 } 1792 1793 if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) || 1794 ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1795 return (0x11); 1796 } else if (scsiq->q_status == ASC_QS_DONE) { 1797 scsiq->remain_bytes += scsiq->extra_bytes; 1798 1799 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1800 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1801 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1802 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1803 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1804 } 1805 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1806 AscStopChip(iot, ioh); 1807 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1808 DvcDelayNanoSecond(60000); 1809 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1810 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1811 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1812 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1813 } 1814 } 1815 (*asc_isr_callback) (sc, scsiq); 1816 1817 return (1); 1818 } else { 1819 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1820 panic("AscIsrQDone: completed scsiq with unknown status"); 1821 1822 return (0x80); 1823 } 1824 } 1825 return (0); 1826 } 1827 1828 1829 /* 1830 * handle all the conditions that may halt the board 1831 * waiting us to intervene 1832 */ 1833 static void 1834 AscIsrChipHalted(sc) 1835 ASC_SOFTC *sc; 1836 { 1837 bus_space_tag_t iot = sc->sc_iot; 1838 bus_space_handle_t ioh = sc->sc_ioh; 1839 EXT_MSG out_msg; 1840 u_int16_t int_halt_code; 1841 u_int16_t halt_q_addr; 1842 u_int8_t halt_qp; 1843 u_int8_t target_ix; 1844 u_int8_t tag_code; 1845 u_int8_t q_status; 1846 u_int8_t q_cntl; 1847 u_int8_t tid_no; 1848 u_int8_t cur_dvc_qng; 1849 u_int8_t asyn_sdtr; 1850 u_int8_t scsi_status; 1851 u_int8_t sdtr_data; 1852 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1853 ASC_SCSI_BIT_ID_TYPE target_id; 1854 1855 1856 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1857 1858 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1859 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1860 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1861 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1862 tid_no = ASC_TIX_TO_TID(target_ix); 1863 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1864 1865 if (sc->pci_fix_asyn_xfer & target_id) { 1866 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1867 } else { 1868 asyn_sdtr = 0; 1869 } 1870 1871 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1872 if (sc->pci_fix_asyn_xfer & target_id) { 1873 AscSetChipSDTR(iot, ioh, 0, tid_no); 1874 sc->sdtr_data[tid_no] = 0; 1875 } 1876 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1877 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1878 if (sc->pci_fix_asyn_xfer & target_id) { 1879 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1880 sc->sdtr_data[tid_no] = asyn_sdtr; 1881 } 1882 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1883 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1884 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1885 tid_no, asyn_sdtr); 1886 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1887 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1888 q_cntl |= ASC_QC_REQ_SENSE; 1889 1890 if (sc->init_sdtr & target_id) { 1891 sc->sdtr_done &= ~target_id; 1892 1893 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1894 q_cntl |= ASC_QC_MSG_OUT; 1895 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1896 (sc->max_sdtr_index - 1)], 1897 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1898 } 1899 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1900 1901 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1902 tag_code &= 0xDC; 1903 1904 if ((sc->pci_fix_asyn_xfer & target_id) && 1905 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1906 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1907 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1908 } 1909 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1910 1911 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1912 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1913 1914 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1915 1916 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1917 scsi_busy &= ~target_id; 1918 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1919 1920 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1921 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1922 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1923 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1924 1925 if ((out_msg.msg_type == MS_EXTEND) && 1926 (out_msg.msg_len == MS_SDTR_LEN) && 1927 (out_msg.msg_req == MS_SDTR_CODE)) { 1928 sc->init_sdtr &= ~target_id; 1929 sc->sdtr_done &= ~target_id; 1930 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1931 sc->sdtr_data[tid_no] = asyn_sdtr; 1932 } 1933 q_cntl &= ~ASC_QC_MSG_OUT; 1934 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1935 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1936 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1937 scsi_status = AscReadLramByte(iot, ioh, 1938 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1939 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1940 1941 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1942 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1943 scsi_busy |= target_id; 1944 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1945 sc->queue_full_or_busy |= target_id; 1946 1947 if (scsi_status == SS_QUEUE_FULL) { 1948 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1949 cur_dvc_qng -= 1; 1950 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1951 1952 AscWriteLramByte(iot, ioh, 1953 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1954 1955 #if ASC_QUEUE_FLOW_CONTROL 1956 if ((sc->device[tid_no] != NULL) && 1957 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1958 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1959 } 1960 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1961 } 1962 } 1963 } 1964 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1965 } 1966 return; 1967 } 1968 1969 1970 static int 1971 AscWaitTixISRDone(sc, target_ix) 1972 ASC_SOFTC *sc; 1973 u_int8_t target_ix; 1974 { 1975 u_int8_t cur_req; 1976 u_int8_t tid_no; 1977 int i = 0; 1978 1979 tid_no = ASC_TIX_TO_TID(target_ix); 1980 while (i++ < 10) { 1981 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1982 break; 1983 1984 DvcSleepMilliSecond(1000L); 1985 if (sc->cur_dvc_qng[tid_no] == cur_req) 1986 break; 1987 } 1988 return (1); 1989 } 1990 1991 static int 1992 AscWaitISRDone(sc) 1993 ASC_SOFTC *sc; 1994 { 1995 int tid; 1996 1997 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1998 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1999 2000 return (1); 2001 } 2002 2003 2004 static u_int8_t 2005 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 2006 bus_space_tag_t iot; 2007 bus_space_handle_t ioh; 2008 u_int16_t q_addr; 2009 ASC_QDONE_INFO *scsiq; 2010 u_int32_t max_dma_count; 2011 { 2012 u_int16_t _val; 2013 u_int8_t sg_queue_cnt; 2014 2015 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 2016 2017 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2018 scsiq->q_status = LO_BYTE(_val); 2019 scsiq->q_no = HI_BYTE(_val); 2020 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 2021 scsiq->cntl = LO_BYTE(_val); 2022 sg_queue_cnt = HI_BYTE(_val); 2023 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 2024 scsiq->sense_len = LO_BYTE(_val); 2025 scsiq->extra_bytes = HI_BYTE(_val); 2026 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 2027 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 2028 scsiq->remain_bytes &= max_dma_count; 2029 2030 return (sg_queue_cnt); 2031 } 2032 2033 2034 static void 2035 AscGetQDoneInfo(iot, ioh, addr, scsiq) 2036 bus_space_tag_t iot; 2037 bus_space_handle_t ioh; 2038 u_int16_t addr; 2039 ASC_QDONE_INFO *scsiq; 2040 { 2041 u_int16_t val; 2042 2043 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2044 2045 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2046 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 2047 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2048 scsiq->d2.target_ix = LO_BYTE(val); 2049 scsiq->d2.flag = HI_BYTE(val); 2050 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2051 scsiq->d2.cdb_len = LO_BYTE(val); 2052 scsiq->d2.tag_code = HI_BYTE(val); 2053 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2054 2055 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2056 scsiq->d3.done_stat = LO_BYTE(val); 2057 scsiq->d3.host_stat = HI_BYTE(val); 2058 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2059 scsiq->d3.scsi_stat = LO_BYTE(val); 2060 scsiq->d3.scsi_msg = HI_BYTE(val); 2061 } 2062 2063 2064 static void 2065 AscToggleIRQAct(iot, ioh) 2066 bus_space_tag_t iot; 2067 bus_space_handle_t ioh; 2068 { 2069 2070 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 2071 ASC_SET_CHIP_STATUS(iot, ioh, 0); 2072 } 2073 2074 2075 static void 2076 AscDisableInterrupt(iot, ioh) 2077 bus_space_tag_t iot; 2078 bus_space_handle_t ioh; 2079 { 2080 u_int16_t cfg; 2081 2082 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2083 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 2084 } 2085 2086 2087 static void 2088 AscEnableInterrupt(iot, ioh) 2089 bus_space_tag_t iot; 2090 bus_space_handle_t ioh; 2091 { 2092 u_int16_t cfg; 2093 2094 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2095 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2096 } 2097 2098 2099 u_int8_t 2100 AscGetChipIRQ(iot, ioh, bus_type) 2101 bus_space_tag_t iot; 2102 bus_space_handle_t ioh; 2103 u_int16_t bus_type; 2104 { 2105 u_int16_t cfg_lsw; 2106 u_int8_t chip_irq; 2107 2108 2109 if (bus_type & ASC_IS_EISA) { 2110 cfg_lsw = AscGetEisaChipCfg(iot, ioh); 2111 chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 2112 if((chip_irq == 13) || (chip_irq > 15)) 2113 return (0); 2114 return(chip_irq); 2115 } 2116 if ((bus_type & ASC_IS_VL) != 0) { 2117 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2118 chip_irq = (cfg_lsw >> 2) & 0x07; 2119 if ((chip_irq == 0) || 2120 (chip_irq == 4) || 2121 (chip_irq == 7)) { 2122 return (0); 2123 } 2124 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2125 } 2126 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2127 chip_irq = (cfg_lsw >> 2) & 0x03; 2128 if (chip_irq == 3) 2129 chip_irq += 2; 2130 return (chip_irq + ASC_MIN_IRQ_NO); 2131 } 2132 2133 2134 static u_int8_t 2135 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2136 bus_space_tag_t iot; 2137 bus_space_handle_t ioh; 2138 u_int8_t irq_no; 2139 u_int16_t bus_type; 2140 { 2141 u_int16_t cfg_lsw; 2142 2143 2144 if (bus_type & ASC_IS_VL) { 2145 if (irq_no) { 2146 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2147 irq_no = 0; 2148 else 2149 irq_no -= ASC_MIN_IRQ_NO - 1; 2150 } 2151 2152 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2153 cfg_lsw |= 0x0010; 2154 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2155 AscToggleIRQAct(iot, ioh); 2156 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2157 cfg_lsw |= (irq_no & 0x07) << 2; 2158 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2159 AscToggleIRQAct(iot, ioh); 2160 2161 return (AscGetChipIRQ(iot, ioh, bus_type)); 2162 } 2163 if (bus_type & ASC_IS_ISA) { 2164 if (irq_no == 15) 2165 irq_no -= 2; 2166 irq_no -= ASC_MIN_IRQ_NO; 2167 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2168 cfg_lsw |= (irq_no & 0x03) << 2; 2169 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2170 2171 return (AscGetChipIRQ(iot, ioh, bus_type)); 2172 } 2173 return (0); 2174 } 2175 2176 2177 static void 2178 AscAckInterrupt(iot, ioh) 2179 bus_space_tag_t iot; 2180 bus_space_handle_t ioh; 2181 { 2182 u_int8_t host_flag; 2183 u_int8_t risc_flag; 2184 u_int16_t loop; 2185 2186 2187 loop = 0; 2188 do { 2189 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2190 if (loop++ > 0x7FFF) 2191 break; 2192 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2193 2194 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2195 (~ASC_HOST_FLAG_ACK_INT); 2196 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2197 host_flag | ASC_HOST_FLAG_ACK_INT); 2198 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2199 2200 loop = 0; 2201 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2202 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2203 if (loop++ > 3) 2204 break; 2205 } 2206 2207 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2208 } 2209 2210 2211 static u_int32_t 2212 AscGetMaxDmaCount(bus_type) 2213 u_int16_t bus_type; 2214 { 2215 if (bus_type & ASC_IS_ISA) 2216 return (ASC_MAX_ISA_DMA_COUNT); 2217 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2218 return (ASC_MAX_VL_DMA_COUNT); 2219 return (ASC_MAX_PCI_DMA_COUNT); 2220 } 2221 2222 2223 u_int16_t 2224 AscGetIsaDmaChannel(iot, ioh) 2225 bus_space_tag_t iot; 2226 bus_space_handle_t ioh; 2227 { 2228 u_int16_t channel; 2229 2230 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2231 if (channel == 0x03) 2232 return (0); 2233 else if (channel == 0x00) 2234 return (7); 2235 return (channel + 4); 2236 } 2237 2238 2239 static u_int16_t 2240 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2241 bus_space_tag_t iot; 2242 bus_space_handle_t ioh; 2243 u_int16_t dma_channel; 2244 { 2245 u_int16_t cfg_lsw; 2246 u_int8_t value; 2247 2248 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2249 if (dma_channel == 7) 2250 value = 0x00; 2251 else 2252 value = dma_channel - 4; 2253 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2254 cfg_lsw |= value; 2255 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2256 return (AscGetIsaDmaChannel(iot, ioh)); 2257 } 2258 return (0); 2259 } 2260 2261 2262 static u_int8_t 2263 AscGetIsaDmaSpeed(iot, ioh) 2264 bus_space_tag_t iot; 2265 bus_space_handle_t ioh; 2266 { 2267 u_int8_t speed_value; 2268 2269 AscSetBank(iot, ioh, 1); 2270 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2271 speed_value &= 0x07; 2272 AscSetBank(iot, ioh, 0); 2273 return (speed_value); 2274 } 2275 2276 2277 static u_int8_t 2278 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2279 bus_space_tag_t iot; 2280 bus_space_handle_t ioh; 2281 u_int8_t speed_value; 2282 { 2283 speed_value &= 0x07; 2284 AscSetBank(iot, ioh, 1); 2285 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2286 AscSetBank(iot, ioh, 0); 2287 return (AscGetIsaDmaSpeed(iot, ioh)); 2288 } 2289 2290 2291 /******************************************************************************/ 2292 /* Messages routines */ 2293 /******************************************************************************/ 2294 2295 2296 static void 2297 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2298 ASC_SOFTC *sc; 2299 u_int16_t halt_q_addr; 2300 u_int8_t q_cntl; 2301 ASC_SCSI_BIT_ID_TYPE target_id; 2302 int tid_no; 2303 u_int8_t asyn_sdtr; 2304 { 2305 bus_space_tag_t iot = sc->sc_iot; 2306 bus_space_handle_t ioh = sc->sc_ioh; 2307 EXT_MSG ext_msg; 2308 u_int8_t sdtr_data; 2309 int sdtr_accept; 2310 2311 2312 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2313 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2314 2315 if (ext_msg.msg_type == MS_EXTEND && 2316 ext_msg.msg_req == MS_SDTR_CODE && 2317 ext_msg.msg_len == MS_SDTR_LEN) { 2318 sdtr_accept = TRUE; 2319 2320 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2321 sdtr_accept = FALSE; 2322 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2323 } 2324 if ((ext_msg.xfer_period < 2325 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2326 (ext_msg.xfer_period > 2327 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2328 sdtr_accept = FALSE; 2329 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2330 } 2331 if (sdtr_accept) { 2332 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2333 ext_msg.req_ack_offset); 2334 if (sdtr_data == 0xFF) { 2335 q_cntl |= ASC_QC_MSG_OUT; 2336 sc->init_sdtr &= ~target_id; 2337 sc->sdtr_done &= ~target_id; 2338 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2339 sc->sdtr_data[tid_no] = asyn_sdtr; 2340 } 2341 } 2342 if (ext_msg.req_ack_offset == 0) { 2343 q_cntl &= ~ASC_QC_MSG_OUT; 2344 sc->init_sdtr &= ~target_id; 2345 sc->sdtr_done &= ~target_id; 2346 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2347 } else { 2348 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2349 q_cntl &= ~ASC_QC_MSG_OUT; 2350 sc->sdtr_done |= target_id; 2351 sc->init_sdtr |= target_id; 2352 sc->pci_fix_asyn_xfer &= ~target_id; 2353 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2354 ext_msg.req_ack_offset); 2355 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2356 sc->sdtr_data[tid_no] = sdtr_data; 2357 } else { 2358 q_cntl |= ASC_QC_MSG_OUT; 2359 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2360 ext_msg.req_ack_offset); 2361 sc->pci_fix_asyn_xfer &= ~target_id; 2362 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2363 ext_msg.req_ack_offset); 2364 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2365 sc->sdtr_data[tid_no] = sdtr_data; 2366 sc->sdtr_done |= target_id; 2367 sc->init_sdtr |= target_id; 2368 } 2369 } 2370 } else if (ext_msg.msg_type == MS_EXTEND && 2371 ext_msg.msg_req == MS_WDTR_CODE && 2372 ext_msg.msg_len == MS_WDTR_LEN) { 2373 ext_msg.wdtr_width = 0; 2374 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2375 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2376 q_cntl |= ASC_QC_MSG_OUT; 2377 } else { 2378 ext_msg.msg_type = M1_MSG_REJECT; 2379 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2380 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2381 q_cntl |= ASC_QC_MSG_OUT; 2382 } 2383 2384 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2385 } 2386 2387 2388 static u_int8_t 2389 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2390 ASC_SOFTC *sc; 2391 u_int8_t sdtr_period; 2392 u_int8_t sdtr_offset; 2393 { 2394 bus_space_tag_t iot = sc->sc_iot; 2395 bus_space_handle_t ioh = sc->sc_ioh; 2396 EXT_MSG sdtr_buf; 2397 u_int8_t sdtr_period_index; 2398 2399 2400 sdtr_buf.msg_type = MS_EXTEND; 2401 sdtr_buf.msg_len = MS_SDTR_LEN; 2402 sdtr_buf.msg_req = MS_SDTR_CODE; 2403 sdtr_buf.xfer_period = sdtr_period; 2404 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2405 sdtr_buf.req_ack_offset = sdtr_offset; 2406 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2407 sc->max_sdtr_index) { 2408 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2409 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2410 return ((sdtr_period_index << 4) | sdtr_offset); 2411 } else { 2412 sdtr_buf.req_ack_offset = 0; 2413 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2414 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2415 return (0); 2416 } 2417 } 2418 2419 2420 /******************************************************************************/ 2421 /* SDTR routines */ 2422 /******************************************************************************/ 2423 2424 2425 static void 2426 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2427 bus_space_tag_t iot; 2428 bus_space_handle_t ioh; 2429 u_int8_t sdtr_data; 2430 u_int8_t tid_no; 2431 { 2432 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2433 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2434 } 2435 2436 2437 static u_int8_t 2438 AscCalSDTRData(sc, sdtr_period, syn_offset) 2439 ASC_SOFTC *sc; 2440 u_int8_t sdtr_period; 2441 u_int8_t syn_offset; 2442 { 2443 u_int8_t byte; 2444 u_int8_t sdtr_period_ix; 2445 2446 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2447 if (sdtr_period_ix > sc->max_sdtr_index) 2448 return (0xFF); 2449 2450 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2451 return (byte); 2452 } 2453 2454 2455 static u_int8_t 2456 AscGetSynPeriodIndex(sc, syn_time) 2457 ASC_SOFTC *sc; 2458 u_int8_t syn_time; 2459 { 2460 u_int8_t *period_table; 2461 int max_index; 2462 int min_index; 2463 int i; 2464 2465 period_table = sc->sdtr_period_tbl; 2466 max_index = sc->max_sdtr_index; 2467 min_index = sc->host_init_sdtr_index; 2468 if ((syn_time <= period_table[max_index])) { 2469 for (i = min_index; i < (max_index - 1); i++) { 2470 if (syn_time <= period_table[i]) 2471 return (i); 2472 } 2473 2474 return (max_index); 2475 } else 2476 return (max_index + 1); 2477 } 2478 2479 2480 /******************************************************************************/ 2481 /* Queue routines */ 2482 /******************************************************************************/ 2483 2484 /* 2485 * Send a command to the board 2486 */ 2487 int 2488 AscExeScsiQueue(sc, scsiq) 2489 ASC_SOFTC *sc; 2490 ASC_SCSI_Q *scsiq; 2491 { 2492 bus_space_tag_t iot = sc->sc_iot; 2493 bus_space_handle_t ioh = sc->sc_ioh; 2494 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2495 int retval; 2496 int n_q_required; 2497 int disable_syn_offset_one_fix; 2498 int i; 2499 u_int32_t addr; 2500 u_int16_t sg_entry_cnt = 0; 2501 u_int16_t sg_entry_cnt_minus_one = 0; 2502 u_int8_t target_ix; 2503 u_int8_t tid_no; 2504 u_int8_t sdtr_data; 2505 u_int8_t extra_bytes; 2506 u_int8_t scsi_cmd; 2507 u_int32_t data_cnt; 2508 2509 2510 scsiq->q1.q_no = 0; 2511 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2512 scsiq->q1.extra_bytes = 0; 2513 2514 retval = ASC_BUSY; 2515 target_ix = scsiq->q2.target_ix; 2516 tid_no = ASC_TIX_TO_TID(target_ix); 2517 n_q_required = 1; 2518 2519 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2520 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2521 sc->sdtr_done &= ~scsiq->q1.target_id; 2522 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2523 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2524 (sc->max_sdtr_index - 1)], 2525 sdtr_data & ASC_SYN_MAX_OFFSET); 2526 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2527 } 2528 /* 2529 * if there is just one segment into S/G list then 2530 * map it as it was a single request, filling 2531 * data_addr and data_cnt of ASC_SCSIQ structure. 2532 */ 2533 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2534 sg_entry_cnt = sg_head->entry_cnt; 2535 2536 if (sg_entry_cnt < 1) 2537 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2538 sg_entry_cnt); 2539 2540 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2541 panic("AscExeScsiQueue: Queue with too many segs."); 2542 2543 if (sg_entry_cnt == 1) { 2544 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2545 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2546 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2547 } 2548 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2549 } 2550 scsi_cmd = scsiq->cdbptr[0]; 2551 disable_syn_offset_one_fix = FALSE; 2552 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2553 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2554 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2555 data_cnt = 0; 2556 for (i = 0; i < sg_entry_cnt; i++) 2557 data_cnt += sg_head->sg_list[i].bytes; 2558 } else { 2559 data_cnt = scsiq->q1.data_cnt; 2560 } 2561 2562 if (data_cnt != 0ul) { 2563 if (data_cnt < 512ul) { 2564 disable_syn_offset_one_fix = TRUE; 2565 } else { 2566 if (scsi_cmd == SCSICMD_Inquiry || 2567 scsi_cmd == SCSICMD_RequestSense || 2568 scsi_cmd == SCSICMD_ReadCapacity || 2569 scsi_cmd == SCSICMD_ReadTOC || 2570 scsi_cmd == SCSICMD_ModeSelect6 || 2571 scsi_cmd == SCSICMD_ModeSense6 || 2572 scsi_cmd == SCSICMD_ModeSelect10 || 2573 scsi_cmd == SCSICMD_ModeSense10) { 2574 disable_syn_offset_one_fix = TRUE; 2575 } 2576 } 2577 } 2578 } 2579 if (disable_syn_offset_one_fix) { 2580 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2581 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2582 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2583 } else { 2584 scsiq->q2.tag_code &= 0x23; 2585 } 2586 2587 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2588 if (sc->bug_fix_cntl) { 2589 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2590 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2591 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2592 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2593 extra_bytes = addr & 0x0003; 2594 if ((extra_bytes != 0) && 2595 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2596 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2597 scsiq->q1.extra_bytes = extra_bytes; 2598 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2599 extra_bytes; 2600 } 2601 } 2602 } 2603 } 2604 sg_head->entry_to_copy = sg_head->entry_cnt; 2605 n_q_required = AscSgListToQueue(sg_entry_cnt); 2606 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2607 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2608 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2609 } 2610 } else { 2611 if (sc->bug_fix_cntl) { 2612 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2613 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2614 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2615 extra_bytes = addr & 0x0003; 2616 if ((extra_bytes != 0) && 2617 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2618 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2619 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2620 scsiq->q1.data_cnt -= extra_bytes; 2621 scsiq->q1.extra_bytes = extra_bytes; 2622 } 2623 } 2624 } 2625 } 2626 } 2627 n_q_required = 1; 2628 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2629 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2630 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2631 } 2632 } 2633 2634 return (retval); 2635 } 2636 2637 2638 static int 2639 AscSendScsiQueue(sc, scsiq, n_q_required) 2640 ASC_SOFTC *sc; 2641 ASC_SCSI_Q *scsiq; 2642 u_int8_t n_q_required; 2643 { 2644 bus_space_tag_t iot = sc->sc_iot; 2645 bus_space_handle_t ioh = sc->sc_ioh; 2646 u_int8_t free_q_head; 2647 u_int8_t next_qp; 2648 u_int8_t tid_no; 2649 u_int8_t target_ix; 2650 int retval; 2651 2652 2653 target_ix = scsiq->q2.target_ix; 2654 tid_no = ASC_TIX_TO_TID(target_ix); 2655 retval = ASC_BUSY; 2656 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2657 2658 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2659 != ASC_QLINK_END) { 2660 if (n_q_required > 1) { 2661 sc->last_q_shortage = 0; 2662 scsiq->sg_head->queue_cnt = n_q_required - 1; 2663 } 2664 scsiq->q1.q_no = free_q_head; 2665 2666 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2667 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2668 sc->cur_total_qng += n_q_required; 2669 sc->cur_dvc_qng[tid_no]++; 2670 } 2671 } 2672 return (retval); 2673 } 2674 2675 2676 static int 2677 AscPutReadySgListQueue(sc, scsiq, q_no) 2678 ASC_SOFTC *sc; 2679 ASC_SCSI_Q *scsiq; 2680 u_int8_t q_no; 2681 { 2682 bus_space_tag_t iot = sc->sc_iot; 2683 bus_space_handle_t ioh = sc->sc_ioh; 2684 int retval; 2685 int i; 2686 ASC_SG_HEAD *sg_head; 2687 ASC_SG_LIST_Q scsi_sg_q; 2688 u_int32_t saved_data_addr; 2689 u_int32_t saved_data_cnt; 2690 u_int16_t sg_list_dwords; 2691 u_int16_t sg_index; 2692 u_int16_t sg_entry_cnt; 2693 u_int16_t q_addr; 2694 u_int8_t next_qp; 2695 2696 2697 saved_data_addr = scsiq->q1.data_addr; 2698 saved_data_cnt = scsiq->q1.data_cnt; 2699 2700 if ((sg_head = scsiq->sg_head) != 0) { 2701 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2702 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2703 sg_entry_cnt = sg_head->entry_cnt - 1; 2704 if (sg_entry_cnt != 0) { 2705 q_addr = ASC_QNO_TO_QADDR(q_no); 2706 sg_index = 1; 2707 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2708 scsi_sg_q.sg_head_qp = q_no; 2709 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2710 2711 for (i = 0; i < sg_head->queue_cnt; i++) { 2712 scsi_sg_q.seq_no = i + 1; 2713 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2714 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2715 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2716 if (i == 0) { 2717 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2718 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2719 } else { 2720 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2721 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2722 } 2723 } else { 2724 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2725 sg_list_dwords = sg_entry_cnt << 1; 2726 if (i == 0) { 2727 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2728 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2729 } else { 2730 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2731 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2732 } 2733 2734 sg_entry_cnt = 0; 2735 } 2736 2737 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2738 scsi_sg_q.q_no = next_qp; 2739 q_addr = ASC_QNO_TO_QADDR(next_qp); 2740 2741 /* 2742 * Tell the board how many entries are in the S/G list 2743 */ 2744 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2745 (u_int16_t *) & scsi_sg_q, 2746 sizeof(ASC_SG_LIST_Q) >> 1); 2747 /* 2748 * Tell the board the addresses of the S/G list segments 2749 */ 2750 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2751 (u_int32_t *) & sg_head->sg_list[sg_index], 2752 sg_list_dwords); 2753 sg_index += ASC_SG_LIST_PER_Q; 2754 } 2755 } 2756 } 2757 retval = AscPutReadyQueue(sc, scsiq, q_no); 2758 scsiq->q1.data_addr = saved_data_addr; 2759 scsiq->q1.data_cnt = saved_data_cnt; 2760 return (retval); 2761 } 2762 2763 2764 static int 2765 AscPutReadyQueue(sc, scsiq, q_no) 2766 ASC_SOFTC *sc; 2767 ASC_SCSI_Q *scsiq; 2768 u_int8_t q_no; 2769 { 2770 bus_space_tag_t iot = sc->sc_iot; 2771 bus_space_handle_t ioh = sc->sc_ioh; 2772 u_int16_t q_addr; 2773 u_int8_t tid_no; 2774 u_int8_t sdtr_data; 2775 u_int8_t syn_period_ix; 2776 u_int8_t syn_offset; 2777 2778 2779 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2780 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2781 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2782 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2783 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2784 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2785 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2786 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2787 } 2788 q_addr = ASC_QNO_TO_QADDR(q_no); 2789 2790 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2791 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2792 } 2793 scsiq->q1.status = ASC_QS_FREE; 2794 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2795 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2796 2797 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2798 2799 /* 2800 * Let's start the command 2801 */ 2802 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2803 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2804 2805 return (ASC_NOERROR); 2806 } 2807 2808 2809 static void 2810 AscPutSCSIQ(iot, ioh, addr, scsiq) 2811 bus_space_tag_t iot; 2812 bus_space_handle_t ioh; 2813 u_int16_t addr; 2814 ASC_SCSI_Q *scsiq; 2815 { 2816 u_int16_t val; 2817 2818 2819 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2820 2821 /* ASC_SCSIQ_1 */ 2822 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2823 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2824 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2825 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2826 val = LO_WORD(scsiq->q1.data_addr); 2827 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2828 val = HI_WORD(scsiq->q1.data_addr); 2829 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2830 val = LO_WORD(scsiq->q1.data_cnt); 2831 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2832 val = HI_WORD(scsiq->q1.data_cnt); 2833 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2834 val = LO_WORD(scsiq->q1.sense_addr); 2835 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2836 val = HI_WORD(scsiq->q1.sense_addr); 2837 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2838 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2839 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2840 2841 /* ASC_SCSIQ_2 */ 2842 val = LO_WORD(scsiq->q2.ccb_ptr); 2843 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2844 val = HI_WORD(scsiq->q2.ccb_ptr); 2845 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2846 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2847 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2848 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2849 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2850 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2851 } 2852 2853 2854 static int 2855 AscSgListToQueue(sg_list) 2856 int sg_list; 2857 { 2858 int n_sg_list_qs; 2859 2860 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2861 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2862 n_sg_list_qs++; 2863 2864 return (n_sg_list_qs + 1); 2865 } 2866 2867 2868 static u_int 2869 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2870 ASC_SOFTC *sc; 2871 u_int8_t target_ix; 2872 u_int8_t n_qs; 2873 { 2874 u_int cur_used_qs; 2875 u_int cur_free_qs; 2876 2877 2878 if (n_qs == 1) { 2879 cur_used_qs = sc->cur_total_qng + 2880 sc->last_q_shortage + 2881 ASC_MIN_FREE_Q; 2882 } else { 2883 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2884 } 2885 2886 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2887 cur_free_qs = sc->max_total_qng - cur_used_qs; 2888 return (cur_free_qs); 2889 } 2890 if (n_qs > 1) 2891 if ((n_qs > sc->last_q_shortage) && 2892 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2893 sc->last_q_shortage = n_qs; 2894 } 2895 return (0); 2896 } 2897 2898 2899 static u_int8_t 2900 AscAllocFreeQueue(iot, ioh, free_q_head) 2901 bus_space_tag_t iot; 2902 bus_space_handle_t ioh; 2903 u_int8_t free_q_head; 2904 { 2905 u_int16_t q_addr; 2906 u_int8_t next_qp; 2907 u_int8_t q_status; 2908 2909 2910 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2911 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2912 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2913 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2914 return (next_qp); 2915 2916 return (ASC_QLINK_END); 2917 } 2918 2919 2920 static u_int8_t 2921 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2922 bus_space_tag_t iot; 2923 bus_space_handle_t ioh; 2924 u_int8_t free_q_head; 2925 u_int8_t n_free_q; 2926 { 2927 u_int8_t i; 2928 2929 for (i = 0; i < n_free_q; i++) { 2930 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2931 if (free_q_head == ASC_QLINK_END) 2932 break; 2933 } 2934 2935 return (free_q_head); 2936 } 2937 2938 2939 static int 2940 AscStopQueueExe(iot, ioh) 2941 bus_space_tag_t iot; 2942 bus_space_handle_t ioh; 2943 { 2944 int count = 0; 2945 2946 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2947 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2948 do { 2949 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2950 ASC_STOP_ACK_RISC_STOP) 2951 return (1); 2952 2953 DvcSleepMilliSecond(100); 2954 } while (count++ < 20); 2955 } 2956 return (0); 2957 } 2958 2959 2960 static void 2961 AscStartQueueExe(iot, ioh) 2962 bus_space_tag_t iot; 2963 bus_space_handle_t ioh; 2964 { 2965 2966 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2967 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2968 } 2969 2970 2971 static void 2972 AscCleanUpBusyQueue(iot, ioh) 2973 bus_space_tag_t iot; 2974 bus_space_handle_t ioh; 2975 { 2976 int count = 0; 2977 u_int8_t stop_code; 2978 2979 2980 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2981 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2982 do { 2983 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2984 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2985 break; 2986 2987 DvcSleepMilliSecond(100); 2988 } while (count++ < 20); 2989 } 2990 } 2991 2992 2993 static int 2994 _AscWaitQDone(iot, ioh, scsiq) 2995 bus_space_tag_t iot; 2996 bus_space_handle_t ioh; 2997 ASC_SCSI_Q *scsiq; 2998 { 2999 u_int16_t q_addr; 3000 u_int8_t q_status; 3001 int count = 0; 3002 3003 while (scsiq->q1.q_no == 0); 3004 3005 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 3006 do { 3007 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 3008 DvcSleepMilliSecond(100L); 3009 if (count++ > 30) 3010 return (0); 3011 3012 } while ((q_status & ASC_QS_READY) != 0); 3013 3014 return (1); 3015 } 3016 3017 3018 static int 3019 AscCleanUpDiscQueue(iot, ioh) 3020 bus_space_tag_t iot; 3021 bus_space_handle_t ioh; 3022 { 3023 int count; 3024 u_int8_t stop_code; 3025 3026 count = 0; 3027 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 3028 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 3029 do { 3030 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 3031 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 3032 break; 3033 3034 DvcSleepMilliSecond(100); 3035 } while (count++ < 20); 3036 } 3037 return (1); 3038 } 3039 3040 3041 /******************************************************************************/ 3042 /* Abort and Reset CCB routines */ 3043 /******************************************************************************/ 3044 3045 3046 int 3047 AscAbortCCB(sc, ccb) 3048 ASC_SOFTC *sc; 3049 ADV_CCB *ccb; 3050 { 3051 bus_space_tag_t iot = sc->sc_iot; 3052 bus_space_handle_t ioh = sc->sc_ioh; 3053 int retval; 3054 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3055 3056 3057 retval = -1; 3058 saved_unit_not_ready = sc->unit_not_ready; 3059 sc->unit_not_ready = 0xFF; 3060 AscWaitISRDone(sc); 3061 if (AscStopQueueExe(iot, ioh) == 1) { 3062 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 3063 retval = 1; 3064 AscCleanUpBusyQueue(iot, ioh); 3065 AscStartQueueExe(iot, ioh); 3066 } else { 3067 retval = 0; 3068 AscStartQueueExe(iot, ioh); 3069 } 3070 } 3071 sc->unit_not_ready = saved_unit_not_ready; 3072 3073 return (retval); 3074 } 3075 3076 3077 static int 3078 AscRiscHaltedAbortCCB(sc, ccb) 3079 ASC_SOFTC *sc; 3080 ADV_CCB *ccb; 3081 { 3082 bus_space_tag_t iot = sc->sc_iot; 3083 bus_space_handle_t ioh = sc->sc_ioh; 3084 u_int16_t q_addr; 3085 u_int8_t q_no; 3086 ASC_QDONE_INFO scsiq_buf; 3087 ASC_QDONE_INFO *scsiq; 3088 ASC_ISR_CALLBACK asc_isr_callback; 3089 int last_int_level; 3090 3091 3092 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3093 last_int_level = DvcEnterCritical(); 3094 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3095 3096 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3097 q_addr = ASC_QNO_TO_QADDR(q_no); 3098 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 3099 q_addr + ASC_SCSIQ_D_CCBPTR); 3100 if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) { 3101 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3102 if (((scsiq->q_status & ASC_QS_READY) != 0) 3103 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 3104 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3105 scsiq->q_status |= ASC_QS_ABORTED; 3106 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3107 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3108 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3109 scsiq->q_status); 3110 (*asc_isr_callback) (sc, scsiq); 3111 return (1); 3112 } 3113 } 3114 } 3115 3116 DvcLeaveCritical(last_int_level); 3117 return (0); 3118 } 3119 3120 3121 static int 3122 AscRiscHaltedAbortTIX(sc, target_ix) 3123 ASC_SOFTC *sc; 3124 u_int8_t target_ix; 3125 { 3126 bus_space_tag_t iot = sc->sc_iot; 3127 bus_space_handle_t ioh = sc->sc_ioh; 3128 u_int16_t q_addr; 3129 u_int8_t q_no; 3130 ASC_QDONE_INFO scsiq_buf; 3131 ASC_QDONE_INFO *scsiq; 3132 ASC_ISR_CALLBACK asc_isr_callback; 3133 int last_int_level; 3134 3135 3136 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3137 last_int_level = DvcEnterCritical(); 3138 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3139 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3140 q_addr = ASC_QNO_TO_QADDR(q_no); 3141 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3142 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3143 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3144 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3145 if (scsiq->d2.target_ix == target_ix) { 3146 scsiq->q_status |= ASC_QS_ABORTED; 3147 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3148 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3149 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3150 scsiq->q_status); 3151 (*asc_isr_callback) (sc, scsiq); 3152 } 3153 } 3154 } 3155 DvcLeaveCritical(last_int_level); 3156 return (1); 3157 } 3158 3159 3160 /* 3161 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3162 * so we cannot use this function with the actual NetBSD SCSI layer 3163 * because at boot time interrupts are disabled. 3164 */ 3165 int 3166 AscResetDevice(sc, target_ix) 3167 ASC_SOFTC *sc; 3168 u_char target_ix; 3169 { 3170 bus_space_tag_t iot = sc->sc_iot; 3171 bus_space_handle_t ioh = sc->sc_ioh; 3172 int retval; 3173 u_int8_t tid_no; 3174 ASC_SCSI_BIT_ID_TYPE target_id; 3175 int i; 3176 ASC_SCSI_REQ_Q scsiq_buf; 3177 ASC_SCSI_REQ_Q *scsiq; 3178 u_int8_t *buf; 3179 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3180 3181 3182 tid_no = ASC_TIX_TO_TID(target_ix); 3183 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3184 saved_unit_not_ready = sc->unit_not_ready; 3185 sc->unit_not_ready = target_id; 3186 retval = ASC_ERROR; 3187 3188 AscWaitTixISRDone(sc, target_ix); 3189 3190 if (AscStopQueueExe(iot, ioh) == 1) { 3191 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3192 AscCleanUpBusyQueue(iot, ioh); 3193 AscStartQueueExe(iot, ioh); 3194 AscWaitTixISRDone(sc, target_ix); 3195 retval = ASC_NOERROR; 3196 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3197 buf = (u_char *) & scsiq_buf; 3198 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3199 *buf++ = 0x00; 3200 scsiq->q1.status = (u_char) ASC_QS_READY; 3201 scsiq->q2.cdb_len = 6; 3202 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3203 scsiq->q1.target_id = target_id; 3204 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3205 scsiq->cdbptr = scsiq->cdb; 3206 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3207 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3208 sc->unit_not_ready &= ~target_id; 3209 sc->sdtr_done |= target_id; 3210 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3211 sc->unit_not_ready = target_id; 3212 DvcSleepMilliSecond(1000); 3213 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3214 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3215 AscCleanUpDiscQueue(iot, ioh); 3216 AscStartQueueExe(iot, ioh); 3217 if (sc->pci_fix_asyn_xfer & target_id) 3218 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3219 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3220 AscWaitTixISRDone(sc, target_ix); 3221 } 3222 } else 3223 retval = ASC_BUSY; 3224 sc->sdtr_done &= ~target_id; 3225 } else { 3226 retval = ASC_ERROR; 3227 AscStartQueueExe(iot, ioh); 3228 } 3229 } 3230 sc->unit_not_ready = saved_unit_not_ready; 3231 return (retval); 3232 } 3233 3234 3235 int 3236 AscResetBus(sc) 3237 ASC_SOFTC *sc; 3238 { 3239 bus_space_tag_t iot = sc->sc_iot; 3240 bus_space_handle_t ioh = sc->sc_ioh; 3241 int retval; 3242 int i; 3243 3244 3245 sc->unit_not_ready = 0xFF; 3246 retval = ASC_NOERROR; 3247 3248 AscWaitISRDone(sc); 3249 AscStopQueueExe(iot, ioh); 3250 sc->sdtr_done = 0; 3251 AscResetChipAndScsiBus(iot, ioh); 3252 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3253 AscReInitLram(sc); 3254 for (i = 0; i <= ASC_MAX_TID; i++) { 3255 sc->cur_dvc_qng[i] = 0; 3256 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3257 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3258 } 3259 3260 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3261 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3262 retval = ASC_ERROR; 3263 3264 if (AscStartChip(iot, ioh) == 0) 3265 retval = ASC_ERROR; 3266 3267 AscStartQueueExe(iot, ioh); 3268 sc->unit_not_ready = 0; 3269 sc->queue_full_or_busy = 0; 3270 return (retval); 3271 } 3272 3273 3274 /******************************************************************************/ 3275 /* Error Handling routines */ 3276 /******************************************************************************/ 3277 3278 3279 static int 3280 AscSetLibErrorCode(sc, err_code) 3281 ASC_SOFTC *sc; 3282 u_int16_t err_code; 3283 { 3284 /* 3285 * if(sc->err_code == 0) { sc->err_code = err_code; 3286 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3287 err_code); 3288 /* 3289 * } 3290 */ 3291 return (err_code); 3292 } 3293 3294 3295 /******************************************************************************/ 3296 /* Handle bugged borads routines */ 3297 /******************************************************************************/ 3298 3299 3300 void 3301 AscInquiryHandling(sc, tid_no, inq) 3302 ASC_SOFTC *sc; 3303 u_int8_t tid_no; 3304 ASC_SCSI_INQUIRY *inq; 3305 { 3306 bus_space_tag_t iot = sc->sc_iot; 3307 bus_space_handle_t ioh = sc->sc_ioh; 3308 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3309 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3310 3311 3312 orig_init_sdtr = sc->init_sdtr; 3313 orig_use_tagged_qng = sc->use_tagged_qng; 3314 3315 sc->init_sdtr &= ~tid_bit; 3316 sc->can_tagged_qng &= ~tid_bit; 3317 sc->use_tagged_qng &= ~tid_bit; 3318 3319 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3320 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3321 sc->init_sdtr |= tid_bit; 3322 3323 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3324 if (AscTagQueuingSafe(inq)) { 3325 sc->use_tagged_qng |= tid_bit; 3326 sc->can_tagged_qng |= tid_bit; 3327 } 3328 } 3329 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3330 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3331 sc->disc_enable); 3332 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3333 sc->use_tagged_qng); 3334 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3335 sc->can_tagged_qng); 3336 3337 sc->max_dvc_qng[tid_no] = 3338 sc->max_tag_qng[tid_no]; 3339 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3340 sc->max_dvc_qng[tid_no]); 3341 } 3342 if (orig_init_sdtr != sc->init_sdtr) 3343 AscAsyncFix(sc, tid_no, inq); 3344 } 3345 3346 3347 static int 3348 AscTagQueuingSafe(inq) 3349 ASC_SCSI_INQUIRY *inq; 3350 { 3351 if ((inq->add_len >= 32) && 3352 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3353 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3354 return 0; 3355 } 3356 return 1; 3357 } 3358 3359 3360 static void 3361 AscAsyncFix(sc, tid_no, inq) 3362 ASC_SOFTC *sc; 3363 u_int8_t tid_no; 3364 ASC_SCSI_INQUIRY *inq; 3365 { 3366 u_int8_t dvc_type; 3367 ASC_SCSI_BIT_ID_TYPE tid_bits; 3368 3369 3370 dvc_type = inq->byte0.peri_dvc_type; 3371 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3372 3373 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3374 if (!(sc->init_sdtr & tid_bits)) { 3375 if ((dvc_type == SCSI_TYPE_CDROM) && 3376 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3377 sc->pci_fix_asyn_xfer_always |= tid_bits; 3378 } 3379 sc->pci_fix_asyn_xfer |= tid_bits; 3380 if ((dvc_type == SCSI_TYPE_PROC) || 3381 (dvc_type == SCSI_TYPE_SCANNER)) { 3382 sc->pci_fix_asyn_xfer &= ~tid_bits; 3383 } 3384 if ((dvc_type == SCSI_TYPE_SASD) && 3385 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3386 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3387 sc->pci_fix_asyn_xfer &= ~tid_bits; 3388 } 3389 if ((dvc_type == SCSI_TYPE_SASD) && 3390 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3391 sc->pci_fix_asyn_xfer &= ~tid_bits; 3392 } 3393 if ((dvc_type == SCSI_TYPE_CDROM) && 3394 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3395 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3396 sc->pci_fix_asyn_xfer &= ~tid_bits; 3397 } 3398 if ((dvc_type == SCSI_TYPE_CDROM) && 3399 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3400 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3401 sc->pci_fix_asyn_xfer &= ~tid_bits; 3402 } 3403 if (sc->pci_fix_asyn_xfer & tid_bits) { 3404 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3405 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3406 } 3407 } 3408 } 3409 } 3410 3411 3412 /******************************************************************************/ 3413 /* Miscellaneous routines */ 3414 /******************************************************************************/ 3415 3416 3417 static int 3418 AscCompareString(str1, str2, len) 3419 u_char *str1; 3420 u_char *str2; 3421 int len; 3422 { 3423 int i; 3424 int diff; 3425 3426 for (i = 0; i < len; i++) { 3427 diff = (int) (str1[i] - str2[i]); 3428 if (diff != 0) 3429 return (diff); 3430 } 3431 3432 return (0); 3433 } 3434 3435 3436 /******************************************************************************/ 3437 /* Device oriented routines */ 3438 /******************************************************************************/ 3439 3440 3441 static int 3442 DvcEnterCritical(void) 3443 { 3444 int s; 3445 3446 s = splbio(); 3447 return (s); 3448 } 3449 3450 3451 static void 3452 DvcLeaveCritical(s) 3453 int s; 3454 { 3455 3456 splx(s); 3457 } 3458 3459 3460 static void 3461 DvcSleepMilliSecond(n) 3462 u_int32_t n; 3463 { 3464 3465 DELAY(n * 1000); 3466 } 3467 3468 #ifdef UNUSED 3469 static void 3470 DvcDelayMicroSecond(n) 3471 u_int32_t n; 3472 { 3473 3474 DELAY(n); 3475 } 3476 #endif 3477 3478 static void 3479 DvcDelayNanoSecond(n) 3480 u_int32_t n; 3481 { 3482 3483 DELAY((n + 999) / 1000); 3484 } 3485
Indexes created Thu Oct 02 10:09:58 GMT 2025