advlib.h revision 1.3 1 1.3 dante /* $NetBSD: advlib.h,v 1.3 1998/09/26 16:02:57 dante Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.1 dante * Definitions for low level routines and data structures
5 1.1 dante * for the Advanced Systems Inc. SCSI controllers chips.
6 1.1 dante *
7 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
8 1.1 dante * All rights reserved.
9 1.1 dante *
10 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
11 1.1 dante *
12 1.1 dante * Redistribution and use in source and binary forms, with or without
13 1.1 dante * modification, are permitted provided that the following conditions
14 1.1 dante * are met:
15 1.1 dante * 1. Redistributions of source code must retain the above copyright
16 1.1 dante * notice, this list of conditions and the following disclaimer.
17 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 dante * notice, this list of conditions and the following disclaimer in the
19 1.1 dante * documentation and/or other materials provided with the distribution.
20 1.1 dante * 3. All advertising materials mentioning features or use of this software
21 1.1 dante * must display the following acknowledgement:
22 1.3 dante * This product includes software developed by the NetBSD
23 1.3 dante * Foundation, Inc. and its contributors.
24 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
25 1.1 dante * contributors may be used to endorse or promote products derived
26 1.1 dante * from this software without specific prior written permission.
27 1.1 dante *
28 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
39 1.1 dante */
40 1.1 dante /*
41 1.1 dante * Ported from:
42 1.1 dante */
43 1.1 dante /*
44 1.1 dante * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
45 1.1 dante *
46 1.1 dante * Copyright (c) 1995-1996 Advanced System Products, Inc.
47 1.1 dante * All Rights Reserved.
48 1.1 dante *
49 1.1 dante * Redistribution and use in source and binary forms, with or without
50 1.1 dante * modification, are permitted provided that redistributions of source
51 1.1 dante * code retain the above copyright notice and this comment without
52 1.1 dante * modification.
53 1.1 dante */
54 1.1 dante
55 1.3 dante #ifndef _ADVANSYS_NARROW_LIBRARY_H_
56 1.3 dante #define _ADVANSYS_NARROW_LIBRARY_H_
57 1.1 dante
58 1.1 dante #include <dev/ic/adv.h>
59 1.1 dante
60 1.1 dante /******************************************************************************/
61 1.1 dante
62 1.1 dante #define ADV_VERSION "3.1E" /* AdvanSys Driver Version */
63 1.1 dante
64 1.1 dante #define ASC_LIB_VERSION_MAJOR 1
65 1.1 dante #define ASC_LIB_VERSION_MINOR 22
66 1.1 dante #define ASC_LIB_SERIAL_NUMBER 113
67 1.1 dante
68 1.1 dante
69 1.1 dante #define ASC_NOERROR 1
70 1.1 dante #define ASC_BUSY 0
71 1.1 dante #define ASC_ERROR -1
72 1.1 dante
73 1.1 dante
74 1.1 dante #define HI_BYTE(x) (*((__u8 *)(&x)+1))
75 1.1 dante #define LO_BYTE(x) (*((__u8 *)&x))
76 1.1 dante #define HI_WORD(x) (*((__u16 *)(&x)+1))
77 1.1 dante #define LO_WORD(x) (*((__u16 *)&x))
78 1.1 dante #ifndef MAKEWORD
79 1.1 dante #define MAKEWORD(lo, hi) ((__u16) (((__u16) lo) | ((__u16) hi << 8)))
80 1.1 dante #endif
81 1.1 dante #ifndef MAKELONG
82 1.1 dante #define MAKELONG(lo, hi) ((__u32) (((__u32) lo) | ((__u32) hi << 16)))
83 1.1 dante #endif
84 1.1 dante #define SwapWords(dWord) ((__u32) ((dWord >> 16) | (dWord << 16)))
85 1.1 dante #define SwapBytes(word) ((__u16) ((word >> 8) | (word << 8)))
86 1.1 dante #define BigToLittle(dWord) ((__u32) (SwapWords(MAKELONG(SwapBytes(LO_WORD(dWord)), SwapBytes(HI_WORD(dWord))))))
87 1.1 dante #define LittleToBig(dWord) BigToLittle(dWord)
88 1.1 dante
89 1.1 dante
90 1.1 dante #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
91 1.1 dante #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
92 1.1 dante #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
93 1.1 dante #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
94 1.1 dante #define ASC_PCI_REVISION_3150 0x02
95 1.1 dante #define ASC_PCI_REVISION_3050 0x03
96 1.1 dante
97 1.1 dante
98 1.1 dante #define ASC_IS_NARROW_BOARD(sc) (((sc)->sc_flags & ASC_WIDE_BOARD) == 0)
99 1.1 dante #define ASC_IS_WIDE_BOARD(sc) ((sc)->sc_flags & ASC_WIDE_BOARD)
100 1.1 dante
101 1.1 dante
102 1.1 dante #define ASC_MAX_SG_QUEUE 7
103 1.1 dante #define ASC_SG_LIST_PER_Q ASC_MAX_SG_QUEUE
104 1.1 dante #define ASC_MAX_SG_LIST (1 + ((ASC_SG_LIST_PER_Q) * (ASC_MAX_SG_QUEUE))) /* SG_ALL */
105 1.1 dante
106 1.1 dante
107 1.1 dante #define ASC_IS_ISA 0x0001
108 1.1 dante #define ASC_IS_ISAPNP 0x0081
109 1.1 dante #define ASC_IS_EISA 0x0002
110 1.1 dante #define ASC_IS_PCI 0x0004
111 1.1 dante #define ASC_IS_PCI_ULTRA 0x0104
112 1.1 dante #define ASC_IS_PCMCIA 0x0008
113 1.1 dante #define ASC_IS_MCA 0x0020
114 1.1 dante #define ASC_IS_VL 0x0040
115 1.1 dante
116 1.1 dante
117 1.1 dante #define ASC_ISA_PNP_PORT_ADDR 0x279
118 1.1 dante #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
119 1.1 dante
120 1.1 dante #define ASC_IS_WIDESCSI_16 0x0100
121 1.1 dante #define ASC_IS_WIDESCSI_32 0x0200
122 1.1 dante #define ASC_IS_BIG_ENDIAN 0x8000
123 1.1 dante
124 1.1 dante
125 1.1 dante #define ASC_CHIP_MIN_VER_VL 0x01
126 1.1 dante #define ASC_CHIP_MAX_VER_VL 0x07
127 1.1 dante #define ASC_CHIP_MIN_VER_PCI 0x09
128 1.1 dante #define ASC_CHIP_MAX_VER_PCI 0x0F
129 1.1 dante #define ASC_CHIP_VER_PCI_BIT 0x08
130 1.1 dante #define ASC_CHIP_MIN_VER_ISA 0x11
131 1.1 dante #define ASC_CHIP_MIN_VER_ISA_PNP 0x21
132 1.1 dante #define ASC_CHIP_MAX_VER_ISA 0x27
133 1.1 dante #define ASC_CHIP_VER_ISA_BIT 0x30
134 1.1 dante #define ASC_CHIP_VER_ISAPNP_BIT 0x20
135 1.1 dante #define ASC_CHIP_VER_ASYN_BUG 0x21
136 1.1 dante #define ASC_CHIP_VER_PCI 0x08
137 1.1 dante #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
138 1.1 dante #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
139 1.1 dante #define ASC_CHIP_MIN_VER_EISA 0x41
140 1.1 dante #define ASC_CHIP_MAX_VER_EISA 0x47
141 1.1 dante #define ASC_CHIP_VER_EISA_BIT 0x40
142 1.1 dante #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
143 1.1 dante
144 1.1 dante
145 1.1 dante #define ASC_MAX_VL_DMA_ADDR 0x07FFFFFFL
146 1.1 dante #define ASC_MAX_VL_DMA_COUNT 0x07FFFFFFL
147 1.1 dante #define ASC_MAX_PCI_DMA_ADDR 0xFFFFFFFFL
148 1.1 dante #define ASC_MAX_PCI_DMA_COUNT 0xFFFFFFFFL
149 1.1 dante #define ASC_MAX_ISA_DMA_ADDR 0x00FFFFFFL
150 1.1 dante #define ASC_MAX_ISA_DMA_COUNT 0x00FFFFFFL
151 1.1 dante #define ASC_MAX_EISA_DMA_ADDR 0x07FFFFFFL
152 1.1 dante #define ASC_MAX_EISA_DMA_COUNT 0x07FFFFFFL
153 1.1 dante
154 1.1 dante
155 1.1 dante #define ASC_SCSI_ID_BITS 3
156 1.1 dante #define ASC_SCSI_TIX_TYPE u_int8_t
157 1.1 dante
158 1.1 dante #define ASC_ALL_DEVICE_BIT_SET 0xFF
159 1.1 dante
160 1.1 dante #ifdef ASC_WIDESCSI_16
161 1.1 dante #undef ASC_SCSI_ID_BITS
162 1.1 dante #define ASC_SCSI_ID_BITS 4
163 1.1 dante #define ASC_ALL_DEVICE_BIT_SET 0xFFFF
164 1.1 dante #endif
165 1.1 dante
166 1.1 dante #ifdef ASC_WIDESCSI_32
167 1.1 dante #undef ASC_SCSI_ID_BITS
168 1.1 dante #define ASC_SCSI_ID_BITS 5
169 1.1 dante #define ASC_ALL_DEVICE_BIT_SET 0xFFFFFFFFL
170 1.1 dante #endif
171 1.1 dante
172 1.1 dante #if ASC_SCSI_ID_BITS == 3
173 1.1 dante #define ASC_SCSI_BIT_ID_TYPE u_int8_t
174 1.1 dante #define ASC_MAX_TID 7
175 1.1 dante #define ASC_MAX_LUN 7
176 1.1 dante #define ASC_SCSI_WIDTH_BIT_SET 0xFF
177 1.1 dante #elif ASC_SCSI_ID_BITS == 4
178 1.1 dante #define ASC_SCSI_BIT_ID_TYPE u_int16_t
179 1.1 dante #define ASC_MAX_TID 15
180 1.1 dante #define ASC_MAX_LUN 7
181 1.1 dante #define ASC_SCSI_WIDTH_BIT_SET 0xFFFF
182 1.1 dante #elif ASC_SCSI_ID_BITS == 5
183 1.1 dante #define ASC_SCSI_BIT_ID_TYPE u_int32_t
184 1.1 dante #define ASC_MAX_TID 31
185 1.1 dante #define ASC_MAX_LUN 7
186 1.1 dante #define ASC_SCSI_WIDTH_BIT_SET 0xFFFFFFFF
187 1.1 dante #else
188 1.1 dante #error ASC_SCSI_ID_BITS definition is wrong
189 1.1 dante #endif
190 1.1 dante
191 1.1 dante
192 1.1 dante #define ASC_MAX_SENSE_LEN 32
193 1.1 dante #define ASC_MIN_SENSE_LEN 14
194 1.1 dante #define ASC_MAX_CDB_LEN 12
195 1.1 dante
196 1.1 dante #define ASC_SCSI_RESET_HOLD_TIME_US 60
197 1.1 dante
198 1.1 dante
199 1.1 dante #define SCSICMD_TestUnitReady 0x00
200 1.1 dante #define SCSICMD_Rewind 0x01
201 1.1 dante #define SCSICMD_Rezero 0x01
202 1.1 dante #define SCSICMD_RequestSense 0x03
203 1.1 dante #define SCSICMD_Format 0x04
204 1.1 dante #define SCSICMD_FormatUnit 0x04
205 1.1 dante #define SCSICMD_Read6 0x08
206 1.1 dante #define SCSICMD_Write6 0x0A
207 1.1 dante #define SCSICMD_Seek6 0x0B
208 1.1 dante #define SCSICMD_Inquiry 0x12
209 1.1 dante #define SCSICMD_Verify6 0x13
210 1.1 dante #define SCSICMD_ModeSelect6 0x15
211 1.1 dante #define SCSICMD_ModeSense6 0x1A
212 1.1 dante #define SCSICMD_StartStopUnit 0x1B
213 1.1 dante #define SCSICMD_LoadUnloadTape 0x1B
214 1.1 dante #define SCSICMD_ReadCapacity 0x25
215 1.1 dante #define SCSICMD_Read10 0x28
216 1.1 dante #define SCSICMD_Write10 0x2A
217 1.1 dante #define SCSICMD_Seek10 0x2B
218 1.1 dante #define SCSICMD_Erase10 0x2C
219 1.1 dante #define SCSICMD_WriteAndVerify10 0x2E
220 1.1 dante #define SCSICMD_Verify10 0x2F
221 1.1 dante #define SCSICMD_WriteBuffer 0x3B
222 1.1 dante #define SCSICMD_ReadBuffer 0x3C
223 1.1 dante #define SCSICMD_ReadLong 0x3E
224 1.1 dante #define SCSICMD_WriteLong 0x3F
225 1.1 dante #define SCSICMD_ReadTOC 0x43
226 1.1 dante #define SCSICMD_ReadHeader 0x44
227 1.1 dante #define SCSICMD_ModeSelect10 0x55
228 1.1 dante #define SCSICMD_ModeSense10 0x5A
229 1.1 dante
230 1.1 dante
231 1.1 dante #define SCSI_TYPE_DASD 0x00
232 1.1 dante #define SCSI_TYPE_SASD 0x01
233 1.1 dante #define SCSI_TYPE_PRN 0x02
234 1.1 dante #define SCSI_TYPE_PROC 0x03
235 1.1 dante #define SCSI_TYPE_WORM 0x04
236 1.1 dante #define SCSI_TYPE_CDROM 0x05
237 1.1 dante #define SCSI_TYPE_SCANNER 0x06
238 1.1 dante #define SCSI_TYPE_OPTMEM 0x07
239 1.1 dante #define SCSI_TYPE_MED_CHG 0x08
240 1.1 dante #define SCSI_TYPE_COMM 0x09
241 1.1 dante #define SCSI_TYPE_UNKNOWN 0x1F
242 1.1 dante #define SCSI_TYPE_NO_DVC 0xFF
243 1.1 dante
244 1.1 dante
245 1.1 dante #define ASC_SCSIDIR_NOCHK 0x00
246 1.1 dante #define ASC_SCSIDIR_T2H 0x08
247 1.1 dante #define ASC_SCSIDIR_H2T 0x10
248 1.1 dante #define ASC_SCSIDIR_NODATA 0x18
249 1.1 dante
250 1.1 dante
251 1.1 dante #define SCSI_SENKEY_NO_SENSE 0x00
252 1.1 dante #define SCSI_SENKEY_UNDEFINED 0x01
253 1.1 dante #define SCSI_SENKEY_NOT_READY 0x02
254 1.1 dante #define SCSI_SENKEY_MEDIUM_ERR 0x03
255 1.1 dante #define SCSI_SENKEY_HW_ERR 0x04
256 1.1 dante #define SCSI_SENKEY_ILLEGAL 0x05
257 1.1 dante #define SCSI_SENKEY_ATTENTION 0x06
258 1.1 dante #define SCSI_SENKEY_PROTECTED 0x07
259 1.1 dante #define SCSI_SENKEY_BLANK 0x08
260 1.1 dante #define SCSI_SENKEY_V_UNIQUE 0x09
261 1.1 dante #define SCSI_SENKEY_CPY_ABORT 0x0A
262 1.1 dante #define SCSI_SENKEY_ABORT 0x0B
263 1.1 dante #define SCSI_SENKEY_EQUAL 0x0C
264 1.1 dante #define SCSI_SENKEY_VOL_OVERFLOW 0x0D
265 1.1 dante #define SCSI_SENKEY_MISCOMP 0x0E
266 1.1 dante #define SCSI_SENKEY_RESERVED 0x0F
267 1.1 dante #define SCSI_ASC_NOMEDIA 0x3A
268 1.1 dante
269 1.1 dante
270 1.1 dante #define ASC_CCB_HOST(x) ((u_int8_t)((u_int8_t)(x) >> 4))
271 1.1 dante #define ASC_CCB_TID(x) ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F))
272 1.1 dante #define ASC_CCB_LUN(x) ((u_int8_t)((uint)(x) >> 13))
273 1.1 dante
274 1.1 dante
275 1.1 dante #define SS_GOOD 0x00
276 1.1 dante #define SS_CHK_CONDITION 0x02
277 1.1 dante #define SS_CONDITION_MET 0x04
278 1.1 dante #define SS_TARGET_BUSY 0x08
279 1.1 dante #define SS_INTERMID 0x10
280 1.1 dante #define SS_INTERMID_COND_MET 0x14
281 1.1 dante #define SS_RSERV_CONFLICT 0x18
282 1.1 dante #define SS_CMD_TERMINATED 0x22
283 1.1 dante #define SS_QUEUE_FULL 0x28
284 1.1 dante
285 1.1 dante
286 1.1 dante #define MS_CMD_DONE 0x00
287 1.1 dante #define MS_EXTEND 0x01
288 1.1 dante #define MS_SDTR_LEN 0x03
289 1.1 dante #define MS_SDTR_CODE 0x01
290 1.1 dante #define MS_WDTR_LEN 0x02
291 1.1 dante #define MS_WDTR_CODE 0x03
292 1.1 dante #define MS_MDP_LEN 0x05
293 1.1 dante #define MS_MDP_CODE 0x00
294 1.1 dante
295 1.1 dante
296 1.1 dante #define M1_SAVE_DATA_PTR 0x02
297 1.1 dante #define M1_RESTORE_PTRS 0x03
298 1.1 dante #define M1_DISCONNECT 0x04
299 1.1 dante #define M1_INIT_DETECTED_ERR 0x05
300 1.1 dante #define M1_ABORT 0x06
301 1.1 dante #define M1_MSG_REJECT 0x07
302 1.1 dante #define M1_NO_OP 0x08
303 1.1 dante #define M1_MSG_PARITY_ERR 0x09
304 1.1 dante #define M1_LINK_CMD_DONE 0x0A
305 1.1 dante #define M1_LINK_CMD_DONE_WFLAG 0x0B
306 1.1 dante #define M1_BUS_DVC_RESET 0x0C
307 1.1 dante #define M1_ABORT_TAG 0x0D
308 1.1 dante #define M1_CLR_QUEUE 0x0E
309 1.1 dante #define M1_INIT_RECOVERY 0x0F
310 1.1 dante #define M1_RELEASE_RECOVERY 0x10
311 1.1 dante #define M1_KILL_IO_PROC 0x11
312 1.1 dante #define M2_QTAG_MSG_SIMPLE 0x20
313 1.1 dante #define M2_QTAG_MSG_HEAD 0x21
314 1.1 dante #define M2_QTAG_MSG_ORDERED 0x22
315 1.1 dante #define M2_IGNORE_WIDE_RESIDUE 0x23
316 1.1 dante
317 1.1 dante
318 1.1 dante /*
319 1.1 dante * SCSI Iquiry structure
320 1.1 dante */
321 1.1 dante
322 1.1 dante typedef struct
323 1.1 dante {
324 1.1 dante u_int8_t peri_dvc_type:5;
325 1.1 dante u_int8_t peri_qualifier:3;
326 1.1 dante } ASC_SCSI_INQ0;
327 1.1 dante
328 1.1 dante typedef struct
329 1.1 dante {
330 1.1 dante u_int8_t dvc_type_modifier:7;
331 1.1 dante u_int8_t rmb:1;
332 1.1 dante } ASC_SCSI_INQ1;
333 1.1 dante
334 1.1 dante typedef struct
335 1.1 dante {
336 1.1 dante u_int8_t ansi_apr_ver:3;
337 1.1 dante u_int8_t ecma_ver:3;
338 1.1 dante u_int8_t iso_ver:2;
339 1.1 dante } ASC_SCSI_INQ2;
340 1.1 dante
341 1.1 dante typedef struct
342 1.1 dante {
343 1.1 dante u_int8_t rsp_data_fmt:4;
344 1.1 dante u_int8_t res:2;
345 1.1 dante u_int8_t TemIOP:1;
346 1.1 dante u_int8_t aenc:1;
347 1.1 dante } ASC_SCSI_INQ3;
348 1.1 dante
349 1.1 dante typedef struct
350 1.1 dante {
351 1.1 dante u_int8_t StfRe:1;
352 1.1 dante u_int8_t CmdQue:1;
353 1.1 dante u_int8_t Reserved:1;
354 1.1 dante u_int8_t Linked:1;
355 1.1 dante u_int8_t Sync:1;
356 1.1 dante u_int8_t WBus16:1;
357 1.1 dante u_int8_t WBus32:1;
358 1.1 dante u_int8_t RelAdr:1;
359 1.1 dante } ASC_SCSI_INQ7;
360 1.1 dante
361 1.1 dante typedef struct
362 1.1 dante {
363 1.1 dante ASC_SCSI_INQ0 byte0;
364 1.1 dante ASC_SCSI_INQ1 byte1;
365 1.1 dante ASC_SCSI_INQ2 byte2;
366 1.1 dante ASC_SCSI_INQ3 byte3;
367 1.1 dante u_int8_t add_len;
368 1.1 dante u_int8_t res1;
369 1.1 dante u_int8_t res2;
370 1.1 dante ASC_SCSI_INQ7 byte7;
371 1.1 dante u_int8_t vendor_id[8];
372 1.1 dante u_int8_t product_id[16];
373 1.1 dante u_int8_t product_rev_level[4];
374 1.1 dante } ASC_SCSI_INQUIRY;
375 1.1 dante
376 1.1 dante
377 1.1 dante /*
378 1.1 dante * SCSIQ Microcode offsets
379 1.1 dante */
380 1.1 dante #define ASC_SCSIQ_CPY_BEG 4
381 1.1 dante #define ASC_SCSIQ_SGHD_CPY_BEG 2
382 1.1 dante #define ASC_SCSIQ_B_FWD 0
383 1.1 dante #define ASC_SCSIQ_B_BWD 1
384 1.1 dante #define ASC_SCSIQ_B_STATUS 2
385 1.1 dante #define ASC_SCSIQ_B_QNO 3
386 1.1 dante #define ASC_SCSIQ_B_CNTL 4
387 1.1 dante #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
388 1.1 dante #define ASC_SCSIQ_D_DATA_ADDR 8
389 1.1 dante #define ASC_SCSIQ_D_DATA_CNT 12
390 1.1 dante #define ASC_SCSIQ_B_SENSE_LEN 20
391 1.1 dante #define ASC_SCSIQ_DONE_INFO_BEG 22
392 1.1 dante #define ASC_SCSIQ_D_CCBPTR 22
393 1.1 dante #define ASC_SCSIQ_B_TARGET_IX 26
394 1.1 dante #define ASC_SCSIQ_B_CDB_LEN 28
395 1.1 dante #define ASC_SCSIQ_B_TAG_CODE 29
396 1.1 dante #define ASC_SCSIQ_W_VM_ID 30
397 1.1 dante #define ASC_SCSIQ_DONE_STATUS 32
398 1.1 dante #define ASC_SCSIQ_HOST_STATUS 33
399 1.1 dante #define ASC_SCSIQ_SCSI_STATUS 34
400 1.1 dante #define ASC_SCSIQ_CDB_BEG 36
401 1.1 dante #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
402 1.1 dante #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
403 1.1 dante #define ASC_SCSIQ_B_SG_WK_QP 49
404 1.1 dante #define ASC_SCSIQ_B_SG_WK_IX 50
405 1.1 dante #define ASC_SCSIQ_W_REQ_COUNT 52
406 1.1 dante #define ASC_SCSIQ_B_LIST_CNT 6
407 1.1 dante #define ASC_SCSIQ_B_CUR_LIST_CNT 7
408 1.1 dante
409 1.1 dante
410 1.1 dante #define ASC_DEF_SCSI1_QNG 4
411 1.1 dante #define ASC_MAX_SCSI1_QNG 4
412 1.1 dante #define ASC_DEF_SCSI2_QNG 16
413 1.1 dante #define ASC_MAX_SCSI2_QNG 32
414 1.1 dante
415 1.1 dante #define ASC_TAG_CODE_MASK 0x23
416 1.1 dante
417 1.1 dante #define ASC_STOP_REQ_RISC_STOP 0x01
418 1.1 dante #define ASC_STOP_ACK_RISC_STOP 0x03
419 1.1 dante #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
420 1.1 dante #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
421 1.1 dante #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
422 1.1 dante
423 1.1 dante #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
424 1.1 dante #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
425 1.1 dante #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
426 1.1 dante #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
427 1.1 dante #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
428 1.1 dante #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
429 1.1 dante #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
430 1.1 dante
431 1.1 dante
432 1.1 dante /*
433 1.1 dante * Structures used to dialog with the RISC engine
434 1.1 dante */
435 1.1 dante
436 1.1 dante typedef struct asc_scisq_1
437 1.1 dante {
438 1.1 dante u_int8_t status; /* see below status values */
439 1.1 dante u_int8_t q_no; /* Queue ID of the first queue for this transaction */
440 1.1 dante u_int8_t cntl; /* see below cntl values */
441 1.1 dante u_int8_t sg_queue_cnt; /* number of SG entries */
442 1.1 dante u_int8_t target_id;
443 1.1 dante u_int8_t target_lun;
444 1.1 dante u_int32_t data_addr; /* physical address of first segment to transef */
445 1.1 dante u_int32_t data_cnt; /* byte count of first segment to transfer */
446 1.1 dante u_int32_t sense_addr; /* physical address of the sense buffer */
447 1.1 dante u_int8_t sense_len; /* lenght of sense buffer */
448 1.1 dante u_int8_t extra_bytes;
449 1.1 dante } ASC_SCSIQ_1;
450 1.1 dante
451 1.1 dante /* status values */
452 1.1 dante #define ASC_QS_FREE 0x00
453 1.1 dante #define ASC_QS_READY 0x01
454 1.1 dante #define ASC_QS_DISC1 0x02
455 1.1 dante #define ASC_QS_DISC2 0x04
456 1.1 dante #define ASC_QS_BUSY 0x08
457 1.1 dante #define ASC_QS_ABORTED 0x40
458 1.1 dante #define ASC_QS_DONE 0x80
459 1.1 dante
460 1.1 dante /* cntl values */
461 1.1 dante #define ASC_QC_NO_CALLBACK 0x01
462 1.1 dante #define ASC_QC_SG_SWAP_QUEUE 0x02
463 1.1 dante #define ASC_QC_SG_HEAD 0x04
464 1.1 dante #define ASC_QC_DATA_IN 0x08
465 1.1 dante #define ASC_QC_DATA_OUT 0x10
466 1.1 dante #define ASC_QC_URGENT 0x20
467 1.1 dante #define ASC_QC_MSG_OUT 0x40
468 1.1 dante #define ASC_QC_REQ_SENSE 0x80
469 1.1 dante
470 1.1 dante
471 1.1 dante typedef struct asc_scisq_2
472 1.1 dante {
473 1.1 dante u_int32_t ccb_ptr; /* pointer to our CCB */
474 1.1 dante u_int8_t target_ix; /* combined TID and LUN */
475 1.1 dante u_int8_t flag;
476 1.1 dante u_int8_t cdb_len; /* bytes of Command Descriptor Block */
477 1.1 dante u_int8_t tag_code; /* type of this transaction. see below */
478 1.1 dante u_int16_t vm_id;
479 1.1 dante } ASC_SCSIQ_2;
480 1.1 dante
481 1.1 dante /* tag_code values */
482 1.1 dante #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
483 1.1 dante #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
484 1.1 dante #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
485 1.1 dante #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
486 1.1 dante
487 1.1 dante
488 1.1 dante typedef struct asc_scsiq_3
489 1.1 dante {
490 1.1 dante u_int8_t done_stat; /* see below done_stat values */
491 1.1 dante u_int8_t host_stat; /* see below host_stat values */
492 1.1 dante u_int8_t scsi_stat;
493 1.1 dante u_int8_t scsi_msg;
494 1.1 dante } ASC_SCSIQ_3;
495 1.1 dante
496 1.1 dante /* done_stat values */
497 1.1 dante #define ASC_QD_IN_PROGRESS 0x00
498 1.1 dante #define ASC_QD_NO_ERROR 0x01
499 1.1 dante #define ASC_QD_ABORTED_BY_HOST 0x02
500 1.1 dante #define ASC_QD_WITH_ERROR 0x04
501 1.1 dante #define ASC_QD_INVALID_REQUEST 0x80
502 1.1 dante #define ASC_QD_INVALID_HOST_NUM 0x81
503 1.1 dante #define ASC_QD_INVALID_DEVICE 0x82
504 1.1 dante #define ASC_QD_ERR_INTERNAL 0xFF
505 1.1 dante
506 1.1 dante /* host_stat values */
507 1.1 dante #define ASC_QHSTA_NO_ERROR 0x00
508 1.1 dante #define ASC_QHSTA_M_SEL_TIMEOUT 0x11
509 1.1 dante #define ASC_QHSTA_M_DATA_OVER_RUN 0x12
510 1.1 dante #define ASC_QHSTA_M_DATA_UNDER_RUN 0x12
511 1.1 dante #define ASC_QHSTA_M_UNEXPECTED_BUS_FREE 0x13
512 1.1 dante #define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
513 1.1 dante #define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
514 1.1 dante #define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
515 1.1 dante #define ASC_QHSTA_D_HOST_ABORT_FAILED 0x23
516 1.1 dante #define ASC_QHSTA_D_EXE_SCSI_Q_FAILED 0x24
517 1.1 dante #define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
518 1.1 dante #define ASC_QHSTA_D_ASPI_NO_BUF_POOL 0x26
519 1.1 dante #define ASC_QHSTA_M_WTM_TIMEOUT 0x41
520 1.1 dante #define ASC_QHSTA_M_BAD_CMPL_STATUS_IN 0x42
521 1.1 dante #define ASC_QHSTA_M_NO_AUTO_REQ_SENSE 0x43
522 1.1 dante #define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
523 1.1 dante #define ASC_QHSTA_M_TARGET_STATUS_BUSY 0x45
524 1.1 dante #define ASC_QHSTA_M_BAD_TAG_CODE 0x46
525 1.1 dante #define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
526 1.1 dante #define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
527 1.1 dante #define ASC_QHSTA_D_LRAM_CMP_ERROR 0x81
528 1.1 dante #define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
529 1.1 dante
530 1.1 dante
531 1.1 dante typedef struct asc_scsiq_4
532 1.1 dante {
533 1.1 dante u_int8_t cdb[ASC_MAX_CDB_LEN];
534 1.1 dante u_int8_t y_first_sg_list_qp;
535 1.1 dante u_int8_t y_working_sg_qp;
536 1.1 dante u_int8_t y_working_sg_ix;
537 1.1 dante u_int8_t y_res;
538 1.1 dante u_int16_t x_req_count;
539 1.1 dante u_int16_t x_reconnect_rtn;
540 1.1 dante u_int32_t x_saved_data_addr;
541 1.1 dante u_int32_t x_saved_data_cnt;
542 1.1 dante } ASC_SCSIQ_4;
543 1.1 dante
544 1.1 dante typedef struct asc_q_done_info
545 1.1 dante {
546 1.1 dante ASC_SCSIQ_2 d2;
547 1.1 dante ASC_SCSIQ_3 d3;
548 1.1 dante u_int8_t q_status;
549 1.1 dante u_int8_t q_no;
550 1.1 dante u_int8_t cntl;
551 1.1 dante u_int8_t sense_len;
552 1.1 dante u_int8_t extra_bytes;
553 1.1 dante u_int8_t res;
554 1.1 dante u_int32_t remain_bytes;
555 1.1 dante } ASC_QDONE_INFO;
556 1.1 dante
557 1.1 dante typedef struct asc_sg_list
558 1.1 dante {
559 1.1 dante u_int32_t addr;
560 1.1 dante u_int32_t bytes;
561 1.1 dante } ASC_SG_LIST;
562 1.1 dante
563 1.1 dante typedef struct asc_sg_head
564 1.1 dante {
565 1.1 dante u_int16_t entry_cnt; /* number of SG entries */
566 1.1 dante u_int16_t queue_cnt; /* number of queues required to store SG entries */
567 1.1 dante u_int16_t entry_to_copy; /* number of SG entries to copy to the board */
568 1.1 dante u_int16_t res;
569 1.1 dante ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
570 1.1 dante } ASC_SG_HEAD;
571 1.1 dante
572 1.1 dante #define ASC_MIN_SG_LIST 2
573 1.1 dante
574 1.1 dante typedef struct asc_min_sg_head
575 1.1 dante {
576 1.1 dante u_int16_t entry_cnt;
577 1.1 dante u_int16_t queue_cnt;
578 1.1 dante u_int16_t entry_to_copy;
579 1.1 dante u_int16_t res;
580 1.1 dante ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
581 1.1 dante } ASC_MIN_SG_HEAD;
582 1.1 dante
583 1.1 dante #define ASC_QCX_SORT 0x0001
584 1.1 dante #define ASC_QCX_COALEASE 0x0002
585 1.1 dante
586 1.1 dante typedef struct asc_scsi_q
587 1.1 dante {
588 1.1 dante ASC_SCSIQ_1 q1;
589 1.1 dante ASC_SCSIQ_2 q2;
590 1.1 dante u_int8_t *cdbptr; /* pointer to CDB to execute */
591 1.1 dante ASC_SG_HEAD *sg_head; /* pointer to SG list */
592 1.1 dante } ASC_SCSI_Q;
593 1.1 dante
594 1.1 dante typedef struct asc_scsi_req_q
595 1.1 dante {
596 1.1 dante ASC_SCSIQ_1 q1;
597 1.1 dante ASC_SCSIQ_2 q2;
598 1.1 dante u_int8_t *cdbptr;
599 1.1 dante ASC_SG_HEAD *sg_head;
600 1.1 dante u_int8_t *sense_ptr;
601 1.1 dante ASC_SCSIQ_3 q3;
602 1.1 dante u_int8_t cdb[ASC_MAX_CDB_LEN];
603 1.1 dante u_int8_t sense[ASC_MIN_SENSE_LEN];
604 1.1 dante } ASC_SCSI_REQ_Q;
605 1.1 dante
606 1.1 dante typedef struct asc_scsi_bios_req_q
607 1.1 dante {
608 1.1 dante ASC_SCSIQ_1 q1;
609 1.1 dante ASC_SCSIQ_2 q2;
610 1.1 dante u_int8_t *cdbptr;
611 1.1 dante ASC_SG_HEAD *sg_head;
612 1.1 dante u_int8_t *sense_ptr;
613 1.1 dante ASC_SCSIQ_3 q3;
614 1.1 dante u_int8_t cdb[ASC_MAX_CDB_LEN];
615 1.1 dante u_int8_t sense[ASC_MIN_SENSE_LEN];
616 1.1 dante } ASC_SCSI_BIOS_REQ_Q;
617 1.1 dante
618 1.1 dante typedef struct asc_risc_q
619 1.1 dante {
620 1.1 dante u_int8_t fwd;
621 1.1 dante u_int8_t bwd;
622 1.1 dante ASC_SCSIQ_1 i1;
623 1.1 dante ASC_SCSIQ_2 i2;
624 1.1 dante ASC_SCSIQ_3 i3;
625 1.1 dante ASC_SCSIQ_4 i4;
626 1.1 dante } ASC_RISC_Q;
627 1.1 dante
628 1.1 dante typedef struct asc_sg_list_q
629 1.1 dante {
630 1.1 dante u_int8_t seq_no;
631 1.1 dante u_int8_t q_no;
632 1.1 dante u_int8_t cntl; /* see below cntl values */
633 1.1 dante u_int8_t sg_head_qp;
634 1.1 dante u_int8_t sg_list_cnt;
635 1.1 dante u_int8_t sg_cur_list_cnt;
636 1.1 dante } ASC_SG_LIST_Q;
637 1.1 dante
638 1.1 dante /* cntl values */
639 1.1 dante #define ASC_QCSG_SG_XFER_LIST 0x02
640 1.1 dante #define ASC_QCSG_SG_XFER_MORE 0x04
641 1.1 dante #define ASC_QCSG_SG_XFER_END 0x08
642 1.1 dante
643 1.1 dante #define ASC_SGQ_B_SG_CNTL 4
644 1.1 dante #define ASC_SGQ_B_SG_HEAD_QP 5
645 1.1 dante #define ASC_SGQ_B_SG_LIST_CNT 6
646 1.1 dante #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
647 1.1 dante #define ASC_SGQ_LIST_BEG 8
648 1.1 dante
649 1.1 dante
650 1.1 dante typedef struct asc_risc_sg_list_q
651 1.1 dante {
652 1.1 dante u_int8_t fwd;
653 1.1 dante u_int8_t bwd;
654 1.1 dante ASC_SG_LIST_Q sg;
655 1.1 dante ASC_SG_LIST sg_list[7];
656 1.1 dante } ASC_RISC_SG_LIST_Q;
657 1.1 dante
658 1.1 dante
659 1.1 dante #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
660 1.1 dante #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
661 1.1 dante
662 1.1 dante #define ASCQ_ERR_NO_ERROR 0x00
663 1.1 dante #define ASCQ_ERR_IO_NOT_FOUND 0x01
664 1.1 dante #define ASCQ_ERR_LOCAL_MEM 0x02
665 1.1 dante #define ASCQ_ERR_CHKSUM 0x03
666 1.1 dante #define ASCQ_ERR_START_CHIP 0x04
667 1.1 dante #define ASCQ_ERR_INT_TARGET_ID 0x05
668 1.1 dante #define ASCQ_ERR_INT_LOCAL_MEM 0x06
669 1.1 dante #define ASCQ_ERR_HALT_RISC 0x07
670 1.1 dante #define ASCQ_ERR_GET_ASPI_ENTRY 0x08
671 1.1 dante #define ASCQ_ERR_CLOSE_ASPI 0x09
672 1.1 dante #define ASCQ_ERR_HOST_INQUIRY 0x0A
673 1.1 dante #define ASCQ_ERR_SAVED_CCB_BAD 0x0B
674 1.1 dante #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
675 1.1 dante #define ASCQ_ERR_Q_STATUS 0x0D
676 1.1 dante #define ASCQ_ERR_WR_SCSIQ 0x0E
677 1.1 dante #define ASCQ_ERR_PC_ADDR 0x0F
678 1.1 dante #define ASCQ_ERR_SYN_OFFSET 0x10
679 1.1 dante #define ASCQ_ERR_SYN_XFER_TIME 0x11
680 1.1 dante #define ASCQ_ERR_LOCK_DMA 0x12
681 1.1 dante #define ASCQ_ERR_UNLOCK_DMA 0x13
682 1.1 dante #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
683 1.1 dante #define ASCQ_ERR_MICRO_CODE_HALT 0x15
684 1.1 dante #define ASCQ_ERR_SET_LRAM_ADDR 0x16
685 1.1 dante #define ASCQ_ERR_CUR_QNG 0x17
686 1.1 dante #define ASCQ_ERR_SG_Q_LINKS 0x18
687 1.1 dante #define ASCQ_ERR_SCSIQ_PTR 0x19
688 1.1 dante #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
689 1.1 dante #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
690 1.1 dante #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
691 1.1 dante #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
692 1.1 dante #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
693 1.1 dante #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
694 1.1 dante #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
695 1.1 dante #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
696 1.1 dante #define ASCQ_ERR_SEND_SCSI_Q 0x22
697 1.1 dante #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
698 1.1 dante #define ASCQ_ERR_RESET_SDTR 0x24
699 1.1 dante
700 1.1 dante #define ASC_WARN_NO_ERROR 0x0000
701 1.1 dante #define ASC_WARN_IO_PORT_ROTATE 0x0001
702 1.1 dante #define ASC_WARN_EEPROM_CHKSUM 0x0002
703 1.1 dante #define ASC_WARN_IRQ_MODIFIED 0x0004
704 1.1 dante #define ASC_WARN_AUTO_CONFIG 0x0008
705 1.1 dante #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
706 1.1 dante #define ASC_WARN_EEPROM_RECOVER 0x0020
707 1.1 dante #define ASC_WARN_CFG_MSW_RECOVER 0x0040
708 1.1 dante #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
709 1.1 dante
710 1.1 dante #define ASC_IERR_WRITE_EEPROM 0x0001
711 1.1 dante #define ASC_IERR_MCODE_CHKSUM 0x0002
712 1.1 dante #define ASC_IERR_SET_PC_ADDR 0x0004
713 1.1 dante #define ASC_IERR_START_STOP_CHIP 0x0008
714 1.1 dante #define ASC_IERR_IRQ_NO 0x0010
715 1.1 dante #define ASC_IERR_SET_IRQ_NO 0x0020
716 1.1 dante #define ASC_IERR_CHIP_VERSION 0x0040
717 1.1 dante #define ASC_IERR_SET_SCSI_ID 0x0080
718 1.1 dante #define ASC_IERR_GET_PHY_ADDR 0x0100
719 1.1 dante #define ASC_IERR_BAD_SIGNATURE 0x0200
720 1.1 dante #define ASC_IERR_NO_BUS_TYPE 0x0400
721 1.1 dante #define ASC_IERR_SCAM 0x0800
722 1.1 dante #define ASC_IERR_SET_SDTR 0x1000
723 1.1 dante #define ASC_IERR_RW_LRAM 0x8000
724 1.1 dante
725 1.1 dante #define ASC_DEF_IRQ_NO 10
726 1.1 dante #define ASC_MAX_IRQ_NO 15
727 1.1 dante #define ASC_MIN_IRQ_NO 10
728 1.1 dante #define ASC_MIN_REMAIN_Q 0x02
729 1.1 dante #define ASC_DEF_MAX_TOTAL_QNG 0xF0
730 1.1 dante #define ASC_MIN_TAG_Q_PER_DVC 0x04
731 1.1 dante #define ASC_DEF_TAG_Q_PER_DVC 0x04
732 1.1 dante #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
733 1.1 dante #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
734 1.1 dante #define ASC_MAX_TOTAL_QNG 240
735 1.1 dante #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
736 1.1 dante #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
737 1.1 dante #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
738 1.1 dante #define ASC_MAX_INRAM_TAG_QNG 16
739 1.1 dante #define ASC_IOADR_TABLE_MAX_IX 11
740 1.1 dante #define ASC_IOADR_GAP 0x10
741 1.1 dante #define ASC_SEARCH_IOP_GAP 0x10
742 1.1 dante #define ASC_MIN_IOP_ADDR 0x0100
743 1.1 dante #define ASC_MAX_IOP_ADDR 0x03F0
744 1.1 dante
745 1.1 dante #define ASC_IOADR_1 0x0110
746 1.1 dante #define ASC_IOADR_2 0x0130
747 1.1 dante #define ASC_IOADR_3 0x0150
748 1.1 dante #define ASC_IOADR_4 0x0190
749 1.1 dante #define ASC_IOADR_5 0x0210
750 1.1 dante #define ASC_IOADR_6 0x0230
751 1.1 dante #define ASC_IOADR_7 0x0250
752 1.1 dante #define ASC_IOADR_8 0x0330
753 1.1 dante
754 1.1 dante #define ASC_IOADR_DEF ASC_IOADR_8
755 1.1 dante #define ASC_LIB_SCSIQ_WK_SP 256
756 1.1 dante #define ASC_MAX_SYN_XFER_NO 16
757 1.1 dante #define ASC_SYN_MAX_OFFSET 0x0F
758 1.1 dante #define ASC_DEF_SDTR_OFFSET 0x0F
759 1.1 dante #define ASC_DEF_SDTR_INDEX 0x00
760 1.1 dante #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
761 1.1 dante
762 1.1 dante
763 1.1 dante /*
764 1.1 dante * This structure is used to handle internal messages
765 1.1 dante * during interrupt handling routine
766 1.1 dante */
767 1.1 dante typedef struct ext_msg
768 1.1 dante {
769 1.1 dante u_int8_t msg_type;
770 1.1 dante u_int8_t msg_len;
771 1.1 dante u_int8_t msg_req;
772 1.1 dante
773 1.1 dante union
774 1.1 dante {
775 1.1 dante struct
776 1.1 dante {
777 1.1 dante u_int8_t sdtr_xfer_period;
778 1.1 dante u_int8_t sdtr_req_ack_offset;
779 1.1 dante } sdtr;
780 1.1 dante
781 1.1 dante struct
782 1.1 dante {
783 1.1 dante u_int8_t wdtr_width;
784 1.1 dante } wdtr;
785 1.1 dante
786 1.1 dante struct
787 1.1 dante {
788 1.1 dante u_int8_t mdp_b3;
789 1.1 dante u_int8_t mdp_b2;
790 1.1 dante u_int8_t mdp_b1;
791 1.1 dante u_int8_t mdp_b0;
792 1.1 dante } mdp;
793 1.1 dante } u_ext_msg;
794 1.1 dante
795 1.1 dante u_int8_t res;
796 1.1 dante } EXT_MSG;
797 1.1 dante
798 1.1 dante #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
799 1.1 dante #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
800 1.1 dante #define wdtr_width u_ext_msg.wdtr.wdtr_width
801 1.1 dante #define mdp_b3 u_ext_msg.mdp_b3
802 1.1 dante #define mdp_b2 u_ext_msg.mdp_b2
803 1.1 dante #define mdp_b1 u_ext_msg.mdp_b1
804 1.1 dante #define mdp_b0 u_ext_msg.mdp_b0
805 1.1 dante
806 1.1 dante
807 1.1 dante #define ASC_DEF_DVC_CNTL 0xFFFF
808 1.1 dante #define ASC_DEF_CHIP_SCSI_ID 7
809 1.1 dante #define ASC_DEF_ISA_DMA_SPEED 4
810 1.1 dante
811 1.1 dante #define ASC_PCI_DEVICE_ID_REV_A 0x1100
812 1.1 dante #define ASC_PCI_DEVICE_ID_REV_B 0x1200
813 1.1 dante
814 1.1 dante #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
815 1.1 dante #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
816 1.1 dante
817 1.1 dante #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
818 1.1 dante
819 1.1 dante #define ASC_MIN_TAGGED_CMD 7
820 1.1 dante
821 1.1 dante #define ASC_MAX_SCSI_RESET_WAIT 30
822 1.1 dante
823 1.1 dante
824 1.1 dante typedef struct asc_softc
825 1.1 dante {
826 1.1 dante struct device sc_dev;
827 1.1 dante
828 1.1 dante bus_space_tag_t sc_iot;
829 1.1 dante bus_space_handle_t sc_ioh;
830 1.1 dante bus_dma_tag_t sc_dmat;
831 1.1 dante bus_dmamap_t sc_dmamap_control; /* maps the control structures */
832 1.1 dante void *sc_ih;
833 1.1 dante
834 1.1 dante struct adv_control *sc_control; /* control structures */
835 1.1 dante TAILQ_HEAD(, adv_ccb) sc_free_ccb, sc_waiting_ccb;
836 1.1 dante struct scsipi_link sc_link; /* prototype for devs */
837 1.1 dante
838 1.1 dante LIST_HEAD(, scsipi_xfer) sc_queue;
839 1.1 dante struct scsipi_xfer *sc_queuelast;
840 1.1 dante
841 1.1 dante u_int8_t *overrun_buf;
842 1.1 dante
843 1.1 dante u_int16_t sc_flags; /* see below sc_flags values */
844 1.1 dante
845 1.1 dante u_int16_t dvc_cntl;
846 1.1 dante u_int16_t bug_fix_cntl;
847 1.1 dante u_int16_t bus_type;
848 1.1 dante
849 1.1 dante ulong isr_callback;
850 1.1 dante
851 1.1 dante ASC_SCSI_BIT_ID_TYPE init_sdtr;
852 1.1 dante ASC_SCSI_BIT_ID_TYPE sdtr_done;
853 1.1 dante ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
854 1.1 dante ASC_SCSI_BIT_ID_TYPE unit_not_ready;
855 1.1 dante ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
856 1.1 dante ASC_SCSI_BIT_ID_TYPE start_motor;
857 1.1 dante
858 1.1 dante ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
859 1.1 dante ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
860 1.1 dante ASC_SCSI_BIT_ID_TYPE disc_enable;
861 1.1 dante ASC_SCSI_BIT_ID_TYPE sdtr_enable;
862 1.1 dante u_int8_t chip_scsi_id;
863 1.1 dante u_int8_t isa_dma_speed;
864 1.1 dante u_int8_t isa_dma_channel;
865 1.1 dante u_int8_t chip_version;
866 1.1 dante u_int16_t pci_device_id;
867 1.1 dante u_int16_t lib_serial_no;
868 1.1 dante u_int16_t lib_version;
869 1.1 dante u_int16_t mcode_date;
870 1.1 dante u_int16_t mcode_version;
871 1.1 dante u_int8_t max_tag_qng[ASC_MAX_TID + 1];
872 1.1 dante u_int8_t sdtr_period_offset[ASC_MAX_TID + 1];
873 1.1 dante u_int8_t adapter_info[6];
874 1.1 dante
875 1.1 dante u_int8_t scsi_reset_wait;
876 1.1 dante u_int8_t max_total_qng;
877 1.1 dante u_int8_t cur_total_qng;
878 1.1 dante u_int8_t irq_no;
879 1.1 dante u_int8_t last_q_shortage;
880 1.1 dante
881 1.1 dante u_int8_t cur_dvc_qng[ASC_MAX_TID + 1];
882 1.1 dante u_int8_t max_dvc_qng[ASC_MAX_TID + 1];
883 1.1 dante u_int8_t sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
884 1.1 dante u_int8_t sdtr_period_tbl_size; /* see below */
885 1.1 dante u_int8_t sdtr_data[ASC_MAX_TID+1];
886 1.1 dante
887 1.1 dante u_int16_t reqcnt[ASC_MAX_TID+1]; /* Starvation request count */
888 1.1 dante
889 1.1 dante u_int32_t max_dma_count;
890 1.1 dante ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
891 1.1 dante ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
892 1.1 dante u_int8_t max_sdtr_index;
893 1.1 dante u_int8_t host_init_sdtr_index;
894 1.1 dante } ASC_SOFTC;
895 1.1 dante
896 1.1 dante /* sc_flags values */
897 1.1 dante #define ASC_HOST_IN_RESET 0x01
898 1.1 dante #define ASC_HOST_IN_ABORT 0x02
899 1.1 dante #define ASC_WIDE_BOARD 0x04
900 1.1 dante #define ASC_SELECT_QUEUE_DEPTHS 0x08
901 1.1 dante
902 1.1 dante /* sdtr_period_tbl_size values */
903 1.1 dante #define SYN_XFER_NS_0 25
904 1.1 dante #define SYN_XFER_NS_1 30
905 1.1 dante #define SYN_XFER_NS_2 35
906 1.1 dante #define SYN_XFER_NS_3 40
907 1.1 dante #define SYN_XFER_NS_4 50
908 1.1 dante #define SYN_XFER_NS_5 60
909 1.1 dante #define SYN_XFER_NS_6 70
910 1.1 dante #define SYN_XFER_NS_7 85
911 1.1 dante
912 1.1 dante #define SYN_ULTRA_XFER_NS_0 12
913 1.1 dante #define SYN_ULTRA_XFER_NS_1 19
914 1.1 dante #define SYN_ULTRA_XFER_NS_2 25
915 1.1 dante #define SYN_ULTRA_XFER_NS_3 32
916 1.1 dante #define SYN_ULTRA_XFER_NS_4 38
917 1.1 dante #define SYN_ULTRA_XFER_NS_5 44
918 1.1 dante #define SYN_ULTRA_XFER_NS_6 50
919 1.1 dante #define SYN_ULTRA_XFER_NS_7 57
920 1.1 dante #define SYN_ULTRA_XFER_NS_8 63
921 1.1 dante #define SYN_ULTRA_XFER_NS_9 69
922 1.1 dante #define SYN_ULTRA_XFER_NS_10 75
923 1.1 dante #define SYN_ULTRA_XFER_NS_11 82
924 1.1 dante #define SYN_ULTRA_XFER_NS_12 88
925 1.1 dante #define SYN_ULTRA_XFER_NS_13 94
926 1.1 dante #define SYN_ULTRA_XFER_NS_14 100
927 1.1 dante #define SYN_ULTRA_XFER_NS_15 107
928 1.1 dante
929 1.1 dante
930 1.1 dante /* second level interrupt callback type definition */
931 1.1 dante typedef int (* ASC_ISR_CALLBACK) (ASC_SOFTC *, ASC_QDONE_INFO *);
932 1.1 dante
933 1.1 dante
934 1.1 dante #define ASC_MCNTL_NO_SEL_TIMEOUT 0x0001
935 1.1 dante #define ASC_MCNTL_NULL_TARGET 0x0002
936 1.1 dante
937 1.1 dante #define ASC_CNTL_INITIATOR 0x0001
938 1.1 dante #define ASC_CNTL_BIOS_GT_1GB 0x0002
939 1.1 dante #define ASC_CNTL_BIOS_GT_2_DISK 0x0004
940 1.1 dante #define ASC_CNTL_BIOS_REMOVABLE 0x0008
941 1.1 dante #define ASC_CNTL_NO_SCAM 0x0010
942 1.1 dante #define ASC_CNTL_INT_MULTI_Q 0x0080
943 1.1 dante #define ASC_CNTL_NO_LUN_SUPPORT 0x0040
944 1.1 dante #define ASC_CNTL_NO_VERIFY_COPY 0x0100
945 1.1 dante #define ASC_CNTL_RESET_SCSI 0x0200
946 1.1 dante #define ASC_CNTL_INIT_INQUIRY 0x0400
947 1.1 dante #define ASC_CNTL_INIT_VERBOSE 0x0800
948 1.1 dante #define ASC_CNTL_SCSI_PARITY 0x1000
949 1.1 dante #define ASC_CNTL_BURST_MODE 0x2000
950 1.1 dante #define ASC_CNTL_SDTR_ENABLE_ULTRA 0x4000
951 1.1 dante
952 1.1 dante #define ASC_EEP_DVC_CFG_BEG_VL 2
953 1.1 dante #define ASC_EEP_MAX_DVC_ADDR_VL 15
954 1.1 dante #define ASC_EEP_DVC_CFG_BEG 32
955 1.1 dante #define ASC_EEP_MAX_DVC_ADDR 45
956 1.1 dante #define ASC_EEP_DEFINED_WORDS 10
957 1.1 dante #define ASC_EEP_MAX_ADDR 63
958 1.1 dante #define ASC_EEP_RES_WORDS 0
959 1.1 dante #define ASC_EEP_MAX_RETRY 20
960 1.1 dante #define ASC_MAX_INIT_BUSY_RETRY 8
961 1.1 dante #define ASC_EEP_ISA_PNP_WSIZE 16
962 1.1 dante
963 1.1 dante
964 1.1 dante /*
965 1.1 dante * This structure is used to read/write EEProm configuration
966 1.1 dante */
967 1.1 dante typedef struct asceep_config
968 1.1 dante {
969 1.1 dante u_int16_t cfg_lsw;
970 1.1 dante u_int16_t cfg_msw;
971 1.1 dante u_int8_t init_sdtr;
972 1.1 dante u_int8_t disc_enable;
973 1.1 dante u_int8_t use_cmd_qng;
974 1.1 dante u_int8_t start_motor;
975 1.1 dante u_int8_t max_total_qng;
976 1.1 dante u_int8_t max_tag_qng;
977 1.1 dante u_int8_t bios_scan;
978 1.1 dante u_int8_t power_up_wait;
979 1.1 dante u_int8_t no_scam;
980 1.1 dante u_int8_t chip_scsi_id:4;
981 1.1 dante u_int8_t isa_dma_speed:4;
982 1.1 dante u_int8_t dos_int13_table[ASC_MAX_TID + 1];
983 1.1 dante u_int8_t adapter_info[6];
984 1.1 dante u_int16_t cntl;
985 1.1 dante u_int16_t chksum;
986 1.1 dante } ASCEEP_CONFIG;
987 1.1 dante
988 1.1 dante #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
989 1.1 dante #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
990 1.1 dante #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
991 1.1 dante
992 1.1 dante #define ASC_EEP_CMD_READ 0x80
993 1.1 dante #define ASC_EEP_CMD_WRITE 0x40
994 1.1 dante #define ASC_EEP_CMD_WRITE_ABLE 0x30
995 1.1 dante #define ASC_EEP_CMD_WRITE_DISABLE 0x00
996 1.1 dante
997 1.1 dante #define ASC_OVERRUN_BSIZE 0x00000048UL
998 1.1 dante
999 1.1 dante #define ASC_CTRL_BREAK_ONCE 0x0001
1000 1.1 dante #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1001 1.1 dante
1002 1.1 dante #define ASCV_MSGOUT_BEG 0x0000
1003 1.1 dante #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1004 1.1 dante #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1005 1.1 dante #define ASCV_BREAK_SAVED_CODE 0x0006
1006 1.1 dante #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1007 1.1 dante #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1008 1.1 dante #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1009 1.1 dante #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1010 1.1 dante #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1011 1.1 dante #define ASCV_MAX_DVC_QNG_BEG 0x0020
1012 1.1 dante #define ASCV_BREAK_ADDR 0x0028
1013 1.1 dante #define ASCV_BREAK_NOTIFY_COUNT 0x002A
1014 1.1 dante #define ASCV_BREAK_CONTROL 0x002C
1015 1.1 dante #define ASCV_BREAK_HIT_COUNT 0x002E
1016 1.1 dante
1017 1.1 dante #define ASCV_ASCDVC_ERR_CODE_W 0x0030
1018 1.1 dante #define ASCV_MCODE_CHKSUM_W 0x0032
1019 1.1 dante #define ASCV_MCODE_SIZE_W 0x0034
1020 1.1 dante #define ASCV_STOP_CODE_B 0x0036
1021 1.1 dante #define ASCV_DVC_ERR_CODE_B 0x0037
1022 1.1 dante #define ASCV_OVERRUN_PADDR_D 0x0038
1023 1.1 dante #define ASCV_OVERRUN_BSIZE_D 0x003C
1024 1.1 dante #define ASCV_HALTCODE_W 0x0040
1025 1.1 dante #define ASCV_CHKSUM_W 0x0042
1026 1.1 dante #define ASCV_MC_DATE_W 0x0044
1027 1.1 dante #define ASCV_MC_VER_W 0x0046
1028 1.1 dante #define ASCV_NEXTRDY_B 0x0048
1029 1.1 dante #define ASCV_DONENEXT_B 0x0049
1030 1.1 dante #define ASCV_USE_TAGGED_QNG_B 0x004A
1031 1.1 dante #define ASCV_SCSIBUSY_B 0x004B
1032 1.1 dante #define ASCV_Q_DONE_IN_PROGRESS_B 0x004C
1033 1.1 dante #define ASCV_CURCDB_B 0x004D
1034 1.1 dante #define ASCV_RCLUN_B 0x004E
1035 1.1 dante #define ASCV_BUSY_QHEAD_B 0x004F
1036 1.1 dante #define ASCV_DISC1_QHEAD_B 0x0050
1037 1.1 dante #define ASCV_DISC_ENABLE_B 0x0052
1038 1.1 dante #define ASCV_CAN_TAGGED_QNG_B 0x0053
1039 1.1 dante #define ASCV_HOSTSCSI_ID_B 0x0055
1040 1.1 dante #define ASCV_MCODE_CNTL_B 0x0056
1041 1.1 dante #define ASCV_NULL_TARGET_B 0x0057
1042 1.1 dante #define ASCV_FREE_Q_HEAD_W 0x0058
1043 1.1 dante #define ASCV_DONE_Q_TAIL_W 0x005A
1044 1.1 dante #define ASCV_FREE_Q_HEAD_B (ASCV_FREE_Q_HEAD_W+1)
1045 1.1 dante #define ASCV_DONE_Q_TAIL_B (ASCV_DONE_Q_TAIL_W+1)
1046 1.1 dante #define ASCV_HOST_FLAG_B 0x005D
1047 1.1 dante #define ASCV_TOTAL_READY_Q_B 0x0064
1048 1.1 dante #define ASCV_VER_SERIAL_B 0x0065
1049 1.1 dante #define ASCV_HALTCODE_SAVED_W 0x0066
1050 1.1 dante #define ASCV_WTM_FLAG_B 0x0068
1051 1.1 dante #define ASCV_RISC_FLAG_B 0x006A
1052 1.1 dante #define ASCV_REQ_SG_LIST_QP 0x006B
1053 1.1 dante
1054 1.1 dante #define ASC_HOST_FLAG_IN_ISR 0x01
1055 1.1 dante #define ASC_HOST_FLAG_ACK_INT 0x02
1056 1.1 dante #define ASC_RISC_FLAG_GEN_INT 0x01
1057 1.1 dante #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1058 1.1 dante
1059 1.1 dante #define ASC_IOP_CTRL 0x0F
1060 1.1 dante #define ASC_IOP_STATUS 0x0E
1061 1.1 dante #define ASC_IOP_INT_ACK ASC_IOP_STATUS
1062 1.1 dante #define ASC_IOP_REG_IFC 0x0D
1063 1.1 dante #define ASC_IOP_SYN_OFFSET 0x0B
1064 1.1 dante #define ASC_IOP_EXTRA_CONTROL 0x0D
1065 1.1 dante #define ASC_IOP_REG_PC 0x0C
1066 1.1 dante #define ASC_IOP_RAM_ADDR 0x0A
1067 1.1 dante #define ASC_IOP_RAM_DATA 0x08
1068 1.1 dante #define ASC_IOP_EEP_DATA 0x06
1069 1.1 dante #define ASC_IOP_EEP_CMD 0x07
1070 1.1 dante #define ASC_IOP_VERSION 0x03
1071 1.1 dante #define ASC_IOP_CONFIG_HIGH 0x04
1072 1.1 dante #define ASC_IOP_CONFIG_LOW 0x02
1073 1.1 dante #define ASC_IOP_SIG_BYTE 0x01
1074 1.1 dante #define ASC_IOP_SIG_WORD 0x00
1075 1.1 dante #define ASC_IOP_REG_DC1 0x0E
1076 1.1 dante #define ASC_IOP_REG_DC0 0x0C
1077 1.1 dante #define ASC_IOP_REG_SB 0x0B
1078 1.1 dante #define ASC_IOP_REG_DA1 0x0A
1079 1.1 dante #define ASC_IOP_REG_DA0 0x08
1080 1.1 dante #define ASC_IOP_REG_SC 0x09
1081 1.1 dante #define ASC_IOP_DMA_SPEED 0x07
1082 1.1 dante #define ASC_IOP_REG_FLAG 0x07
1083 1.1 dante #define ASC_IOP_FIFO_H 0x06
1084 1.1 dante #define ASC_IOP_FIFO_L 0x04
1085 1.1 dante #define ASC_IOP_REG_ID 0x05
1086 1.1 dante #define ASC_IOP_REG_QP 0x03
1087 1.1 dante #define ASC_IOP_REG_IH 0x02
1088 1.1 dante #define ASC_IOP_REG_IX 0x01
1089 1.1 dante #define ASC_IOP_REG_AX 0x00
1090 1.1 dante
1091 1.1 dante #define ASC_IFC_REG_LOCK 0x00
1092 1.1 dante #define ASC_IFC_REG_UNLOCK 0x09
1093 1.1 dante #define ASC_IFC_WR_EN_FILTER 0x10
1094 1.1 dante #define ASC_IFC_RD_NO_EEPROM 0x10
1095 1.1 dante #define ASC_IFC_SLEW_RATE 0x20
1096 1.1 dante #define ASC_IFC_ACT_NEG 0x40
1097 1.1 dante #define ASC_IFC_INP_FILTER 0x80
1098 1.1 dante #define ASC_IFC_INIT_DEFAULT (ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK)
1099 1.1 dante
1100 1.1 dante #define SC_SEL 0x80
1101 1.1 dante #define SC_BSY 0x40
1102 1.1 dante #define SC_ACK 0x20
1103 1.1 dante #define SC_REQ 0x10
1104 1.1 dante #define SC_ATN 0x08
1105 1.1 dante #define SC_IO 0x04
1106 1.1 dante #define SC_CD 0x02
1107 1.1 dante #define SC_MSG 0x01
1108 1.1 dante
1109 1.1 dante #define SEC_SCSI_CTL 0x80
1110 1.1 dante #define SEC_ACTIVE_NEGATE 0x40
1111 1.1 dante #define SEC_SLEW_RATE 0x20
1112 1.1 dante #define SEC_ENABLE_FILTER 0x10
1113 1.1 dante
1114 1.1 dante #define ASC_HALT_EXTMSG_IN 0x8000
1115 1.1 dante #define ASC_HALT_CHK_CONDITION 0x8100
1116 1.1 dante #define ASC_HALT_SS_QUEUE_FULL 0x8200
1117 1.1 dante #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300
1118 1.1 dante #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400
1119 1.1 dante #define ASC_HALT_SDTR_REJECTED 0x4000
1120 1.1 dante
1121 1.1 dante #define ASC_MAX_QNO 0xF8
1122 1.1 dante
1123 1.1 dante #define ASC_DATA_SEC_BEG 0x0080
1124 1.1 dante #define ASC_DATA_SEC_END 0x0080
1125 1.1 dante #define ASC_CODE_SEC_BEG 0x0080
1126 1.1 dante #define ASC_CODE_SEC_END 0x0080
1127 1.1 dante #define ASC_QADR_BEG (0x4000)
1128 1.1 dante #define ASC_QADR_USED (ASC_MAX_QNO * 64)
1129 1.1 dante #define ASC_QADR_END 0x7FFF
1130 1.1 dante #define ASC_QLAST_ADR 0x7FC0
1131 1.1 dante #define ASC_QBLK_SIZE 0x40
1132 1.1 dante #define ASC_BIOS_DATA_QBEG 0xF8
1133 1.1 dante #define ASC_MIN_ACTIVE_QNO 0x01
1134 1.1 dante #define ASC_QLINK_END 0xFF
1135 1.1 dante #define ASC_EEPROM_WORDS 0x10
1136 1.1 dante #define ASC_MAX_MGS_LEN 0x10
1137 1.1 dante
1138 1.1 dante #define ASC_BIOS_ADDR_DEF 0xDC00
1139 1.1 dante #define ASC_BIOS_SIZE 0x3800
1140 1.1 dante #define ASC_BIOS_RAM_OFF 0x3800
1141 1.1 dante #define ASC_BIOS_RAM_SIZE 0x800
1142 1.1 dante #define ASC_BIOS_MIN_ADDR 0xC000
1143 1.1 dante #define ASC_BIOS_MAX_ADDR 0xEC00
1144 1.1 dante #define ASC_BIOS_BANK_SIZE 0x0400
1145 1.1 dante
1146 1.1 dante #define ASC_MCODE_START_ADDR 0x0080
1147 1.1 dante
1148 1.1 dante #define ASC_CFG0_HOST_INT_ON 0x0020
1149 1.1 dante #define ASC_CFG0_BIOS_ON 0x0040
1150 1.1 dante #define ASC_CFG0_VERA_BURST_ON 0x0080
1151 1.1 dante #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1152 1.1 dante #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1153 1.1 dante #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1154 1.1 dante #define ASC_CFG_MSW_CLR_MASK 0x3080
1155 1.1 dante
1156 1.1 dante #define ASC_CSW_TEST1 0x8000
1157 1.1 dante #define ASC_CSW_AUTO_CONFIG 0x4000
1158 1.1 dante #define ASC_CSW_RESERVED1 0x2000
1159 1.1 dante #define ASC_CSW_IRQ_WRITTEN 0x1000
1160 1.1 dante #define ASC_CSW_33MHZ_SELECTED 0x0800
1161 1.1 dante #define ASC_CSW_TEST2 0x0400
1162 1.1 dante #define ASC_CSW_TEST3 0x0200
1163 1.1 dante #define ASC_CSW_RESERVED2 0x0100
1164 1.1 dante #define ASC_CSW_DMA_DONE 0x0080
1165 1.1 dante #define ASC_CSW_FIFO_RDY 0x0040
1166 1.1 dante #define ASC_CSW_EEP_READ_DONE 0x0020
1167 1.1 dante #define ASC_CSW_HALTED 0x0010
1168 1.1 dante #define ASC_CSW_SCSI_RESET_ACTIVE 0x0008
1169 1.1 dante #define ASC_CSW_PARITY_ERR 0x0004
1170 1.1 dante #define ASC_CSW_SCSI_RESET_LATCH 0x0002
1171 1.1 dante #define ASC_CSW_INT_PENDING 0x0001
1172 1.1 dante
1173 1.1 dante #define ASC_CIW_CLR_SCSI_RESET_INT 0x1000
1174 1.1 dante #define ASC_CIW_INT_ACK 0x0100
1175 1.1 dante #define ASC_CIW_TEST1 0x0200
1176 1.1 dante #define ASC_CIW_TEST2 0x0400
1177 1.1 dante #define ASC_CIW_SEL_33MHZ 0x0800
1178 1.1 dante #define ASC_CIW_IRQ_ACT 0x1000
1179 1.1 dante
1180 1.1 dante #define ASC_CC_CHIP_RESET 0x80
1181 1.1 dante #define ASC_CC_SCSI_RESET 0x40
1182 1.1 dante #define ASC_CC_HALT 0x20
1183 1.1 dante #define ASC_CC_SINGLE_STEP 0x10
1184 1.1 dante #define ASC_CC_DMA_ABLE 0x08
1185 1.1 dante #define ASC_CC_TEST 0x04
1186 1.1 dante #define ASC_CC_BANK_ONE 0x02
1187 1.1 dante #define ASC_CC_DIAG 0x01
1188 1.1 dante
1189 1.1 dante #define ASC_1000_ID0W 0x04C1
1190 1.1 dante #define ASC_1000_ID0W_FIX 0x00C1
1191 1.1 dante #define ASC_1000_ID1B 0x25
1192 1.1 dante
1193 1.1 dante #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1194 1.1 dante #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1195 1.1 dante #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1196 1.1 dante #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1197 1.1 dante #define ASC_EISA_REV_IOP_MASK (0x0C83)
1198 1.1 dante #define ASC_EISA_PID_IOP_MASK (0x0C80)
1199 1.1 dante #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1200 1.1 dante
1201 1.1 dante #define ASC_GET_EISA_SLOT(iop) ((iop) & 0xF000)
1202 1.1 dante
1203 1.1 dante #define ASC_EISA_ID_740 0x01745004UL
1204 1.1 dante #define ASC_EISA_ID_750 0x01755004UL
1205 1.1 dante
1206 1.1 dante #define ASC_INS_HALTINT 0x6281
1207 1.1 dante #define ASC_INS_HALT 0x6280
1208 1.1 dante #define ASC_INS_SINT 0x6200
1209 1.1 dante #define ASC_INS_RFLAG_WTM 0x7380
1210 1.1 dante
1211 1.1 dante
1212 1.1 dante /******************************************************************************/
1213 1.1 dante /* Macro */
1214 1.1 dante /******************************************************************************/
1215 1.1 dante
1216 1.1 dante /*
1217 1.1 dante * These Macros are used to deal with board CPU Registers and LRAM
1218 1.1 dante */
1219 1.1 dante
1220 1.1 dante #define ASC_GET_QDONE_IN_PROGRESS(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B)
1221 1.1 dante #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val)
1222 1.1 dante #define ASC_GET_VAR_FREE_QHEAD(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W)
1223 1.1 dante #define ASC_GET_VAR_DONE_QTAIL(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W)
1224 1.1 dante #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val)
1225 1.1 dante #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val)
1226 1.1 dante #define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B)
1227 1.1 dante #define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B)
1228 1.1 dante #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val)
1229 1.1 dante #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val)
1230 1.1 dante #define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ;
1231 1.1 dante #define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ;
1232 1.1 dante #define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ;
1233 1.1 dante #define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ;
1234 1.1 dante #define ASC_SYN_INDEX_TO_PERIOD(sc, index) (u_int8_t)((sc)->sdtr_period_tbl[ (index) ])
1235 1.1 dante #define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE)
1236 1.1 dante #define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD)
1237 1.1 dante #define ASC_GET_CHIP_VER_NO(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_VERSION)
1238 1.1 dante #define ASC_GET_CHIP_CFG_LSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW)
1239 1.1 dante #define ASC_GET_CHIP_CFG_MSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH)
1240 1.1 dante #define ASC_SET_CHIP_CFG_LSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data)
1241 1.1 dante #define ASC_SET_CHIP_CFG_MSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data)
1242 1.1 dante #define ASC_GET_CHIP_EEP_CMD(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD)
1243 1.1 dante #define ASC_SET_CHIP_EEP_CMD(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data)
1244 1.1 dante #define ASC_GET_CHIP_EEP_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA)
1245 1.1 dante #define ASC_SET_CHIP_EEP_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data)
1246 1.1 dante #define ASC_GET_CHIP_LRAM_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR)
1247 1.1 dante #define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr)
1248 1.1 dante #define ASC_GET_CHIP_LRAM_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
1249 1.1 dante #define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
1250 1.1 dante #if BYTE_ORDER == BIG_ENDIAN
1251 1.1 dante #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) swap_bytes(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA))
1252 1.1 dante #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, swap_bytes(data))
1253 1.1 dante #else
1254 1.1 dante #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
1255 1.1 dante #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
1256 1.1 dante #endif
1257 1.1 dante #define ASC_GET_CHIP_IFC(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC)
1258 1.1 dante #define ASC_SET_CHIP_IFC(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data)
1259 1.1 dante #define ASC_GET_CHIP_STATUS(iot, ioh) (u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS)
1260 1.1 dante #define ASC_SET_CHIP_STATUS(iot, ioh, cs_val) bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val)
1261 1.1 dante #define ASC_GET_CHIP_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_CTRL)
1262 1.1 dante #define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val) bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val)
1263 1.1 dante #define ASC_GET_CHIP_SYN(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET)
1264 1.1 dante #define ASC_SET_CHIP_SYN(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data)
1265 1.1 dante #define ASC_SET_PC_ADDR(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data)
1266 1.1 dante #define ASC_GET_PC_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC)
1267 1.1 dante #define ASC_IS_INT_PENDING(iot, ioh) (ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH))
1268 1.1 dante #define ASC_GET_CHIP_SCSI_ID(iot, ioh) ((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID)
1269 1.1 dante #define ASC_GET_EXTRA_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL)
1270 1.1 dante #define ASC_SET_EXTRA_CONTROL(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data)
1271 1.1 dante #define ASC_READ_CHIP_AX(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX)
1272 1.1 dante #define ASC_WRITE_CHIP_AX(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data)
1273 1.1 dante #define ASC_READ_CHIP_IX(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX)
1274 1.1 dante #define ASC_WRITE_CHIP_IX(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data)
1275 1.1 dante #define ASC_READ_CHIP_IH(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH)
1276 1.1 dante #define ASC_WRITE_CHIP_IH(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data)
1277 1.1 dante #define ASC_READ_CHIP_QP(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP)
1278 1.1 dante #define ASC_WRITE_CHIP_QP(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data)
1279 1.1 dante #define ASC_READ_CHIP_FIFO_L(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L)
1280 1.1 dante #define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data)
1281 1.1 dante #define ASC_READ_CHIP_FIFO_H(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H)
1282 1.1 dante #define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data)
1283 1.1 dante #define ASC_READ_CHIP_DMA_SPEED(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED)
1284 1.1 dante #define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data)
1285 1.1 dante #define ASC_READ_CHIP_DA0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0)
1286 1.1 dante #define ASC_WRITE_CHIP_DA0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data)
1287 1.1 dante #define ASC_READ_CHIP_DA1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1)
1288 1.1 dante #define ASC_WRITE_CHIP_DA1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data)
1289 1.1 dante #define ASC_READ_CHIP_DC0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0)
1290 1.1 dante #define ASC_WRITE_CHIP_DC0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data)
1291 1.1 dante #define ASC_READ_CHIP_DC1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1)
1292 1.1 dante #define ASC_WRITE_CHIP_DC1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data)
1293 1.1 dante #define ASC_READ_CHIP_DVC_ID(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID)
1294 1.1 dante #define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data)
1295 1.1 dante
1296 1.1 dante
1297 1.1 dante /******************************************************************************/
1298 1.1 dante /* Exported functions */
1299 1.1 dante /******************************************************************************/
1300 1.1 dante
1301 1.1 dante
1302 1.1 dante void AscInitASC_SOFTC __P((ASC_SOFTC *));
1303 1.1 dante u_int16_t AscInitFromEEP __P((ASC_SOFTC *));
1304 1.1 dante u_int16_t AscInitFromASC_SOFTC __P((ASC_SOFTC *));
1305 1.1 dante int AscInitDriver __P((ASC_SOFTC *));
1306 1.1 dante void AscReInitLram __P((ASC_SOFTC *));
1307 1.1 dante int AscFindSignature __P((bus_space_tag_t, bus_space_handle_t));
1308 1.1 dante int AscISR __P((ASC_SOFTC *));
1309 1.1 dante int AscExeScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *));
1310 1.1 dante void AscInquiryHandling __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *));
1311 1.1 dante int AscAbortCCB __P((ASC_SOFTC *, u_int32_t));
1312 1.1 dante int AscResetBus __P((ASC_SOFTC *));
1313 1.1 dante int AscResetDevice __P((ASC_SOFTC *, u_char));
1314 1.1 dante
1315 1.1 dante
1316 1.1 dante /******************************************************************************/
1317 1.3 dante #endif /* _ADVANSYS_NARROW_LIBRARY_H_ */
1318