advlib.h revision 1.1
1 /* 2 * Definitions for low level routines and data structures 3 * for the Advanced Systems Inc. SCSI controllers chips. 4 * 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Ported from: 40 */ 41 /* 42 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 43 * 44 * Copyright (c) 1995-1996 Advanced System Products, Inc. 45 * All Rights Reserved. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that redistributions of source 49 * code retain the above copyright notice and this comment without 50 * modification. 51 */ 52 53 #ifndef _ADVANSYS_LIBRARY_H_ 54 #define _ADVANSYS_LIBRARY_H_ 55 56 #include <dev/ic/adv.h> 57 58 /******************************************************************************/ 59 60 #define ADV_VERSION "3.1E" /* AdvanSys Driver Version */ 61 62 #define ASC_LIB_VERSION_MAJOR 1 63 #define ASC_LIB_VERSION_MINOR 22 64 #define ASC_LIB_SERIAL_NUMBER 113 65 66 67 #define ASC_NOERROR 1 68 #define ASC_BUSY 0 69 #define ASC_ERROR -1 70 71 72 #define HI_BYTE(x) (*((__u8 *)(&x)+1)) 73 #define LO_BYTE(x) (*((__u8 *)&x)) 74 #define HI_WORD(x) (*((__u16 *)(&x)+1)) 75 #define LO_WORD(x) (*((__u16 *)&x)) 76 #ifndef MAKEWORD 77 #define MAKEWORD(lo, hi) ((__u16) (((__u16) lo) | ((__u16) hi << 8))) 78 #endif 79 #ifndef MAKELONG 80 #define MAKELONG(lo, hi) ((__u32) (((__u32) lo) | ((__u32) hi << 16))) 81 #endif 82 #define SwapWords(dWord) ((__u32) ((dWord >> 16) | (dWord << 16))) 83 #define SwapBytes(word) ((__u16) ((word >> 8) | (word << 8))) 84 #define BigToLittle(dWord) ((__u32) (SwapWords(MAKELONG(SwapBytes(LO_WORD(dWord)), SwapBytes(HI_WORD(dWord)))))) 85 #define LittleToBig(dWord) BigToLittle(dWord) 86 87 88 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF) 89 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F) 90 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7) 91 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF)) 92 #define ASC_PCI_REVISION_3150 0x02 93 #define ASC_PCI_REVISION_3050 0x03 94 95 96 #define ASC_IS_NARROW_BOARD(sc) (((sc)->sc_flags & ASC_WIDE_BOARD) == 0) 97 #define ASC_IS_WIDE_BOARD(sc) ((sc)->sc_flags & ASC_WIDE_BOARD) 98 99 100 #define ASC_MAX_SG_QUEUE 7 101 #define ASC_SG_LIST_PER_Q ASC_MAX_SG_QUEUE 102 #define ASC_MAX_SG_LIST (1 + ((ASC_SG_LIST_PER_Q) * (ASC_MAX_SG_QUEUE))) /* SG_ALL */ 103 104 105 #define ASC_IS_ISA 0x0001 106 #define ASC_IS_ISAPNP 0x0081 107 #define ASC_IS_EISA 0x0002 108 #define ASC_IS_PCI 0x0004 109 #define ASC_IS_PCI_ULTRA 0x0104 110 #define ASC_IS_PCMCIA 0x0008 111 #define ASC_IS_MCA 0x0020 112 #define ASC_IS_VL 0x0040 113 114 115 #define ASC_ISA_PNP_PORT_ADDR 0x279 116 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800) 117 118 #define ASC_IS_WIDESCSI_16 0x0100 119 #define ASC_IS_WIDESCSI_32 0x0200 120 #define ASC_IS_BIG_ENDIAN 0x8000 121 122 123 #define ASC_CHIP_MIN_VER_VL 0x01 124 #define ASC_CHIP_MAX_VER_VL 0x07 125 #define ASC_CHIP_MIN_VER_PCI 0x09 126 #define ASC_CHIP_MAX_VER_PCI 0x0F 127 #define ASC_CHIP_VER_PCI_BIT 0x08 128 #define ASC_CHIP_MIN_VER_ISA 0x11 129 #define ASC_CHIP_MIN_VER_ISA_PNP 0x21 130 #define ASC_CHIP_MAX_VER_ISA 0x27 131 #define ASC_CHIP_VER_ISA_BIT 0x30 132 #define ASC_CHIP_VER_ISAPNP_BIT 0x20 133 #define ASC_CHIP_VER_ASYN_BUG 0x21 134 #define ASC_CHIP_VER_PCI 0x08 135 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 136 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 137 #define ASC_CHIP_MIN_VER_EISA 0x41 138 #define ASC_CHIP_MAX_VER_EISA 0x47 139 #define ASC_CHIP_VER_EISA_BIT 0x40 140 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 141 142 143 #define ASC_MAX_VL_DMA_ADDR 0x07FFFFFFL 144 #define ASC_MAX_VL_DMA_COUNT 0x07FFFFFFL 145 #define ASC_MAX_PCI_DMA_ADDR 0xFFFFFFFFL 146 #define ASC_MAX_PCI_DMA_COUNT 0xFFFFFFFFL 147 #define ASC_MAX_ISA_DMA_ADDR 0x00FFFFFFL 148 #define ASC_MAX_ISA_DMA_COUNT 0x00FFFFFFL 149 #define ASC_MAX_EISA_DMA_ADDR 0x07FFFFFFL 150 #define ASC_MAX_EISA_DMA_COUNT 0x07FFFFFFL 151 152 153 #define ASC_SCSI_ID_BITS 3 154 #define ASC_SCSI_TIX_TYPE u_int8_t 155 156 #define ASC_ALL_DEVICE_BIT_SET 0xFF 157 158 #ifdef ASC_WIDESCSI_16 159 #undef ASC_SCSI_ID_BITS 160 #define ASC_SCSI_ID_BITS 4 161 #define ASC_ALL_DEVICE_BIT_SET 0xFFFF 162 #endif 163 164 #ifdef ASC_WIDESCSI_32 165 #undef ASC_SCSI_ID_BITS 166 #define ASC_SCSI_ID_BITS 5 167 #define ASC_ALL_DEVICE_BIT_SET 0xFFFFFFFFL 168 #endif 169 170 #if ASC_SCSI_ID_BITS == 3 171 #define ASC_SCSI_BIT_ID_TYPE u_int8_t 172 #define ASC_MAX_TID 7 173 #define ASC_MAX_LUN 7 174 #define ASC_SCSI_WIDTH_BIT_SET 0xFF 175 #elif ASC_SCSI_ID_BITS == 4 176 #define ASC_SCSI_BIT_ID_TYPE u_int16_t 177 #define ASC_MAX_TID 15 178 #define ASC_MAX_LUN 7 179 #define ASC_SCSI_WIDTH_BIT_SET 0xFFFF 180 #elif ASC_SCSI_ID_BITS == 5 181 #define ASC_SCSI_BIT_ID_TYPE u_int32_t 182 #define ASC_MAX_TID 31 183 #define ASC_MAX_LUN 7 184 #define ASC_SCSI_WIDTH_BIT_SET 0xFFFFFFFF 185 #else 186 #error ASC_SCSI_ID_BITS definition is wrong 187 #endif 188 189 190 #define ASC_MAX_SENSE_LEN 32 191 #define ASC_MIN_SENSE_LEN 14 192 #define ASC_MAX_CDB_LEN 12 193 194 #define ASC_SCSI_RESET_HOLD_TIME_US 60 195 196 197 #define SCSICMD_TestUnitReady 0x00 198 #define SCSICMD_Rewind 0x01 199 #define SCSICMD_Rezero 0x01 200 #define SCSICMD_RequestSense 0x03 201 #define SCSICMD_Format 0x04 202 #define SCSICMD_FormatUnit 0x04 203 #define SCSICMD_Read6 0x08 204 #define SCSICMD_Write6 0x0A 205 #define SCSICMD_Seek6 0x0B 206 #define SCSICMD_Inquiry 0x12 207 #define SCSICMD_Verify6 0x13 208 #define SCSICMD_ModeSelect6 0x15 209 #define SCSICMD_ModeSense6 0x1A 210 #define SCSICMD_StartStopUnit 0x1B 211 #define SCSICMD_LoadUnloadTape 0x1B 212 #define SCSICMD_ReadCapacity 0x25 213 #define SCSICMD_Read10 0x28 214 #define SCSICMD_Write10 0x2A 215 #define SCSICMD_Seek10 0x2B 216 #define SCSICMD_Erase10 0x2C 217 #define SCSICMD_WriteAndVerify10 0x2E 218 #define SCSICMD_Verify10 0x2F 219 #define SCSICMD_WriteBuffer 0x3B 220 #define SCSICMD_ReadBuffer 0x3C 221 #define SCSICMD_ReadLong 0x3E 222 #define SCSICMD_WriteLong 0x3F 223 #define SCSICMD_ReadTOC 0x43 224 #define SCSICMD_ReadHeader 0x44 225 #define SCSICMD_ModeSelect10 0x55 226 #define SCSICMD_ModeSense10 0x5A 227 228 229 #define SCSI_TYPE_DASD 0x00 230 #define SCSI_TYPE_SASD 0x01 231 #define SCSI_TYPE_PRN 0x02 232 #define SCSI_TYPE_PROC 0x03 233 #define SCSI_TYPE_WORM 0x04 234 #define SCSI_TYPE_CDROM 0x05 235 #define SCSI_TYPE_SCANNER 0x06 236 #define SCSI_TYPE_OPTMEM 0x07 237 #define SCSI_TYPE_MED_CHG 0x08 238 #define SCSI_TYPE_COMM 0x09 239 #define SCSI_TYPE_UNKNOWN 0x1F 240 #define SCSI_TYPE_NO_DVC 0xFF 241 242 243 #define ASC_SCSIDIR_NOCHK 0x00 244 #define ASC_SCSIDIR_T2H 0x08 245 #define ASC_SCSIDIR_H2T 0x10 246 #define ASC_SCSIDIR_NODATA 0x18 247 248 249 #define SCSI_SENKEY_NO_SENSE 0x00 250 #define SCSI_SENKEY_UNDEFINED 0x01 251 #define SCSI_SENKEY_NOT_READY 0x02 252 #define SCSI_SENKEY_MEDIUM_ERR 0x03 253 #define SCSI_SENKEY_HW_ERR 0x04 254 #define SCSI_SENKEY_ILLEGAL 0x05 255 #define SCSI_SENKEY_ATTENTION 0x06 256 #define SCSI_SENKEY_PROTECTED 0x07 257 #define SCSI_SENKEY_BLANK 0x08 258 #define SCSI_SENKEY_V_UNIQUE 0x09 259 #define SCSI_SENKEY_CPY_ABORT 0x0A 260 #define SCSI_SENKEY_ABORT 0x0B 261 #define SCSI_SENKEY_EQUAL 0x0C 262 #define SCSI_SENKEY_VOL_OVERFLOW 0x0D 263 #define SCSI_SENKEY_MISCOMP 0x0E 264 #define SCSI_SENKEY_RESERVED 0x0F 265 #define SCSI_ASC_NOMEDIA 0x3A 266 267 268 #define ASC_CCB_HOST(x) ((u_int8_t)((u_int8_t)(x) >> 4)) 269 #define ASC_CCB_TID(x) ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F)) 270 #define ASC_CCB_LUN(x) ((u_int8_t)((uint)(x) >> 13)) 271 272 273 #define SS_GOOD 0x00 274 #define SS_CHK_CONDITION 0x02 275 #define SS_CONDITION_MET 0x04 276 #define SS_TARGET_BUSY 0x08 277 #define SS_INTERMID 0x10 278 #define SS_INTERMID_COND_MET 0x14 279 #define SS_RSERV_CONFLICT 0x18 280 #define SS_CMD_TERMINATED 0x22 281 #define SS_QUEUE_FULL 0x28 282 283 284 #define MS_CMD_DONE 0x00 285 #define MS_EXTEND 0x01 286 #define MS_SDTR_LEN 0x03 287 #define MS_SDTR_CODE 0x01 288 #define MS_WDTR_LEN 0x02 289 #define MS_WDTR_CODE 0x03 290 #define MS_MDP_LEN 0x05 291 #define MS_MDP_CODE 0x00 292 293 294 #define M1_SAVE_DATA_PTR 0x02 295 #define M1_RESTORE_PTRS 0x03 296 #define M1_DISCONNECT 0x04 297 #define M1_INIT_DETECTED_ERR 0x05 298 #define M1_ABORT 0x06 299 #define M1_MSG_REJECT 0x07 300 #define M1_NO_OP 0x08 301 #define M1_MSG_PARITY_ERR 0x09 302 #define M1_LINK_CMD_DONE 0x0A 303 #define M1_LINK_CMD_DONE_WFLAG 0x0B 304 #define M1_BUS_DVC_RESET 0x0C 305 #define M1_ABORT_TAG 0x0D 306 #define M1_CLR_QUEUE 0x0E 307 #define M1_INIT_RECOVERY 0x0F 308 #define M1_RELEASE_RECOVERY 0x10 309 #define M1_KILL_IO_PROC 0x11 310 #define M2_QTAG_MSG_SIMPLE 0x20 311 #define M2_QTAG_MSG_HEAD 0x21 312 #define M2_QTAG_MSG_ORDERED 0x22 313 #define M2_IGNORE_WIDE_RESIDUE 0x23 314 315 316 /* 317 * SCSI Iquiry structure 318 */ 319 320 typedef struct 321 { 322 u_int8_t peri_dvc_type:5; 323 u_int8_t peri_qualifier:3; 324 } ASC_SCSI_INQ0; 325 326 typedef struct 327 { 328 u_int8_t dvc_type_modifier:7; 329 u_int8_t rmb:1; 330 } ASC_SCSI_INQ1; 331 332 typedef struct 333 { 334 u_int8_t ansi_apr_ver:3; 335 u_int8_t ecma_ver:3; 336 u_int8_t iso_ver:2; 337 } ASC_SCSI_INQ2; 338 339 typedef struct 340 { 341 u_int8_t rsp_data_fmt:4; 342 u_int8_t res:2; 343 u_int8_t TemIOP:1; 344 u_int8_t aenc:1; 345 } ASC_SCSI_INQ3; 346 347 typedef struct 348 { 349 u_int8_t StfRe:1; 350 u_int8_t CmdQue:1; 351 u_int8_t Reserved:1; 352 u_int8_t Linked:1; 353 u_int8_t Sync:1; 354 u_int8_t WBus16:1; 355 u_int8_t WBus32:1; 356 u_int8_t RelAdr:1; 357 } ASC_SCSI_INQ7; 358 359 typedef struct 360 { 361 ASC_SCSI_INQ0 byte0; 362 ASC_SCSI_INQ1 byte1; 363 ASC_SCSI_INQ2 byte2; 364 ASC_SCSI_INQ3 byte3; 365 u_int8_t add_len; 366 u_int8_t res1; 367 u_int8_t res2; 368 ASC_SCSI_INQ7 byte7; 369 u_int8_t vendor_id[8]; 370 u_int8_t product_id[16]; 371 u_int8_t product_rev_level[4]; 372 } ASC_SCSI_INQUIRY; 373 374 375 /* 376 * SCSIQ Microcode offsets 377 */ 378 #define ASC_SCSIQ_CPY_BEG 4 379 #define ASC_SCSIQ_SGHD_CPY_BEG 2 380 #define ASC_SCSIQ_B_FWD 0 381 #define ASC_SCSIQ_B_BWD 1 382 #define ASC_SCSIQ_B_STATUS 2 383 #define ASC_SCSIQ_B_QNO 3 384 #define ASC_SCSIQ_B_CNTL 4 385 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 386 #define ASC_SCSIQ_D_DATA_ADDR 8 387 #define ASC_SCSIQ_D_DATA_CNT 12 388 #define ASC_SCSIQ_B_SENSE_LEN 20 389 #define ASC_SCSIQ_DONE_INFO_BEG 22 390 #define ASC_SCSIQ_D_CCBPTR 22 391 #define ASC_SCSIQ_B_TARGET_IX 26 392 #define ASC_SCSIQ_B_CDB_LEN 28 393 #define ASC_SCSIQ_B_TAG_CODE 29 394 #define ASC_SCSIQ_W_VM_ID 30 395 #define ASC_SCSIQ_DONE_STATUS 32 396 #define ASC_SCSIQ_HOST_STATUS 33 397 #define ASC_SCSIQ_SCSI_STATUS 34 398 #define ASC_SCSIQ_CDB_BEG 36 399 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 400 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 401 #define ASC_SCSIQ_B_SG_WK_QP 49 402 #define ASC_SCSIQ_B_SG_WK_IX 50 403 #define ASC_SCSIQ_W_REQ_COUNT 52 404 #define ASC_SCSIQ_B_LIST_CNT 6 405 #define ASC_SCSIQ_B_CUR_LIST_CNT 7 406 407 408 #define ASC_DEF_SCSI1_QNG 4 409 #define ASC_MAX_SCSI1_QNG 4 410 #define ASC_DEF_SCSI2_QNG 16 411 #define ASC_MAX_SCSI2_QNG 32 412 413 #define ASC_TAG_CODE_MASK 0x23 414 415 #define ASC_STOP_REQ_RISC_STOP 0x01 416 #define ASC_STOP_ACK_RISC_STOP 0x03 417 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 418 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 419 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 420 421 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 422 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 423 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 424 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 425 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 426 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 427 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 428 429 430 /* 431 * Structures used to dialog with the RISC engine 432 */ 433 434 typedef struct asc_scisq_1 435 { 436 u_int8_t status; /* see below status values */ 437 u_int8_t q_no; /* Queue ID of the first queue for this transaction */ 438 u_int8_t cntl; /* see below cntl values */ 439 u_int8_t sg_queue_cnt; /* number of SG entries */ 440 u_int8_t target_id; 441 u_int8_t target_lun; 442 u_int32_t data_addr; /* physical address of first segment to transef */ 443 u_int32_t data_cnt; /* byte count of first segment to transfer */ 444 u_int32_t sense_addr; /* physical address of the sense buffer */ 445 u_int8_t sense_len; /* lenght of sense buffer */ 446 u_int8_t extra_bytes; 447 } ASC_SCSIQ_1; 448 449 /* status values */ 450 #define ASC_QS_FREE 0x00 451 #define ASC_QS_READY 0x01 452 #define ASC_QS_DISC1 0x02 453 #define ASC_QS_DISC2 0x04 454 #define ASC_QS_BUSY 0x08 455 #define ASC_QS_ABORTED 0x40 456 #define ASC_QS_DONE 0x80 457 458 /* cntl values */ 459 #define ASC_QC_NO_CALLBACK 0x01 460 #define ASC_QC_SG_SWAP_QUEUE 0x02 461 #define ASC_QC_SG_HEAD 0x04 462 #define ASC_QC_DATA_IN 0x08 463 #define ASC_QC_DATA_OUT 0x10 464 #define ASC_QC_URGENT 0x20 465 #define ASC_QC_MSG_OUT 0x40 466 #define ASC_QC_REQ_SENSE 0x80 467 468 469 typedef struct asc_scisq_2 470 { 471 u_int32_t ccb_ptr; /* pointer to our CCB */ 472 u_int8_t target_ix; /* combined TID and LUN */ 473 u_int8_t flag; 474 u_int8_t cdb_len; /* bytes of Command Descriptor Block */ 475 u_int8_t tag_code; /* type of this transaction. see below */ 476 u_int16_t vm_id; 477 } ASC_SCSIQ_2; 478 479 /* tag_code values */ 480 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 481 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 482 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 483 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 484 485 486 typedef struct asc_scsiq_3 487 { 488 u_int8_t done_stat; /* see below done_stat values */ 489 u_int8_t host_stat; /* see below host_stat values */ 490 u_int8_t scsi_stat; 491 u_int8_t scsi_msg; 492 } ASC_SCSIQ_3; 493 494 /* done_stat values */ 495 #define ASC_QD_IN_PROGRESS 0x00 496 #define ASC_QD_NO_ERROR 0x01 497 #define ASC_QD_ABORTED_BY_HOST 0x02 498 #define ASC_QD_WITH_ERROR 0x04 499 #define ASC_QD_INVALID_REQUEST 0x80 500 #define ASC_QD_INVALID_HOST_NUM 0x81 501 #define ASC_QD_INVALID_DEVICE 0x82 502 #define ASC_QD_ERR_INTERNAL 0xFF 503 504 /* host_stat values */ 505 #define ASC_QHSTA_NO_ERROR 0x00 506 #define ASC_QHSTA_M_SEL_TIMEOUT 0x11 507 #define ASC_QHSTA_M_DATA_OVER_RUN 0x12 508 #define ASC_QHSTA_M_DATA_UNDER_RUN 0x12 509 #define ASC_QHSTA_M_UNEXPECTED_BUS_FREE 0x13 510 #define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 511 #define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 512 #define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 513 #define ASC_QHSTA_D_HOST_ABORT_FAILED 0x23 514 #define ASC_QHSTA_D_EXE_SCSI_Q_FAILED 0x24 515 #define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 516 #define ASC_QHSTA_D_ASPI_NO_BUF_POOL 0x26 517 #define ASC_QHSTA_M_WTM_TIMEOUT 0x41 518 #define ASC_QHSTA_M_BAD_CMPL_STATUS_IN 0x42 519 #define ASC_QHSTA_M_NO_AUTO_REQ_SENSE 0x43 520 #define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 521 #define ASC_QHSTA_M_TARGET_STATUS_BUSY 0x45 522 #define ASC_QHSTA_M_BAD_TAG_CODE 0x46 523 #define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 524 #define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 525 #define ASC_QHSTA_D_LRAM_CMP_ERROR 0x81 526 #define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 527 528 529 typedef struct asc_scsiq_4 530 { 531 u_int8_t cdb[ASC_MAX_CDB_LEN]; 532 u_int8_t y_first_sg_list_qp; 533 u_int8_t y_working_sg_qp; 534 u_int8_t y_working_sg_ix; 535 u_int8_t y_res; 536 u_int16_t x_req_count; 537 u_int16_t x_reconnect_rtn; 538 u_int32_t x_saved_data_addr; 539 u_int32_t x_saved_data_cnt; 540 } ASC_SCSIQ_4; 541 542 typedef struct asc_q_done_info 543 { 544 ASC_SCSIQ_2 d2; 545 ASC_SCSIQ_3 d3; 546 u_int8_t q_status; 547 u_int8_t q_no; 548 u_int8_t cntl; 549 u_int8_t sense_len; 550 u_int8_t extra_bytes; 551 u_int8_t res; 552 u_int32_t remain_bytes; 553 } ASC_QDONE_INFO; 554 555 typedef struct asc_sg_list 556 { 557 u_int32_t addr; 558 u_int32_t bytes; 559 } ASC_SG_LIST; 560 561 typedef struct asc_sg_head 562 { 563 u_int16_t entry_cnt; /* number of SG entries */ 564 u_int16_t queue_cnt; /* number of queues required to store SG entries */ 565 u_int16_t entry_to_copy; /* number of SG entries to copy to the board */ 566 u_int16_t res; 567 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST]; 568 } ASC_SG_HEAD; 569 570 #define ASC_MIN_SG_LIST 2 571 572 typedef struct asc_min_sg_head 573 { 574 u_int16_t entry_cnt; 575 u_int16_t queue_cnt; 576 u_int16_t entry_to_copy; 577 u_int16_t res; 578 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST]; 579 } ASC_MIN_SG_HEAD; 580 581 #define ASC_QCX_SORT 0x0001 582 #define ASC_QCX_COALEASE 0x0002 583 584 typedef struct asc_scsi_q 585 { 586 ASC_SCSIQ_1 q1; 587 ASC_SCSIQ_2 q2; 588 u_int8_t *cdbptr; /* pointer to CDB to execute */ 589 ASC_SG_HEAD *sg_head; /* pointer to SG list */ 590 } ASC_SCSI_Q; 591 592 typedef struct asc_scsi_req_q 593 { 594 ASC_SCSIQ_1 q1; 595 ASC_SCSIQ_2 q2; 596 u_int8_t *cdbptr; 597 ASC_SG_HEAD *sg_head; 598 u_int8_t *sense_ptr; 599 ASC_SCSIQ_3 q3; 600 u_int8_t cdb[ASC_MAX_CDB_LEN]; 601 u_int8_t sense[ASC_MIN_SENSE_LEN]; 602 } ASC_SCSI_REQ_Q; 603 604 typedef struct asc_scsi_bios_req_q 605 { 606 ASC_SCSIQ_1 q1; 607 ASC_SCSIQ_2 q2; 608 u_int8_t *cdbptr; 609 ASC_SG_HEAD *sg_head; 610 u_int8_t *sense_ptr; 611 ASC_SCSIQ_3 q3; 612 u_int8_t cdb[ASC_MAX_CDB_LEN]; 613 u_int8_t sense[ASC_MIN_SENSE_LEN]; 614 } ASC_SCSI_BIOS_REQ_Q; 615 616 typedef struct asc_risc_q 617 { 618 u_int8_t fwd; 619 u_int8_t bwd; 620 ASC_SCSIQ_1 i1; 621 ASC_SCSIQ_2 i2; 622 ASC_SCSIQ_3 i3; 623 ASC_SCSIQ_4 i4; 624 } ASC_RISC_Q; 625 626 typedef struct asc_sg_list_q 627 { 628 u_int8_t seq_no; 629 u_int8_t q_no; 630 u_int8_t cntl; /* see below cntl values */ 631 u_int8_t sg_head_qp; 632 u_int8_t sg_list_cnt; 633 u_int8_t sg_cur_list_cnt; 634 } ASC_SG_LIST_Q; 635 636 /* cntl values */ 637 #define ASC_QCSG_SG_XFER_LIST 0x02 638 #define ASC_QCSG_SG_XFER_MORE 0x04 639 #define ASC_QCSG_SG_XFER_END 0x08 640 641 #define ASC_SGQ_B_SG_CNTL 4 642 #define ASC_SGQ_B_SG_HEAD_QP 5 643 #define ASC_SGQ_B_SG_LIST_CNT 6 644 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 645 #define ASC_SGQ_LIST_BEG 8 646 647 648 typedef struct asc_risc_sg_list_q 649 { 650 u_int8_t fwd; 651 u_int8_t bwd; 652 ASC_SG_LIST_Q sg; 653 ASC_SG_LIST sg_list[7]; 654 } ASC_RISC_SG_LIST_Q; 655 656 657 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL 658 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024 659 660 #define ASCQ_ERR_NO_ERROR 0x00 661 #define ASCQ_ERR_IO_NOT_FOUND 0x01 662 #define ASCQ_ERR_LOCAL_MEM 0x02 663 #define ASCQ_ERR_CHKSUM 0x03 664 #define ASCQ_ERR_START_CHIP 0x04 665 #define ASCQ_ERR_INT_TARGET_ID 0x05 666 #define ASCQ_ERR_INT_LOCAL_MEM 0x06 667 #define ASCQ_ERR_HALT_RISC 0x07 668 #define ASCQ_ERR_GET_ASPI_ENTRY 0x08 669 #define ASCQ_ERR_CLOSE_ASPI 0x09 670 #define ASCQ_ERR_HOST_INQUIRY 0x0A 671 #define ASCQ_ERR_SAVED_CCB_BAD 0x0B 672 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C 673 #define ASCQ_ERR_Q_STATUS 0x0D 674 #define ASCQ_ERR_WR_SCSIQ 0x0E 675 #define ASCQ_ERR_PC_ADDR 0x0F 676 #define ASCQ_ERR_SYN_OFFSET 0x10 677 #define ASCQ_ERR_SYN_XFER_TIME 0x11 678 #define ASCQ_ERR_LOCK_DMA 0x12 679 #define ASCQ_ERR_UNLOCK_DMA 0x13 680 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14 681 #define ASCQ_ERR_MICRO_CODE_HALT 0x15 682 #define ASCQ_ERR_SET_LRAM_ADDR 0x16 683 #define ASCQ_ERR_CUR_QNG 0x17 684 #define ASCQ_ERR_SG_Q_LINKS 0x18 685 #define ASCQ_ERR_SCSIQ_PTR 0x19 686 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A 687 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 688 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 689 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D 690 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E 691 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F 692 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20 693 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21 694 #define ASCQ_ERR_SEND_SCSI_Q 0x22 695 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23 696 #define ASCQ_ERR_RESET_SDTR 0x24 697 698 #define ASC_WARN_NO_ERROR 0x0000 699 #define ASC_WARN_IO_PORT_ROTATE 0x0001 700 #define ASC_WARN_EEPROM_CHKSUM 0x0002 701 #define ASC_WARN_IRQ_MODIFIED 0x0004 702 #define ASC_WARN_AUTO_CONFIG 0x0008 703 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 704 #define ASC_WARN_EEPROM_RECOVER 0x0020 705 #define ASC_WARN_CFG_MSW_RECOVER 0x0040 706 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 707 708 #define ASC_IERR_WRITE_EEPROM 0x0001 709 #define ASC_IERR_MCODE_CHKSUM 0x0002 710 #define ASC_IERR_SET_PC_ADDR 0x0004 711 #define ASC_IERR_START_STOP_CHIP 0x0008 712 #define ASC_IERR_IRQ_NO 0x0010 713 #define ASC_IERR_SET_IRQ_NO 0x0020 714 #define ASC_IERR_CHIP_VERSION 0x0040 715 #define ASC_IERR_SET_SCSI_ID 0x0080 716 #define ASC_IERR_GET_PHY_ADDR 0x0100 717 #define ASC_IERR_BAD_SIGNATURE 0x0200 718 #define ASC_IERR_NO_BUS_TYPE 0x0400 719 #define ASC_IERR_SCAM 0x0800 720 #define ASC_IERR_SET_SDTR 0x1000 721 #define ASC_IERR_RW_LRAM 0x8000 722 723 #define ASC_DEF_IRQ_NO 10 724 #define ASC_MAX_IRQ_NO 15 725 #define ASC_MIN_IRQ_NO 10 726 #define ASC_MIN_REMAIN_Q 0x02 727 #define ASC_DEF_MAX_TOTAL_QNG 0xF0 728 #define ASC_MIN_TAG_Q_PER_DVC 0x04 729 #define ASC_DEF_TAG_Q_PER_DVC 0x04 730 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q 731 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 732 #define ASC_MAX_TOTAL_QNG 240 733 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 734 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 735 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 736 #define ASC_MAX_INRAM_TAG_QNG 16 737 #define ASC_IOADR_TABLE_MAX_IX 11 738 #define ASC_IOADR_GAP 0x10 739 #define ASC_SEARCH_IOP_GAP 0x10 740 #define ASC_MIN_IOP_ADDR 0x0100 741 #define ASC_MAX_IOP_ADDR 0x03F0 742 743 #define ASC_IOADR_1 0x0110 744 #define ASC_IOADR_2 0x0130 745 #define ASC_IOADR_3 0x0150 746 #define ASC_IOADR_4 0x0190 747 #define ASC_IOADR_5 0x0210 748 #define ASC_IOADR_6 0x0230 749 #define ASC_IOADR_7 0x0250 750 #define ASC_IOADR_8 0x0330 751 752 #define ASC_IOADR_DEF ASC_IOADR_8 753 #define ASC_LIB_SCSIQ_WK_SP 256 754 #define ASC_MAX_SYN_XFER_NO 16 755 #define ASC_SYN_MAX_OFFSET 0x0F 756 #define ASC_DEF_SDTR_OFFSET 0x0F 757 #define ASC_DEF_SDTR_INDEX 0x00 758 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 759 760 761 /* 762 * This structure is used to handle internal messages 763 * during interrupt handling routine 764 */ 765 typedef struct ext_msg 766 { 767 u_int8_t msg_type; 768 u_int8_t msg_len; 769 u_int8_t msg_req; 770 771 union 772 { 773 struct 774 { 775 u_int8_t sdtr_xfer_period; 776 u_int8_t sdtr_req_ack_offset; 777 } sdtr; 778 779 struct 780 { 781 u_int8_t wdtr_width; 782 } wdtr; 783 784 struct 785 { 786 u_int8_t mdp_b3; 787 u_int8_t mdp_b2; 788 u_int8_t mdp_b1; 789 u_int8_t mdp_b0; 790 } mdp; 791 } u_ext_msg; 792 793 u_int8_t res; 794 } EXT_MSG; 795 796 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 797 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 798 #define wdtr_width u_ext_msg.wdtr.wdtr_width 799 #define mdp_b3 u_ext_msg.mdp_b3 800 #define mdp_b2 u_ext_msg.mdp_b2 801 #define mdp_b1 u_ext_msg.mdp_b1 802 #define mdp_b0 u_ext_msg.mdp_b0 803 804 805 #define ASC_DEF_DVC_CNTL 0xFFFF 806 #define ASC_DEF_CHIP_SCSI_ID 7 807 #define ASC_DEF_ISA_DMA_SPEED 4 808 809 #define ASC_PCI_DEVICE_ID_REV_A 0x1100 810 #define ASC_PCI_DEVICE_ID_REV_B 0x1200 811 812 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 813 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 814 815 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 816 817 #define ASC_MIN_TAGGED_CMD 7 818 819 #define ASC_MAX_SCSI_RESET_WAIT 30 820 821 822 typedef struct asc_softc 823 { 824 struct device sc_dev; 825 826 bus_space_tag_t sc_iot; 827 bus_space_handle_t sc_ioh; 828 bus_dma_tag_t sc_dmat; 829 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 830 void *sc_ih; 831 832 struct adv_control *sc_control; /* control structures */ 833 TAILQ_HEAD(, adv_ccb) sc_free_ccb, sc_waiting_ccb; 834 struct scsipi_link sc_link; /* prototype for devs */ 835 836 LIST_HEAD(, scsipi_xfer) sc_queue; 837 struct scsipi_xfer *sc_queuelast; 838 839 u_int8_t *overrun_buf; 840 841 u_int16_t sc_flags; /* see below sc_flags values */ 842 843 u_int16_t dvc_cntl; 844 u_int16_t bug_fix_cntl; 845 u_int16_t bus_type; 846 847 ulong isr_callback; 848 849 ASC_SCSI_BIT_ID_TYPE init_sdtr; 850 ASC_SCSI_BIT_ID_TYPE sdtr_done; 851 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 852 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 853 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 854 ASC_SCSI_BIT_ID_TYPE start_motor; 855 856 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 857 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 858 ASC_SCSI_BIT_ID_TYPE disc_enable; 859 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 860 u_int8_t chip_scsi_id; 861 u_int8_t isa_dma_speed; 862 u_int8_t isa_dma_channel; 863 u_int8_t chip_version; 864 u_int16_t pci_device_id; 865 u_int16_t lib_serial_no; 866 u_int16_t lib_version; 867 u_int16_t mcode_date; 868 u_int16_t mcode_version; 869 u_int8_t max_tag_qng[ASC_MAX_TID + 1]; 870 u_int8_t sdtr_period_offset[ASC_MAX_TID + 1]; 871 u_int8_t adapter_info[6]; 872 873 u_int8_t scsi_reset_wait; 874 u_int8_t max_total_qng; 875 u_int8_t cur_total_qng; 876 u_int8_t irq_no; 877 u_int8_t last_q_shortage; 878 879 u_int8_t cur_dvc_qng[ASC_MAX_TID + 1]; 880 u_int8_t max_dvc_qng[ASC_MAX_TID + 1]; 881 u_int8_t sdtr_period_tbl[ASC_MAX_SYN_XFER_NO]; 882 u_int8_t sdtr_period_tbl_size; /* see below */ 883 u_int8_t sdtr_data[ASC_MAX_TID+1]; 884 885 u_int16_t reqcnt[ASC_MAX_TID+1]; /* Starvation request count */ 886 887 u_int32_t max_dma_count; 888 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 889 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 890 u_int8_t max_sdtr_index; 891 u_int8_t host_init_sdtr_index; 892 } ASC_SOFTC; 893 894 /* sc_flags values */ 895 #define ASC_HOST_IN_RESET 0x01 896 #define ASC_HOST_IN_ABORT 0x02 897 #define ASC_WIDE_BOARD 0x04 898 #define ASC_SELECT_QUEUE_DEPTHS 0x08 899 900 /* sdtr_period_tbl_size values */ 901 #define SYN_XFER_NS_0 25 902 #define SYN_XFER_NS_1 30 903 #define SYN_XFER_NS_2 35 904 #define SYN_XFER_NS_3 40 905 #define SYN_XFER_NS_4 50 906 #define SYN_XFER_NS_5 60 907 #define SYN_XFER_NS_6 70 908 #define SYN_XFER_NS_7 85 909 910 #define SYN_ULTRA_XFER_NS_0 12 911 #define SYN_ULTRA_XFER_NS_1 19 912 #define SYN_ULTRA_XFER_NS_2 25 913 #define SYN_ULTRA_XFER_NS_3 32 914 #define SYN_ULTRA_XFER_NS_4 38 915 #define SYN_ULTRA_XFER_NS_5 44 916 #define SYN_ULTRA_XFER_NS_6 50 917 #define SYN_ULTRA_XFER_NS_7 57 918 #define SYN_ULTRA_XFER_NS_8 63 919 #define SYN_ULTRA_XFER_NS_9 69 920 #define SYN_ULTRA_XFER_NS_10 75 921 #define SYN_ULTRA_XFER_NS_11 82 922 #define SYN_ULTRA_XFER_NS_12 88 923 #define SYN_ULTRA_XFER_NS_13 94 924 #define SYN_ULTRA_XFER_NS_14 100 925 #define SYN_ULTRA_XFER_NS_15 107 926 927 928 /* second level interrupt callback type definition */ 929 typedef int (* ASC_ISR_CALLBACK) (ASC_SOFTC *, ASC_QDONE_INFO *); 930 931 932 #define ASC_MCNTL_NO_SEL_TIMEOUT 0x0001 933 #define ASC_MCNTL_NULL_TARGET 0x0002 934 935 #define ASC_CNTL_INITIATOR 0x0001 936 #define ASC_CNTL_BIOS_GT_1GB 0x0002 937 #define ASC_CNTL_BIOS_GT_2_DISK 0x0004 938 #define ASC_CNTL_BIOS_REMOVABLE 0x0008 939 #define ASC_CNTL_NO_SCAM 0x0010 940 #define ASC_CNTL_INT_MULTI_Q 0x0080 941 #define ASC_CNTL_NO_LUN_SUPPORT 0x0040 942 #define ASC_CNTL_NO_VERIFY_COPY 0x0100 943 #define ASC_CNTL_RESET_SCSI 0x0200 944 #define ASC_CNTL_INIT_INQUIRY 0x0400 945 #define ASC_CNTL_INIT_VERBOSE 0x0800 946 #define ASC_CNTL_SCSI_PARITY 0x1000 947 #define ASC_CNTL_BURST_MODE 0x2000 948 #define ASC_CNTL_SDTR_ENABLE_ULTRA 0x4000 949 950 #define ASC_EEP_DVC_CFG_BEG_VL 2 951 #define ASC_EEP_MAX_DVC_ADDR_VL 15 952 #define ASC_EEP_DVC_CFG_BEG 32 953 #define ASC_EEP_MAX_DVC_ADDR 45 954 #define ASC_EEP_DEFINED_WORDS 10 955 #define ASC_EEP_MAX_ADDR 63 956 #define ASC_EEP_RES_WORDS 0 957 #define ASC_EEP_MAX_RETRY 20 958 #define ASC_MAX_INIT_BUSY_RETRY 8 959 #define ASC_EEP_ISA_PNP_WSIZE 16 960 961 962 /* 963 * This structure is used to read/write EEProm configuration 964 */ 965 typedef struct asceep_config 966 { 967 u_int16_t cfg_lsw; 968 u_int16_t cfg_msw; 969 u_int8_t init_sdtr; 970 u_int8_t disc_enable; 971 u_int8_t use_cmd_qng; 972 u_int8_t start_motor; 973 u_int8_t max_total_qng; 974 u_int8_t max_tag_qng; 975 u_int8_t bios_scan; 976 u_int8_t power_up_wait; 977 u_int8_t no_scam; 978 u_int8_t chip_scsi_id:4; 979 u_int8_t isa_dma_speed:4; 980 u_int8_t dos_int13_table[ASC_MAX_TID + 1]; 981 u_int8_t adapter_info[6]; 982 u_int16_t cntl; 983 u_int16_t chksum; 984 } ASCEEP_CONFIG; 985 986 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800 987 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080 988 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020 989 990 #define ASC_EEP_CMD_READ 0x80 991 #define ASC_EEP_CMD_WRITE 0x40 992 #define ASC_EEP_CMD_WRITE_ABLE 0x30 993 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 994 995 #define ASC_OVERRUN_BSIZE 0x00000048UL 996 997 #define ASC_CTRL_BREAK_ONCE 0x0001 998 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002 999 1000 #define ASCV_MSGOUT_BEG 0x0000 1001 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 1002 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 1003 #define ASCV_BREAK_SAVED_CODE 0x0006 1004 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 1005 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 1006 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 1007 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 1008 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 1009 #define ASCV_MAX_DVC_QNG_BEG 0x0020 1010 #define ASCV_BREAK_ADDR 0x0028 1011 #define ASCV_BREAK_NOTIFY_COUNT 0x002A 1012 #define ASCV_BREAK_CONTROL 0x002C 1013 #define ASCV_BREAK_HIT_COUNT 0x002E 1014 1015 #define ASCV_ASCDVC_ERR_CODE_W 0x0030 1016 #define ASCV_MCODE_CHKSUM_W 0x0032 1017 #define ASCV_MCODE_SIZE_W 0x0034 1018 #define ASCV_STOP_CODE_B 0x0036 1019 #define ASCV_DVC_ERR_CODE_B 0x0037 1020 #define ASCV_OVERRUN_PADDR_D 0x0038 1021 #define ASCV_OVERRUN_BSIZE_D 0x003C 1022 #define ASCV_HALTCODE_W 0x0040 1023 #define ASCV_CHKSUM_W 0x0042 1024 #define ASCV_MC_DATE_W 0x0044 1025 #define ASCV_MC_VER_W 0x0046 1026 #define ASCV_NEXTRDY_B 0x0048 1027 #define ASCV_DONENEXT_B 0x0049 1028 #define ASCV_USE_TAGGED_QNG_B 0x004A 1029 #define ASCV_SCSIBUSY_B 0x004B 1030 #define ASCV_Q_DONE_IN_PROGRESS_B 0x004C 1031 #define ASCV_CURCDB_B 0x004D 1032 #define ASCV_RCLUN_B 0x004E 1033 #define ASCV_BUSY_QHEAD_B 0x004F 1034 #define ASCV_DISC1_QHEAD_B 0x0050 1035 #define ASCV_DISC_ENABLE_B 0x0052 1036 #define ASCV_CAN_TAGGED_QNG_B 0x0053 1037 #define ASCV_HOSTSCSI_ID_B 0x0055 1038 #define ASCV_MCODE_CNTL_B 0x0056 1039 #define ASCV_NULL_TARGET_B 0x0057 1040 #define ASCV_FREE_Q_HEAD_W 0x0058 1041 #define ASCV_DONE_Q_TAIL_W 0x005A 1042 #define ASCV_FREE_Q_HEAD_B (ASCV_FREE_Q_HEAD_W+1) 1043 #define ASCV_DONE_Q_TAIL_B (ASCV_DONE_Q_TAIL_W+1) 1044 #define ASCV_HOST_FLAG_B 0x005D 1045 #define ASCV_TOTAL_READY_Q_B 0x0064 1046 #define ASCV_VER_SERIAL_B 0x0065 1047 #define ASCV_HALTCODE_SAVED_W 0x0066 1048 #define ASCV_WTM_FLAG_B 0x0068 1049 #define ASCV_RISC_FLAG_B 0x006A 1050 #define ASCV_REQ_SG_LIST_QP 0x006B 1051 1052 #define ASC_HOST_FLAG_IN_ISR 0x01 1053 #define ASC_HOST_FLAG_ACK_INT 0x02 1054 #define ASC_RISC_FLAG_GEN_INT 0x01 1055 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 1056 1057 #define ASC_IOP_CTRL 0x0F 1058 #define ASC_IOP_STATUS 0x0E 1059 #define ASC_IOP_INT_ACK ASC_IOP_STATUS 1060 #define ASC_IOP_REG_IFC 0x0D 1061 #define ASC_IOP_SYN_OFFSET 0x0B 1062 #define ASC_IOP_EXTRA_CONTROL 0x0D 1063 #define ASC_IOP_REG_PC 0x0C 1064 #define ASC_IOP_RAM_ADDR 0x0A 1065 #define ASC_IOP_RAM_DATA 0x08 1066 #define ASC_IOP_EEP_DATA 0x06 1067 #define ASC_IOP_EEP_CMD 0x07 1068 #define ASC_IOP_VERSION 0x03 1069 #define ASC_IOP_CONFIG_HIGH 0x04 1070 #define ASC_IOP_CONFIG_LOW 0x02 1071 #define ASC_IOP_SIG_BYTE 0x01 1072 #define ASC_IOP_SIG_WORD 0x00 1073 #define ASC_IOP_REG_DC1 0x0E 1074 #define ASC_IOP_REG_DC0 0x0C 1075 #define ASC_IOP_REG_SB 0x0B 1076 #define ASC_IOP_REG_DA1 0x0A 1077 #define ASC_IOP_REG_DA0 0x08 1078 #define ASC_IOP_REG_SC 0x09 1079 #define ASC_IOP_DMA_SPEED 0x07 1080 #define ASC_IOP_REG_FLAG 0x07 1081 #define ASC_IOP_FIFO_H 0x06 1082 #define ASC_IOP_FIFO_L 0x04 1083 #define ASC_IOP_REG_ID 0x05 1084 #define ASC_IOP_REG_QP 0x03 1085 #define ASC_IOP_REG_IH 0x02 1086 #define ASC_IOP_REG_IX 0x01 1087 #define ASC_IOP_REG_AX 0x00 1088 1089 #define ASC_IFC_REG_LOCK 0x00 1090 #define ASC_IFC_REG_UNLOCK 0x09 1091 #define ASC_IFC_WR_EN_FILTER 0x10 1092 #define ASC_IFC_RD_NO_EEPROM 0x10 1093 #define ASC_IFC_SLEW_RATE 0x20 1094 #define ASC_IFC_ACT_NEG 0x40 1095 #define ASC_IFC_INP_FILTER 0x80 1096 #define ASC_IFC_INIT_DEFAULT (ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK) 1097 1098 #define SC_SEL 0x80 1099 #define SC_BSY 0x40 1100 #define SC_ACK 0x20 1101 #define SC_REQ 0x10 1102 #define SC_ATN 0x08 1103 #define SC_IO 0x04 1104 #define SC_CD 0x02 1105 #define SC_MSG 0x01 1106 1107 #define SEC_SCSI_CTL 0x80 1108 #define SEC_ACTIVE_NEGATE 0x40 1109 #define SEC_SLEW_RATE 0x20 1110 #define SEC_ENABLE_FILTER 0x10 1111 1112 #define ASC_HALT_EXTMSG_IN 0x8000 1113 #define ASC_HALT_CHK_CONDITION 0x8100 1114 #define ASC_HALT_SS_QUEUE_FULL 0x8200 1115 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 1116 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 1117 #define ASC_HALT_SDTR_REJECTED 0x4000 1118 1119 #define ASC_MAX_QNO 0xF8 1120 1121 #define ASC_DATA_SEC_BEG 0x0080 1122 #define ASC_DATA_SEC_END 0x0080 1123 #define ASC_CODE_SEC_BEG 0x0080 1124 #define ASC_CODE_SEC_END 0x0080 1125 #define ASC_QADR_BEG (0x4000) 1126 #define ASC_QADR_USED (ASC_MAX_QNO * 64) 1127 #define ASC_QADR_END 0x7FFF 1128 #define ASC_QLAST_ADR 0x7FC0 1129 #define ASC_QBLK_SIZE 0x40 1130 #define ASC_BIOS_DATA_QBEG 0xF8 1131 #define ASC_MIN_ACTIVE_QNO 0x01 1132 #define ASC_QLINK_END 0xFF 1133 #define ASC_EEPROM_WORDS 0x10 1134 #define ASC_MAX_MGS_LEN 0x10 1135 1136 #define ASC_BIOS_ADDR_DEF 0xDC00 1137 #define ASC_BIOS_SIZE 0x3800 1138 #define ASC_BIOS_RAM_OFF 0x3800 1139 #define ASC_BIOS_RAM_SIZE 0x800 1140 #define ASC_BIOS_MIN_ADDR 0xC000 1141 #define ASC_BIOS_MAX_ADDR 0xEC00 1142 #define ASC_BIOS_BANK_SIZE 0x0400 1143 1144 #define ASC_MCODE_START_ADDR 0x0080 1145 1146 #define ASC_CFG0_HOST_INT_ON 0x0020 1147 #define ASC_CFG0_BIOS_ON 0x0040 1148 #define ASC_CFG0_VERA_BURST_ON 0x0080 1149 #define ASC_CFG0_SCSI_PARITY_ON 0x0800 1150 #define ASC_CFG1_SCSI_TARGET_ON 0x0080 1151 #define ASC_CFG1_LRAM_8BITS_ON 0x0800 1152 #define ASC_CFG_MSW_CLR_MASK 0x3080 1153 1154 #define ASC_CSW_TEST1 0x8000 1155 #define ASC_CSW_AUTO_CONFIG 0x4000 1156 #define ASC_CSW_RESERVED1 0x2000 1157 #define ASC_CSW_IRQ_WRITTEN 0x1000 1158 #define ASC_CSW_33MHZ_SELECTED 0x0800 1159 #define ASC_CSW_TEST2 0x0400 1160 #define ASC_CSW_TEST3 0x0200 1161 #define ASC_CSW_RESERVED2 0x0100 1162 #define ASC_CSW_DMA_DONE 0x0080 1163 #define ASC_CSW_FIFO_RDY 0x0040 1164 #define ASC_CSW_EEP_READ_DONE 0x0020 1165 #define ASC_CSW_HALTED 0x0010 1166 #define ASC_CSW_SCSI_RESET_ACTIVE 0x0008 1167 #define ASC_CSW_PARITY_ERR 0x0004 1168 #define ASC_CSW_SCSI_RESET_LATCH 0x0002 1169 #define ASC_CSW_INT_PENDING 0x0001 1170 1171 #define ASC_CIW_CLR_SCSI_RESET_INT 0x1000 1172 #define ASC_CIW_INT_ACK 0x0100 1173 #define ASC_CIW_TEST1 0x0200 1174 #define ASC_CIW_TEST2 0x0400 1175 #define ASC_CIW_SEL_33MHZ 0x0800 1176 #define ASC_CIW_IRQ_ACT 0x1000 1177 1178 #define ASC_CC_CHIP_RESET 0x80 1179 #define ASC_CC_SCSI_RESET 0x40 1180 #define ASC_CC_HALT 0x20 1181 #define ASC_CC_SINGLE_STEP 0x10 1182 #define ASC_CC_DMA_ABLE 0x08 1183 #define ASC_CC_TEST 0x04 1184 #define ASC_CC_BANK_ONE 0x02 1185 #define ASC_CC_DIAG 0x01 1186 1187 #define ASC_1000_ID0W 0x04C1 1188 #define ASC_1000_ID0W_FIX 0x00C1 1189 #define ASC_1000_ID1B 0x25 1190 1191 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50) 1192 #define ASC_EISA_SMALL_IOP_GAP (0x0020) 1193 #define ASC_EISA_MIN_IOP_ADDR (0x0C30) 1194 #define ASC_EISA_MAX_IOP_ADDR (0xFC50) 1195 #define ASC_EISA_REV_IOP_MASK (0x0C83) 1196 #define ASC_EISA_PID_IOP_MASK (0x0C80) 1197 #define ASC_EISA_CFG_IOP_MASK (0x0C86) 1198 1199 #define ASC_GET_EISA_SLOT(iop) ((iop) & 0xF000) 1200 1201 #define ASC_EISA_ID_740 0x01745004UL 1202 #define ASC_EISA_ID_750 0x01755004UL 1203 1204 #define ASC_INS_HALTINT 0x6281 1205 #define ASC_INS_HALT 0x6280 1206 #define ASC_INS_SINT 0x6200 1207 #define ASC_INS_RFLAG_WTM 0x7380 1208 1209 1210 /******************************************************************************/ 1211 /* Macro */ 1212 /******************************************************************************/ 1213 1214 /* 1215 * These Macros are used to deal with board CPU Registers and LRAM 1216 */ 1217 1218 #define ASC_GET_QDONE_IN_PROGRESS(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B) 1219 #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val) 1220 #define ASC_GET_VAR_FREE_QHEAD(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W) 1221 #define ASC_GET_VAR_DONE_QTAIL(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W) 1222 #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val) 1223 #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val) 1224 #define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B) 1225 #define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B) 1226 #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val) 1227 #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val) 1228 #define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ; 1229 #define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ; 1230 #define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ; 1231 #define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ; 1232 #define ASC_SYN_INDEX_TO_PERIOD(sc, index) (u_int8_t)((sc)->sdtr_period_tbl[ (index) ]) 1233 #define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE) 1234 #define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD) 1235 #define ASC_GET_CHIP_VER_NO(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_VERSION) 1236 #define ASC_GET_CHIP_CFG_LSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW) 1237 #define ASC_GET_CHIP_CFG_MSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH) 1238 #define ASC_SET_CHIP_CFG_LSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data) 1239 #define ASC_SET_CHIP_CFG_MSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data) 1240 #define ASC_GET_CHIP_EEP_CMD(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD) 1241 #define ASC_SET_CHIP_EEP_CMD(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data) 1242 #define ASC_GET_CHIP_EEP_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA) 1243 #define ASC_SET_CHIP_EEP_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data) 1244 #define ASC_GET_CHIP_LRAM_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR) 1245 #define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr) 1246 #define ASC_GET_CHIP_LRAM_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA) 1247 #define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data) 1248 #if BYTE_ORDER == BIG_ENDIAN 1249 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) swap_bytes(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)) 1250 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, swap_bytes(data)) 1251 #else 1252 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA) 1253 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data) 1254 #endif 1255 #define ASC_GET_CHIP_IFC(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC) 1256 #define ASC_SET_CHIP_IFC(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data) 1257 #define ASC_GET_CHIP_STATUS(iot, ioh) (u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS) 1258 #define ASC_SET_CHIP_STATUS(iot, ioh, cs_val) bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val) 1259 #define ASC_GET_CHIP_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_CTRL) 1260 #define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val) bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val) 1261 #define ASC_GET_CHIP_SYN(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET) 1262 #define ASC_SET_CHIP_SYN(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data) 1263 #define ASC_SET_PC_ADDR(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data) 1264 #define ASC_GET_PC_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC) 1265 #define ASC_IS_INT_PENDING(iot, ioh) (ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH)) 1266 #define ASC_GET_CHIP_SCSI_ID(iot, ioh) ((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID) 1267 #define ASC_GET_EXTRA_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL) 1268 #define ASC_SET_EXTRA_CONTROL(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data) 1269 #define ASC_READ_CHIP_AX(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX) 1270 #define ASC_WRITE_CHIP_AX(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data) 1271 #define ASC_READ_CHIP_IX(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX) 1272 #define ASC_WRITE_CHIP_IX(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data) 1273 #define ASC_READ_CHIP_IH(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH) 1274 #define ASC_WRITE_CHIP_IH(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data) 1275 #define ASC_READ_CHIP_QP(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP) 1276 #define ASC_WRITE_CHIP_QP(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data) 1277 #define ASC_READ_CHIP_FIFO_L(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L) 1278 #define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data) 1279 #define ASC_READ_CHIP_FIFO_H(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H) 1280 #define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data) 1281 #define ASC_READ_CHIP_DMA_SPEED(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED) 1282 #define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data) 1283 #define ASC_READ_CHIP_DA0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0) 1284 #define ASC_WRITE_CHIP_DA0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data) 1285 #define ASC_READ_CHIP_DA1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1) 1286 #define ASC_WRITE_CHIP_DA1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data) 1287 #define ASC_READ_CHIP_DC0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0) 1288 #define ASC_WRITE_CHIP_DC0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data) 1289 #define ASC_READ_CHIP_DC1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1) 1290 #define ASC_WRITE_CHIP_DC1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data) 1291 #define ASC_READ_CHIP_DVC_ID(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID) 1292 #define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data) 1293 1294 1295 /******************************************************************************/ 1296 /* Exported functions */ 1297 /******************************************************************************/ 1298 1299 1300 void AscInitASC_SOFTC __P((ASC_SOFTC *)); 1301 u_int16_t AscInitFromEEP __P((ASC_SOFTC *)); 1302 u_int16_t AscInitFromASC_SOFTC __P((ASC_SOFTC *)); 1303 int AscInitDriver __P((ASC_SOFTC *)); 1304 void AscReInitLram __P((ASC_SOFTC *)); 1305 int AscFindSignature __P((bus_space_tag_t, bus_space_handle_t)); 1306 int AscISR __P((ASC_SOFTC *)); 1307 int AscExeScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *)); 1308 void AscInquiryHandling __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 1309 int AscAbortCCB __P((ASC_SOFTC *, u_int32_t)); 1310 int AscResetBus __P((ASC_SOFTC *)); 1311 int AscResetDevice __P((ASC_SOFTC *, u_char)); 1312 1313 1314 /******************************************************************************/ 1315 #endif /* _ADVANSYS_LIBRARY_H_ */ 1316
Indexes created Wed Sep 24 05:09:52 GMT 2025