advlib.h revision 1.2
1 /* $NetBSD: advlib.h,v 1.2 1998/08/29 13:45:57 dante Exp $ */ 2 3 /* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-1996 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55 #ifndef _ADVANSYS_LIBRARY_H_ 56 #define _ADVANSYS_LIBRARY_H_ 57 58 #include <dev/ic/adv.h> 59 60 /******************************************************************************/ 61 62 #define ADV_VERSION "3.1E" /* AdvanSys Driver Version */ 63 64 #define ASC_LIB_VERSION_MAJOR 1 65 #define ASC_LIB_VERSION_MINOR 22 66 #define ASC_LIB_SERIAL_NUMBER 113 67 68 69 #define ASC_NOERROR 1 70 #define ASC_BUSY 0 71 #define ASC_ERROR -1 72 73 74 #define HI_BYTE(x) (*((__u8 *)(&x)+1)) 75 #define LO_BYTE(x) (*((__u8 *)&x)) 76 #define HI_WORD(x) (*((__u16 *)(&x)+1)) 77 #define LO_WORD(x) (*((__u16 *)&x)) 78 #ifndef MAKEWORD 79 #define MAKEWORD(lo, hi) ((__u16) (((__u16) lo) | ((__u16) hi << 8))) 80 #endif 81 #ifndef MAKELONG 82 #define MAKELONG(lo, hi) ((__u32) (((__u32) lo) | ((__u32) hi << 16))) 83 #endif 84 #define SwapWords(dWord) ((__u32) ((dWord >> 16) | (dWord << 16))) 85 #define SwapBytes(word) ((__u16) ((word >> 8) | (word << 8))) 86 #define BigToLittle(dWord) ((__u32) (SwapWords(MAKELONG(SwapBytes(LO_WORD(dWord)), SwapBytes(HI_WORD(dWord)))))) 87 #define LittleToBig(dWord) BigToLittle(dWord) 88 89 90 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF) 91 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F) 92 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7) 93 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF)) 94 #define ASC_PCI_REVISION_3150 0x02 95 #define ASC_PCI_REVISION_3050 0x03 96 97 98 #define ASC_IS_NARROW_BOARD(sc) (((sc)->sc_flags & ASC_WIDE_BOARD) == 0) 99 #define ASC_IS_WIDE_BOARD(sc) ((sc)->sc_flags & ASC_WIDE_BOARD) 100 101 102 #define ASC_MAX_SG_QUEUE 7 103 #define ASC_SG_LIST_PER_Q ASC_MAX_SG_QUEUE 104 #define ASC_MAX_SG_LIST (1 + ((ASC_SG_LIST_PER_Q) * (ASC_MAX_SG_QUEUE))) /* SG_ALL */ 105 106 107 #define ASC_IS_ISA 0x0001 108 #define ASC_IS_ISAPNP 0x0081 109 #define ASC_IS_EISA 0x0002 110 #define ASC_IS_PCI 0x0004 111 #define ASC_IS_PCI_ULTRA 0x0104 112 #define ASC_IS_PCMCIA 0x0008 113 #define ASC_IS_MCA 0x0020 114 #define ASC_IS_VL 0x0040 115 116 117 #define ASC_ISA_PNP_PORT_ADDR 0x279 118 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800) 119 120 #define ASC_IS_WIDESCSI_16 0x0100 121 #define ASC_IS_WIDESCSI_32 0x0200 122 #define ASC_IS_BIG_ENDIAN 0x8000 123 124 125 #define ASC_CHIP_MIN_VER_VL 0x01 126 #define ASC_CHIP_MAX_VER_VL 0x07 127 #define ASC_CHIP_MIN_VER_PCI 0x09 128 #define ASC_CHIP_MAX_VER_PCI 0x0F 129 #define ASC_CHIP_VER_PCI_BIT 0x08 130 #define ASC_CHIP_MIN_VER_ISA 0x11 131 #define ASC_CHIP_MIN_VER_ISA_PNP 0x21 132 #define ASC_CHIP_MAX_VER_ISA 0x27 133 #define ASC_CHIP_VER_ISA_BIT 0x30 134 #define ASC_CHIP_VER_ISAPNP_BIT 0x20 135 #define ASC_CHIP_VER_ASYN_BUG 0x21 136 #define ASC_CHIP_VER_PCI 0x08 137 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 138 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 139 #define ASC_CHIP_MIN_VER_EISA 0x41 140 #define ASC_CHIP_MAX_VER_EISA 0x47 141 #define ASC_CHIP_VER_EISA_BIT 0x40 142 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 143 144 145 #define ASC_MAX_VL_DMA_ADDR 0x07FFFFFFL 146 #define ASC_MAX_VL_DMA_COUNT 0x07FFFFFFL 147 #define ASC_MAX_PCI_DMA_ADDR 0xFFFFFFFFL 148 #define ASC_MAX_PCI_DMA_COUNT 0xFFFFFFFFL 149 #define ASC_MAX_ISA_DMA_ADDR 0x00FFFFFFL 150 #define ASC_MAX_ISA_DMA_COUNT 0x00FFFFFFL 151 #define ASC_MAX_EISA_DMA_ADDR 0x07FFFFFFL 152 #define ASC_MAX_EISA_DMA_COUNT 0x07FFFFFFL 153 154 155 #define ASC_SCSI_ID_BITS 3 156 #define ASC_SCSI_TIX_TYPE u_int8_t 157 158 #define ASC_ALL_DEVICE_BIT_SET 0xFF 159 160 #ifdef ASC_WIDESCSI_16 161 #undef ASC_SCSI_ID_BITS 162 #define ASC_SCSI_ID_BITS 4 163 #define ASC_ALL_DEVICE_BIT_SET 0xFFFF 164 #endif 165 166 #ifdef ASC_WIDESCSI_32 167 #undef ASC_SCSI_ID_BITS 168 #define ASC_SCSI_ID_BITS 5 169 #define ASC_ALL_DEVICE_BIT_SET 0xFFFFFFFFL 170 #endif 171 172 #if ASC_SCSI_ID_BITS == 3 173 #define ASC_SCSI_BIT_ID_TYPE u_int8_t 174 #define ASC_MAX_TID 7 175 #define ASC_MAX_LUN 7 176 #define ASC_SCSI_WIDTH_BIT_SET 0xFF 177 #elif ASC_SCSI_ID_BITS == 4 178 #define ASC_SCSI_BIT_ID_TYPE u_int16_t 179 #define ASC_MAX_TID 15 180 #define ASC_MAX_LUN 7 181 #define ASC_SCSI_WIDTH_BIT_SET 0xFFFF 182 #elif ASC_SCSI_ID_BITS == 5 183 #define ASC_SCSI_BIT_ID_TYPE u_int32_t 184 #define ASC_MAX_TID 31 185 #define ASC_MAX_LUN 7 186 #define ASC_SCSI_WIDTH_BIT_SET 0xFFFFFFFF 187 #else 188 #error ASC_SCSI_ID_BITS definition is wrong 189 #endif 190 191 192 #define ASC_MAX_SENSE_LEN 32 193 #define ASC_MIN_SENSE_LEN 14 194 #define ASC_MAX_CDB_LEN 12 195 196 #define ASC_SCSI_RESET_HOLD_TIME_US 60 197 198 199 #define SCSICMD_TestUnitReady 0x00 200 #define SCSICMD_Rewind 0x01 201 #define SCSICMD_Rezero 0x01 202 #define SCSICMD_RequestSense 0x03 203 #define SCSICMD_Format 0x04 204 #define SCSICMD_FormatUnit 0x04 205 #define SCSICMD_Read6 0x08 206 #define SCSICMD_Write6 0x0A 207 #define SCSICMD_Seek6 0x0B 208 #define SCSICMD_Inquiry 0x12 209 #define SCSICMD_Verify6 0x13 210 #define SCSICMD_ModeSelect6 0x15 211 #define SCSICMD_ModeSense6 0x1A 212 #define SCSICMD_StartStopUnit 0x1B 213 #define SCSICMD_LoadUnloadTape 0x1B 214 #define SCSICMD_ReadCapacity 0x25 215 #define SCSICMD_Read10 0x28 216 #define SCSICMD_Write10 0x2A 217 #define SCSICMD_Seek10 0x2B 218 #define SCSICMD_Erase10 0x2C 219 #define SCSICMD_WriteAndVerify10 0x2E 220 #define SCSICMD_Verify10 0x2F 221 #define SCSICMD_WriteBuffer 0x3B 222 #define SCSICMD_ReadBuffer 0x3C 223 #define SCSICMD_ReadLong 0x3E 224 #define SCSICMD_WriteLong 0x3F 225 #define SCSICMD_ReadTOC 0x43 226 #define SCSICMD_ReadHeader 0x44 227 #define SCSICMD_ModeSelect10 0x55 228 #define SCSICMD_ModeSense10 0x5A 229 230 231 #define SCSI_TYPE_DASD 0x00 232 #define SCSI_TYPE_SASD 0x01 233 #define SCSI_TYPE_PRN 0x02 234 #define SCSI_TYPE_PROC 0x03 235 #define SCSI_TYPE_WORM 0x04 236 #define SCSI_TYPE_CDROM 0x05 237 #define SCSI_TYPE_SCANNER 0x06 238 #define SCSI_TYPE_OPTMEM 0x07 239 #define SCSI_TYPE_MED_CHG 0x08 240 #define SCSI_TYPE_COMM 0x09 241 #define SCSI_TYPE_UNKNOWN 0x1F 242 #define SCSI_TYPE_NO_DVC 0xFF 243 244 245 #define ASC_SCSIDIR_NOCHK 0x00 246 #define ASC_SCSIDIR_T2H 0x08 247 #define ASC_SCSIDIR_H2T 0x10 248 #define ASC_SCSIDIR_NODATA 0x18 249 250 251 #define SCSI_SENKEY_NO_SENSE 0x00 252 #define SCSI_SENKEY_UNDEFINED 0x01 253 #define SCSI_SENKEY_NOT_READY 0x02 254 #define SCSI_SENKEY_MEDIUM_ERR 0x03 255 #define SCSI_SENKEY_HW_ERR 0x04 256 #define SCSI_SENKEY_ILLEGAL 0x05 257 #define SCSI_SENKEY_ATTENTION 0x06 258 #define SCSI_SENKEY_PROTECTED 0x07 259 #define SCSI_SENKEY_BLANK 0x08 260 #define SCSI_SENKEY_V_UNIQUE 0x09 261 #define SCSI_SENKEY_CPY_ABORT 0x0A 262 #define SCSI_SENKEY_ABORT 0x0B 263 #define SCSI_SENKEY_EQUAL 0x0C 264 #define SCSI_SENKEY_VOL_OVERFLOW 0x0D 265 #define SCSI_SENKEY_MISCOMP 0x0E 266 #define SCSI_SENKEY_RESERVED 0x0F 267 #define SCSI_ASC_NOMEDIA 0x3A 268 269 270 #define ASC_CCB_HOST(x) ((u_int8_t)((u_int8_t)(x) >> 4)) 271 #define ASC_CCB_TID(x) ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F)) 272 #define ASC_CCB_LUN(x) ((u_int8_t)((uint)(x) >> 13)) 273 274 275 #define SS_GOOD 0x00 276 #define SS_CHK_CONDITION 0x02 277 #define SS_CONDITION_MET 0x04 278 #define SS_TARGET_BUSY 0x08 279 #define SS_INTERMID 0x10 280 #define SS_INTERMID_COND_MET 0x14 281 #define SS_RSERV_CONFLICT 0x18 282 #define SS_CMD_TERMINATED 0x22 283 #define SS_QUEUE_FULL 0x28 284 285 286 #define MS_CMD_DONE 0x00 287 #define MS_EXTEND 0x01 288 #define MS_SDTR_LEN 0x03 289 #define MS_SDTR_CODE 0x01 290 #define MS_WDTR_LEN 0x02 291 #define MS_WDTR_CODE 0x03 292 #define MS_MDP_LEN 0x05 293 #define MS_MDP_CODE 0x00 294 295 296 #define M1_SAVE_DATA_PTR 0x02 297 #define M1_RESTORE_PTRS 0x03 298 #define M1_DISCONNECT 0x04 299 #define M1_INIT_DETECTED_ERR 0x05 300 #define M1_ABORT 0x06 301 #define M1_MSG_REJECT 0x07 302 #define M1_NO_OP 0x08 303 #define M1_MSG_PARITY_ERR 0x09 304 #define M1_LINK_CMD_DONE 0x0A 305 #define M1_LINK_CMD_DONE_WFLAG 0x0B 306 #define M1_BUS_DVC_RESET 0x0C 307 #define M1_ABORT_TAG 0x0D 308 #define M1_CLR_QUEUE 0x0E 309 #define M1_INIT_RECOVERY 0x0F 310 #define M1_RELEASE_RECOVERY 0x10 311 #define M1_KILL_IO_PROC 0x11 312 #define M2_QTAG_MSG_SIMPLE 0x20 313 #define M2_QTAG_MSG_HEAD 0x21 314 #define M2_QTAG_MSG_ORDERED 0x22 315 #define M2_IGNORE_WIDE_RESIDUE 0x23 316 317 318 /* 319 * SCSI Iquiry structure 320 */ 321 322 typedef struct 323 { 324 u_int8_t peri_dvc_type:5; 325 u_int8_t peri_qualifier:3; 326 } ASC_SCSI_INQ0; 327 328 typedef struct 329 { 330 u_int8_t dvc_type_modifier:7; 331 u_int8_t rmb:1; 332 } ASC_SCSI_INQ1; 333 334 typedef struct 335 { 336 u_int8_t ansi_apr_ver:3; 337 u_int8_t ecma_ver:3; 338 u_int8_t iso_ver:2; 339 } ASC_SCSI_INQ2; 340 341 typedef struct 342 { 343 u_int8_t rsp_data_fmt:4; 344 u_int8_t res:2; 345 u_int8_t TemIOP:1; 346 u_int8_t aenc:1; 347 } ASC_SCSI_INQ3; 348 349 typedef struct 350 { 351 u_int8_t StfRe:1; 352 u_int8_t CmdQue:1; 353 u_int8_t Reserved:1; 354 u_int8_t Linked:1; 355 u_int8_t Sync:1; 356 u_int8_t WBus16:1; 357 u_int8_t WBus32:1; 358 u_int8_t RelAdr:1; 359 } ASC_SCSI_INQ7; 360 361 typedef struct 362 { 363 ASC_SCSI_INQ0 byte0; 364 ASC_SCSI_INQ1 byte1; 365 ASC_SCSI_INQ2 byte2; 366 ASC_SCSI_INQ3 byte3; 367 u_int8_t add_len; 368 u_int8_t res1; 369 u_int8_t res2; 370 ASC_SCSI_INQ7 byte7; 371 u_int8_t vendor_id[8]; 372 u_int8_t product_id[16]; 373 u_int8_t product_rev_level[4]; 374 } ASC_SCSI_INQUIRY; 375 376 377 /* 378 * SCSIQ Microcode offsets 379 */ 380 #define ASC_SCSIQ_CPY_BEG 4 381 #define ASC_SCSIQ_SGHD_CPY_BEG 2 382 #define ASC_SCSIQ_B_FWD 0 383 #define ASC_SCSIQ_B_BWD 1 384 #define ASC_SCSIQ_B_STATUS 2 385 #define ASC_SCSIQ_B_QNO 3 386 #define ASC_SCSIQ_B_CNTL 4 387 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 388 #define ASC_SCSIQ_D_DATA_ADDR 8 389 #define ASC_SCSIQ_D_DATA_CNT 12 390 #define ASC_SCSIQ_B_SENSE_LEN 20 391 #define ASC_SCSIQ_DONE_INFO_BEG 22 392 #define ASC_SCSIQ_D_CCBPTR 22 393 #define ASC_SCSIQ_B_TARGET_IX 26 394 #define ASC_SCSIQ_B_CDB_LEN 28 395 #define ASC_SCSIQ_B_TAG_CODE 29 396 #define ASC_SCSIQ_W_VM_ID 30 397 #define ASC_SCSIQ_DONE_STATUS 32 398 #define ASC_SCSIQ_HOST_STATUS 33 399 #define ASC_SCSIQ_SCSI_STATUS 34 400 #define ASC_SCSIQ_CDB_BEG 36 401 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 402 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 403 #define ASC_SCSIQ_B_SG_WK_QP 49 404 #define ASC_SCSIQ_B_SG_WK_IX 50 405 #define ASC_SCSIQ_W_REQ_COUNT 52 406 #define ASC_SCSIQ_B_LIST_CNT 6 407 #define ASC_SCSIQ_B_CUR_LIST_CNT 7 408 409 410 #define ASC_DEF_SCSI1_QNG 4 411 #define ASC_MAX_SCSI1_QNG 4 412 #define ASC_DEF_SCSI2_QNG 16 413 #define ASC_MAX_SCSI2_QNG 32 414 415 #define ASC_TAG_CODE_MASK 0x23 416 417 #define ASC_STOP_REQ_RISC_STOP 0x01 418 #define ASC_STOP_ACK_RISC_STOP 0x03 419 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 420 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 421 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 422 423 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 424 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 425 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 426 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 427 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 428 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 429 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 430 431 432 /* 433 * Structures used to dialog with the RISC engine 434 */ 435 436 typedef struct asc_scisq_1 437 { 438 u_int8_t status; /* see below status values */ 439 u_int8_t q_no; /* Queue ID of the first queue for this transaction */ 440 u_int8_t cntl; /* see below cntl values */ 441 u_int8_t sg_queue_cnt; /* number of SG entries */ 442 u_int8_t target_id; 443 u_int8_t target_lun; 444 u_int32_t data_addr; /* physical address of first segment to transef */ 445 u_int32_t data_cnt; /* byte count of first segment to transfer */ 446 u_int32_t sense_addr; /* physical address of the sense buffer */ 447 u_int8_t sense_len; /* lenght of sense buffer */ 448 u_int8_t extra_bytes; 449 } ASC_SCSIQ_1; 450 451 /* status values */ 452 #define ASC_QS_FREE 0x00 453 #define ASC_QS_READY 0x01 454 #define ASC_QS_DISC1 0x02 455 #define ASC_QS_DISC2 0x04 456 #define ASC_QS_BUSY 0x08 457 #define ASC_QS_ABORTED 0x40 458 #define ASC_QS_DONE 0x80 459 460 /* cntl values */ 461 #define ASC_QC_NO_CALLBACK 0x01 462 #define ASC_QC_SG_SWAP_QUEUE 0x02 463 #define ASC_QC_SG_HEAD 0x04 464 #define ASC_QC_DATA_IN 0x08 465 #define ASC_QC_DATA_OUT 0x10 466 #define ASC_QC_URGENT 0x20 467 #define ASC_QC_MSG_OUT 0x40 468 #define ASC_QC_REQ_SENSE 0x80 469 470 471 typedef struct asc_scisq_2 472 { 473 u_int32_t ccb_ptr; /* pointer to our CCB */ 474 u_int8_t target_ix; /* combined TID and LUN */ 475 u_int8_t flag; 476 u_int8_t cdb_len; /* bytes of Command Descriptor Block */ 477 u_int8_t tag_code; /* type of this transaction. see below */ 478 u_int16_t vm_id; 479 } ASC_SCSIQ_2; 480 481 /* tag_code values */ 482 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 483 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 484 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 485 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 486 487 488 typedef struct asc_scsiq_3 489 { 490 u_int8_t done_stat; /* see below done_stat values */ 491 u_int8_t host_stat; /* see below host_stat values */ 492 u_int8_t scsi_stat; 493 u_int8_t scsi_msg; 494 } ASC_SCSIQ_3; 495 496 /* done_stat values */ 497 #define ASC_QD_IN_PROGRESS 0x00 498 #define ASC_QD_NO_ERROR 0x01 499 #define ASC_QD_ABORTED_BY_HOST 0x02 500 #define ASC_QD_WITH_ERROR 0x04 501 #define ASC_QD_INVALID_REQUEST 0x80 502 #define ASC_QD_INVALID_HOST_NUM 0x81 503 #define ASC_QD_INVALID_DEVICE 0x82 504 #define ASC_QD_ERR_INTERNAL 0xFF 505 506 /* host_stat values */ 507 #define ASC_QHSTA_NO_ERROR 0x00 508 #define ASC_QHSTA_M_SEL_TIMEOUT 0x11 509 #define ASC_QHSTA_M_DATA_OVER_RUN 0x12 510 #define ASC_QHSTA_M_DATA_UNDER_RUN 0x12 511 #define ASC_QHSTA_M_UNEXPECTED_BUS_FREE 0x13 512 #define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 513 #define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 514 #define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 515 #define ASC_QHSTA_D_HOST_ABORT_FAILED 0x23 516 #define ASC_QHSTA_D_EXE_SCSI_Q_FAILED 0x24 517 #define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 518 #define ASC_QHSTA_D_ASPI_NO_BUF_POOL 0x26 519 #define ASC_QHSTA_M_WTM_TIMEOUT 0x41 520 #define ASC_QHSTA_M_BAD_CMPL_STATUS_IN 0x42 521 #define ASC_QHSTA_M_NO_AUTO_REQ_SENSE 0x43 522 #define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 523 #define ASC_QHSTA_M_TARGET_STATUS_BUSY 0x45 524 #define ASC_QHSTA_M_BAD_TAG_CODE 0x46 525 #define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 526 #define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 527 #define ASC_QHSTA_D_LRAM_CMP_ERROR 0x81 528 #define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 529 530 531 typedef struct asc_scsiq_4 532 { 533 u_int8_t cdb[ASC_MAX_CDB_LEN]; 534 u_int8_t y_first_sg_list_qp; 535 u_int8_t y_working_sg_qp; 536 u_int8_t y_working_sg_ix; 537 u_int8_t y_res; 538 u_int16_t x_req_count; 539 u_int16_t x_reconnect_rtn; 540 u_int32_t x_saved_data_addr; 541 u_int32_t x_saved_data_cnt; 542 } ASC_SCSIQ_4; 543 544 typedef struct asc_q_done_info 545 { 546 ASC_SCSIQ_2 d2; 547 ASC_SCSIQ_3 d3; 548 u_int8_t q_status; 549 u_int8_t q_no; 550 u_int8_t cntl; 551 u_int8_t sense_len; 552 u_int8_t extra_bytes; 553 u_int8_t res; 554 u_int32_t remain_bytes; 555 } ASC_QDONE_INFO; 556 557 typedef struct asc_sg_list 558 { 559 u_int32_t addr; 560 u_int32_t bytes; 561 } ASC_SG_LIST; 562 563 typedef struct asc_sg_head 564 { 565 u_int16_t entry_cnt; /* number of SG entries */ 566 u_int16_t queue_cnt; /* number of queues required to store SG entries */ 567 u_int16_t entry_to_copy; /* number of SG entries to copy to the board */ 568 u_int16_t res; 569 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST]; 570 } ASC_SG_HEAD; 571 572 #define ASC_MIN_SG_LIST 2 573 574 typedef struct asc_min_sg_head 575 { 576 u_int16_t entry_cnt; 577 u_int16_t queue_cnt; 578 u_int16_t entry_to_copy; 579 u_int16_t res; 580 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST]; 581 } ASC_MIN_SG_HEAD; 582 583 #define ASC_QCX_SORT 0x0001 584 #define ASC_QCX_COALEASE 0x0002 585 586 typedef struct asc_scsi_q 587 { 588 ASC_SCSIQ_1 q1; 589 ASC_SCSIQ_2 q2; 590 u_int8_t *cdbptr; /* pointer to CDB to execute */ 591 ASC_SG_HEAD *sg_head; /* pointer to SG list */ 592 } ASC_SCSI_Q; 593 594 typedef struct asc_scsi_req_q 595 { 596 ASC_SCSIQ_1 q1; 597 ASC_SCSIQ_2 q2; 598 u_int8_t *cdbptr; 599 ASC_SG_HEAD *sg_head; 600 u_int8_t *sense_ptr; 601 ASC_SCSIQ_3 q3; 602 u_int8_t cdb[ASC_MAX_CDB_LEN]; 603 u_int8_t sense[ASC_MIN_SENSE_LEN]; 604 } ASC_SCSI_REQ_Q; 605 606 typedef struct asc_scsi_bios_req_q 607 { 608 ASC_SCSIQ_1 q1; 609 ASC_SCSIQ_2 q2; 610 u_int8_t *cdbptr; 611 ASC_SG_HEAD *sg_head; 612 u_int8_t *sense_ptr; 613 ASC_SCSIQ_3 q3; 614 u_int8_t cdb[ASC_MAX_CDB_LEN]; 615 u_int8_t sense[ASC_MIN_SENSE_LEN]; 616 } ASC_SCSI_BIOS_REQ_Q; 617 618 typedef struct asc_risc_q 619 { 620 u_int8_t fwd; 621 u_int8_t bwd; 622 ASC_SCSIQ_1 i1; 623 ASC_SCSIQ_2 i2; 624 ASC_SCSIQ_3 i3; 625 ASC_SCSIQ_4 i4; 626 } ASC_RISC_Q; 627 628 typedef struct asc_sg_list_q 629 { 630 u_int8_t seq_no; 631 u_int8_t q_no; 632 u_int8_t cntl; /* see below cntl values */ 633 u_int8_t sg_head_qp; 634 u_int8_t sg_list_cnt; 635 u_int8_t sg_cur_list_cnt; 636 } ASC_SG_LIST_Q; 637 638 /* cntl values */ 639 #define ASC_QCSG_SG_XFER_LIST 0x02 640 #define ASC_QCSG_SG_XFER_MORE 0x04 641 #define ASC_QCSG_SG_XFER_END 0x08 642 643 #define ASC_SGQ_B_SG_CNTL 4 644 #define ASC_SGQ_B_SG_HEAD_QP 5 645 #define ASC_SGQ_B_SG_LIST_CNT 6 646 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 647 #define ASC_SGQ_LIST_BEG 8 648 649 650 typedef struct asc_risc_sg_list_q 651 { 652 u_int8_t fwd; 653 u_int8_t bwd; 654 ASC_SG_LIST_Q sg; 655 ASC_SG_LIST sg_list[7]; 656 } ASC_RISC_SG_LIST_Q; 657 658 659 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL 660 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024 661 662 #define ASCQ_ERR_NO_ERROR 0x00 663 #define ASCQ_ERR_IO_NOT_FOUND 0x01 664 #define ASCQ_ERR_LOCAL_MEM 0x02 665 #define ASCQ_ERR_CHKSUM 0x03 666 #define ASCQ_ERR_START_CHIP 0x04 667 #define ASCQ_ERR_INT_TARGET_ID 0x05 668 #define ASCQ_ERR_INT_LOCAL_MEM 0x06 669 #define ASCQ_ERR_HALT_RISC 0x07 670 #define ASCQ_ERR_GET_ASPI_ENTRY 0x08 671 #define ASCQ_ERR_CLOSE_ASPI 0x09 672 #define ASCQ_ERR_HOST_INQUIRY 0x0A 673 #define ASCQ_ERR_SAVED_CCB_BAD 0x0B 674 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C 675 #define ASCQ_ERR_Q_STATUS 0x0D 676 #define ASCQ_ERR_WR_SCSIQ 0x0E 677 #define ASCQ_ERR_PC_ADDR 0x0F 678 #define ASCQ_ERR_SYN_OFFSET 0x10 679 #define ASCQ_ERR_SYN_XFER_TIME 0x11 680 #define ASCQ_ERR_LOCK_DMA 0x12 681 #define ASCQ_ERR_UNLOCK_DMA 0x13 682 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14 683 #define ASCQ_ERR_MICRO_CODE_HALT 0x15 684 #define ASCQ_ERR_SET_LRAM_ADDR 0x16 685 #define ASCQ_ERR_CUR_QNG 0x17 686 #define ASCQ_ERR_SG_Q_LINKS 0x18 687 #define ASCQ_ERR_SCSIQ_PTR 0x19 688 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A 689 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 690 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 691 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D 692 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E 693 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F 694 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20 695 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21 696 #define ASCQ_ERR_SEND_SCSI_Q 0x22 697 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23 698 #define ASCQ_ERR_RESET_SDTR 0x24 699 700 #define ASC_WARN_NO_ERROR 0x0000 701 #define ASC_WARN_IO_PORT_ROTATE 0x0001 702 #define ASC_WARN_EEPROM_CHKSUM 0x0002 703 #define ASC_WARN_IRQ_MODIFIED 0x0004 704 #define ASC_WARN_AUTO_CONFIG 0x0008 705 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 706 #define ASC_WARN_EEPROM_RECOVER 0x0020 707 #define ASC_WARN_CFG_MSW_RECOVER 0x0040 708 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 709 710 #define ASC_IERR_WRITE_EEPROM 0x0001 711 #define ASC_IERR_MCODE_CHKSUM 0x0002 712 #define ASC_IERR_SET_PC_ADDR 0x0004 713 #define ASC_IERR_START_STOP_CHIP 0x0008 714 #define ASC_IERR_IRQ_NO 0x0010 715 #define ASC_IERR_SET_IRQ_NO 0x0020 716 #define ASC_IERR_CHIP_VERSION 0x0040 717 #define ASC_IERR_SET_SCSI_ID 0x0080 718 #define ASC_IERR_GET_PHY_ADDR 0x0100 719 #define ASC_IERR_BAD_SIGNATURE 0x0200 720 #define ASC_IERR_NO_BUS_TYPE 0x0400 721 #define ASC_IERR_SCAM 0x0800 722 #define ASC_IERR_SET_SDTR 0x1000 723 #define ASC_IERR_RW_LRAM 0x8000 724 725 #define ASC_DEF_IRQ_NO 10 726 #define ASC_MAX_IRQ_NO 15 727 #define ASC_MIN_IRQ_NO 10 728 #define ASC_MIN_REMAIN_Q 0x02 729 #define ASC_DEF_MAX_TOTAL_QNG 0xF0 730 #define ASC_MIN_TAG_Q_PER_DVC 0x04 731 #define ASC_DEF_TAG_Q_PER_DVC 0x04 732 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q 733 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 734 #define ASC_MAX_TOTAL_QNG 240 735 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 736 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 737 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 738 #define ASC_MAX_INRAM_TAG_QNG 16 739 #define ASC_IOADR_TABLE_MAX_IX 11 740 #define ASC_IOADR_GAP 0x10 741 #define ASC_SEARCH_IOP_GAP 0x10 742 #define ASC_MIN_IOP_ADDR 0x0100 743 #define ASC_MAX_IOP_ADDR 0x03F0 744 745 #define ASC_IOADR_1 0x0110 746 #define ASC_IOADR_2 0x0130 747 #define ASC_IOADR_3 0x0150 748 #define ASC_IOADR_4 0x0190 749 #define ASC_IOADR_5 0x0210 750 #define ASC_IOADR_6 0x0230 751 #define ASC_IOADR_7 0x0250 752 #define ASC_IOADR_8 0x0330 753 754 #define ASC_IOADR_DEF ASC_IOADR_8 755 #define ASC_LIB_SCSIQ_WK_SP 256 756 #define ASC_MAX_SYN_XFER_NO 16 757 #define ASC_SYN_MAX_OFFSET 0x0F 758 #define ASC_DEF_SDTR_OFFSET 0x0F 759 #define ASC_DEF_SDTR_INDEX 0x00 760 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 761 762 763 /* 764 * This structure is used to handle internal messages 765 * during interrupt handling routine 766 */ 767 typedef struct ext_msg 768 { 769 u_int8_t msg_type; 770 u_int8_t msg_len; 771 u_int8_t msg_req; 772 773 union 774 { 775 struct 776 { 777 u_int8_t sdtr_xfer_period; 778 u_int8_t sdtr_req_ack_offset; 779 } sdtr; 780 781 struct 782 { 783 u_int8_t wdtr_width; 784 } wdtr; 785 786 struct 787 { 788 u_int8_t mdp_b3; 789 u_int8_t mdp_b2; 790 u_int8_t mdp_b1; 791 u_int8_t mdp_b0; 792 } mdp; 793 } u_ext_msg; 794 795 u_int8_t res; 796 } EXT_MSG; 797 798 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 799 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 800 #define wdtr_width u_ext_msg.wdtr.wdtr_width 801 #define mdp_b3 u_ext_msg.mdp_b3 802 #define mdp_b2 u_ext_msg.mdp_b2 803 #define mdp_b1 u_ext_msg.mdp_b1 804 #define mdp_b0 u_ext_msg.mdp_b0 805 806 807 #define ASC_DEF_DVC_CNTL 0xFFFF 808 #define ASC_DEF_CHIP_SCSI_ID 7 809 #define ASC_DEF_ISA_DMA_SPEED 4 810 811 #define ASC_PCI_DEVICE_ID_REV_A 0x1100 812 #define ASC_PCI_DEVICE_ID_REV_B 0x1200 813 814 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 815 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 816 817 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 818 819 #define ASC_MIN_TAGGED_CMD 7 820 821 #define ASC_MAX_SCSI_RESET_WAIT 30 822 823 824 typedef struct asc_softc 825 { 826 struct device sc_dev; 827 828 bus_space_tag_t sc_iot; 829 bus_space_handle_t sc_ioh; 830 bus_dma_tag_t sc_dmat; 831 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 832 void *sc_ih; 833 834 struct adv_control *sc_control; /* control structures */ 835 TAILQ_HEAD(, adv_ccb) sc_free_ccb, sc_waiting_ccb; 836 struct scsipi_link sc_link; /* prototype for devs */ 837 838 LIST_HEAD(, scsipi_xfer) sc_queue; 839 struct scsipi_xfer *sc_queuelast; 840 841 u_int8_t *overrun_buf; 842 843 u_int16_t sc_flags; /* see below sc_flags values */ 844 845 u_int16_t dvc_cntl; 846 u_int16_t bug_fix_cntl; 847 u_int16_t bus_type; 848 849 ulong isr_callback; 850 851 ASC_SCSI_BIT_ID_TYPE init_sdtr; 852 ASC_SCSI_BIT_ID_TYPE sdtr_done; 853 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 854 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 855 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 856 ASC_SCSI_BIT_ID_TYPE start_motor; 857 858 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 859 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 860 ASC_SCSI_BIT_ID_TYPE disc_enable; 861 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 862 u_int8_t chip_scsi_id; 863 u_int8_t isa_dma_speed; 864 u_int8_t isa_dma_channel; 865 u_int8_t chip_version; 866 u_int16_t pci_device_id; 867 u_int16_t lib_serial_no; 868 u_int16_t lib_version; 869 u_int16_t mcode_date; 870 u_int16_t mcode_version; 871 u_int8_t max_tag_qng[ASC_MAX_TID + 1]; 872 u_int8_t sdtr_period_offset[ASC_MAX_TID + 1]; 873 u_int8_t adapter_info[6]; 874 875 u_int8_t scsi_reset_wait; 876 u_int8_t max_total_qng; 877 u_int8_t cur_total_qng; 878 u_int8_t irq_no; 879 u_int8_t last_q_shortage; 880 881 u_int8_t cur_dvc_qng[ASC_MAX_TID + 1]; 882 u_int8_t max_dvc_qng[ASC_MAX_TID + 1]; 883 u_int8_t sdtr_period_tbl[ASC_MAX_SYN_XFER_NO]; 884 u_int8_t sdtr_period_tbl_size; /* see below */ 885 u_int8_t sdtr_data[ASC_MAX_TID+1]; 886 887 u_int16_t reqcnt[ASC_MAX_TID+1]; /* Starvation request count */ 888 889 u_int32_t max_dma_count; 890 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 891 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 892 u_int8_t max_sdtr_index; 893 u_int8_t host_init_sdtr_index; 894 } ASC_SOFTC; 895 896 /* sc_flags values */ 897 #define ASC_HOST_IN_RESET 0x01 898 #define ASC_HOST_IN_ABORT 0x02 899 #define ASC_WIDE_BOARD 0x04 900 #define ASC_SELECT_QUEUE_DEPTHS 0x08 901 902 /* sdtr_period_tbl_size values */ 903 #define SYN_XFER_NS_0 25 904 #define SYN_XFER_NS_1 30 905 #define SYN_XFER_NS_2 35 906 #define SYN_XFER_NS_3 40 907 #define SYN_XFER_NS_4 50 908 #define SYN_XFER_NS_5 60 909 #define SYN_XFER_NS_6 70 910 #define SYN_XFER_NS_7 85 911 912 #define SYN_ULTRA_XFER_NS_0 12 913 #define SYN_ULTRA_XFER_NS_1 19 914 #define SYN_ULTRA_XFER_NS_2 25 915 #define SYN_ULTRA_XFER_NS_3 32 916 #define SYN_ULTRA_XFER_NS_4 38 917 #define SYN_ULTRA_XFER_NS_5 44 918 #define SYN_ULTRA_XFER_NS_6 50 919 #define SYN_ULTRA_XFER_NS_7 57 920 #define SYN_ULTRA_XFER_NS_8 63 921 #define SYN_ULTRA_XFER_NS_9 69 922 #define SYN_ULTRA_XFER_NS_10 75 923 #define SYN_ULTRA_XFER_NS_11 82 924 #define SYN_ULTRA_XFER_NS_12 88 925 #define SYN_ULTRA_XFER_NS_13 94 926 #define SYN_ULTRA_XFER_NS_14 100 927 #define SYN_ULTRA_XFER_NS_15 107 928 929 930 /* second level interrupt callback type definition */ 931 typedef int (* ASC_ISR_CALLBACK) (ASC_SOFTC *, ASC_QDONE_INFO *); 932 933 934 #define ASC_MCNTL_NO_SEL_TIMEOUT 0x0001 935 #define ASC_MCNTL_NULL_TARGET 0x0002 936 937 #define ASC_CNTL_INITIATOR 0x0001 938 #define ASC_CNTL_BIOS_GT_1GB 0x0002 939 #define ASC_CNTL_BIOS_GT_2_DISK 0x0004 940 #define ASC_CNTL_BIOS_REMOVABLE 0x0008 941 #define ASC_CNTL_NO_SCAM 0x0010 942 #define ASC_CNTL_INT_MULTI_Q 0x0080 943 #define ASC_CNTL_NO_LUN_SUPPORT 0x0040 944 #define ASC_CNTL_NO_VERIFY_COPY 0x0100 945 #define ASC_CNTL_RESET_SCSI 0x0200 946 #define ASC_CNTL_INIT_INQUIRY 0x0400 947 #define ASC_CNTL_INIT_VERBOSE 0x0800 948 #define ASC_CNTL_SCSI_PARITY 0x1000 949 #define ASC_CNTL_BURST_MODE 0x2000 950 #define ASC_CNTL_SDTR_ENABLE_ULTRA 0x4000 951 952 #define ASC_EEP_DVC_CFG_BEG_VL 2 953 #define ASC_EEP_MAX_DVC_ADDR_VL 15 954 #define ASC_EEP_DVC_CFG_BEG 32 955 #define ASC_EEP_MAX_DVC_ADDR 45 956 #define ASC_EEP_DEFINED_WORDS 10 957 #define ASC_EEP_MAX_ADDR 63 958 #define ASC_EEP_RES_WORDS 0 959 #define ASC_EEP_MAX_RETRY 20 960 #define ASC_MAX_INIT_BUSY_RETRY 8 961 #define ASC_EEP_ISA_PNP_WSIZE 16 962 963 964 /* 965 * This structure is used to read/write EEProm configuration 966 */ 967 typedef struct asceep_config 968 { 969 u_int16_t cfg_lsw; 970 u_int16_t cfg_msw; 971 u_int8_t init_sdtr; 972 u_int8_t disc_enable; 973 u_int8_t use_cmd_qng; 974 u_int8_t start_motor; 975 u_int8_t max_total_qng; 976 u_int8_t max_tag_qng; 977 u_int8_t bios_scan; 978 u_int8_t power_up_wait; 979 u_int8_t no_scam; 980 u_int8_t chip_scsi_id:4; 981 u_int8_t isa_dma_speed:4; 982 u_int8_t dos_int13_table[ASC_MAX_TID + 1]; 983 u_int8_t adapter_info[6]; 984 u_int16_t cntl; 985 u_int16_t chksum; 986 } ASCEEP_CONFIG; 987 988 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800 989 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080 990 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020 991 992 #define ASC_EEP_CMD_READ 0x80 993 #define ASC_EEP_CMD_WRITE 0x40 994 #define ASC_EEP_CMD_WRITE_ABLE 0x30 995 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 996 997 #define ASC_OVERRUN_BSIZE 0x00000048UL 998 999 #define ASC_CTRL_BREAK_ONCE 0x0001 1000 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002 1001 1002 #define ASCV_MSGOUT_BEG 0x0000 1003 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 1004 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 1005 #define ASCV_BREAK_SAVED_CODE 0x0006 1006 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 1007 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 1008 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 1009 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 1010 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 1011 #define ASCV_MAX_DVC_QNG_BEG 0x0020 1012 #define ASCV_BREAK_ADDR 0x0028 1013 #define ASCV_BREAK_NOTIFY_COUNT 0x002A 1014 #define ASCV_BREAK_CONTROL 0x002C 1015 #define ASCV_BREAK_HIT_COUNT 0x002E 1016 1017 #define ASCV_ASCDVC_ERR_CODE_W 0x0030 1018 #define ASCV_MCODE_CHKSUM_W 0x0032 1019 #define ASCV_MCODE_SIZE_W 0x0034 1020 #define ASCV_STOP_CODE_B 0x0036 1021 #define ASCV_DVC_ERR_CODE_B 0x0037 1022 #define ASCV_OVERRUN_PADDR_D 0x0038 1023 #define ASCV_OVERRUN_BSIZE_D 0x003C 1024 #define ASCV_HALTCODE_W 0x0040 1025 #define ASCV_CHKSUM_W 0x0042 1026 #define ASCV_MC_DATE_W 0x0044 1027 #define ASCV_MC_VER_W 0x0046 1028 #define ASCV_NEXTRDY_B 0x0048 1029 #define ASCV_DONENEXT_B 0x0049 1030 #define ASCV_USE_TAGGED_QNG_B 0x004A 1031 #define ASCV_SCSIBUSY_B 0x004B 1032 #define ASCV_Q_DONE_IN_PROGRESS_B 0x004C 1033 #define ASCV_CURCDB_B 0x004D 1034 #define ASCV_RCLUN_B 0x004E 1035 #define ASCV_BUSY_QHEAD_B 0x004F 1036 #define ASCV_DISC1_QHEAD_B 0x0050 1037 #define ASCV_DISC_ENABLE_B 0x0052 1038 #define ASCV_CAN_TAGGED_QNG_B 0x0053 1039 #define ASCV_HOSTSCSI_ID_B 0x0055 1040 #define ASCV_MCODE_CNTL_B 0x0056 1041 #define ASCV_NULL_TARGET_B 0x0057 1042 #define ASCV_FREE_Q_HEAD_W 0x0058 1043 #define ASCV_DONE_Q_TAIL_W 0x005A 1044 #define ASCV_FREE_Q_HEAD_B (ASCV_FREE_Q_HEAD_W+1) 1045 #define ASCV_DONE_Q_TAIL_B (ASCV_DONE_Q_TAIL_W+1) 1046 #define ASCV_HOST_FLAG_B 0x005D 1047 #define ASCV_TOTAL_READY_Q_B 0x0064 1048 #define ASCV_VER_SERIAL_B 0x0065 1049 #define ASCV_HALTCODE_SAVED_W 0x0066 1050 #define ASCV_WTM_FLAG_B 0x0068 1051 #define ASCV_RISC_FLAG_B 0x006A 1052 #define ASCV_REQ_SG_LIST_QP 0x006B 1053 1054 #define ASC_HOST_FLAG_IN_ISR 0x01 1055 #define ASC_HOST_FLAG_ACK_INT 0x02 1056 #define ASC_RISC_FLAG_GEN_INT 0x01 1057 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 1058 1059 #define ASC_IOP_CTRL 0x0F 1060 #define ASC_IOP_STATUS 0x0E 1061 #define ASC_IOP_INT_ACK ASC_IOP_STATUS 1062 #define ASC_IOP_REG_IFC 0x0D 1063 #define ASC_IOP_SYN_OFFSET 0x0B 1064 #define ASC_IOP_EXTRA_CONTROL 0x0D 1065 #define ASC_IOP_REG_PC 0x0C 1066 #define ASC_IOP_RAM_ADDR 0x0A 1067 #define ASC_IOP_RAM_DATA 0x08 1068 #define ASC_IOP_EEP_DATA 0x06 1069 #define ASC_IOP_EEP_CMD 0x07 1070 #define ASC_IOP_VERSION 0x03 1071 #define ASC_IOP_CONFIG_HIGH 0x04 1072 #define ASC_IOP_CONFIG_LOW 0x02 1073 #define ASC_IOP_SIG_BYTE 0x01 1074 #define ASC_IOP_SIG_WORD 0x00 1075 #define ASC_IOP_REG_DC1 0x0E 1076 #define ASC_IOP_REG_DC0 0x0C 1077 #define ASC_IOP_REG_SB 0x0B 1078 #define ASC_IOP_REG_DA1 0x0A 1079 #define ASC_IOP_REG_DA0 0x08 1080 #define ASC_IOP_REG_SC 0x09 1081 #define ASC_IOP_DMA_SPEED 0x07 1082 #define ASC_IOP_REG_FLAG 0x07 1083 #define ASC_IOP_FIFO_H 0x06 1084 #define ASC_IOP_FIFO_L 0x04 1085 #define ASC_IOP_REG_ID 0x05 1086 #define ASC_IOP_REG_QP 0x03 1087 #define ASC_IOP_REG_IH 0x02 1088 #define ASC_IOP_REG_IX 0x01 1089 #define ASC_IOP_REG_AX 0x00 1090 1091 #define ASC_IFC_REG_LOCK 0x00 1092 #define ASC_IFC_REG_UNLOCK 0x09 1093 #define ASC_IFC_WR_EN_FILTER 0x10 1094 #define ASC_IFC_RD_NO_EEPROM 0x10 1095 #define ASC_IFC_SLEW_RATE 0x20 1096 #define ASC_IFC_ACT_NEG 0x40 1097 #define ASC_IFC_INP_FILTER 0x80 1098 #define ASC_IFC_INIT_DEFAULT (ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK) 1099 1100 #define SC_SEL 0x80 1101 #define SC_BSY 0x40 1102 #define SC_ACK 0x20 1103 #define SC_REQ 0x10 1104 #define SC_ATN 0x08 1105 #define SC_IO 0x04 1106 #define SC_CD 0x02 1107 #define SC_MSG 0x01 1108 1109 #define SEC_SCSI_CTL 0x80 1110 #define SEC_ACTIVE_NEGATE 0x40 1111 #define SEC_SLEW_RATE 0x20 1112 #define SEC_ENABLE_FILTER 0x10 1113 1114 #define ASC_HALT_EXTMSG_IN 0x8000 1115 #define ASC_HALT_CHK_CONDITION 0x8100 1116 #define ASC_HALT_SS_QUEUE_FULL 0x8200 1117 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 1118 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 1119 #define ASC_HALT_SDTR_REJECTED 0x4000 1120 1121 #define ASC_MAX_QNO 0xF8 1122 1123 #define ASC_DATA_SEC_BEG 0x0080 1124 #define ASC_DATA_SEC_END 0x0080 1125 #define ASC_CODE_SEC_BEG 0x0080 1126 #define ASC_CODE_SEC_END 0x0080 1127 #define ASC_QADR_BEG (0x4000) 1128 #define ASC_QADR_USED (ASC_MAX_QNO * 64) 1129 #define ASC_QADR_END 0x7FFF 1130 #define ASC_QLAST_ADR 0x7FC0 1131 #define ASC_QBLK_SIZE 0x40 1132 #define ASC_BIOS_DATA_QBEG 0xF8 1133 #define ASC_MIN_ACTIVE_QNO 0x01 1134 #define ASC_QLINK_END 0xFF 1135 #define ASC_EEPROM_WORDS 0x10 1136 #define ASC_MAX_MGS_LEN 0x10 1137 1138 #define ASC_BIOS_ADDR_DEF 0xDC00 1139 #define ASC_BIOS_SIZE 0x3800 1140 #define ASC_BIOS_RAM_OFF 0x3800 1141 #define ASC_BIOS_RAM_SIZE 0x800 1142 #define ASC_BIOS_MIN_ADDR 0xC000 1143 #define ASC_BIOS_MAX_ADDR 0xEC00 1144 #define ASC_BIOS_BANK_SIZE 0x0400 1145 1146 #define ASC_MCODE_START_ADDR 0x0080 1147 1148 #define ASC_CFG0_HOST_INT_ON 0x0020 1149 #define ASC_CFG0_BIOS_ON 0x0040 1150 #define ASC_CFG0_VERA_BURST_ON 0x0080 1151 #define ASC_CFG0_SCSI_PARITY_ON 0x0800 1152 #define ASC_CFG1_SCSI_TARGET_ON 0x0080 1153 #define ASC_CFG1_LRAM_8BITS_ON 0x0800 1154 #define ASC_CFG_MSW_CLR_MASK 0x3080 1155 1156 #define ASC_CSW_TEST1 0x8000 1157 #define ASC_CSW_AUTO_CONFIG 0x4000 1158 #define ASC_CSW_RESERVED1 0x2000 1159 #define ASC_CSW_IRQ_WRITTEN 0x1000 1160 #define ASC_CSW_33MHZ_SELECTED 0x0800 1161 #define ASC_CSW_TEST2 0x0400 1162 #define ASC_CSW_TEST3 0x0200 1163 #define ASC_CSW_RESERVED2 0x0100 1164 #define ASC_CSW_DMA_DONE 0x0080 1165 #define ASC_CSW_FIFO_RDY 0x0040 1166 #define ASC_CSW_EEP_READ_DONE 0x0020 1167 #define ASC_CSW_HALTED 0x0010 1168 #define ASC_CSW_SCSI_RESET_ACTIVE 0x0008 1169 #define ASC_CSW_PARITY_ERR 0x0004 1170 #define ASC_CSW_SCSI_RESET_LATCH 0x0002 1171 #define ASC_CSW_INT_PENDING 0x0001 1172 1173 #define ASC_CIW_CLR_SCSI_RESET_INT 0x1000 1174 #define ASC_CIW_INT_ACK 0x0100 1175 #define ASC_CIW_TEST1 0x0200 1176 #define ASC_CIW_TEST2 0x0400 1177 #define ASC_CIW_SEL_33MHZ 0x0800 1178 #define ASC_CIW_IRQ_ACT 0x1000 1179 1180 #define ASC_CC_CHIP_RESET 0x80 1181 #define ASC_CC_SCSI_RESET 0x40 1182 #define ASC_CC_HALT 0x20 1183 #define ASC_CC_SINGLE_STEP 0x10 1184 #define ASC_CC_DMA_ABLE 0x08 1185 #define ASC_CC_TEST 0x04 1186 #define ASC_CC_BANK_ONE 0x02 1187 #define ASC_CC_DIAG 0x01 1188 1189 #define ASC_1000_ID0W 0x04C1 1190 #define ASC_1000_ID0W_FIX 0x00C1 1191 #define ASC_1000_ID1B 0x25 1192 1193 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50) 1194 #define ASC_EISA_SMALL_IOP_GAP (0x0020) 1195 #define ASC_EISA_MIN_IOP_ADDR (0x0C30) 1196 #define ASC_EISA_MAX_IOP_ADDR (0xFC50) 1197 #define ASC_EISA_REV_IOP_MASK (0x0C83) 1198 #define ASC_EISA_PID_IOP_MASK (0x0C80) 1199 #define ASC_EISA_CFG_IOP_MASK (0x0C86) 1200 1201 #define ASC_GET_EISA_SLOT(iop) ((iop) & 0xF000) 1202 1203 #define ASC_EISA_ID_740 0x01745004UL 1204 #define ASC_EISA_ID_750 0x01755004UL 1205 1206 #define ASC_INS_HALTINT 0x6281 1207 #define ASC_INS_HALT 0x6280 1208 #define ASC_INS_SINT 0x6200 1209 #define ASC_INS_RFLAG_WTM 0x7380 1210 1211 1212 /******************************************************************************/ 1213 /* Macro */ 1214 /******************************************************************************/ 1215 1216 /* 1217 * These Macros are used to deal with board CPU Registers and LRAM 1218 */ 1219 1220 #define ASC_GET_QDONE_IN_PROGRESS(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B) 1221 #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val) 1222 #define ASC_GET_VAR_FREE_QHEAD(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W) 1223 #define ASC_GET_VAR_DONE_QTAIL(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W) 1224 #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val) 1225 #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val) 1226 #define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B) 1227 #define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B) 1228 #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val) 1229 #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val) 1230 #define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ; 1231 #define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ; 1232 #define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ; 1233 #define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ; 1234 #define ASC_SYN_INDEX_TO_PERIOD(sc, index) (u_int8_t)((sc)->sdtr_period_tbl[ (index) ]) 1235 #define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE) 1236 #define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD) 1237 #define ASC_GET_CHIP_VER_NO(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_VERSION) 1238 #define ASC_GET_CHIP_CFG_LSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW) 1239 #define ASC_GET_CHIP_CFG_MSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH) 1240 #define ASC_SET_CHIP_CFG_LSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data) 1241 #define ASC_SET_CHIP_CFG_MSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data) 1242 #define ASC_GET_CHIP_EEP_CMD(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD) 1243 #define ASC_SET_CHIP_EEP_CMD(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data) 1244 #define ASC_GET_CHIP_EEP_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA) 1245 #define ASC_SET_CHIP_EEP_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data) 1246 #define ASC_GET_CHIP_LRAM_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR) 1247 #define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr) 1248 #define ASC_GET_CHIP_LRAM_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA) 1249 #define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data) 1250 #if BYTE_ORDER == BIG_ENDIAN 1251 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) swap_bytes(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)) 1252 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, swap_bytes(data)) 1253 #else 1254 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA) 1255 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data) 1256 #endif 1257 #define ASC_GET_CHIP_IFC(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC) 1258 #define ASC_SET_CHIP_IFC(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data) 1259 #define ASC_GET_CHIP_STATUS(iot, ioh) (u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS) 1260 #define ASC_SET_CHIP_STATUS(iot, ioh, cs_val) bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val) 1261 #define ASC_GET_CHIP_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_CTRL) 1262 #define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val) bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val) 1263 #define ASC_GET_CHIP_SYN(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET) 1264 #define ASC_SET_CHIP_SYN(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data) 1265 #define ASC_SET_PC_ADDR(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data) 1266 #define ASC_GET_PC_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC) 1267 #define ASC_IS_INT_PENDING(iot, ioh) (ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH)) 1268 #define ASC_GET_CHIP_SCSI_ID(iot, ioh) ((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID) 1269 #define ASC_GET_EXTRA_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL) 1270 #define ASC_SET_EXTRA_CONTROL(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data) 1271 #define ASC_READ_CHIP_AX(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX) 1272 #define ASC_WRITE_CHIP_AX(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data) 1273 #define ASC_READ_CHIP_IX(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX) 1274 #define ASC_WRITE_CHIP_IX(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data) 1275 #define ASC_READ_CHIP_IH(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH) 1276 #define ASC_WRITE_CHIP_IH(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data) 1277 #define ASC_READ_CHIP_QP(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP) 1278 #define ASC_WRITE_CHIP_QP(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data) 1279 #define ASC_READ_CHIP_FIFO_L(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L) 1280 #define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data) 1281 #define ASC_READ_CHIP_FIFO_H(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H) 1282 #define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data) 1283 #define ASC_READ_CHIP_DMA_SPEED(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED) 1284 #define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data) 1285 #define ASC_READ_CHIP_DA0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0) 1286 #define ASC_WRITE_CHIP_DA0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data) 1287 #define ASC_READ_CHIP_DA1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1) 1288 #define ASC_WRITE_CHIP_DA1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data) 1289 #define ASC_READ_CHIP_DC0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0) 1290 #define ASC_WRITE_CHIP_DC0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data) 1291 #define ASC_READ_CHIP_DC1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1) 1292 #define ASC_WRITE_CHIP_DC1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data) 1293 #define ASC_READ_CHIP_DVC_ID(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID) 1294 #define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data) 1295 1296 1297 /******************************************************************************/ 1298 /* Exported functions */ 1299 /******************************************************************************/ 1300 1301 1302 void AscInitASC_SOFTC __P((ASC_SOFTC *)); 1303 u_int16_t AscInitFromEEP __P((ASC_SOFTC *)); 1304 u_int16_t AscInitFromASC_SOFTC __P((ASC_SOFTC *)); 1305 int AscInitDriver __P((ASC_SOFTC *)); 1306 void AscReInitLram __P((ASC_SOFTC *)); 1307 int AscFindSignature __P((bus_space_tag_t, bus_space_handle_t)); 1308 int AscISR __P((ASC_SOFTC *)); 1309 int AscExeScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *)); 1310 void AscInquiryHandling __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 1311 int AscAbortCCB __P((ASC_SOFTC *, u_int32_t)); 1312 int AscResetBus __P((ASC_SOFTC *)); 1313 int AscResetDevice __P((ASC_SOFTC *, u_char)); 1314 1315 1316 /******************************************************************************/ 1317 #endif /* _ADVANSYS_LIBRARY_H_ */ 1318
Indexes created Tue Sep 23 07:09:52 GMT 2025