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adw.c revision 1.12.2.1
      1  1.12.2.1  thorpej /* $NetBSD: adw.c,v 1.12.2.1 1999/10/19 17:47:30 thorpej Exp $	 */
      2       1.1    dante 
      3       1.1    dante /*
      4       1.1    dante  * Generic driver for the Advanced Systems Inc. SCSI controllers
      5       1.1    dante  *
      6       1.1    dante  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      7       1.1    dante  * All rights reserved.
      8       1.1    dante  *
      9       1.1    dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10       1.1    dante  *
     11       1.1    dante  * Redistribution and use in source and binary forms, with or without
     12       1.1    dante  * modification, are permitted provided that the following conditions
     13       1.1    dante  * are met:
     14       1.1    dante  * 1. Redistributions of source code must retain the above copyright
     15       1.1    dante  *    notice, this list of conditions and the following disclaimer.
     16       1.1    dante  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1    dante  *    notice, this list of conditions and the following disclaimer in the
     18       1.1    dante  *    documentation and/or other materials provided with the distribution.
     19       1.1    dante  * 3. All advertising materials mentioning features or use of this software
     20       1.1    dante  *    must display the following acknowledgement:
     21       1.1    dante  *        This product includes software developed by the NetBSD
     22       1.1    dante  *        Foundation, Inc. and its contributors.
     23       1.1    dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24       1.1    dante  *    contributors may be used to endorse or promote products derived
     25       1.1    dante  *    from this software without specific prior written permission.
     26       1.1    dante  *
     27       1.1    dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28       1.1    dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29       1.1    dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30       1.1    dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31       1.1    dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32       1.1    dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33       1.1    dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34       1.1    dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35       1.1    dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36       1.1    dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37       1.1    dante  * POSSIBILITY OF SUCH DAMAGE.
     38       1.1    dante  */
     39       1.1    dante 
     40       1.1    dante #include <sys/types.h>
     41       1.1    dante #include <sys/param.h>
     42       1.1    dante #include <sys/systm.h>
     43       1.1    dante #include <sys/kernel.h>
     44       1.1    dante #include <sys/errno.h>
     45       1.1    dante #include <sys/ioctl.h>
     46       1.1    dante #include <sys/device.h>
     47       1.1    dante #include <sys/malloc.h>
     48       1.1    dante #include <sys/buf.h>
     49       1.1    dante #include <sys/proc.h>
     50       1.1    dante #include <sys/user.h>
     51       1.1    dante 
     52       1.1    dante #include <machine/bus.h>
     53       1.1    dante #include <machine/intr.h>
     54       1.1    dante 
     55       1.1    dante #include <vm/vm.h>
     56       1.1    dante #include <vm/vm_param.h>
     57       1.1    dante #include <vm/pmap.h>
     58       1.1    dante 
     59       1.1    dante #include <dev/scsipi/scsi_all.h>
     60       1.1    dante #include <dev/scsipi/scsipi_all.h>
     61       1.1    dante #include <dev/scsipi/scsiconf.h>
     62       1.1    dante 
     63       1.1    dante #include <dev/ic/adwlib.h>
     64       1.1    dante #include <dev/ic/adw.h>
     65       1.1    dante 
     66       1.1    dante #ifndef DDB
     67      1.11    dante #define	Debugger()	panic("should call debugger here (adw.c)")
     68       1.2    dante #endif				/* ! DDB */
     69       1.1    dante 
     70       1.1    dante /******************************************************************************/
     71       1.1    dante 
     72       1.1    dante 
     73       1.1    dante static int adw_alloc_ccbs __P((ADW_SOFTC *));
     74       1.1    dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
     75       1.1    dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
     76       1.1    dante static void adw_reset_ccb __P((ADW_CCB *));
     77       1.1    dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
     78       1.1    dante static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int));
     79       1.1    dante static void adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *));
     80       1.1    dante static void adw_start_ccbs __P((ADW_SOFTC *));
     81       1.1    dante 
     82  1.12.2.1  thorpej static void adw_scsipi_request __P((struct scsipi_channel *,
     83  1.12.2.1  thorpej 	scsipi_adapter_req_t, void *));
     84  1.12.2.1  thorpej static int adw_build_req __P((ADW_SOFTC *, ADW_CCB *));
     85       1.7    dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *));
     86       1.1    dante static void adwminphys __P((struct buf *));
     87       1.1    dante static void adw_wide_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
     88      1.11    dante static void adw_sbreset_callback __P((ADW_SOFTC *));
     89       1.1    dante 
     90       1.1    dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
     91       1.1    dante static void adw_timeout __P((void *));
     92       1.1    dante 
     93       1.1    dante 
     94       1.1    dante /******************************************************************************/
     95       1.1    dante 
     96       1.1    dante #define ADW_ABORT_TIMEOUT       10000	/* time to wait for abort (mSec) */
     97       1.1    dante #define ADW_WATCH_TIMEOUT       10000	/* time to wait for watchdog (mSec) */
     98       1.1    dante 
     99       1.1    dante /******************************************************************************/
    100       1.7    dante /*                                Control Blocks routines                     */
    101       1.1    dante /******************************************************************************/
    102       1.1    dante 
    103       1.1    dante 
    104       1.1    dante static int
    105       1.1    dante adw_alloc_ccbs(sc)
    106       1.1    dante 	ADW_SOFTC      *sc;
    107       1.1    dante {
    108       1.1    dante 	bus_dma_segment_t seg;
    109       1.1    dante 	int             error, rseg;
    110       1.1    dante 
    111       1.1    dante 	/*
    112       1.1    dante          * Allocate the control blocks.
    113       1.1    dante          */
    114       1.1    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
    115       1.1    dante 			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    116       1.1    dante 		printf("%s: unable to allocate control structures,"
    117       1.1    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    118       1.1    dante 		return (error);
    119       1.1    dante 	}
    120       1.1    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    121       1.1    dante 		   sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
    122       1.1    dante 				 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    123       1.1    dante 		printf("%s: unable to map control structures, error = %d\n",
    124       1.1    dante 		       sc->sc_dev.dv_xname, error);
    125       1.1    dante 		return (error);
    126       1.1    dante 	}
    127       1.1    dante 	/*
    128       1.1    dante          * Create and load the DMA map used for the control blocks.
    129       1.1    dante          */
    130       1.1    dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
    131       1.1    dante 			   1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
    132       1.1    dante 				       &sc->sc_dmamap_control)) != 0) {
    133       1.1    dante 		printf("%s: unable to create control DMA map, error = %d\n",
    134       1.1    dante 		       sc->sc_dev.dv_xname, error);
    135       1.1    dante 		return (error);
    136       1.1    dante 	}
    137       1.1    dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    138       1.1    dante 			   sc->sc_control, sizeof(struct adw_control), NULL,
    139       1.1    dante 				     BUS_DMA_NOWAIT)) != 0) {
    140       1.1    dante 		printf("%s: unable to load control DMA map, error = %d\n",
    141       1.1    dante 		       sc->sc_dev.dv_xname, error);
    142       1.1    dante 		return (error);
    143       1.1    dante 	}
    144       1.1    dante 	return (0);
    145       1.1    dante }
    146       1.1    dante 
    147       1.1    dante 
    148       1.1    dante /*
    149       1.1    dante  * Create a set of ccbs and add them to the free list.  Called once
    150       1.1    dante  * by adw_init().  We return the number of CCBs successfully created.
    151       1.1    dante  */
    152       1.1    dante static int
    153       1.1    dante adw_create_ccbs(sc, ccbstore, count)
    154       1.1    dante 	ADW_SOFTC      *sc;
    155       1.1    dante 	ADW_CCB        *ccbstore;
    156       1.1    dante 	int             count;
    157       1.1    dante {
    158       1.1    dante 	ADW_CCB        *ccb;
    159       1.1    dante 	int             i, error;
    160       1.1    dante 
    161       1.1    dante 	bzero(ccbstore, sizeof(ADW_CCB) * count);
    162       1.1    dante 	for (i = 0; i < count; i++) {
    163       1.1    dante 		ccb = &ccbstore[i];
    164       1.1    dante 		if ((error = adw_init_ccb(sc, ccb)) != 0) {
    165       1.1    dante 			printf("%s: unable to initialize ccb, error = %d\n",
    166       1.1    dante 			       sc->sc_dev.dv_xname, error);
    167       1.1    dante 			return (i);
    168       1.1    dante 		}
    169       1.1    dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    170       1.1    dante 	}
    171       1.1    dante 
    172       1.1    dante 	return (i);
    173       1.1    dante }
    174       1.1    dante 
    175       1.1    dante 
    176       1.1    dante /*
    177       1.1    dante  * A ccb is put onto the free list.
    178       1.1    dante  */
    179       1.1    dante static void
    180       1.1    dante adw_free_ccb(sc, ccb)
    181       1.1    dante 	ADW_SOFTC      *sc;
    182       1.1    dante 	ADW_CCB        *ccb;
    183       1.1    dante {
    184       1.1    dante 	int             s;
    185       1.1    dante 
    186       1.1    dante 	s = splbio();
    187       1.1    dante 
    188       1.1    dante 	adw_reset_ccb(ccb);
    189       1.1    dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    190       1.1    dante 
    191       1.1    dante 	/*
    192       1.1    dante          * If there were none, wake anybody waiting for one to come free,
    193       1.1    dante          * starting with queued entries.
    194       1.1    dante          */
    195       1.1    dante 	if (ccb->chain.tqe_next == 0)
    196       1.1    dante 		wakeup(&sc->sc_free_ccb);
    197       1.1    dante 
    198       1.1    dante 	splx(s);
    199       1.1    dante }
    200       1.1    dante 
    201       1.1    dante 
    202       1.1    dante static void
    203       1.1    dante adw_reset_ccb(ccb)
    204       1.1    dante 	ADW_CCB        *ccb;
    205       1.1    dante {
    206       1.1    dante 
    207       1.1    dante 	ccb->flags = 0;
    208       1.1    dante }
    209       1.1    dante 
    210       1.1    dante 
    211       1.1    dante static int
    212       1.1    dante adw_init_ccb(sc, ccb)
    213       1.1    dante 	ADW_SOFTC      *sc;
    214       1.1    dante 	ADW_CCB        *ccb;
    215       1.1    dante {
    216       1.7    dante 	int	hashnum, error;
    217       1.1    dante 
    218       1.1    dante 	/*
    219       1.1    dante          * Create the DMA map for this CCB.
    220       1.1    dante          */
    221       1.1    dante 	error = bus_dmamap_create(sc->sc_dmat,
    222       1.1    dante 				  (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    223       1.1    dante 			 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    224       1.1    dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    225       1.1    dante 	if (error) {
    226       1.1    dante 		printf("%s: unable to create DMA map, error = %d\n",
    227       1.1    dante 		       sc->sc_dev.dv_xname, error);
    228       1.1    dante 		return (error);
    229       1.1    dante 	}
    230       1.7    dante 
    231       1.7    dante 	/*
    232       1.7    dante 	 * put in the phystokv hash table
    233       1.7    dante 	 * Never gets taken out.
    234       1.7    dante 	 */
    235       1.7    dante 	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    236       1.7    dante 	    ADW_CCB_OFF(ccb);
    237       1.7    dante 	hashnum = CCB_HASH(ccb->hashkey);
    238       1.7    dante 	ccb->nexthash = sc->sc_ccbhash[hashnum];
    239       1.7    dante 	sc->sc_ccbhash[hashnum] = ccb;
    240       1.1    dante 	adw_reset_ccb(ccb);
    241       1.1    dante 	return (0);
    242       1.1    dante }
    243       1.1    dante 
    244       1.1    dante 
    245       1.1    dante /*
    246       1.1    dante  * Get a free ccb
    247       1.1    dante  *
    248       1.1    dante  * If there are none, see if we can allocate a new one
    249       1.1    dante  */
    250       1.1    dante static ADW_CCB *
    251       1.1    dante adw_get_ccb(sc, flags)
    252       1.1    dante 	ADW_SOFTC      *sc;
    253       1.1    dante 	int             flags;
    254       1.1    dante {
    255       1.1    dante 	ADW_CCB        *ccb = 0;
    256       1.1    dante 	int             s;
    257       1.1    dante 
    258       1.1    dante 	s = splbio();
    259       1.1    dante 
    260       1.1    dante 	/*
    261       1.1    dante          * If we can and have to, sleep waiting for one to come free
    262       1.1    dante          * but only if we can't allocate a new one.
    263       1.1    dante          */
    264       1.1    dante 	for (;;) {
    265       1.1    dante 		ccb = sc->sc_free_ccb.tqh_first;
    266       1.1    dante 		if (ccb) {
    267       1.1    dante 			TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    268       1.1    dante 			break;
    269       1.1    dante 		}
    270      1.12  thorpej 		if ((flags & XS_CTL_NOSLEEP) != 0)
    271       1.1    dante 			goto out;
    272       1.1    dante 
    273       1.1    dante 		tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
    274       1.1    dante 	}
    275       1.1    dante 
    276       1.1    dante 	ccb->flags |= CCB_ALLOC;
    277       1.1    dante 
    278       1.1    dante out:
    279       1.1    dante 	splx(s);
    280       1.1    dante 	return (ccb);
    281       1.1    dante }
    282       1.1    dante 
    283       1.1    dante 
    284       1.1    dante /*
    285       1.7    dante  * Given a physical address, find the ccb that it corresponds to.
    286       1.7    dante  */
    287       1.7    dante ADW_CCB *
    288       1.7    dante adw_ccb_phys_kv(sc, ccb_phys)
    289       1.7    dante 	ADW_SOFTC	*sc;
    290       1.9  thorpej 	u_int32_t	ccb_phys;
    291       1.7    dante {
    292       1.7    dante 	int hashnum = CCB_HASH(ccb_phys);
    293       1.7    dante 	ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
    294       1.7    dante 
    295       1.7    dante 	while (ccb) {
    296       1.7    dante 		if (ccb->hashkey == ccb_phys)
    297       1.7    dante 			break;
    298       1.7    dante 		ccb = ccb->nexthash;
    299       1.7    dante 	}
    300       1.7    dante 	return (ccb);
    301       1.7    dante }
    302       1.7    dante 
    303       1.7    dante 
    304       1.7    dante /*
    305       1.1    dante  * Queue a CCB to be sent to the controller, and send it if possible.
    306       1.1    dante  */
    307       1.1    dante static void
    308       1.1    dante adw_queue_ccb(sc, ccb)
    309       1.1    dante 	ADW_SOFTC      *sc;
    310       1.1    dante 	ADW_CCB        *ccb;
    311       1.1    dante {
    312      1.11    dante 	int		s;
    313       1.1    dante 
    314      1.11    dante 	s = splbio();
    315       1.1    dante 	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    316      1.11    dante 	splx(s);
    317       1.1    dante 
    318       1.1    dante 	adw_start_ccbs(sc);
    319       1.1    dante }
    320       1.1    dante 
    321       1.1    dante 
    322       1.1    dante static void
    323       1.1    dante adw_start_ccbs(sc)
    324       1.1    dante 	ADW_SOFTC      *sc;
    325       1.1    dante {
    326       1.1    dante 	ADW_CCB        *ccb;
    327      1.11    dante 	int		s;
    328       1.1    dante 
    329       1.1    dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    330       1.1    dante 
    331      1.11    dante 		while (AdvExeScsiQueue(sc, &ccb->scsiq) == ADW_BUSY);
    332      1.11    dante 
    333      1.11    dante 		s = splbio();
    334       1.1    dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    335      1.11    dante 		splx(s);
    336       1.1    dante 
    337      1.12  thorpej 		if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
    338       1.1    dante 			timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000);
    339       1.1    dante 	}
    340       1.1    dante }
    341       1.1    dante 
    342       1.1    dante 
    343       1.1    dante /******************************************************************************/
    344       1.7    dante /*                           SCSI layer interfacing routines                  */
    345       1.1    dante /******************************************************************************/
    346       1.1    dante 
    347       1.1    dante 
    348       1.1    dante int
    349       1.1    dante adw_init(sc)
    350       1.1    dante 	ADW_SOFTC      *sc;
    351       1.1    dante {
    352       1.2    dante 	u_int16_t       warn_code;
    353       1.1    dante 
    354       1.1    dante 
    355       1.1    dante 	sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
    356       1.2    dante 		ADW_LIB_VERSION_MINOR;
    357       1.1    dante 	sc->cfg.chip_version =
    358       1.1    dante 		ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
    359       1.1    dante 
    360       1.1    dante 	/*
    361       1.1    dante 	 * Reset the chip to start and allow register writes.
    362       1.1    dante 	 */
    363       1.1    dante 	if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
    364       1.1    dante 		panic("adw_init: adw_find_signature failed");
    365       1.2    dante 	} else {
    366       1.1    dante 		AdvResetChip(sc->sc_iot, sc->sc_ioh);
    367       1.1    dante 
    368       1.1    dante 		warn_code = AdvInitFromEEP(sc);
    369       1.2    dante 		if (warn_code & ASC_WARN_EEPROM_CHKSUM)
    370       1.1    dante 			printf("%s: Bad checksum found. "
    371       1.2    dante 			       "Setting default values\n",
    372       1.2    dante 			       sc->sc_dev.dv_xname);
    373       1.2    dante 		if (warn_code & ASC_WARN_EEPROM_TERMINATION)
    374       1.1    dante 			printf("%s: Bad bus termination setting."
    375       1.2    dante 			       "Using automatic termination.\n",
    376       1.2    dante 			       sc->sc_dev.dv_xname);
    377       1.1    dante 
    378       1.1    dante 		/*
    379       1.1    dante 		 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
    380       1.1    dante 		 * Resets should be performed.
    381       1.1    dante 		 */
    382       1.1    dante 		if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
    383       1.1    dante 			AdvResetSCSIBus(sc);
    384       1.1    dante 	}
    385       1.1    dante 
    386       1.8    dante 	sc->isr_callback = (ADW_CALLBACK) adw_wide_isr_callback;
    387      1.11    dante 	sc->sbreset_callback = (ADW_CALLBACK) adw_sbreset_callback;
    388       1.1    dante 
    389       1.1    dante 	return (0);
    390       1.1    dante }
    391       1.1    dante 
    392       1.1    dante 
    393       1.1    dante void
    394       1.1    dante adw_attach(sc)
    395       1.1    dante 	ADW_SOFTC      *sc;
    396       1.1    dante {
    397  1.12.2.1  thorpej 	struct scsipi_adapter *adapt = &sc->sc_adapter;
    398  1.12.2.1  thorpej 	struct scsipi_channel *chan = &sc->sc_channel;
    399       1.1    dante 	int             i, error;
    400       1.1    dante 
    401       1.1    dante 	/*
    402       1.1    dante 	 * Initialize the ASC3550.
    403       1.1    dante 	 */
    404       1.2    dante 	switch (AdvInitAsc3550Driver(sc)) {
    405       1.2    dante 	case ASC_IERR_MCODE_CHKSUM:
    406       1.2    dante 		panic("%s: Microcode checksum error",
    407       1.2    dante 		      sc->sc_dev.dv_xname);
    408       1.2    dante 		break;
    409       1.2    dante 
    410       1.2    dante 	case ASC_IERR_ILLEGAL_CONNECTION:
    411       1.2    dante 		panic("%s: All three connectors are in use",
    412       1.2    dante 		      sc->sc_dev.dv_xname);
    413       1.2    dante 		break;
    414       1.2    dante 
    415       1.2    dante 	case ASC_IERR_REVERSED_CABLE:
    416       1.2    dante 		panic("%s: Cable is reversed",
    417       1.2    dante 		      sc->sc_dev.dv_xname);
    418       1.2    dante 		break;
    419       1.2    dante 
    420       1.2    dante 	case ASC_IERR_SINGLE_END_DEVICE:
    421       1.2    dante 		panic("%s: single-ended device is attached to"
    422       1.2    dante 		      " one of the connectors",
    423       1.2    dante 		      sc->sc_dev.dv_xname);
    424       1.2    dante 		break;
    425       1.1    dante 	}
    426       1.1    dante 
    427       1.4  thorpej 	/*
    428  1.12.2.1  thorpej 	 * Fill in the scsipi_adapter.
    429       1.4  thorpej 	 */
    430  1.12.2.1  thorpej 	memset(adapt, 0, sizeof(*adapt));
    431  1.12.2.1  thorpej 	adapt->adapt_dev = &sc->sc_dev;
    432  1.12.2.1  thorpej 	adapt->adapt_nchannels = 1;
    433  1.12.2.1  thorpej 	/* adapt_openings filled in below */
    434  1.12.2.1  thorpej 	/* adapt_max_periph filled in below */
    435  1.12.2.1  thorpej 	adapt->adapt_request = adw_scsipi_request;
    436  1.12.2.1  thorpej 	adapt->adapt_minphys = adwminphys;
    437       1.1    dante 
    438       1.1    dante 	/*
    439  1.12.2.1  thorpej 	 * Fill in the scsipi_channel.
    440  1.12.2.1  thorpej 	 */
    441  1.12.2.1  thorpej 	memset(chan, 0, sizeof(*chan));
    442  1.12.2.1  thorpej 	chan->chan_adapter = adapt;
    443  1.12.2.1  thorpej 	chan->chan_bustype = &scsi_bustype;
    444  1.12.2.1  thorpej 	chan->chan_channel = 0;
    445  1.12.2.1  thorpej 	chan->chan_ntargets = ADW_MAX_TID + 1;
    446  1.12.2.1  thorpej 	chan->chan_nluns = 7;
    447  1.12.2.1  thorpej 	chan->chan_id = sc->chip_scsi_id;
    448       1.1    dante 
    449       1.1    dante 	TAILQ_INIT(&sc->sc_free_ccb);
    450       1.1    dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    451       1.1    dante 
    452       1.1    dante 	/*
    453       1.1    dante          * Allocate the Control Blocks.
    454       1.1    dante          */
    455       1.1    dante 	error = adw_alloc_ccbs(sc);
    456       1.1    dante 	if (error)
    457       1.1    dante 		return; /* (error) */ ;
    458       1.1    dante 
    459       1.1    dante 	/*
    460       1.1    dante 	 * Create and initialize the Control Blocks.
    461       1.1    dante 	 */
    462       1.1    dante 	i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
    463       1.1    dante 	if (i == 0) {
    464       1.1    dante 		printf("%s: unable to create control blocks\n",
    465       1.1    dante 		       sc->sc_dev.dv_xname);
    466       1.1    dante 		return; /* (ENOMEM) */ ;
    467       1.1    dante 	} else if (i != ADW_MAX_CCB) {
    468       1.1    dante 		printf("%s: WARNING: only %d of %d control blocks"
    469       1.2    dante 		       " created\n",
    470       1.2    dante 		       sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
    471       1.1    dante 	}
    472  1.12.2.1  thorpej 
    473  1.12.2.1  thorpej 	adapt->adapt_openings = i;
    474  1.12.2.1  thorpej 	adapt->adapt_max_periph = adapt->adapt_openings;
    475  1.12.2.1  thorpej 
    476  1.12.2.1  thorpej 	config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
    477       1.1    dante }
    478       1.1    dante 
    479       1.1    dante 
    480       1.1    dante static void
    481       1.1    dante adwminphys(bp)
    482       1.1    dante 	struct buf     *bp;
    483       1.1    dante {
    484       1.1    dante 
    485       1.1    dante 	if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
    486       1.1    dante 		bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
    487       1.1    dante 	minphys(bp);
    488       1.1    dante }
    489       1.1    dante 
    490       1.1    dante 
    491       1.1    dante /*
    492       1.2    dante  * start a scsi operation given the command and the data address.
    493       1.2    dante  * Also needs the unit, target and lu.
    494       1.1    dante  */
    495  1.12.2.1  thorpej static void
    496  1.12.2.1  thorpej adw_scsipi_request(chan, req, arg)
    497  1.12.2.1  thorpej 	struct scsipi_channel *chan;
    498  1.12.2.1  thorpej 	scsipi_adapter_req_t req;
    499  1.12.2.1  thorpej 	void *arg;
    500       1.1    dante {
    501  1.12.2.1  thorpej 	struct scsipi_xfer *xs;
    502  1.12.2.1  thorpej 	ADW_SOFTC      *sc = (void *)chan->chan_adapter->adapt_dev;
    503       1.1    dante 	ADW_CCB        *ccb;
    504       1.1    dante 
    505  1.12.2.1  thorpej 	switch (req) {
    506  1.12.2.1  thorpej 	case ADAPTER_REQ_RUN_XFER:
    507  1.12.2.1  thorpej 		xs = arg;
    508       1.1    dante 
    509       1.1    dante 		/*
    510  1.12.2.1  thorpej 		 * Get a CCB to use.
    511  1.12.2.1  thorpej 		 */
    512  1.12.2.1  thorpej 		ccb = adw_get_ccb(sc, xs->xs_control);
    513  1.12.2.1  thorpej #ifdef DIAGNOSTIC
    514       1.1    dante 		/*
    515  1.12.2.1  thorpej 		 * This should never happen as we track the resources
    516  1.12.2.1  thorpej 		 * in the mid-layer.
    517  1.12.2.1  thorpej 		 */
    518  1.12.2.1  thorpej 		if (ccb == NULL) {
    519  1.12.2.1  thorpej 			scsipi_printaddr(xs->xs_periph);
    520  1.12.2.1  thorpej 			printf("unable to allocate ccb\n");
    521  1.12.2.1  thorpej 			panic("adw_scsipi_request");
    522       1.1    dante 		}
    523  1.12.2.1  thorpej #endif
    524       1.1    dante 
    525  1.12.2.1  thorpej 		ccb->xs = xs;
    526  1.12.2.1  thorpej 		ccb->timeout = xs->timeout;
    527       1.1    dante 
    528  1.12.2.1  thorpej 		if (adw_build_req(sc, ccb)) {
    529  1.12.2.1  thorpej 			adw_queue_ccb(sc, ccb);
    530       1.1    dante 
    531  1.12.2.1  thorpej 			if ((xs->xs_control & XS_CTL_POLL) == 0)
    532  1.12.2.1  thorpej 				return;
    533       1.1    dante 
    534  1.12.2.1  thorpej 			/*
    535  1.12.2.1  thorpej 			 * Not allowed to use interrupts, poll for completion.
    536  1.12.2.1  thorpej 			 */
    537  1.12.2.1  thorpej 			if (adw_poll(sc, xs, ccb->timeout)) {
    538       1.1    dante 				adw_timeout(ccb);
    539  1.12.2.1  thorpej 				if (adw_poll(sc, xs, ccb->timeout))
    540  1.12.2.1  thorpej 					adw_timeout(ccb);
    541  1.12.2.1  thorpej 			}
    542       1.1    dante 		}
    543  1.12.2.1  thorpej 		return;
    544  1.12.2.1  thorpej 
    545  1.12.2.1  thorpej 	case ADAPTER_REQ_GROW_RESOURCES:
    546  1.12.2.1  thorpej 		/* XXX Not supported. */
    547  1.12.2.1  thorpej 		return;
    548  1.12.2.1  thorpej 
    549  1.12.2.1  thorpej 	case ADAPTER_REQ_SET_XFER_MODE:
    550  1.12.2.1  thorpej 		/* XXX XXX XXX */
    551  1.12.2.1  thorpej 		return;
    552  1.12.2.1  thorpej 
    553  1.12.2.1  thorpej 	case ADAPTER_REQ_GET_XFER_MODE:
    554  1.12.2.1  thorpej 		/* XXX XXX XXX */
    555  1.12.2.1  thorpej 		return;
    556       1.1    dante 	}
    557       1.1    dante }
    558       1.1    dante 
    559       1.1    dante /*
    560       1.1    dante  * Build a request structure for the Wide Boards.
    561       1.1    dante  */
    562       1.1    dante static int
    563  1.12.2.1  thorpej adw_build_req(sc, ccb)
    564  1.12.2.1  thorpej 	ADW_SOFTC	*sc;
    565  1.12.2.1  thorpej 	ADW_CCB		*ccb;
    566       1.1    dante {
    567  1.12.2.1  thorpej 	struct scsipi_xfer *xs = ccb->xs;
    568  1.12.2.1  thorpej 	struct scsipi_periph *periph = xs->xs_periph;
    569       1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    570       1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    571       1.2    dante 	int             error;
    572       1.1    dante 
    573       1.1    dante 	scsiqp = &ccb->scsiq;
    574       1.1    dante 	bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
    575       1.1    dante 
    576       1.1    dante 	/*
    577       1.7    dante 	 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
    578       1.7    dante 	 * physical CCB structure.
    579       1.1    dante 	 */
    580      1.10  thorpej 	scsiqp->ccb_ptr = ccb->hashkey;
    581       1.1    dante 
    582       1.1    dante 	/*
    583       1.1    dante 	 * Build the ADW_SCSI_REQ_Q request.
    584       1.1    dante 	 */
    585       1.1    dante 
    586       1.1    dante 	/*
    587       1.1    dante 	 * Set CDB length and copy it to the request structure.
    588       1.1    dante 	 */
    589       1.1    dante 	bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen);
    590       1.1    dante 
    591  1.12.2.1  thorpej 	scsiqp->target_id = periph->periph_target;
    592  1.12.2.1  thorpej 	scsiqp->target_lun = periph->periph_lun;
    593       1.1    dante 
    594       1.7    dante 	scsiqp->vsense_addr = &ccb->scsi_sense;
    595      1.10  thorpej 	scsiqp->sense_addr = ccb->hashkey +
    596      1.10  thorpej 	    offsetof(struct adw_ccb, scsi_sense);
    597       1.1    dante 	scsiqp->sense_len = sizeof(struct scsipi_sense_data);
    598       1.1    dante 
    599       1.1    dante 	/*
    600       1.1    dante 	 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
    601       1.1    dante 	 */
    602       1.1    dante 	if (xs->datalen) {
    603       1.1    dante 		/*
    604       1.1    dante                  * Map the DMA transfer.
    605       1.1    dante                  */
    606       1.1    dante #ifdef TFS
    607      1.12  thorpej 		if (xs->xs_control & SCSI_DATA_UIO) {
    608       1.1    dante 			error = bus_dmamap_load_uio(dmat,
    609  1.12.2.1  thorpej 			    ccb->dmamap_xfer, (struct uio *) xs->data,
    610  1.12.2.1  thorpej 			    (xs->xs_control & XS_CTL_NOSLEEP) ?
    611  1.12.2.1  thorpej 			     BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    612       1.1    dante 		} else
    613  1.12.2.1  thorpej #endif /* TFS */
    614       1.1    dante 		{
    615       1.1    dante 			error = bus_dmamap_load(dmat,
    616  1.12.2.1  thorpej 			    ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
    617  1.12.2.1  thorpej 			    (xs->xs_control & XS_CTL_NOSLEEP) ?
    618  1.12.2.1  thorpej 			     BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    619       1.1    dante 		}
    620       1.1    dante 
    621       1.1    dante 		if (error) {
    622       1.1    dante 			if (error == EFBIG) {
    623  1.12.2.1  thorpej 				printf("%s: adw_scsipi_request, more than "
    624  1.12.2.1  thorpej 				    "%d dma segments\n",
    625  1.12.2.1  thorpej 				    sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
    626       1.1    dante 			} else {
    627  1.12.2.1  thorpej 				printf("%s: adw_scsipi_request, error %d "
    628  1.12.2.1  thorpej 				    "loading dma map\n",
    629  1.12.2.1  thorpej 				    sc->sc_dev.dv_xname, error);
    630       1.1    dante 			}
    631       1.1    dante 
    632       1.1    dante 			adw_free_ccb(sc, ccb);
    633  1.12.2.1  thorpej 			xs->error = XS_DRIVER_STUFFUP;
    634  1.12.2.1  thorpej 			scsipi_done(xs);
    635       1.1    dante 			return (0);
    636       1.1    dante 		}
    637       1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    638  1.12.2.1  thorpej 		    ccb->dmamap_xfer->dm_mapsize,
    639  1.12.2.1  thorpej 		    (xs->xs_control & XS_CTL_DATA_IN) ?
    640  1.12.2.1  thorpej 		    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
    641       1.1    dante 
    642       1.1    dante 		/*
    643       1.1    dante 		 * Build scatter-gather list.
    644       1.1    dante 		 */
    645       1.1    dante 		scsiqp->data_cnt = xs->datalen;
    646       1.7    dante 		scsiqp->vdata_addr = xs->data;
    647       1.1    dante 		scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
    648       1.7    dante 		bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
    649       1.7    dante 		adw_build_sglist(ccb, scsiqp, ccb->sg_block);
    650       1.1    dante 	} else {
    651       1.1    dante 		/*
    652       1.1    dante                  * No data xfer, use non S/G values.
    653       1.1    dante                  */
    654       1.1    dante 		scsiqp->data_cnt = 0;
    655       1.1    dante 		scsiqp->vdata_addr = 0;
    656       1.1    dante 		scsiqp->data_addr = 0;
    657       1.1    dante 	}
    658       1.1    dante 
    659       1.1    dante 	return (1);
    660       1.1    dante }
    661       1.1    dante 
    662       1.1    dante 
    663       1.1    dante /*
    664       1.1    dante  * Build scatter-gather list for Wide Boards.
    665       1.1    dante  */
    666       1.1    dante static void
    667       1.7    dante adw_build_sglist(ccb, scsiqp, sg_block)
    668       1.2    dante 	ADW_CCB        *ccb;
    669       1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    670       1.7    dante 	ADW_SG_BLOCK   *sg_block;
    671       1.1    dante {
    672       1.9  thorpej 	u_long          sg_block_next_addr;	/* block and its next */
    673       1.9  thorpej 	u_int32_t       sg_block_physical_addr;
    674       1.2    dante 	int             sg_block_index, i;	/* how many SG entries */
    675       1.1    dante 	bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
    676       1.2    dante 	int             sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
    677       1.1    dante 
    678       1.1    dante 
    679       1.9  thorpej 	sg_block_next_addr = (u_long) sg_block;	/* allow math operation */
    680      1.10  thorpej 	sg_block_physical_addr = ccb->hashkey +
    681      1.10  thorpej 	    offsetof(struct adw_ccb, sg_block[0]);
    682       1.1    dante 	scsiqp->sg_real_addr = sg_block_physical_addr;
    683       1.1    dante 
    684       1.1    dante 	/*
    685       1.1    dante 	 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
    686       1.1    dante 	 * then split the request into multiple sg-list blocks.
    687       1.1    dante 	 */
    688       1.1    dante 
    689       1.1    dante 	sg_block_index = 0;
    690       1.2    dante 	do {
    691       1.1    dante 		sg_block->first_entry_no = sg_block_index;
    692       1.2    dante 		for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
    693       1.1    dante 			sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
    694       1.1    dante 			sg_block->sg_list[i].sg_count = sg_list->ds_len;
    695       1.1    dante 
    696       1.2    dante 			if (--sg_elem_cnt == 0) {
    697       1.1    dante 				/* last entry, get out */
    698       1.1    dante 				scsiqp->sg_entry_cnt = sg_block_index + i + 1;
    699       1.1    dante 				sg_block->last_entry_no = sg_block_index + i;
    700       1.2    dante 				sg_block->sg_ptr = NULL; /* next link = NULL */
    701       1.1    dante 				return;
    702       1.1    dante 			}
    703       1.1    dante 			sg_list++;
    704       1.1    dante 		}
    705       1.1    dante 		sg_block_next_addr += sizeof(ADW_SG_BLOCK);
    706       1.1    dante 		sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
    707       1.1    dante 
    708       1.1    dante 		sg_block_index += NO_OF_SG_PER_BLOCK;
    709       1.9  thorpej 		sg_block->sg_ptr = sg_block_physical_addr;
    710       1.1    dante 		sg_block->last_entry_no = sg_block_index - 1;
    711       1.2    dante 		sg_block = (ADW_SG_BLOCK *) sg_block_next_addr;	/* virt. addr */
    712      1.10  thorpej 	} while (1);
    713       1.1    dante }
    714       1.1    dante 
    715       1.1    dante 
    716       1.1    dante int
    717       1.1    dante adw_intr(arg)
    718       1.1    dante 	void           *arg;
    719       1.1    dante {
    720       1.1    dante 	ADW_SOFTC      *sc = arg;
    721       1.1    dante 
    722       1.1    dante 	AdvISR(sc);
    723       1.1    dante 	return (1);
    724       1.1    dante }
    725       1.1    dante 
    726       1.1    dante 
    727       1.1    dante /*
    728       1.1    dante  * Poll a particular unit, looking for a particular xs
    729       1.1    dante  */
    730       1.1    dante static int
    731       1.1    dante adw_poll(sc, xs, count)
    732       1.1    dante 	ADW_SOFTC      *sc;
    733       1.1    dante 	struct scsipi_xfer *xs;
    734       1.1    dante 	int             count;
    735       1.1    dante {
    736       1.1    dante 
    737       1.1    dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
    738       1.1    dante 	while (count) {
    739       1.1    dante 		adw_intr(sc);
    740      1.12  thorpej 		if (xs->xs_status & XS_STS_DONE)
    741       1.1    dante 			return (0);
    742       1.1    dante 		delay(1000);	/* only happens in boot so ok */
    743       1.1    dante 		count--;
    744       1.1    dante 	}
    745       1.1    dante 	return (1);
    746       1.1    dante }
    747       1.1    dante 
    748       1.1    dante 
    749       1.1    dante static void
    750       1.1    dante adw_timeout(arg)
    751       1.1    dante 	void           *arg;
    752       1.1    dante {
    753       1.1    dante 	ADW_CCB        *ccb = arg;
    754       1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    755  1.12.2.1  thorpej 	struct scsipi_periph *periph = xs->xs_periph;
    756  1.12.2.1  thorpej 	ADW_SOFTC      *sc =
    757  1.12.2.1  thorpej 	    (void *)periph->periph_channel->chan_adapter->adapt_dev;
    758       1.1    dante 	int             s;
    759       1.1    dante 
    760  1.12.2.1  thorpej 	scsipi_printaddr(periph);
    761       1.1    dante 	printf("timed out");
    762       1.1    dante 
    763       1.1    dante 	s = splbio();
    764       1.1    dante 
    765       1.1    dante 	/*
    766       1.1    dante          * If it has been through before, then a previous abort has failed,
    767       1.1    dante          * don't try abort again, reset the bus instead.
    768       1.1    dante          */
    769      1.11    dante 	if (ccb->flags & CCB_ABORTED) {
    770      1.11    dante 	/*
    771      1.11    dante 	 * Abort Timed Out
    772      1.11    dante 	 * Lets try resetting the bus!
    773      1.11    dante 	 */
    774      1.11    dante 		printf(" AGAIN. Resetting SCSI Bus\n");
    775      1.11    dante 		ccb->flags &= ~CCB_ABORTED;
    776      1.11    dante 		/* AdvResetSCSIBus() will call sbreset_callback() */
    777       1.1    dante 		AdvResetSCSIBus(sc);
    778       1.1    dante 	} else {
    779      1.11    dante 	/*
    780      1.11    dante 	 * Abort the operation that has timed out
    781      1.11    dante 	 */
    782       1.1    dante 		printf("\n");
    783      1.11    dante 		xs->error = XS_TIMEOUT;
    784      1.11    dante 		ccb->flags |= CCB_ABORTING;
    785      1.11    dante 		/* ADW_ABORT_CCB() will implicitly call isr_callback() */
    786       1.1    dante 		ADW_ABORT_CCB(sc, ccb);
    787       1.1    dante 	}
    788       1.1    dante 
    789       1.1    dante 	splx(s);
    790       1.1    dante }
    791       1.1    dante 
    792       1.1    dante 
    793       1.1    dante /******************************************************************************/
    794       1.7    dante /*                           WIDE boards Interrupt callbacks                  */
    795       1.1    dante /******************************************************************************/
    796       1.1    dante 
    797       1.1    dante 
    798       1.1    dante /*
    799       1.1    dante  * adw_wide_isr_callback() - Second Level Interrupt Handler called by AdvISR()
    800       1.1    dante  *
    801       1.1    dante  * Interrupt callback function for the Wide SCSI Adv Library.
    802       1.1    dante  */
    803       1.1    dante static void
    804       1.1    dante adw_wide_isr_callback(sc, scsiq)
    805       1.1    dante 	ADW_SOFTC      *sc;
    806       1.1    dante 	ADW_SCSI_REQ_Q *scsiq;
    807       1.1    dante {
    808       1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    809       1.7    dante 	ADW_CCB        *ccb;
    810       1.7    dante 	struct scsipi_xfer *xs;
    811       1.1    dante 	struct scsipi_sense_data *s1, *s2;
    812      1.11    dante 	int		 s;
    813       1.2    dante 	//int           underrun = ASC_FALSE;
    814       1.1    dante 
    815       1.7    dante 
    816       1.7    dante 	ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
    817      1.11    dante 
    818      1.11    dante 	untimeout(adw_timeout, ccb);
    819      1.11    dante 
    820      1.11    dante 	if(ccb->flags & CCB_ABORTING) {
    821      1.11    dante 		printf("Retrying request\n");
    822      1.11    dante 		ccb->flags &= ~CCB_ABORTING;
    823      1.11    dante 		ccb->flags |= CCB_ABORTED;
    824      1.11    dante 		s = splbio();
    825      1.11    dante 		adw_queue_ccb(sc, ccb);
    826      1.11    dante 		splx(s);
    827      1.11    dante 		return;
    828      1.11    dante 	}
    829      1.11    dante 
    830       1.7    dante 	xs = ccb->xs;
    831       1.1    dante 
    832       1.1    dante 
    833       1.1    dante 	/*
    834       1.1    dante          * If we were a data transfer, unload the map that described
    835       1.1    dante          * the data buffer.
    836       1.1    dante          */
    837       1.1    dante 	if (xs->datalen) {
    838       1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    839       1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    840      1.12  thorpej 			 (xs->xs_control & XS_CTL_DATA_IN) ?
    841      1.12  thorpej 			 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
    842       1.1    dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
    843       1.1    dante 	}
    844       1.1    dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
    845       1.1    dante 		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
    846       1.1    dante 		Debugger();
    847       1.1    dante 		return;
    848       1.1    dante 	}
    849       1.1    dante 	/*
    850       1.1    dante 	 * Check for an underrun condition.
    851       1.1    dante 	 */
    852       1.2    dante 	/*
    853       1.2    dante 	 * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
    854       1.2    dante 	 * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
    855       1.2    dante 	 * scsiqp->data_cnt); underrun = ASC_TRUE; }
    856       1.2    dante 	 */
    857       1.1    dante 	/*
    858       1.1    dante 	 * 'done_status' contains the command's ending status.
    859       1.1    dante 	 */
    860       1.1    dante 	switch (scsiq->done_status) {
    861       1.1    dante 	case QD_NO_ERROR:
    862       1.1    dante 		switch (scsiq->host_status) {
    863       1.1    dante 		case QHSTA_NO_ERROR:
    864       1.1    dante 			xs->error = XS_NOERROR;
    865       1.1    dante 			xs->resid = 0;
    866       1.1    dante 			break;
    867      1.11    dante 		case QHSTA_M_SEL_TIMEOUT:
    868       1.1    dante 		default:
    869       1.1    dante 			/* QHSTA error occurred. */
    870       1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    871       1.1    dante 			break;
    872       1.1    dante 		}
    873       1.1    dante 		/*
    874       1.1    dante 		 * If there was an underrun without any other error,
    875       1.1    dante 		 * set DID_ERROR to indicate the underrun error.
    876       1.1    dante 		 *
    877       1.1    dante 		 * Note: There is no way yet to indicate the number
    878       1.1    dante 		 * of underrun bytes.
    879       1.1    dante 		 */
    880       1.2    dante 		/*
    881       1.2    dante 		 * if (xs->error == XS_NOERROR && underrun == ASC_TRUE) {
    882       1.2    dante 		 * scp->result = HOST_BYTE(DID_UNDERRUN); }
    883       1.2    dante 		 */ break;
    884       1.1    dante 
    885       1.1    dante 	case QD_WITH_ERROR:
    886       1.1    dante 		switch (scsiq->host_status) {
    887       1.1    dante 		case QHSTA_NO_ERROR:
    888      1.11    dante 			switch(scsiq->scsi_status) {
    889      1.11    dante 			case SS_CHK_CONDITION:
    890      1.11    dante 			case SS_CMD_TERMINATED:
    891       1.1    dante 				s1 = &ccb->scsi_sense;
    892       1.1    dante 				s2 = &xs->sense.scsi_sense;
    893       1.1    dante 				*s2 = *s1;
    894       1.1    dante 				xs->error = XS_SENSE;
    895      1.11    dante 				break;
    896      1.11    dante 			case SS_TARGET_BUSY:
    897      1.11    dante 			case SS_RSERV_CONFLICT:
    898      1.11    dante 			case SS_QUEUE_FULL:
    899      1.11    dante 				xs->error = XS_DRIVER_STUFFUP;
    900      1.11    dante 				break;
    901      1.11    dante 			case SS_CONDITION_MET:
    902      1.11    dante 			case SS_INTERMID:
    903      1.11    dante 			case SS_INTERMID_COND_MET:
    904       1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    905      1.11    dante 				break;
    906      1.11    dante 			case SS_GOOD:
    907      1.11    dante 				break;
    908       1.1    dante 			}
    909       1.1    dante 			break;
    910       1.1    dante 
    911      1.11    dante 		case QHSTA_M_SEL_TIMEOUT:
    912      1.11    dante 			xs->error = XS_DRIVER_STUFFUP;
    913      1.11    dante 			break;
    914      1.11    dante 
    915       1.1    dante 		default:
    916       1.1    dante 			/* Some other QHSTA error occurred. */
    917       1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    918       1.1    dante 			break;
    919       1.1    dante 		}
    920       1.1    dante 		break;
    921       1.1    dante 
    922       1.1    dante 	case QD_ABORTED_BY_HOST:
    923      1.11    dante 		xs->error = XS_DRIVER_STUFFUP;
    924      1.11    dante 		break;
    925      1.11    dante 
    926       1.1    dante 	default:
    927       1.1    dante 		xs->error = XS_DRIVER_STUFFUP;
    928       1.1    dante 		break;
    929       1.1    dante 	}
    930       1.1    dante 
    931       1.1    dante 	adw_free_ccb(sc, ccb);
    932      1.12  thorpej 	xs->xs_status |= XS_STS_DONE;
    933       1.1    dante 	scsipi_done(xs);
    934      1.11    dante }
    935      1.11    dante 
    936      1.11    dante 
    937      1.11    dante static void
    938      1.11    dante adw_sbreset_callback(sc)
    939      1.11    dante 	ADW_SOFTC	*sc;
    940      1.11    dante {
    941       1.1    dante }
    942