adw.c revision 1.12.2.2 1 1.12.2.2 thorpej /* $NetBSD: adw.c,v 1.12.2.2 1999/10/19 22:53:43 thorpej Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.1 dante * Generic driver for the Advanced Systems Inc. SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.1 dante * This product includes software developed by the NetBSD
22 1.1 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.1 dante #include <sys/kernel.h>
44 1.1 dante #include <sys/errno.h>
45 1.1 dante #include <sys/ioctl.h>
46 1.1 dante #include <sys/device.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/buf.h>
49 1.1 dante #include <sys/proc.h>
50 1.1 dante #include <sys/user.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <vm/vm.h>
56 1.1 dante #include <vm/vm_param.h>
57 1.1 dante #include <vm/pmap.h>
58 1.1 dante
59 1.1 dante #include <dev/scsipi/scsi_all.h>
60 1.1 dante #include <dev/scsipi/scsipi_all.h>
61 1.1 dante #include <dev/scsipi/scsiconf.h>
62 1.1 dante
63 1.1 dante #include <dev/ic/adwlib.h>
64 1.1 dante #include <dev/ic/adw.h>
65 1.1 dante
66 1.1 dante #ifndef DDB
67 1.11 dante #define Debugger() panic("should call debugger here (adw.c)")
68 1.2 dante #endif /* ! DDB */
69 1.1 dante
70 1.1 dante /******************************************************************************/
71 1.1 dante
72 1.1 dante
73 1.1 dante static int adw_alloc_ccbs __P((ADW_SOFTC *));
74 1.1 dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
75 1.1 dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
76 1.1 dante static void adw_reset_ccb __P((ADW_CCB *));
77 1.1 dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
78 1.12.2.2 thorpej static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *));
79 1.1 dante static void adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *));
80 1.1 dante static void adw_start_ccbs __P((ADW_SOFTC *));
81 1.1 dante
82 1.12.2.1 thorpej static void adw_scsipi_request __P((struct scsipi_channel *,
83 1.12.2.1 thorpej scsipi_adapter_req_t, void *));
84 1.12.2.1 thorpej static int adw_build_req __P((ADW_SOFTC *, ADW_CCB *));
85 1.7 dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *));
86 1.1 dante static void adwminphys __P((struct buf *));
87 1.1 dante static void adw_wide_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
88 1.11 dante static void adw_sbreset_callback __P((ADW_SOFTC *));
89 1.1 dante
90 1.1 dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
91 1.1 dante static void adw_timeout __P((void *));
92 1.1 dante
93 1.1 dante
94 1.1 dante /******************************************************************************/
95 1.1 dante
96 1.1 dante #define ADW_ABORT_TIMEOUT 10000 /* time to wait for abort (mSec) */
97 1.1 dante #define ADW_WATCH_TIMEOUT 10000 /* time to wait for watchdog (mSec) */
98 1.1 dante
99 1.1 dante /******************************************************************************/
100 1.7 dante /* Control Blocks routines */
101 1.1 dante /******************************************************************************/
102 1.1 dante
103 1.1 dante
104 1.1 dante static int
105 1.1 dante adw_alloc_ccbs(sc)
106 1.1 dante ADW_SOFTC *sc;
107 1.1 dante {
108 1.1 dante bus_dma_segment_t seg;
109 1.1 dante int error, rseg;
110 1.1 dante
111 1.1 dante /*
112 1.1 dante * Allocate the control blocks.
113 1.1 dante */
114 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
115 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
116 1.1 dante printf("%s: unable to allocate control structures,"
117 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
118 1.1 dante return (error);
119 1.1 dante }
120 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
121 1.1 dante sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
122 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
123 1.1 dante printf("%s: unable to map control structures, error = %d\n",
124 1.1 dante sc->sc_dev.dv_xname, error);
125 1.1 dante return (error);
126 1.1 dante }
127 1.1 dante /*
128 1.1 dante * Create and load the DMA map used for the control blocks.
129 1.1 dante */
130 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
131 1.1 dante 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
132 1.1 dante &sc->sc_dmamap_control)) != 0) {
133 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
134 1.1 dante sc->sc_dev.dv_xname, error);
135 1.1 dante return (error);
136 1.1 dante }
137 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
138 1.1 dante sc->sc_control, sizeof(struct adw_control), NULL,
139 1.1 dante BUS_DMA_NOWAIT)) != 0) {
140 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
141 1.1 dante sc->sc_dev.dv_xname, error);
142 1.1 dante return (error);
143 1.1 dante }
144 1.1 dante return (0);
145 1.1 dante }
146 1.1 dante
147 1.1 dante
148 1.1 dante /*
149 1.1 dante * Create a set of ccbs and add them to the free list. Called once
150 1.1 dante * by adw_init(). We return the number of CCBs successfully created.
151 1.1 dante */
152 1.1 dante static int
153 1.1 dante adw_create_ccbs(sc, ccbstore, count)
154 1.1 dante ADW_SOFTC *sc;
155 1.1 dante ADW_CCB *ccbstore;
156 1.1 dante int count;
157 1.1 dante {
158 1.1 dante ADW_CCB *ccb;
159 1.1 dante int i, error;
160 1.1 dante
161 1.1 dante bzero(ccbstore, sizeof(ADW_CCB) * count);
162 1.1 dante for (i = 0; i < count; i++) {
163 1.1 dante ccb = &ccbstore[i];
164 1.1 dante if ((error = adw_init_ccb(sc, ccb)) != 0) {
165 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
166 1.1 dante sc->sc_dev.dv_xname, error);
167 1.1 dante return (i);
168 1.1 dante }
169 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
170 1.1 dante }
171 1.1 dante
172 1.1 dante return (i);
173 1.1 dante }
174 1.1 dante
175 1.1 dante
176 1.1 dante /*
177 1.1 dante * A ccb is put onto the free list.
178 1.1 dante */
179 1.1 dante static void
180 1.1 dante adw_free_ccb(sc, ccb)
181 1.1 dante ADW_SOFTC *sc;
182 1.1 dante ADW_CCB *ccb;
183 1.1 dante {
184 1.1 dante int s;
185 1.1 dante
186 1.1 dante s = splbio();
187 1.1 dante adw_reset_ccb(ccb);
188 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
189 1.1 dante splx(s);
190 1.1 dante }
191 1.1 dante
192 1.1 dante
193 1.1 dante static void
194 1.1 dante adw_reset_ccb(ccb)
195 1.1 dante ADW_CCB *ccb;
196 1.1 dante {
197 1.1 dante
198 1.1 dante ccb->flags = 0;
199 1.1 dante }
200 1.1 dante
201 1.1 dante
202 1.1 dante static int
203 1.1 dante adw_init_ccb(sc, ccb)
204 1.1 dante ADW_SOFTC *sc;
205 1.1 dante ADW_CCB *ccb;
206 1.1 dante {
207 1.7 dante int hashnum, error;
208 1.1 dante
209 1.1 dante /*
210 1.1 dante * Create the DMA map for this CCB.
211 1.1 dante */
212 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
213 1.1 dante (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
214 1.1 dante ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
215 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
216 1.1 dante if (error) {
217 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
218 1.1 dante sc->sc_dev.dv_xname, error);
219 1.1 dante return (error);
220 1.1 dante }
221 1.7 dante
222 1.7 dante /*
223 1.7 dante * put in the phystokv hash table
224 1.7 dante * Never gets taken out.
225 1.7 dante */
226 1.7 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
227 1.7 dante ADW_CCB_OFF(ccb);
228 1.7 dante hashnum = CCB_HASH(ccb->hashkey);
229 1.7 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
230 1.7 dante sc->sc_ccbhash[hashnum] = ccb;
231 1.1 dante adw_reset_ccb(ccb);
232 1.1 dante return (0);
233 1.1 dante }
234 1.1 dante
235 1.1 dante
236 1.1 dante /*
237 1.1 dante * Get a free ccb
238 1.1 dante *
239 1.1 dante * If there are none, see if we can allocate a new one
240 1.1 dante */
241 1.1 dante static ADW_CCB *
242 1.12.2.2 thorpej adw_get_ccb(sc)
243 1.1 dante ADW_SOFTC *sc;
244 1.1 dante {
245 1.1 dante ADW_CCB *ccb = 0;
246 1.1 dante int s;
247 1.1 dante
248 1.1 dante s = splbio();
249 1.12.2.2 thorpej ccb = TAILQ_FIRST(&sc->sc_free_ccb);
250 1.12.2.2 thorpej if (ccb != NULL) {
251 1.12.2.2 thorpej TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
252 1.12.2.2 thorpej ccb->flags |= CCB_ALLOC;
253 1.1 dante }
254 1.1 dante splx(s);
255 1.1 dante return (ccb);
256 1.1 dante }
257 1.1 dante
258 1.1 dante
259 1.1 dante /*
260 1.7 dante * Given a physical address, find the ccb that it corresponds to.
261 1.7 dante */
262 1.7 dante ADW_CCB *
263 1.7 dante adw_ccb_phys_kv(sc, ccb_phys)
264 1.7 dante ADW_SOFTC *sc;
265 1.9 thorpej u_int32_t ccb_phys;
266 1.7 dante {
267 1.7 dante int hashnum = CCB_HASH(ccb_phys);
268 1.7 dante ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
269 1.7 dante
270 1.7 dante while (ccb) {
271 1.7 dante if (ccb->hashkey == ccb_phys)
272 1.7 dante break;
273 1.7 dante ccb = ccb->nexthash;
274 1.7 dante }
275 1.7 dante return (ccb);
276 1.7 dante }
277 1.7 dante
278 1.7 dante
279 1.7 dante /*
280 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
281 1.1 dante */
282 1.1 dante static void
283 1.1 dante adw_queue_ccb(sc, ccb)
284 1.1 dante ADW_SOFTC *sc;
285 1.1 dante ADW_CCB *ccb;
286 1.1 dante {
287 1.11 dante int s;
288 1.1 dante
289 1.11 dante s = splbio();
290 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
291 1.11 dante splx(s);
292 1.1 dante
293 1.1 dante adw_start_ccbs(sc);
294 1.1 dante }
295 1.1 dante
296 1.1 dante
297 1.1 dante static void
298 1.1 dante adw_start_ccbs(sc)
299 1.1 dante ADW_SOFTC *sc;
300 1.1 dante {
301 1.1 dante ADW_CCB *ccb;
302 1.11 dante int s;
303 1.1 dante
304 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
305 1.1 dante
306 1.11 dante while (AdvExeScsiQueue(sc, &ccb->scsiq) == ADW_BUSY);
307 1.11 dante
308 1.11 dante s = splbio();
309 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
310 1.11 dante splx(s);
311 1.1 dante
312 1.12 thorpej if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
313 1.1 dante timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000);
314 1.1 dante }
315 1.1 dante }
316 1.1 dante
317 1.1 dante
318 1.1 dante /******************************************************************************/
319 1.7 dante /* SCSI layer interfacing routines */
320 1.1 dante /******************************************************************************/
321 1.1 dante
322 1.1 dante
323 1.1 dante int
324 1.1 dante adw_init(sc)
325 1.1 dante ADW_SOFTC *sc;
326 1.1 dante {
327 1.2 dante u_int16_t warn_code;
328 1.1 dante
329 1.1 dante
330 1.1 dante sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
331 1.2 dante ADW_LIB_VERSION_MINOR;
332 1.1 dante sc->cfg.chip_version =
333 1.1 dante ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
334 1.1 dante
335 1.1 dante /*
336 1.1 dante * Reset the chip to start and allow register writes.
337 1.1 dante */
338 1.1 dante if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
339 1.1 dante panic("adw_init: adw_find_signature failed");
340 1.2 dante } else {
341 1.1 dante AdvResetChip(sc->sc_iot, sc->sc_ioh);
342 1.1 dante
343 1.1 dante warn_code = AdvInitFromEEP(sc);
344 1.2 dante if (warn_code & ASC_WARN_EEPROM_CHKSUM)
345 1.1 dante printf("%s: Bad checksum found. "
346 1.2 dante "Setting default values\n",
347 1.2 dante sc->sc_dev.dv_xname);
348 1.2 dante if (warn_code & ASC_WARN_EEPROM_TERMINATION)
349 1.1 dante printf("%s: Bad bus termination setting."
350 1.2 dante "Using automatic termination.\n",
351 1.2 dante sc->sc_dev.dv_xname);
352 1.1 dante
353 1.1 dante /*
354 1.1 dante * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
355 1.1 dante * Resets should be performed.
356 1.1 dante */
357 1.1 dante if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
358 1.1 dante AdvResetSCSIBus(sc);
359 1.1 dante }
360 1.1 dante
361 1.8 dante sc->isr_callback = (ADW_CALLBACK) adw_wide_isr_callback;
362 1.11 dante sc->sbreset_callback = (ADW_CALLBACK) adw_sbreset_callback;
363 1.1 dante
364 1.1 dante return (0);
365 1.1 dante }
366 1.1 dante
367 1.1 dante
368 1.1 dante void
369 1.1 dante adw_attach(sc)
370 1.1 dante ADW_SOFTC *sc;
371 1.1 dante {
372 1.12.2.1 thorpej struct scsipi_adapter *adapt = &sc->sc_adapter;
373 1.12.2.1 thorpej struct scsipi_channel *chan = &sc->sc_channel;
374 1.1 dante int i, error;
375 1.1 dante
376 1.1 dante /*
377 1.1 dante * Initialize the ASC3550.
378 1.1 dante */
379 1.2 dante switch (AdvInitAsc3550Driver(sc)) {
380 1.2 dante case ASC_IERR_MCODE_CHKSUM:
381 1.2 dante panic("%s: Microcode checksum error",
382 1.2 dante sc->sc_dev.dv_xname);
383 1.2 dante break;
384 1.2 dante
385 1.2 dante case ASC_IERR_ILLEGAL_CONNECTION:
386 1.2 dante panic("%s: All three connectors are in use",
387 1.2 dante sc->sc_dev.dv_xname);
388 1.2 dante break;
389 1.2 dante
390 1.2 dante case ASC_IERR_REVERSED_CABLE:
391 1.2 dante panic("%s: Cable is reversed",
392 1.2 dante sc->sc_dev.dv_xname);
393 1.2 dante break;
394 1.2 dante
395 1.2 dante case ASC_IERR_SINGLE_END_DEVICE:
396 1.2 dante panic("%s: single-ended device is attached to"
397 1.2 dante " one of the connectors",
398 1.2 dante sc->sc_dev.dv_xname);
399 1.2 dante break;
400 1.1 dante }
401 1.1 dante
402 1.4 thorpej /*
403 1.12.2.1 thorpej * Fill in the scsipi_adapter.
404 1.4 thorpej */
405 1.12.2.1 thorpej memset(adapt, 0, sizeof(*adapt));
406 1.12.2.1 thorpej adapt->adapt_dev = &sc->sc_dev;
407 1.12.2.1 thorpej adapt->adapt_nchannels = 1;
408 1.12.2.1 thorpej /* adapt_openings filled in below */
409 1.12.2.1 thorpej /* adapt_max_periph filled in below */
410 1.12.2.1 thorpej adapt->adapt_request = adw_scsipi_request;
411 1.12.2.1 thorpej adapt->adapt_minphys = adwminphys;
412 1.1 dante
413 1.1 dante /*
414 1.12.2.1 thorpej * Fill in the scsipi_channel.
415 1.12.2.1 thorpej */
416 1.12.2.1 thorpej memset(chan, 0, sizeof(*chan));
417 1.12.2.1 thorpej chan->chan_adapter = adapt;
418 1.12.2.1 thorpej chan->chan_bustype = &scsi_bustype;
419 1.12.2.1 thorpej chan->chan_channel = 0;
420 1.12.2.1 thorpej chan->chan_ntargets = ADW_MAX_TID + 1;
421 1.12.2.1 thorpej chan->chan_nluns = 7;
422 1.12.2.1 thorpej chan->chan_id = sc->chip_scsi_id;
423 1.1 dante
424 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
425 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
426 1.1 dante
427 1.1 dante /*
428 1.1 dante * Allocate the Control Blocks.
429 1.1 dante */
430 1.1 dante error = adw_alloc_ccbs(sc);
431 1.1 dante if (error)
432 1.1 dante return; /* (error) */ ;
433 1.1 dante
434 1.1 dante /*
435 1.1 dante * Create and initialize the Control Blocks.
436 1.1 dante */
437 1.1 dante i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
438 1.1 dante if (i == 0) {
439 1.1 dante printf("%s: unable to create control blocks\n",
440 1.1 dante sc->sc_dev.dv_xname);
441 1.1 dante return; /* (ENOMEM) */ ;
442 1.1 dante } else if (i != ADW_MAX_CCB) {
443 1.1 dante printf("%s: WARNING: only %d of %d control blocks"
444 1.2 dante " created\n",
445 1.2 dante sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
446 1.1 dante }
447 1.12.2.1 thorpej
448 1.12.2.1 thorpej adapt->adapt_openings = i;
449 1.12.2.1 thorpej adapt->adapt_max_periph = adapt->adapt_openings;
450 1.12.2.1 thorpej
451 1.12.2.1 thorpej config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
452 1.1 dante }
453 1.1 dante
454 1.1 dante
455 1.1 dante static void
456 1.1 dante adwminphys(bp)
457 1.1 dante struct buf *bp;
458 1.1 dante {
459 1.1 dante
460 1.1 dante if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
461 1.1 dante bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
462 1.1 dante minphys(bp);
463 1.1 dante }
464 1.1 dante
465 1.1 dante
466 1.1 dante /*
467 1.2 dante * start a scsi operation given the command and the data address.
468 1.2 dante * Also needs the unit, target and lu.
469 1.1 dante */
470 1.12.2.1 thorpej static void
471 1.12.2.1 thorpej adw_scsipi_request(chan, req, arg)
472 1.12.2.1 thorpej struct scsipi_channel *chan;
473 1.12.2.1 thorpej scsipi_adapter_req_t req;
474 1.12.2.1 thorpej void *arg;
475 1.1 dante {
476 1.12.2.1 thorpej struct scsipi_xfer *xs;
477 1.12.2.1 thorpej ADW_SOFTC *sc = (void *)chan->chan_adapter->adapt_dev;
478 1.1 dante ADW_CCB *ccb;
479 1.1 dante
480 1.12.2.1 thorpej switch (req) {
481 1.12.2.1 thorpej case ADAPTER_REQ_RUN_XFER:
482 1.12.2.1 thorpej xs = arg;
483 1.1 dante
484 1.1 dante /*
485 1.12.2.1 thorpej * Get a CCB to use.
486 1.12.2.1 thorpej */
487 1.12.2.2 thorpej ccb = adw_get_ccb(sc);
488 1.12.2.1 thorpej #ifdef DIAGNOSTIC
489 1.1 dante /*
490 1.12.2.1 thorpej * This should never happen as we track the resources
491 1.12.2.1 thorpej * in the mid-layer.
492 1.12.2.1 thorpej */
493 1.12.2.1 thorpej if (ccb == NULL) {
494 1.12.2.1 thorpej scsipi_printaddr(xs->xs_periph);
495 1.12.2.1 thorpej printf("unable to allocate ccb\n");
496 1.12.2.1 thorpej panic("adw_scsipi_request");
497 1.1 dante }
498 1.12.2.1 thorpej #endif
499 1.1 dante
500 1.12.2.1 thorpej ccb->xs = xs;
501 1.12.2.1 thorpej ccb->timeout = xs->timeout;
502 1.1 dante
503 1.12.2.1 thorpej if (adw_build_req(sc, ccb)) {
504 1.12.2.1 thorpej adw_queue_ccb(sc, ccb);
505 1.1 dante
506 1.12.2.1 thorpej if ((xs->xs_control & XS_CTL_POLL) == 0)
507 1.12.2.1 thorpej return;
508 1.1 dante
509 1.12.2.1 thorpej /*
510 1.12.2.1 thorpej * Not allowed to use interrupts, poll for completion.
511 1.12.2.1 thorpej */
512 1.12.2.1 thorpej if (adw_poll(sc, xs, ccb->timeout)) {
513 1.1 dante adw_timeout(ccb);
514 1.12.2.1 thorpej if (adw_poll(sc, xs, ccb->timeout))
515 1.12.2.1 thorpej adw_timeout(ccb);
516 1.12.2.1 thorpej }
517 1.1 dante }
518 1.12.2.1 thorpej return;
519 1.12.2.1 thorpej
520 1.12.2.1 thorpej case ADAPTER_REQ_GROW_RESOURCES:
521 1.12.2.1 thorpej /* XXX Not supported. */
522 1.12.2.1 thorpej return;
523 1.12.2.1 thorpej
524 1.12.2.1 thorpej case ADAPTER_REQ_SET_XFER_MODE:
525 1.12.2.1 thorpej /* XXX XXX XXX */
526 1.12.2.1 thorpej return;
527 1.12.2.1 thorpej
528 1.12.2.1 thorpej case ADAPTER_REQ_GET_XFER_MODE:
529 1.12.2.1 thorpej /* XXX XXX XXX */
530 1.12.2.1 thorpej return;
531 1.1 dante }
532 1.1 dante }
533 1.1 dante
534 1.1 dante /*
535 1.1 dante * Build a request structure for the Wide Boards.
536 1.1 dante */
537 1.1 dante static int
538 1.12.2.1 thorpej adw_build_req(sc, ccb)
539 1.12.2.1 thorpej ADW_SOFTC *sc;
540 1.12.2.1 thorpej ADW_CCB *ccb;
541 1.1 dante {
542 1.12.2.1 thorpej struct scsipi_xfer *xs = ccb->xs;
543 1.12.2.1 thorpej struct scsipi_periph *periph = xs->xs_periph;
544 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
545 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
546 1.2 dante int error;
547 1.1 dante
548 1.1 dante scsiqp = &ccb->scsiq;
549 1.1 dante bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
550 1.1 dante
551 1.1 dante /*
552 1.7 dante * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
553 1.7 dante * physical CCB structure.
554 1.1 dante */
555 1.10 thorpej scsiqp->ccb_ptr = ccb->hashkey;
556 1.1 dante
557 1.1 dante /*
558 1.1 dante * Build the ADW_SCSI_REQ_Q request.
559 1.1 dante */
560 1.1 dante
561 1.1 dante /*
562 1.1 dante * Set CDB length and copy it to the request structure.
563 1.1 dante */
564 1.1 dante bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen);
565 1.1 dante
566 1.12.2.1 thorpej scsiqp->target_id = periph->periph_target;
567 1.12.2.1 thorpej scsiqp->target_lun = periph->periph_lun;
568 1.1 dante
569 1.7 dante scsiqp->vsense_addr = &ccb->scsi_sense;
570 1.10 thorpej scsiqp->sense_addr = ccb->hashkey +
571 1.10 thorpej offsetof(struct adw_ccb, scsi_sense);
572 1.1 dante scsiqp->sense_len = sizeof(struct scsipi_sense_data);
573 1.1 dante
574 1.1 dante /*
575 1.1 dante * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
576 1.1 dante */
577 1.1 dante if (xs->datalen) {
578 1.1 dante /*
579 1.1 dante * Map the DMA transfer.
580 1.1 dante */
581 1.1 dante #ifdef TFS
582 1.12 thorpej if (xs->xs_control & SCSI_DATA_UIO) {
583 1.1 dante error = bus_dmamap_load_uio(dmat,
584 1.12.2.1 thorpej ccb->dmamap_xfer, (struct uio *) xs->data,
585 1.12.2.1 thorpej (xs->xs_control & XS_CTL_NOSLEEP) ?
586 1.12.2.1 thorpej BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
587 1.1 dante } else
588 1.12.2.1 thorpej #endif /* TFS */
589 1.1 dante {
590 1.1 dante error = bus_dmamap_load(dmat,
591 1.12.2.1 thorpej ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
592 1.12.2.1 thorpej (xs->xs_control & XS_CTL_NOSLEEP) ?
593 1.12.2.1 thorpej BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
594 1.1 dante }
595 1.1 dante
596 1.1 dante if (error) {
597 1.1 dante if (error == EFBIG) {
598 1.12.2.1 thorpej printf("%s: adw_scsipi_request, more than "
599 1.12.2.1 thorpej "%d dma segments\n",
600 1.12.2.1 thorpej sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
601 1.1 dante } else {
602 1.12.2.1 thorpej printf("%s: adw_scsipi_request, error %d "
603 1.12.2.1 thorpej "loading dma map\n",
604 1.12.2.1 thorpej sc->sc_dev.dv_xname, error);
605 1.1 dante }
606 1.1 dante
607 1.1 dante adw_free_ccb(sc, ccb);
608 1.12.2.1 thorpej xs->error = XS_DRIVER_STUFFUP;
609 1.12.2.1 thorpej scsipi_done(xs);
610 1.1 dante return (0);
611 1.1 dante }
612 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
613 1.12.2.1 thorpej ccb->dmamap_xfer->dm_mapsize,
614 1.12.2.1 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
615 1.12.2.1 thorpej BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
616 1.1 dante
617 1.1 dante /*
618 1.1 dante * Build scatter-gather list.
619 1.1 dante */
620 1.1 dante scsiqp->data_cnt = xs->datalen;
621 1.7 dante scsiqp->vdata_addr = xs->data;
622 1.1 dante scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
623 1.7 dante bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
624 1.7 dante adw_build_sglist(ccb, scsiqp, ccb->sg_block);
625 1.1 dante } else {
626 1.1 dante /*
627 1.1 dante * No data xfer, use non S/G values.
628 1.1 dante */
629 1.1 dante scsiqp->data_cnt = 0;
630 1.1 dante scsiqp->vdata_addr = 0;
631 1.1 dante scsiqp->data_addr = 0;
632 1.1 dante }
633 1.1 dante
634 1.1 dante return (1);
635 1.1 dante }
636 1.1 dante
637 1.1 dante
638 1.1 dante /*
639 1.1 dante * Build scatter-gather list for Wide Boards.
640 1.1 dante */
641 1.1 dante static void
642 1.7 dante adw_build_sglist(ccb, scsiqp, sg_block)
643 1.2 dante ADW_CCB *ccb;
644 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
645 1.7 dante ADW_SG_BLOCK *sg_block;
646 1.1 dante {
647 1.9 thorpej u_long sg_block_next_addr; /* block and its next */
648 1.9 thorpej u_int32_t sg_block_physical_addr;
649 1.2 dante int sg_block_index, i; /* how many SG entries */
650 1.1 dante bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
651 1.2 dante int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
652 1.1 dante
653 1.1 dante
654 1.9 thorpej sg_block_next_addr = (u_long) sg_block; /* allow math operation */
655 1.10 thorpej sg_block_physical_addr = ccb->hashkey +
656 1.10 thorpej offsetof(struct adw_ccb, sg_block[0]);
657 1.1 dante scsiqp->sg_real_addr = sg_block_physical_addr;
658 1.1 dante
659 1.1 dante /*
660 1.1 dante * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
661 1.1 dante * then split the request into multiple sg-list blocks.
662 1.1 dante */
663 1.1 dante
664 1.1 dante sg_block_index = 0;
665 1.2 dante do {
666 1.1 dante sg_block->first_entry_no = sg_block_index;
667 1.2 dante for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
668 1.1 dante sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
669 1.1 dante sg_block->sg_list[i].sg_count = sg_list->ds_len;
670 1.1 dante
671 1.2 dante if (--sg_elem_cnt == 0) {
672 1.1 dante /* last entry, get out */
673 1.1 dante scsiqp->sg_entry_cnt = sg_block_index + i + 1;
674 1.1 dante sg_block->last_entry_no = sg_block_index + i;
675 1.2 dante sg_block->sg_ptr = NULL; /* next link = NULL */
676 1.1 dante return;
677 1.1 dante }
678 1.1 dante sg_list++;
679 1.1 dante }
680 1.1 dante sg_block_next_addr += sizeof(ADW_SG_BLOCK);
681 1.1 dante sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
682 1.1 dante
683 1.1 dante sg_block_index += NO_OF_SG_PER_BLOCK;
684 1.9 thorpej sg_block->sg_ptr = sg_block_physical_addr;
685 1.1 dante sg_block->last_entry_no = sg_block_index - 1;
686 1.2 dante sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
687 1.10 thorpej } while (1);
688 1.1 dante }
689 1.1 dante
690 1.1 dante
691 1.1 dante int
692 1.1 dante adw_intr(arg)
693 1.1 dante void *arg;
694 1.1 dante {
695 1.1 dante ADW_SOFTC *sc = arg;
696 1.1 dante
697 1.1 dante AdvISR(sc);
698 1.1 dante return (1);
699 1.1 dante }
700 1.1 dante
701 1.1 dante
702 1.1 dante /*
703 1.1 dante * Poll a particular unit, looking for a particular xs
704 1.1 dante */
705 1.1 dante static int
706 1.1 dante adw_poll(sc, xs, count)
707 1.1 dante ADW_SOFTC *sc;
708 1.1 dante struct scsipi_xfer *xs;
709 1.1 dante int count;
710 1.1 dante {
711 1.1 dante
712 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
713 1.1 dante while (count) {
714 1.1 dante adw_intr(sc);
715 1.12 thorpej if (xs->xs_status & XS_STS_DONE)
716 1.1 dante return (0);
717 1.1 dante delay(1000); /* only happens in boot so ok */
718 1.1 dante count--;
719 1.1 dante }
720 1.1 dante return (1);
721 1.1 dante }
722 1.1 dante
723 1.1 dante
724 1.1 dante static void
725 1.1 dante adw_timeout(arg)
726 1.1 dante void *arg;
727 1.1 dante {
728 1.1 dante ADW_CCB *ccb = arg;
729 1.1 dante struct scsipi_xfer *xs = ccb->xs;
730 1.12.2.1 thorpej struct scsipi_periph *periph = xs->xs_periph;
731 1.12.2.1 thorpej ADW_SOFTC *sc =
732 1.12.2.1 thorpej (void *)periph->periph_channel->chan_adapter->adapt_dev;
733 1.1 dante int s;
734 1.1 dante
735 1.12.2.1 thorpej scsipi_printaddr(periph);
736 1.1 dante printf("timed out");
737 1.1 dante
738 1.1 dante s = splbio();
739 1.1 dante
740 1.1 dante /*
741 1.1 dante * If it has been through before, then a previous abort has failed,
742 1.1 dante * don't try abort again, reset the bus instead.
743 1.1 dante */
744 1.11 dante if (ccb->flags & CCB_ABORTED) {
745 1.11 dante /*
746 1.11 dante * Abort Timed Out
747 1.11 dante * Lets try resetting the bus!
748 1.11 dante */
749 1.11 dante printf(" AGAIN. Resetting SCSI Bus\n");
750 1.11 dante ccb->flags &= ~CCB_ABORTED;
751 1.11 dante /* AdvResetSCSIBus() will call sbreset_callback() */
752 1.1 dante AdvResetSCSIBus(sc);
753 1.1 dante } else {
754 1.11 dante /*
755 1.11 dante * Abort the operation that has timed out
756 1.11 dante */
757 1.1 dante printf("\n");
758 1.11 dante xs->error = XS_TIMEOUT;
759 1.11 dante ccb->flags |= CCB_ABORTING;
760 1.11 dante /* ADW_ABORT_CCB() will implicitly call isr_callback() */
761 1.1 dante ADW_ABORT_CCB(sc, ccb);
762 1.1 dante }
763 1.1 dante
764 1.1 dante splx(s);
765 1.1 dante }
766 1.1 dante
767 1.1 dante
768 1.1 dante /******************************************************************************/
769 1.7 dante /* WIDE boards Interrupt callbacks */
770 1.1 dante /******************************************************************************/
771 1.1 dante
772 1.1 dante
773 1.1 dante /*
774 1.1 dante * adw_wide_isr_callback() - Second Level Interrupt Handler called by AdvISR()
775 1.1 dante *
776 1.1 dante * Interrupt callback function for the Wide SCSI Adv Library.
777 1.1 dante */
778 1.1 dante static void
779 1.1 dante adw_wide_isr_callback(sc, scsiq)
780 1.1 dante ADW_SOFTC *sc;
781 1.1 dante ADW_SCSI_REQ_Q *scsiq;
782 1.1 dante {
783 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
784 1.7 dante ADW_CCB *ccb;
785 1.7 dante struct scsipi_xfer *xs;
786 1.1 dante struct scsipi_sense_data *s1, *s2;
787 1.11 dante int s;
788 1.2 dante //int underrun = ASC_FALSE;
789 1.1 dante
790 1.7 dante
791 1.7 dante ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
792 1.11 dante
793 1.11 dante untimeout(adw_timeout, ccb);
794 1.11 dante
795 1.11 dante if(ccb->flags & CCB_ABORTING) {
796 1.11 dante printf("Retrying request\n");
797 1.11 dante ccb->flags &= ~CCB_ABORTING;
798 1.11 dante ccb->flags |= CCB_ABORTED;
799 1.11 dante s = splbio();
800 1.11 dante adw_queue_ccb(sc, ccb);
801 1.11 dante splx(s);
802 1.11 dante return;
803 1.11 dante }
804 1.11 dante
805 1.7 dante xs = ccb->xs;
806 1.1 dante
807 1.1 dante
808 1.1 dante /*
809 1.1 dante * If we were a data transfer, unload the map that described
810 1.1 dante * the data buffer.
811 1.1 dante */
812 1.1 dante if (xs->datalen) {
813 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
814 1.1 dante ccb->dmamap_xfer->dm_mapsize,
815 1.12 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
816 1.12 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
817 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
818 1.1 dante }
819 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
820 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
821 1.1 dante Debugger();
822 1.1 dante return;
823 1.1 dante }
824 1.1 dante /*
825 1.1 dante * Check for an underrun condition.
826 1.1 dante */
827 1.2 dante /*
828 1.2 dante * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
829 1.2 dante * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
830 1.2 dante * scsiqp->data_cnt); underrun = ASC_TRUE; }
831 1.2 dante */
832 1.1 dante /*
833 1.1 dante * 'done_status' contains the command's ending status.
834 1.1 dante */
835 1.1 dante switch (scsiq->done_status) {
836 1.1 dante case QD_NO_ERROR:
837 1.1 dante switch (scsiq->host_status) {
838 1.1 dante case QHSTA_NO_ERROR:
839 1.1 dante xs->error = XS_NOERROR;
840 1.1 dante xs->resid = 0;
841 1.1 dante break;
842 1.11 dante case QHSTA_M_SEL_TIMEOUT:
843 1.1 dante default:
844 1.1 dante /* QHSTA error occurred. */
845 1.1 dante xs->error = XS_DRIVER_STUFFUP;
846 1.1 dante break;
847 1.1 dante }
848 1.1 dante /*
849 1.1 dante * If there was an underrun without any other error,
850 1.1 dante * set DID_ERROR to indicate the underrun error.
851 1.1 dante *
852 1.1 dante * Note: There is no way yet to indicate the number
853 1.1 dante * of underrun bytes.
854 1.1 dante */
855 1.2 dante /*
856 1.2 dante * if (xs->error == XS_NOERROR && underrun == ASC_TRUE) {
857 1.2 dante * scp->result = HOST_BYTE(DID_UNDERRUN); }
858 1.2 dante */ break;
859 1.1 dante
860 1.1 dante case QD_WITH_ERROR:
861 1.1 dante switch (scsiq->host_status) {
862 1.1 dante case QHSTA_NO_ERROR:
863 1.11 dante switch(scsiq->scsi_status) {
864 1.11 dante case SS_CHK_CONDITION:
865 1.11 dante case SS_CMD_TERMINATED:
866 1.1 dante s1 = &ccb->scsi_sense;
867 1.1 dante s2 = &xs->sense.scsi_sense;
868 1.1 dante *s2 = *s1;
869 1.1 dante xs->error = XS_SENSE;
870 1.11 dante break;
871 1.11 dante case SS_TARGET_BUSY:
872 1.11 dante case SS_RSERV_CONFLICT:
873 1.11 dante case SS_QUEUE_FULL:
874 1.11 dante xs->error = XS_DRIVER_STUFFUP;
875 1.11 dante break;
876 1.11 dante case SS_CONDITION_MET:
877 1.11 dante case SS_INTERMID:
878 1.11 dante case SS_INTERMID_COND_MET:
879 1.1 dante xs->error = XS_DRIVER_STUFFUP;
880 1.11 dante break;
881 1.11 dante case SS_GOOD:
882 1.11 dante break;
883 1.1 dante }
884 1.1 dante break;
885 1.1 dante
886 1.11 dante case QHSTA_M_SEL_TIMEOUT:
887 1.11 dante xs->error = XS_DRIVER_STUFFUP;
888 1.11 dante break;
889 1.11 dante
890 1.1 dante default:
891 1.1 dante /* Some other QHSTA error occurred. */
892 1.1 dante xs->error = XS_DRIVER_STUFFUP;
893 1.1 dante break;
894 1.1 dante }
895 1.1 dante break;
896 1.1 dante
897 1.1 dante case QD_ABORTED_BY_HOST:
898 1.11 dante xs->error = XS_DRIVER_STUFFUP;
899 1.11 dante break;
900 1.11 dante
901 1.1 dante default:
902 1.1 dante xs->error = XS_DRIVER_STUFFUP;
903 1.1 dante break;
904 1.1 dante }
905 1.1 dante
906 1.1 dante adw_free_ccb(sc, ccb);
907 1.12 thorpej xs->xs_status |= XS_STS_DONE;
908 1.1 dante scsipi_done(xs);
909 1.11 dante }
910 1.11 dante
911 1.11 dante
912 1.11 dante static void
913 1.11 dante adw_sbreset_callback(sc)
914 1.11 dante ADW_SOFTC *sc;
915 1.11 dante {
916 1.1 dante }
917