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adw.c revision 1.13
      1  1.13    dante /* $NetBSD: adw.c,v 1.13 2000/02/03 20:29:15 dante Exp $	 */
      2   1.1    dante 
      3   1.1    dante /*
      4   1.1    dante  * Generic driver for the Advanced Systems Inc. SCSI controllers
      5   1.1    dante  *
      6  1.13    dante  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
      7   1.1    dante  * All rights reserved.
      8   1.1    dante  *
      9   1.1    dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10   1.1    dante  *
     11   1.1    dante  * Redistribution and use in source and binary forms, with or without
     12   1.1    dante  * modification, are permitted provided that the following conditions
     13   1.1    dante  * are met:
     14   1.1    dante  * 1. Redistributions of source code must retain the above copyright
     15   1.1    dante  *    notice, this list of conditions and the following disclaimer.
     16   1.1    dante  * 2. Redistributions in binary form must reproduce the above copyright
     17   1.1    dante  *    notice, this list of conditions and the following disclaimer in the
     18   1.1    dante  *    documentation and/or other materials provided with the distribution.
     19   1.1    dante  * 3. All advertising materials mentioning features or use of this software
     20   1.1    dante  *    must display the following acknowledgement:
     21   1.1    dante  *        This product includes software developed by the NetBSD
     22   1.1    dante  *        Foundation, Inc. and its contributors.
     23   1.1    dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24   1.1    dante  *    contributors may be used to endorse or promote products derived
     25   1.1    dante  *    from this software without specific prior written permission.
     26   1.1    dante  *
     27   1.1    dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28   1.1    dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29   1.1    dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30   1.1    dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31   1.1    dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32   1.1    dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33   1.1    dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34   1.1    dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35   1.1    dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36   1.1    dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37   1.1    dante  * POSSIBILITY OF SUCH DAMAGE.
     38   1.1    dante  */
     39   1.1    dante 
     40   1.1    dante #include <sys/types.h>
     41   1.1    dante #include <sys/param.h>
     42   1.1    dante #include <sys/systm.h>
     43   1.1    dante #include <sys/kernel.h>
     44   1.1    dante #include <sys/errno.h>
     45   1.1    dante #include <sys/ioctl.h>
     46   1.1    dante #include <sys/device.h>
     47   1.1    dante #include <sys/malloc.h>
     48   1.1    dante #include <sys/buf.h>
     49   1.1    dante #include <sys/proc.h>
     50   1.1    dante #include <sys/user.h>
     51   1.1    dante 
     52   1.1    dante #include <machine/bus.h>
     53   1.1    dante #include <machine/intr.h>
     54   1.1    dante 
     55   1.1    dante #include <vm/vm.h>
     56   1.1    dante #include <vm/vm_param.h>
     57   1.1    dante #include <vm/pmap.h>
     58   1.1    dante 
     59   1.1    dante #include <dev/scsipi/scsi_all.h>
     60   1.1    dante #include <dev/scsipi/scsipi_all.h>
     61   1.1    dante #include <dev/scsipi/scsiconf.h>
     62   1.1    dante 
     63   1.1    dante #include <dev/ic/adwlib.h>
     64   1.1    dante #include <dev/ic/adw.h>
     65   1.1    dante 
     66   1.1    dante #ifndef DDB
     67  1.11    dante #define	Debugger()	panic("should call debugger here (adw.c)")
     68   1.2    dante #endif				/* ! DDB */
     69   1.1    dante 
     70   1.1    dante /******************************************************************************/
     71   1.1    dante 
     72   1.1    dante 
     73  1.13    dante static int adw_alloc_controls __P((ADW_SOFTC *));
     74  1.13    dante static int adw_alloc_carriers __P((ADW_SOFTC *));
     75  1.13    dante static int adw_create_carriers __P((ADW_SOFTC *));
     76  1.13    dante static int adw_init_carrier __P((ADW_SOFTC *, ADW_CARRIER *));
     77   1.1    dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
     78   1.1    dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
     79   1.1    dante static void adw_reset_ccb __P((ADW_CCB *));
     80   1.1    dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
     81   1.1    dante static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int));
     82  1.13    dante static int adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *, int));
     83   1.1    dante 
     84   1.1    dante static int adw_scsi_cmd __P((struct scsipi_xfer *));
     85   1.1    dante static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *));
     86   1.7    dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *));
     87   1.1    dante static void adwminphys __P((struct buf *));
     88  1.13    dante static void adw_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
     89  1.13    dante static void adw_async_callback __P((ADW_SOFTC *, u_int8_t));
     90   1.1    dante 
     91   1.1    dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
     92   1.1    dante static void adw_timeout __P((void *));
     93   1.1    dante 
     94   1.1    dante 
     95   1.1    dante /******************************************************************************/
     96   1.1    dante 
     97   1.1    dante 
     98   1.1    dante /* the below structure is so we have a default dev struct for out link struct */
     99   1.1    dante struct scsipi_device adw_dev =
    100   1.1    dante {
    101   1.1    dante 	NULL,			/* Use default error handler */
    102   1.1    dante 	NULL,			/* have a queue, served by this */
    103   1.1    dante 	NULL,			/* have no async handler */
    104   1.1    dante 	NULL,			/* Use default 'done' routine */
    105   1.1    dante };
    106   1.1    dante 
    107   1.1    dante 
    108   1.1    dante #define ADW_ABORT_TIMEOUT       10000	/* time to wait for abort (mSec) */
    109   1.1    dante #define ADW_WATCH_TIMEOUT       10000	/* time to wait for watchdog (mSec) */
    110   1.1    dante 
    111   1.1    dante 
    112   1.1    dante /******************************************************************************/
    113   1.7    dante /*                                Control Blocks routines                     */
    114   1.1    dante /******************************************************************************/
    115   1.1    dante 
    116   1.1    dante 
    117   1.1    dante static int
    118  1.13    dante adw_alloc_controls(sc)
    119   1.1    dante 	ADW_SOFTC      *sc;
    120   1.1    dante {
    121   1.1    dante 	bus_dma_segment_t seg;
    122   1.1    dante 	int             error, rseg;
    123   1.1    dante 
    124   1.1    dante 	/*
    125  1.13    dante          * Allocate the control structure.
    126   1.1    dante          */
    127   1.1    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
    128   1.1    dante 			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    129   1.1    dante 		printf("%s: unable to allocate control structures,"
    130   1.1    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    131   1.1    dante 		return (error);
    132   1.1    dante 	}
    133   1.1    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    134   1.1    dante 		   sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
    135   1.1    dante 				 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    136   1.1    dante 		printf("%s: unable to map control structures, error = %d\n",
    137   1.1    dante 		       sc->sc_dev.dv_xname, error);
    138   1.1    dante 		return (error);
    139   1.1    dante 	}
    140  1.13    dante 
    141   1.1    dante 	/*
    142   1.1    dante          * Create and load the DMA map used for the control blocks.
    143   1.1    dante          */
    144   1.1    dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
    145   1.1    dante 			   1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
    146   1.1    dante 				       &sc->sc_dmamap_control)) != 0) {
    147   1.1    dante 		printf("%s: unable to create control DMA map, error = %d\n",
    148   1.1    dante 		       sc->sc_dev.dv_xname, error);
    149   1.1    dante 		return (error);
    150   1.1    dante 	}
    151   1.1    dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    152   1.1    dante 			   sc->sc_control, sizeof(struct adw_control), NULL,
    153   1.1    dante 				     BUS_DMA_NOWAIT)) != 0) {
    154   1.1    dante 		printf("%s: unable to load control DMA map, error = %d\n",
    155   1.1    dante 		       sc->sc_dev.dv_xname, error);
    156   1.1    dante 		return (error);
    157   1.1    dante 	}
    158  1.13    dante 
    159  1.13    dante 	return (0);
    160  1.13    dante }
    161  1.13    dante 
    162  1.13    dante 
    163  1.13    dante static int
    164  1.13    dante adw_alloc_carriers(sc)
    165  1.13    dante 	ADW_SOFTC      *sc;
    166  1.13    dante {
    167  1.13    dante 	bus_dma_segment_t seg;
    168  1.13    dante 	int             error, rseg;
    169  1.13    dante 
    170  1.13    dante 	/*
    171  1.13    dante          * Allocate the control structure.
    172  1.13    dante          */
    173  1.13    dante 	sc->sc_control->carriers = malloc(ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    174  1.13    dante 			M_DEVBUF, M_WAITOK);
    175  1.13    dante 	if(!sc->sc_control->carriers) {
    176  1.13    dante 		printf("%s: malloc() failed in allocating carrier structures,"
    177  1.13    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    178  1.13    dante 		return (error);
    179  1.13    dante 	}
    180  1.13    dante 
    181  1.13    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
    182  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    183  1.13    dante 			NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    184  1.13    dante 		printf("%s: unable to allocate carrier structures,"
    185  1.13    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    186  1.13    dante 		return (error);
    187  1.13    dante 	}
    188  1.13    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    189  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    190  1.13    dante 			(caddr_t *) &sc->sc_control->carriers,
    191  1.13    dante 			BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    192  1.13    dante 		printf("%s: unable to map carrier structures,"
    193  1.13    dante 			" error = %d\n", sc->sc_dev.dv_xname, error);
    194  1.13    dante 		return (error);
    195  1.13    dante 	}
    196  1.13    dante 
    197  1.13    dante 	/*
    198  1.13    dante          * Create and load the DMA map used for the control blocks.
    199  1.13    dante          */
    200  1.13    dante 	if ((error = bus_dmamap_create(sc->sc_dmat,
    201  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 1,
    202  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 0, BUS_DMA_NOWAIT,
    203  1.13    dante 			&sc->sc_dmamap_carrier)) != 0) {
    204  1.13    dante 		printf("%s: unable to create carriers DMA map,"
    205  1.13    dante 			" error = %d\n", sc->sc_dev.dv_xname, error);
    206  1.13    dante 		return (error);
    207  1.13    dante 	}
    208  1.13    dante 	if ((error = bus_dmamap_load(sc->sc_dmat,
    209  1.13    dante 			sc->sc_dmamap_carrier, sc->sc_control->carriers,
    210  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER, NULL,
    211  1.13    dante 			BUS_DMA_NOWAIT)) != 0) {
    212  1.13    dante 		printf("%s: unable to load carriers DMA map,"
    213  1.13    dante 			" error = %d\n", sc->sc_dev.dv_xname, error);
    214  1.13    dante 		return (error);
    215  1.13    dante 	}
    216  1.13    dante 
    217  1.13    dante 	error = bus_dmamap_create(sc->sc_dmat, ADW_CARRIER_SIZE* ADW_MAX_CARRIER,
    218  1.13    dante 			1, ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    219  1.13    dante 			0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
    220  1.13    dante 			&sc->sc_control->dmamap_xfer);
    221  1.13    dante 	if (error) {
    222  1.13    dante 		printf("%s: unable to create Carrier DMA map, error = %d\n",
    223  1.13    dante 		       sc->sc_dev.dv_xname, error);
    224  1.13    dante 		return (error);
    225  1.13    dante 	}
    226  1.13    dante 
    227   1.1    dante 	return (0);
    228   1.1    dante }
    229   1.1    dante 
    230   1.1    dante 
    231   1.1    dante /*
    232  1.13    dante  * Create a set of Carriers and add them to the free list.  Called once
    233  1.13    dante  * by adw_init().  We return the number of Carriers successfully created.
    234  1.13    dante  */
    235  1.13    dante static int
    236  1.13    dante adw_create_carriers(sc)
    237  1.13    dante 	ADW_SOFTC	*sc;
    238  1.13    dante {
    239  1.13    dante 	ADW_CARRIER	*carr;
    240  1.13    dante 	u_int32_t	carr_next = NULL;
    241  1.13    dante 	int		i, error;
    242  1.13    dante 
    243  1.13    dante 	for(i=0; i < ADW_MAX_CARRIER; i++) {
    244  1.13    dante 		carr = (ADW_CARRIER *)(((u_int8_t *)sc->sc_control->carriers) +
    245  1.13    dante 				(ADW_CARRIER_SIZE * i));
    246  1.13    dante 		if ((error = adw_init_carrier(sc, carr)) != 0) {
    247  1.13    dante 			printf("%s: unable to initialize carrier, error = %d\n",
    248  1.13    dante 			       sc->sc_dev.dv_xname, error);
    249  1.13    dante 			return (i);
    250  1.13    dante 		}
    251  1.13    dante 		carr->next_vpa = carr_next;
    252  1.13    dante 		carr_next = carr->carr_pa;
    253  1.13    dante carr->id = i;
    254  1.13    dante 	}
    255  1.13    dante 	sc->carr_freelist = carr;
    256  1.13    dante 	return (i);
    257  1.13    dante }
    258  1.13    dante 
    259  1.13    dante 
    260  1.13    dante static int
    261  1.13    dante adw_init_carrier(sc, carr)
    262  1.13    dante 	ADW_SOFTC	*sc;
    263  1.13    dante 	ADW_CARRIER	*carr;
    264  1.13    dante {
    265  1.13    dante 	u_int32_t	carr_pa;
    266  1.13    dante 	int		/*error, */hashnum;
    267  1.13    dante 
    268  1.13    dante 	/*
    269  1.13    dante          * Create the DMA map for all of the Carriers.
    270  1.13    dante          */
    271  1.13    dante /*	error = bus_dmamap_create(sc->sc_dmat, ADW_CARRIER_SIZE,
    272  1.13    dante 			1, ADW_CARRIER_SIZE,
    273  1.13    dante 			0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
    274  1.13    dante 			&carr->dmamap_xfer);
    275  1.13    dante 	if (error) {
    276  1.13    dante 		printf("%s: unable to create Carrier DMA map, error = %d\n",
    277  1.13    dante 		       sc->sc_dev.dv_xname, error);
    278  1.13    dante 		return (error);
    279  1.13    dante 	}
    280  1.13    dante */
    281  1.13    dante 	/*
    282  1.13    dante 	 * put in the phystokv hash table
    283  1.13    dante 	 * Never gets taken out.
    284  1.13    dante 	 */
    285  1.13    dante 	carr_pa = ADW_CARRIER_ADDR(sc, carr);
    286  1.13    dante 	carr->carr_pa = carr_pa;
    287  1.13    dante 	hashnum = CARRIER_HASH(carr_pa);
    288  1.13    dante 	carr->nexthash = sc->sc_carrhash[hashnum];
    289  1.13    dante 	sc->sc_carrhash[hashnum] = carr;
    290  1.13    dante 
    291  1.13    dante 	return(0);
    292  1.13    dante }
    293  1.13    dante 
    294  1.13    dante 
    295  1.13    dante /*
    296  1.13    dante  * Given a physical address, find the Carrier that it corresponds to.
    297  1.13    dante  */
    298  1.13    dante ADW_CARRIER *
    299  1.13    dante adw_carrier_phys_kv(sc, carr_phys)
    300  1.13    dante 	ADW_SOFTC	*sc;
    301  1.13    dante 	u_int32_t	carr_phys;
    302  1.13    dante {
    303  1.13    dante 	int hashnum = CARRIER_HASH(carr_phys);
    304  1.13    dante 	ADW_CARRIER *carr = sc->sc_carrhash[hashnum];
    305  1.13    dante 
    306  1.13    dante 	while (carr) {
    307  1.13    dante 		if (carr->carr_pa == carr_phys)
    308  1.13    dante 			break;
    309  1.13    dante 		carr = carr->nexthash;
    310  1.13    dante 	}
    311  1.13    dante 	return (carr);
    312  1.13    dante }
    313  1.13    dante 
    314  1.13    dante 
    315  1.13    dante /*
    316   1.1    dante  * Create a set of ccbs and add them to the free list.  Called once
    317   1.1    dante  * by adw_init().  We return the number of CCBs successfully created.
    318   1.1    dante  */
    319   1.1    dante static int
    320   1.1    dante adw_create_ccbs(sc, ccbstore, count)
    321   1.1    dante 	ADW_SOFTC      *sc;
    322   1.1    dante 	ADW_CCB        *ccbstore;
    323   1.1    dante 	int             count;
    324   1.1    dante {
    325   1.1    dante 	ADW_CCB        *ccb;
    326   1.1    dante 	int             i, error;
    327   1.1    dante 
    328   1.1    dante 	for (i = 0; i < count; i++) {
    329   1.1    dante 		ccb = &ccbstore[i];
    330   1.1    dante 		if ((error = adw_init_ccb(sc, ccb)) != 0) {
    331   1.1    dante 			printf("%s: unable to initialize ccb, error = %d\n",
    332   1.1    dante 			       sc->sc_dev.dv_xname, error);
    333   1.1    dante 			return (i);
    334   1.1    dante 		}
    335   1.1    dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    336   1.1    dante 	}
    337   1.1    dante 
    338   1.1    dante 	return (i);
    339   1.1    dante }
    340   1.1    dante 
    341   1.1    dante 
    342   1.1    dante /*
    343   1.1    dante  * A ccb is put onto the free list.
    344   1.1    dante  */
    345   1.1    dante static void
    346   1.1    dante adw_free_ccb(sc, ccb)
    347   1.1    dante 	ADW_SOFTC      *sc;
    348   1.1    dante 	ADW_CCB        *ccb;
    349   1.1    dante {
    350   1.1    dante 	int             s;
    351   1.1    dante 
    352   1.1    dante 	s = splbio();
    353   1.1    dante 
    354   1.1    dante 	adw_reset_ccb(ccb);
    355   1.1    dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    356   1.1    dante 
    357   1.1    dante 	/*
    358   1.1    dante          * If there were none, wake anybody waiting for one to come free,
    359   1.1    dante          * starting with queued entries.
    360   1.1    dante          */
    361   1.1    dante 	if (ccb->chain.tqe_next == 0)
    362   1.1    dante 		wakeup(&sc->sc_free_ccb);
    363   1.1    dante 
    364   1.1    dante 	splx(s);
    365   1.1    dante }
    366   1.1    dante 
    367   1.1    dante 
    368   1.1    dante static void
    369   1.1    dante adw_reset_ccb(ccb)
    370   1.1    dante 	ADW_CCB        *ccb;
    371   1.1    dante {
    372   1.1    dante 
    373   1.1    dante 	ccb->flags = 0;
    374   1.1    dante }
    375   1.1    dante 
    376   1.1    dante 
    377   1.1    dante static int
    378   1.1    dante adw_init_ccb(sc, ccb)
    379   1.1    dante 	ADW_SOFTC      *sc;
    380   1.1    dante 	ADW_CCB        *ccb;
    381   1.1    dante {
    382   1.7    dante 	int	hashnum, error;
    383   1.1    dante 
    384   1.1    dante 	/*
    385   1.1    dante          * Create the DMA map for this CCB.
    386   1.1    dante          */
    387   1.1    dante 	error = bus_dmamap_create(sc->sc_dmat,
    388   1.1    dante 				  (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    389   1.1    dante 			 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    390   1.1    dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    391   1.1    dante 	if (error) {
    392  1.13    dante 		printf("%s: unable to create CCB DMA map, error = %d\n",
    393   1.1    dante 		       sc->sc_dev.dv_xname, error);
    394   1.1    dante 		return (error);
    395   1.1    dante 	}
    396   1.7    dante 
    397   1.7    dante 	/*
    398   1.7    dante 	 * put in the phystokv hash table
    399   1.7    dante 	 * Never gets taken out.
    400   1.7    dante 	 */
    401   1.7    dante 	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    402   1.7    dante 	    ADW_CCB_OFF(ccb);
    403   1.7    dante 	hashnum = CCB_HASH(ccb->hashkey);
    404   1.7    dante 	ccb->nexthash = sc->sc_ccbhash[hashnum];
    405   1.7    dante 	sc->sc_ccbhash[hashnum] = ccb;
    406   1.1    dante 	adw_reset_ccb(ccb);
    407   1.1    dante 	return (0);
    408   1.1    dante }
    409   1.1    dante 
    410   1.1    dante 
    411   1.1    dante /*
    412   1.1    dante  * Get a free ccb
    413   1.1    dante  *
    414   1.1    dante  * If there are none, see if we can allocate a new one
    415   1.1    dante  */
    416   1.1    dante static ADW_CCB *
    417   1.1    dante adw_get_ccb(sc, flags)
    418   1.1    dante 	ADW_SOFTC      *sc;
    419   1.1    dante 	int             flags;
    420   1.1    dante {
    421   1.1    dante 	ADW_CCB        *ccb = 0;
    422   1.1    dante 	int             s;
    423   1.1    dante 
    424   1.1    dante 	s = splbio();
    425   1.1    dante 
    426   1.1    dante 	/*
    427   1.1    dante          * If we can and have to, sleep waiting for one to come free
    428   1.1    dante          * but only if we can't allocate a new one.
    429   1.1    dante          */
    430   1.1    dante 	for (;;) {
    431   1.1    dante 		ccb = sc->sc_free_ccb.tqh_first;
    432   1.1    dante 		if (ccb) {
    433   1.1    dante 			TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    434   1.1    dante 			break;
    435   1.1    dante 		}
    436  1.12  thorpej 		if ((flags & XS_CTL_NOSLEEP) != 0)
    437   1.1    dante 			goto out;
    438   1.1    dante 
    439   1.1    dante 		tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
    440   1.1    dante 	}
    441   1.1    dante 
    442   1.1    dante 	ccb->flags |= CCB_ALLOC;
    443   1.1    dante 
    444   1.1    dante out:
    445   1.1    dante 	splx(s);
    446   1.1    dante 	return (ccb);
    447   1.1    dante }
    448   1.1    dante 
    449   1.1    dante 
    450   1.1    dante /*
    451   1.7    dante  * Given a physical address, find the ccb that it corresponds to.
    452   1.7    dante  */
    453   1.7    dante ADW_CCB *
    454   1.7    dante adw_ccb_phys_kv(sc, ccb_phys)
    455   1.7    dante 	ADW_SOFTC	*sc;
    456   1.9  thorpej 	u_int32_t	ccb_phys;
    457   1.7    dante {
    458   1.7    dante 	int hashnum = CCB_HASH(ccb_phys);
    459   1.7    dante 	ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
    460   1.7    dante 
    461   1.7    dante 	while (ccb) {
    462   1.7    dante 		if (ccb->hashkey == ccb_phys)
    463   1.7    dante 			break;
    464   1.7    dante 		ccb = ccb->nexthash;
    465   1.7    dante 	}
    466   1.7    dante 	return (ccb);
    467   1.7    dante }
    468   1.7    dante 
    469   1.7    dante 
    470   1.7    dante /*
    471   1.1    dante  * Queue a CCB to be sent to the controller, and send it if possible.
    472   1.1    dante  */
    473  1.13    dante static int
    474  1.13    dante adw_queue_ccb(sc, ccb, retry)
    475   1.1    dante 	ADW_SOFTC      *sc;
    476   1.1    dante 	ADW_CCB        *ccb;
    477  1.13    dante 	int		retry;
    478   1.1    dante {
    479  1.13    dante 	int		errcode;
    480   1.1    dante 
    481  1.13    dante 	if(!retry)
    482  1.13    dante 		TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    483   1.1    dante 
    484  1.13    dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    485   1.1    dante 
    486  1.13    dante 		errcode = AdvExeScsiQueue(sc, &ccb->scsiq);
    487  1.13    dante 		switch(errcode) {
    488  1.13    dante 		case ADW_SUCCESS:
    489  1.13    dante 			break;
    490   1.1    dante 
    491  1.13    dante 		case ADW_BUSY:
    492  1.13    dante 			printf("ADW_BUSY\n");
    493  1.13    dante 			return(ADW_BUSY);
    494  1.13    dante 
    495  1.13    dante 		case ADW_ERROR:
    496  1.13    dante 			printf("ADW_ERROR\n");
    497  1.13    dante 			TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    498  1.13    dante 			return(ADW_ERROR);
    499  1.13    dante 		}
    500  1.11    dante 
    501   1.1    dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    502   1.1    dante 
    503  1.12  thorpej 		if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
    504   1.1    dante 			timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000);
    505   1.1    dante 	}
    506  1.13    dante 
    507  1.13    dante 	return(errcode);
    508   1.1    dante }
    509   1.1    dante 
    510   1.1    dante 
    511   1.1    dante /******************************************************************************/
    512   1.7    dante /*                           SCSI layer interfacing routines                  */
    513   1.1    dante /******************************************************************************/
    514   1.1    dante 
    515   1.1    dante 
    516   1.1    dante int
    517   1.1    dante adw_init(sc)
    518   1.1    dante 	ADW_SOFTC      *sc;
    519   1.1    dante {
    520   1.2    dante 	u_int16_t       warn_code;
    521   1.1    dante 
    522   1.1    dante 
    523   1.1    dante 	sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
    524   1.2    dante 		ADW_LIB_VERSION_MINOR;
    525   1.1    dante 	sc->cfg.chip_version =
    526   1.1    dante 		ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
    527   1.1    dante 
    528   1.1    dante 	/*
    529   1.1    dante 	 * Reset the chip to start and allow register writes.
    530   1.1    dante 	 */
    531   1.1    dante 	if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
    532   1.1    dante 		panic("adw_init: adw_find_signature failed");
    533   1.2    dante 	} else {
    534   1.1    dante 		AdvResetChip(sc->sc_iot, sc->sc_ioh);
    535   1.1    dante 
    536  1.13    dante 		warn_code = (sc->chip_type == ADV_CHIP_ASC3550)?
    537  1.13    dante 				AdvInitFrom3550EEP(sc) :
    538  1.13    dante 				AdvInitFrom38C0800EEP(sc);
    539  1.13    dante 
    540   1.2    dante 		if (warn_code & ASC_WARN_EEPROM_CHKSUM)
    541   1.1    dante 			printf("%s: Bad checksum found. "
    542   1.2    dante 			       "Setting default values\n",
    543   1.2    dante 			       sc->sc_dev.dv_xname);
    544   1.2    dante 		if (warn_code & ASC_WARN_EEPROM_TERMINATION)
    545   1.1    dante 			printf("%s: Bad bus termination setting."
    546   1.2    dante 			       "Using automatic termination.\n",
    547   1.2    dante 			       sc->sc_dev.dv_xname);
    548   1.1    dante 	}
    549   1.1    dante 
    550  1.13    dante 	sc->isr_callback = (ADW_CALLBACK) adw_isr_callback;
    551  1.13    dante 	sc->async_callback = (ADW_CALLBACK) adw_async_callback;
    552   1.1    dante 
    553   1.1    dante 	return (0);
    554   1.1    dante }
    555   1.1    dante 
    556   1.1    dante 
    557   1.1    dante void
    558   1.1    dante adw_attach(sc)
    559   1.1    dante 	ADW_SOFTC      *sc;
    560   1.1    dante {
    561   1.1    dante 	int             i, error;
    562   1.1    dante 
    563   1.1    dante 
    564  1.13    dante 	TAILQ_INIT(&sc->sc_free_ccb);
    565  1.13    dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    566  1.13    dante 	TAILQ_INIT(&sc->sc_queue);
    567  1.13    dante 
    568  1.13    dante 
    569  1.13    dante 	/*
    570  1.13    dante          * Allocate the Control Blocks.
    571  1.13    dante          */
    572  1.13    dante 	error = adw_alloc_controls(sc);
    573  1.13    dante 	if (error)
    574  1.13    dante 		return; /* (error) */ ;
    575  1.13    dante 
    576  1.13    dante 	bzero(sc->sc_control, sizeof(struct adw_control));
    577  1.13    dante 
    578  1.13    dante 	/*
    579  1.13    dante 	 * Create and initialize the Control Blocks.
    580  1.13    dante 	 */
    581  1.13    dante 	i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
    582  1.13    dante 	if (i == 0) {
    583  1.13    dante 		printf("%s: unable to create Control Blocks\n",
    584  1.13    dante 		       sc->sc_dev.dv_xname);
    585  1.13    dante 		return; /* (ENOMEM) */ ;
    586  1.13    dante 	} else if (i != ADW_MAX_CCB) {
    587  1.13    dante 		printf("%s: WARNING: only %d of %d Control Blocks"
    588  1.13    dante 		       " created\n",
    589  1.13    dante 		       sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
    590  1.13    dante 	}
    591  1.13    dante 
    592  1.13    dante 	/*
    593  1.13    dante 	 * Create and initialize the Carriers.
    594  1.13    dante 	 */
    595  1.13    dante 	error = adw_alloc_carriers(sc);
    596  1.13    dante 	if (error)
    597  1.13    dante 		return; /* (error) */ ;
    598  1.13    dante 
    599  1.13    dante 	bzero(sc->sc_control->carriers, ADW_CARRIER_SIZE * ADW_MAX_CARRIER);
    600  1.13    dante 
    601  1.13    dante 	i = adw_create_carriers(sc);
    602  1.13    dante 	if (i == 0) {
    603  1.13    dante 		printf("%s: unable to create Carriers\n",
    604  1.13    dante 		       sc->sc_dev.dv_xname);
    605  1.13    dante 		return; /* (ENOMEM) */ ;
    606  1.13    dante 	} else if (i != ADW_MAX_CARRIER) {
    607  1.13    dante 		printf("%s: WARNING: only %d of %d Carriers created\n",
    608  1.13    dante 		       sc->sc_dev.dv_xname, i, ADW_MAX_CARRIER);
    609  1.13    dante 	}
    610  1.13    dante 
    611  1.13    dante 
    612   1.1    dante 	/*
    613   1.1    dante 	 * Initialize the ASC3550.
    614   1.1    dante 	 */
    615  1.13    dante 	error = (sc->chip_type == ADV_CHIP_ASC3550)?
    616  1.13    dante 			AdvInitAsc3550Driver(sc) :
    617  1.13    dante 			AdvInitAsc38C0800Driver(sc);
    618  1.13    dante 	switch (error) {
    619   1.2    dante 	case ASC_IERR_MCODE_CHKSUM:
    620   1.2    dante 		panic("%s: Microcode checksum error",
    621   1.2    dante 		      sc->sc_dev.dv_xname);
    622   1.2    dante 		break;
    623   1.2    dante 
    624   1.2    dante 	case ASC_IERR_ILLEGAL_CONNECTION:
    625   1.2    dante 		panic("%s: All three connectors are in use",
    626   1.2    dante 		      sc->sc_dev.dv_xname);
    627   1.2    dante 		break;
    628   1.2    dante 
    629   1.2    dante 	case ASC_IERR_REVERSED_CABLE:
    630   1.2    dante 		panic("%s: Cable is reversed",
    631   1.2    dante 		      sc->sc_dev.dv_xname);
    632   1.2    dante 		break;
    633   1.2    dante 
    634   1.2    dante 	case ASC_IERR_SINGLE_END_DEVICE:
    635   1.2    dante 		panic("%s: single-ended device is attached to"
    636   1.2    dante 		      " one of the connectors",
    637   1.2    dante 		      sc->sc_dev.dv_xname);
    638   1.2    dante 		break;
    639  1.13    dante 
    640  1.13    dante 	case ASC_IERR_NO_CARRIER:
    641  1.13    dante 		panic("%s: no carrier",
    642  1.13    dante 		      sc->sc_dev.dv_xname);
    643  1.13    dante 		break;
    644  1.13    dante 
    645  1.13    dante 	case ASC_WARN_BUSRESET_ERROR:
    646  1.13    dante 		printf("%s: WARNING: Bus Reset Error\n",
    647  1.13    dante 		      sc->sc_dev.dv_xname);
    648  1.13    dante 		break;
    649   1.1    dante 	}
    650   1.1    dante 
    651   1.4  thorpej 	/*
    652   1.4  thorpej 	 * Fill in the adapter.
    653   1.4  thorpej 	 */
    654   1.4  thorpej 	sc->sc_adapter.scsipi_cmd = adw_scsi_cmd;
    655   1.4  thorpej 	sc->sc_adapter.scsipi_minphys = adwminphys;
    656   1.1    dante 
    657   1.1    dante 	/*
    658   1.1    dante          * fill in the prototype scsipi_link.
    659   1.1    dante          */
    660   1.1    dante 	sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
    661   1.1    dante 	sc->sc_link.adapter_softc = sc;
    662   1.1    dante 	sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
    663   1.4  thorpej 	sc->sc_link.adapter = &sc->sc_adapter;
    664   1.1    dante 	sc->sc_link.device = &adw_dev;
    665   1.1    dante 	sc->sc_link.openings = 4;
    666   1.1    dante 	sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID;
    667   1.5   mjacob 	sc->sc_link.scsipi_scsi.max_lun = 7;
    668   1.1    dante 	sc->sc_link.type = BUS_SCSI;
    669   1.1    dante 
    670   1.1    dante 
    671   1.1    dante 	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
    672   1.1    dante }
    673   1.1    dante 
    674   1.1    dante 
    675   1.1    dante static void
    676   1.1    dante adwminphys(bp)
    677   1.1    dante 	struct buf     *bp;
    678   1.1    dante {
    679   1.1    dante 
    680   1.1    dante 	if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
    681   1.1    dante 		bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
    682   1.1    dante 	minphys(bp);
    683   1.1    dante }
    684   1.1    dante 
    685   1.1    dante 
    686   1.1    dante /*
    687   1.2    dante  * start a scsi operation given the command and the data address.
    688   1.2    dante  * Also needs the unit, target and lu.
    689   1.1    dante  */
    690   1.1    dante static int
    691   1.1    dante adw_scsi_cmd(xs)
    692   1.1    dante 	struct scsipi_xfer *xs;
    693   1.1    dante {
    694   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    695   1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    696   1.1    dante 	ADW_CCB        *ccb;
    697  1.13    dante 	int             s, fromqueue = 1, dontqueue = 0, retry = 0;
    698   1.1    dante 
    699   1.1    dante 	s = splbio();		/* protect the queue */
    700   1.1    dante 
    701   1.1    dante 	/*
    702   1.1    dante          * If we're running the queue from adw_done(), we've been
    703   1.1    dante          * called with the first queue entry as our argument.
    704   1.1    dante          */
    705   1.6  thorpej 	if (xs == TAILQ_FIRST(&sc->sc_queue)) {
    706   1.6  thorpej 		TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    707   1.1    dante 		fromqueue = 1;
    708   1.1    dante 	} else {
    709   1.1    dante 
    710   1.1    dante 		/* Polled requests can't be queued for later. */
    711  1.12  thorpej 		dontqueue = xs->xs_control & XS_CTL_POLL;
    712   1.1    dante 
    713   1.1    dante 		/*
    714   1.1    dante                  * If there are jobs in the queue, run them first.
    715   1.1    dante                  */
    716   1.6  thorpej 		if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
    717   1.1    dante 			/*
    718   1.1    dante                          * If we can't queue, we have to abort, since
    719   1.1    dante                          * we have to preserve order.
    720   1.1    dante                          */
    721   1.1    dante 			if (dontqueue) {
    722   1.1    dante 				splx(s);
    723   1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    724   1.1    dante 				return (TRY_AGAIN_LATER);
    725   1.1    dante 			}
    726   1.1    dante 			/*
    727   1.1    dante                          * Swap with the first queue entry.
    728   1.1    dante                          */
    729   1.6  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    730   1.6  thorpej 			xs = TAILQ_FIRST(&sc->sc_queue);
    731   1.6  thorpej 			TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    732   1.1    dante 			fromqueue = 1;
    733   1.1    dante 		}
    734   1.1    dante 	}
    735   1.1    dante 
    736   1.1    dante 
    737   1.1    dante 	/*
    738   1.1    dante          * get a ccb to use. If the transfer
    739   1.1    dante          * is from a buf (possibly from interrupt time)
    740   1.1    dante          * then we can't allow it to sleep
    741   1.1    dante          */
    742   1.1    dante 
    743  1.12  thorpej 	if ((ccb = adw_get_ccb(sc, xs->xs_control)) == NULL) {
    744   1.1    dante 		/*
    745   1.1    dante                  * If we can't queue, we lose.
    746   1.1    dante                  */
    747   1.1    dante 		if (dontqueue) {
    748   1.1    dante 			splx(s);
    749   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    750   1.1    dante 			return (TRY_AGAIN_LATER);
    751   1.1    dante 		}
    752   1.1    dante 		/*
    753   1.1    dante                  * Stuff ourselves into the queue, in front
    754   1.1    dante                  * if we came off in the first place.
    755   1.1    dante                  */
    756   1.6  thorpej 		if (fromqueue)
    757   1.6  thorpej 			TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
    758   1.6  thorpej 		else
    759   1.6  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    760   1.1    dante 		splx(s);
    761   1.1    dante 		return (SUCCESSFULLY_QUEUED);
    762   1.1    dante 	}
    763   1.1    dante 	splx(s);		/* done playing with the queue */
    764   1.1    dante 
    765   1.1    dante 	ccb->xs = xs;
    766   1.1    dante 	ccb->timeout = xs->timeout;
    767   1.1    dante 
    768   1.2    dante 	if (adw_build_req(xs, ccb)) {
    769  1.13    dante retryagain:
    770  1.13    dante 		s = splbio();
    771  1.13    dante 		retry = adw_queue_ccb(sc, ccb, retry);
    772  1.13    dante 		splx(s);
    773  1.13    dante 
    774  1.13    dante 		switch(retry) {
    775  1.13    dante 		case ADW_BUSY:
    776  1.13    dante 			goto retryagain;
    777  1.13    dante 
    778  1.13    dante 		case ADW_ERROR:
    779  1.13    dante 			xs->error = XS_DRIVER_STUFFUP;
    780  1.13    dante 			return (COMPLETE);
    781  1.13    dante 
    782  1.13    dante 		}
    783   1.1    dante 
    784   1.1    dante 		/*
    785   1.1    dante 	         * Usually return SUCCESSFULLY QUEUED
    786   1.1    dante 	         */
    787  1.12  thorpej 		if ((xs->xs_control & XS_CTL_POLL) == 0)
    788   1.1    dante 			return (SUCCESSFULLY_QUEUED);
    789   1.1    dante 
    790   1.1    dante 		/*
    791   1.1    dante 	         * If we can't use interrupts, poll on completion
    792   1.1    dante 	         */
    793   1.1    dante 		if (adw_poll(sc, xs, ccb->timeout)) {
    794   1.1    dante 			adw_timeout(ccb);
    795   1.1    dante 			if (adw_poll(sc, xs, ccb->timeout))
    796   1.1    dante 				adw_timeout(ccb);
    797   1.1    dante 		}
    798   1.1    dante 	}
    799   1.2    dante 	return (COMPLETE);
    800   1.1    dante }
    801   1.1    dante 
    802   1.1    dante 
    803   1.1    dante /*
    804   1.1    dante  * Build a request structure for the Wide Boards.
    805   1.1    dante  */
    806   1.1    dante static int
    807   1.1    dante adw_build_req(xs, ccb)
    808   1.2    dante 	struct scsipi_xfer *xs;
    809   1.2    dante 	ADW_CCB        *ccb;
    810   1.1    dante {
    811   1.2    dante 	struct scsipi_link *sc_link = xs->sc_link;
    812   1.2    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    813   1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    814   1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    815   1.2    dante 	int             error;
    816   1.1    dante 
    817   1.1    dante 	scsiqp = &ccb->scsiq;
    818   1.1    dante 	bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
    819   1.1    dante 
    820   1.1    dante 	/*
    821   1.7    dante 	 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
    822   1.7    dante 	 * physical CCB structure.
    823   1.1    dante 	 */
    824  1.10  thorpej 	scsiqp->ccb_ptr = ccb->hashkey;
    825   1.1    dante 
    826   1.1    dante 	/*
    827   1.1    dante 	 * Build the ADW_SCSI_REQ_Q request.
    828   1.1    dante 	 */
    829   1.1    dante 
    830   1.1    dante 	/*
    831   1.1    dante 	 * Set CDB length and copy it to the request structure.
    832   1.1    dante 	 */
    833   1.1    dante 	bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen);
    834   1.1    dante 
    835   1.1    dante 	scsiqp->target_id = sc_link->scsipi_scsi.target;
    836   1.1    dante 	scsiqp->target_lun = sc_link->scsipi_scsi.lun;
    837   1.1    dante 
    838   1.7    dante 	scsiqp->vsense_addr = &ccb->scsi_sense;
    839  1.13    dante 	scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    840  1.13    dante 			ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
    841  1.13    dante /*	scsiqp->sense_addr = ccb->hashkey +
    842  1.10  thorpej 	    offsetof(struct adw_ccb, scsi_sense);
    843  1.13    dante */	scsiqp->sense_len = sizeof(struct scsipi_sense_data);
    844   1.1    dante 
    845   1.1    dante 	/*
    846   1.1    dante 	 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
    847   1.1    dante 	 */
    848   1.1    dante 	if (xs->datalen) {
    849   1.1    dante 		/*
    850   1.1    dante                  * Map the DMA transfer.
    851   1.1    dante                  */
    852   1.1    dante #ifdef TFS
    853  1.12  thorpej 		if (xs->xs_control & SCSI_DATA_UIO) {
    854   1.1    dante 			error = bus_dmamap_load_uio(dmat,
    855   1.2    dante 				ccb->dmamap_xfer, (struct uio *) xs->data,
    856  1.12  thorpej 				(xs->xs_control & XS_CTL_NOSLEEP) ?
    857  1.12  thorpej 				BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    858   1.1    dante 		} else
    859  1.13    dante #endif		/* TFS */
    860   1.1    dante 		{
    861   1.1    dante 			error = bus_dmamap_load(dmat,
    862   1.2    dante 			      ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
    863  1.12  thorpej 				(xs->xs_control & XS_CTL_NOSLEEP) ?
    864  1.12  thorpej 				BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    865   1.1    dante 		}
    866   1.1    dante 
    867   1.1    dante 		if (error) {
    868   1.1    dante 			if (error == EFBIG) {
    869   1.1    dante 				printf("%s: adw_scsi_cmd, more than %d dma"
    870   1.1    dante 				       " segments\n",
    871   1.1    dante 				       sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
    872   1.1    dante 			} else {
    873   1.1    dante 				printf("%s: adw_scsi_cmd, error %d loading"
    874   1.1    dante 				       " dma map\n",
    875   1.1    dante 				       sc->sc_dev.dv_xname, error);
    876   1.1    dante 			}
    877   1.1    dante 
    878   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    879   1.1    dante 			adw_free_ccb(sc, ccb);
    880   1.1    dante 			return (0);
    881   1.1    dante 		}
    882   1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    883   1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    884  1.13    dante 				(xs->xs_control & XS_CTL_DATA_IN) ?
    885  1.13    dante 				BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
    886   1.1    dante 
    887   1.1    dante 		/*
    888   1.1    dante 		 * Build scatter-gather list.
    889   1.1    dante 		 */
    890   1.1    dante 		scsiqp->data_cnt = xs->datalen;
    891   1.7    dante 		scsiqp->vdata_addr = xs->data;
    892   1.1    dante 		scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
    893   1.7    dante 		bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
    894   1.7    dante 		adw_build_sglist(ccb, scsiqp, ccb->sg_block);
    895   1.1    dante 	} else {
    896   1.1    dante 		/*
    897   1.1    dante                  * No data xfer, use non S/G values.
    898   1.1    dante                  */
    899   1.1    dante 		scsiqp->data_cnt = 0;
    900   1.1    dante 		scsiqp->vdata_addr = 0;
    901   1.1    dante 		scsiqp->data_addr = 0;
    902   1.1    dante 	}
    903   1.1    dante 
    904   1.1    dante 	return (1);
    905   1.1    dante }
    906   1.1    dante 
    907   1.1    dante 
    908   1.1    dante /*
    909   1.1    dante  * Build scatter-gather list for Wide Boards.
    910   1.1    dante  */
    911   1.1    dante static void
    912   1.7    dante adw_build_sglist(ccb, scsiqp, sg_block)
    913   1.2    dante 	ADW_CCB        *ccb;
    914   1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    915   1.7    dante 	ADW_SG_BLOCK   *sg_block;
    916   1.1    dante {
    917   1.9  thorpej 	u_long          sg_block_next_addr;	/* block and its next */
    918   1.9  thorpej 	u_int32_t       sg_block_physical_addr;
    919  1.13    dante 	int             i;	/* how many SG entries */
    920   1.1    dante 	bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
    921   1.2    dante 	int             sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
    922   1.1    dante 
    923   1.1    dante 
    924   1.9  thorpej 	sg_block_next_addr = (u_long) sg_block;	/* allow math operation */
    925  1.10  thorpej 	sg_block_physical_addr = ccb->hashkey +
    926  1.10  thorpej 	    offsetof(struct adw_ccb, sg_block[0]);
    927   1.1    dante 	scsiqp->sg_real_addr = sg_block_physical_addr;
    928   1.1    dante 
    929   1.1    dante 	/*
    930   1.1    dante 	 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
    931   1.1    dante 	 * then split the request into multiple sg-list blocks.
    932   1.1    dante 	 */
    933   1.1    dante 
    934   1.2    dante 	do {
    935   1.2    dante 		for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
    936   1.1    dante 			sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
    937   1.1    dante 			sg_block->sg_list[i].sg_count = sg_list->ds_len;
    938   1.1    dante 
    939   1.2    dante 			if (--sg_elem_cnt == 0) {
    940   1.1    dante 				/* last entry, get out */
    941  1.13    dante 				sg_block->sg_cnt = i + i;
    942   1.2    dante 				sg_block->sg_ptr = NULL; /* next link = NULL */
    943   1.1    dante 				return;
    944   1.1    dante 			}
    945   1.1    dante 			sg_list++;
    946   1.1    dante 		}
    947   1.1    dante 		sg_block_next_addr += sizeof(ADW_SG_BLOCK);
    948   1.1    dante 		sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
    949   1.1    dante 
    950  1.13    dante 		sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
    951   1.9  thorpej 		sg_block->sg_ptr = sg_block_physical_addr;
    952   1.2    dante 		sg_block = (ADW_SG_BLOCK *) sg_block_next_addr;	/* virt. addr */
    953  1.10  thorpej 	} while (1);
    954   1.1    dante }
    955   1.1    dante 
    956   1.1    dante 
    957   1.1    dante int
    958   1.1    dante adw_intr(arg)
    959   1.1    dante 	void           *arg;
    960   1.1    dante {
    961   1.1    dante 	ADW_SOFTC      *sc = arg;
    962   1.1    dante 	struct scsipi_xfer *xs;
    963   1.1    dante 
    964   1.1    dante 
    965  1.13    dante 	if(AdvISR(sc) != ADW_FALSE) {
    966  1.13    dante 		/*
    967  1.13    dante 	         * If there are queue entries in the software queue, try to
    968  1.13    dante 	         * run the first one.  We should be more or less guaranteed
    969  1.13    dante 	         * to succeed, since we just freed a CCB.
    970  1.13    dante 	         *
    971  1.13    dante 	         * NOTE: adw_scsi_cmd() relies on our calling it with
    972  1.13    dante 	         * the first entry in the queue.
    973  1.13    dante 	         */
    974  1.13    dante 		if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
    975  1.13    dante 			(void) adw_scsi_cmd(xs);
    976  1.13    dante 	}
    977   1.1    dante 
    978   1.1    dante 	return (1);
    979   1.1    dante }
    980   1.1    dante 
    981   1.1    dante 
    982   1.1    dante /*
    983   1.1    dante  * Poll a particular unit, looking for a particular xs
    984   1.1    dante  */
    985   1.1    dante static int
    986   1.1    dante adw_poll(sc, xs, count)
    987   1.1    dante 	ADW_SOFTC      *sc;
    988   1.1    dante 	struct scsipi_xfer *xs;
    989   1.1    dante 	int             count;
    990   1.1    dante {
    991   1.1    dante 
    992   1.1    dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
    993   1.1    dante 	while (count) {
    994   1.1    dante 		adw_intr(sc);
    995  1.12  thorpej 		if (xs->xs_status & XS_STS_DONE)
    996   1.1    dante 			return (0);
    997   1.1    dante 		delay(1000);	/* only happens in boot so ok */
    998   1.1    dante 		count--;
    999   1.1    dante 	}
   1000   1.1    dante 	return (1);
   1001   1.1    dante }
   1002   1.1    dante 
   1003   1.1    dante 
   1004   1.1    dante static void
   1005   1.1    dante adw_timeout(arg)
   1006   1.1    dante 	void           *arg;
   1007   1.1    dante {
   1008   1.1    dante 	ADW_CCB        *ccb = arg;
   1009   1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
   1010   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
   1011   1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
   1012   1.1    dante 	int             s;
   1013   1.1    dante 
   1014   1.1    dante 	scsi_print_addr(sc_link);
   1015   1.1    dante 	printf("timed out");
   1016   1.1    dante 
   1017   1.1    dante 	s = splbio();
   1018   1.1    dante 
   1019   1.1    dante 	/*
   1020   1.1    dante          * If it has been through before, then a previous abort has failed,
   1021   1.1    dante          * don't try abort again, reset the bus instead.
   1022   1.1    dante          */
   1023  1.11    dante 	if (ccb->flags & CCB_ABORTED) {
   1024  1.11    dante 	/*
   1025  1.11    dante 	 * Abort Timed Out
   1026  1.11    dante 	 * Lets try resetting the bus!
   1027  1.11    dante 	 */
   1028  1.11    dante 		printf(" AGAIN. Resetting SCSI Bus\n");
   1029  1.11    dante 		ccb->flags &= ~CCB_ABORTED;
   1030  1.11    dante 		/* AdvResetSCSIBus() will call sbreset_callback() */
   1031   1.1    dante 		AdvResetSCSIBus(sc);
   1032   1.1    dante 	} else {
   1033  1.11    dante 	/*
   1034  1.11    dante 	 * Abort the operation that has timed out
   1035  1.11    dante 	 */
   1036   1.1    dante 		printf("\n");
   1037  1.11    dante 		xs->error = XS_TIMEOUT;
   1038  1.11    dante 		ccb->flags |= CCB_ABORTING;
   1039  1.11    dante 		/* ADW_ABORT_CCB() will implicitly call isr_callback() */
   1040   1.1    dante 		ADW_ABORT_CCB(sc, ccb);
   1041   1.1    dante 	}
   1042   1.1    dante 
   1043   1.1    dante 	splx(s);
   1044   1.1    dante }
   1045   1.1    dante 
   1046   1.1    dante 
   1047   1.1    dante /******************************************************************************/
   1048   1.7    dante /*                           WIDE boards Interrupt callbacks                  */
   1049   1.1    dante /******************************************************************************/
   1050   1.1    dante 
   1051   1.1    dante 
   1052   1.1    dante /*
   1053  1.13    dante  * adw__isr_callback() - Second Level Interrupt Handler called by AdvISR()
   1054   1.1    dante  *
   1055   1.1    dante  * Interrupt callback function for the Wide SCSI Adv Library.
   1056   1.1    dante  */
   1057   1.1    dante static void
   1058  1.13    dante adw_isr_callback(sc, scsiq)
   1059   1.1    dante 	ADW_SOFTC      *sc;
   1060   1.1    dante 	ADW_SCSI_REQ_Q *scsiq;
   1061   1.1    dante {
   1062   1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
   1063   1.7    dante 	ADW_CCB        *ccb;
   1064   1.7    dante 	struct scsipi_xfer *xs;
   1065   1.1    dante 	struct scsipi_sense_data *s1, *s2;
   1066  1.13    dante //	int		 s;
   1067   1.1    dante 
   1068   1.7    dante 
   1069   1.7    dante 	ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
   1070  1.11    dante 
   1071  1.11    dante 	untimeout(adw_timeout, ccb);
   1072  1.11    dante 
   1073  1.13    dante /*	if(ccb->flags & CCB_ABORTING) {
   1074  1.11    dante 		printf("Retrying request\n");
   1075  1.11    dante 		ccb->flags &= ~CCB_ABORTING;
   1076  1.11    dante 		ccb->flags |= CCB_ABORTED;
   1077  1.11    dante 		s = splbio();
   1078  1.11    dante 		adw_queue_ccb(sc, ccb);
   1079  1.11    dante 		splx(s);
   1080  1.11    dante 		return;
   1081  1.11    dante 	}
   1082  1.13    dante */
   1083   1.7    dante 	xs = ccb->xs;
   1084   1.1    dante 
   1085   1.1    dante 	/*
   1086   1.1    dante          * If we were a data transfer, unload the map that described
   1087   1.1    dante          * the data buffer.
   1088   1.1    dante          */
   1089   1.1    dante 	if (xs->datalen) {
   1090   1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
   1091   1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
   1092  1.12  thorpej 			 (xs->xs_control & XS_CTL_DATA_IN) ?
   1093  1.12  thorpej 			 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   1094   1.1    dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
   1095   1.1    dante 	}
   1096   1.1    dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
   1097   1.1    dante 		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
   1098   1.1    dante 		Debugger();
   1099   1.1    dante 		return;
   1100   1.1    dante 	}
   1101   1.1    dante 	/*
   1102   1.1    dante 	 * Check for an underrun condition.
   1103   1.1    dante 	 */
   1104   1.2    dante 	/*
   1105   1.2    dante 	 * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
   1106   1.2    dante 	 * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
   1107   1.2    dante 	 * scsiqp->data_cnt); underrun = ASC_TRUE; }
   1108   1.2    dante 	 */
   1109   1.1    dante 	/*
   1110   1.1    dante 	 * 'done_status' contains the command's ending status.
   1111   1.1    dante 	 */
   1112   1.1    dante 	switch (scsiq->done_status) {
   1113   1.1    dante 	case QD_NO_ERROR:
   1114   1.1    dante 		switch (scsiq->host_status) {
   1115   1.1    dante 		case QHSTA_NO_ERROR:
   1116   1.1    dante 			xs->error = XS_NOERROR;
   1117   1.1    dante 			xs->resid = 0;
   1118   1.1    dante 			break;
   1119   1.1    dante 		default:
   1120   1.1    dante 			/* QHSTA error occurred. */
   1121   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
   1122   1.1    dante 			break;
   1123   1.1    dante 		}
   1124  1.13    dante 		break;
   1125   1.1    dante 
   1126   1.1    dante 	case QD_WITH_ERROR:
   1127   1.1    dante 		switch (scsiq->host_status) {
   1128   1.1    dante 		case QHSTA_NO_ERROR:
   1129  1.11    dante 			switch(scsiq->scsi_status) {
   1130  1.11    dante 			case SS_CHK_CONDITION:
   1131  1.11    dante 			case SS_CMD_TERMINATED:
   1132   1.1    dante 				s1 = &ccb->scsi_sense;
   1133   1.1    dante 				s2 = &xs->sense.scsi_sense;
   1134   1.1    dante 				*s2 = *s1;
   1135   1.1    dante 				xs->error = XS_SENSE;
   1136  1.11    dante 				break;
   1137  1.11    dante 			case SS_TARGET_BUSY:
   1138  1.11    dante 			case SS_RSERV_CONFLICT:
   1139  1.11    dante 			case SS_QUEUE_FULL:
   1140  1.11    dante 				xs->error = XS_DRIVER_STUFFUP;
   1141  1.11    dante 				break;
   1142  1.11    dante 			case SS_CONDITION_MET:
   1143  1.11    dante 			case SS_INTERMID:
   1144  1.11    dante 			case SS_INTERMID_COND_MET:
   1145   1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
   1146  1.11    dante 				break;
   1147  1.11    dante 			case SS_GOOD:
   1148  1.11    dante 				break;
   1149   1.1    dante 			}
   1150   1.1    dante 			break;
   1151   1.1    dante 
   1152  1.11    dante 		case QHSTA_M_SEL_TIMEOUT:
   1153  1.11    dante 			xs->error = XS_DRIVER_STUFFUP;
   1154  1.11    dante 			break;
   1155  1.11    dante 
   1156   1.1    dante 		default:
   1157   1.1    dante 			/* Some other QHSTA error occurred. */
   1158   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
   1159   1.1    dante 			break;
   1160   1.1    dante 		}
   1161   1.1    dante 		break;
   1162   1.1    dante 
   1163   1.1    dante 	case QD_ABORTED_BY_HOST:
   1164  1.11    dante 		xs->error = XS_DRIVER_STUFFUP;
   1165  1.11    dante 		break;
   1166  1.11    dante 
   1167   1.1    dante 	default:
   1168   1.1    dante 		xs->error = XS_DRIVER_STUFFUP;
   1169   1.1    dante 		break;
   1170   1.1    dante 	}
   1171   1.1    dante 
   1172   1.1    dante 	adw_free_ccb(sc, ccb);
   1173  1.12  thorpej 	xs->xs_status |= XS_STS_DONE;
   1174   1.1    dante 	scsipi_done(xs);
   1175  1.11    dante }
   1176  1.11    dante 
   1177  1.11    dante 
   1178  1.13    dante /*
   1179  1.13    dante  * adv_async_callback() - Adv Library asynchronous event callback function.
   1180  1.13    dante  */
   1181  1.11    dante static void
   1182  1.13    dante adw_async_callback(sc, code)
   1183  1.11    dante 	ADW_SOFTC	*sc;
   1184  1.13    dante 	u_int8_t	code;
   1185  1.11    dante {
   1186  1.13    dante 	switch (code) {
   1187  1.13    dante 	case ADV_ASYNC_SCSI_BUS_RESET_DET:
   1188  1.13    dante 		/*
   1189  1.13    dante 		 * The firmware detected a SCSI Bus reset.
   1190  1.13    dante 		 */
   1191  1.13    dante 		break;
   1192  1.13    dante 
   1193  1.13    dante 	case ADV_ASYNC_RDMA_FAILURE:
   1194  1.13    dante 		/*
   1195  1.13    dante 		 * Handle RDMA failure by resetting the SCSI Bus and
   1196  1.13    dante 		 * possibly the chip if it is unresponsive. Log the error
   1197  1.13    dante 		 * with a unique code.
   1198  1.13    dante 		 */
   1199  1.13    dante 		AdvResetSCSIBus(sc);
   1200  1.13    dante 		break;
   1201  1.13    dante 
   1202  1.13    dante 	case ADV_HOST_SCSI_BUS_RESET:
   1203  1.13    dante                /*
   1204  1.13    dante                 * Host generated SCSI bus reset occurred.
   1205  1.13    dante                 */
   1206  1.13    dante               break;
   1207  1.13    dante 
   1208  1.13    dante 	default:
   1209  1.13    dante 		break;
   1210  1.13    dante 	}
   1211   1.1    dante }
   1212