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adw.c revision 1.17
      1  1.17  thorpej /* $NetBSD: adw.c,v 1.17 2000/05/03 18:58:37 thorpej Exp $	 */
      2   1.1    dante 
      3   1.1    dante /*
      4   1.1    dante  * Generic driver for the Advanced Systems Inc. SCSI controllers
      5   1.1    dante  *
      6  1.13    dante  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
      7   1.1    dante  * All rights reserved.
      8   1.1    dante  *
      9   1.1    dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10   1.1    dante  *
     11   1.1    dante  * Redistribution and use in source and binary forms, with or without
     12   1.1    dante  * modification, are permitted provided that the following conditions
     13   1.1    dante  * are met:
     14   1.1    dante  * 1. Redistributions of source code must retain the above copyright
     15   1.1    dante  *    notice, this list of conditions and the following disclaimer.
     16   1.1    dante  * 2. Redistributions in binary form must reproduce the above copyright
     17   1.1    dante  *    notice, this list of conditions and the following disclaimer in the
     18   1.1    dante  *    documentation and/or other materials provided with the distribution.
     19   1.1    dante  * 3. All advertising materials mentioning features or use of this software
     20   1.1    dante  *    must display the following acknowledgement:
     21   1.1    dante  *        This product includes software developed by the NetBSD
     22   1.1    dante  *        Foundation, Inc. and its contributors.
     23   1.1    dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24   1.1    dante  *    contributors may be used to endorse or promote products derived
     25   1.1    dante  *    from this software without specific prior written permission.
     26   1.1    dante  *
     27   1.1    dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28   1.1    dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29   1.1    dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30   1.1    dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31   1.1    dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32   1.1    dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33   1.1    dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34   1.1    dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35   1.1    dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36   1.1    dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37   1.1    dante  * POSSIBILITY OF SUCH DAMAGE.
     38   1.1    dante  */
     39   1.1    dante 
     40   1.1    dante #include <sys/types.h>
     41   1.1    dante #include <sys/param.h>
     42   1.1    dante #include <sys/systm.h>
     43  1.15  thorpej #include <sys/callout.h>
     44   1.1    dante #include <sys/kernel.h>
     45   1.1    dante #include <sys/errno.h>
     46   1.1    dante #include <sys/ioctl.h>
     47   1.1    dante #include <sys/device.h>
     48   1.1    dante #include <sys/malloc.h>
     49   1.1    dante #include <sys/buf.h>
     50   1.1    dante #include <sys/proc.h>
     51   1.1    dante #include <sys/user.h>
     52   1.1    dante 
     53   1.1    dante #include <machine/bus.h>
     54   1.1    dante #include <machine/intr.h>
     55   1.1    dante 
     56   1.1    dante #include <vm/vm.h>
     57   1.1    dante #include <vm/vm_param.h>
     58   1.1    dante #include <vm/pmap.h>
     59   1.1    dante 
     60   1.1    dante #include <dev/scsipi/scsi_all.h>
     61   1.1    dante #include <dev/scsipi/scsipi_all.h>
     62   1.1    dante #include <dev/scsipi/scsiconf.h>
     63   1.1    dante 
     64   1.1    dante #include <dev/ic/adwlib.h>
     65   1.1    dante #include <dev/ic/adw.h>
     66   1.1    dante 
     67   1.1    dante #ifndef DDB
     68  1.11    dante #define	Debugger()	panic("should call debugger here (adw.c)")
     69   1.2    dante #endif				/* ! DDB */
     70   1.1    dante 
     71   1.1    dante /******************************************************************************/
     72   1.1    dante 
     73   1.1    dante 
     74  1.13    dante static int adw_alloc_controls __P((ADW_SOFTC *));
     75  1.13    dante static int adw_alloc_carriers __P((ADW_SOFTC *));
     76  1.13    dante static int adw_create_carriers __P((ADW_SOFTC *));
     77  1.13    dante static int adw_init_carrier __P((ADW_SOFTC *, ADW_CARRIER *));
     78   1.1    dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
     79   1.1    dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
     80   1.1    dante static void adw_reset_ccb __P((ADW_CCB *));
     81   1.1    dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
     82   1.1    dante static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int));
     83  1.13    dante static int adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *, int));
     84   1.1    dante 
     85   1.1    dante static int adw_scsi_cmd __P((struct scsipi_xfer *));
     86  1.14  thorpej static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *, int));
     87   1.7    dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *));
     88   1.1    dante static void adwminphys __P((struct buf *));
     89  1.13    dante static void adw_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
     90  1.13    dante static void adw_async_callback __P((ADW_SOFTC *, u_int8_t));
     91   1.1    dante 
     92   1.1    dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
     93   1.1    dante static void adw_timeout __P((void *));
     94   1.1    dante 
     95   1.1    dante 
     96   1.1    dante /******************************************************************************/
     97   1.1    dante 
     98   1.1    dante 
     99   1.1    dante /* the below structure is so we have a default dev struct for out link struct */
    100   1.1    dante struct scsipi_device adw_dev =
    101   1.1    dante {
    102   1.1    dante 	NULL,			/* Use default error handler */
    103   1.1    dante 	NULL,			/* have a queue, served by this */
    104   1.1    dante 	NULL,			/* have no async handler */
    105   1.1    dante 	NULL,			/* Use default 'done' routine */
    106   1.1    dante };
    107   1.1    dante 
    108   1.1    dante 
    109   1.1    dante #define ADW_ABORT_TIMEOUT       10000	/* time to wait for abort (mSec) */
    110   1.1    dante #define ADW_WATCH_TIMEOUT       10000	/* time to wait for watchdog (mSec) */
    111   1.1    dante 
    112   1.1    dante 
    113   1.1    dante /******************************************************************************/
    114   1.7    dante /*                                Control Blocks routines                     */
    115   1.1    dante /******************************************************************************/
    116   1.1    dante 
    117   1.1    dante 
    118   1.1    dante static int
    119  1.13    dante adw_alloc_controls(sc)
    120   1.1    dante 	ADW_SOFTC      *sc;
    121   1.1    dante {
    122   1.1    dante 	bus_dma_segment_t seg;
    123   1.1    dante 	int             error, rseg;
    124   1.1    dante 
    125   1.1    dante 	/*
    126  1.13    dante          * Allocate the control structure.
    127   1.1    dante          */
    128   1.1    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
    129   1.1    dante 			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    130   1.1    dante 		printf("%s: unable to allocate control structures,"
    131   1.1    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    132   1.1    dante 		return (error);
    133   1.1    dante 	}
    134   1.1    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    135   1.1    dante 		   sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
    136   1.1    dante 				 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    137   1.1    dante 		printf("%s: unable to map control structures, error = %d\n",
    138   1.1    dante 		       sc->sc_dev.dv_xname, error);
    139   1.1    dante 		return (error);
    140   1.1    dante 	}
    141  1.13    dante 
    142   1.1    dante 	/*
    143   1.1    dante          * Create and load the DMA map used for the control blocks.
    144   1.1    dante          */
    145   1.1    dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
    146   1.1    dante 			   1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
    147   1.1    dante 				       &sc->sc_dmamap_control)) != 0) {
    148   1.1    dante 		printf("%s: unable to create control DMA map, error = %d\n",
    149   1.1    dante 		       sc->sc_dev.dv_xname, error);
    150   1.1    dante 		return (error);
    151   1.1    dante 	}
    152   1.1    dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    153   1.1    dante 			   sc->sc_control, sizeof(struct adw_control), NULL,
    154   1.1    dante 				     BUS_DMA_NOWAIT)) != 0) {
    155   1.1    dante 		printf("%s: unable to load control DMA map, error = %d\n",
    156   1.1    dante 		       sc->sc_dev.dv_xname, error);
    157   1.1    dante 		return (error);
    158   1.1    dante 	}
    159  1.13    dante 
    160  1.13    dante 	return (0);
    161  1.13    dante }
    162  1.13    dante 
    163  1.13    dante 
    164  1.13    dante static int
    165  1.13    dante adw_alloc_carriers(sc)
    166  1.13    dante 	ADW_SOFTC      *sc;
    167  1.13    dante {
    168  1.13    dante 	bus_dma_segment_t seg;
    169  1.13    dante 	int             error, rseg;
    170  1.13    dante 
    171  1.13    dante 	/*
    172  1.13    dante          * Allocate the control structure.
    173  1.13    dante          */
    174  1.13    dante 	sc->sc_control->carriers = malloc(ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    175  1.13    dante 			M_DEVBUF, M_WAITOK);
    176  1.13    dante 	if(!sc->sc_control->carriers) {
    177  1.17  thorpej 		error = ENOMEM;
    178  1.13    dante 		printf("%s: malloc() failed in allocating carrier structures,"
    179  1.13    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    180  1.13    dante 		return (error);
    181  1.13    dante 	}
    182  1.13    dante 
    183  1.13    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
    184  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    185  1.13    dante 			NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    186  1.13    dante 		printf("%s: unable to allocate carrier structures,"
    187  1.13    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    188  1.13    dante 		return (error);
    189  1.13    dante 	}
    190  1.13    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    191  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    192  1.13    dante 			(caddr_t *) &sc->sc_control->carriers,
    193  1.13    dante 			BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    194  1.13    dante 		printf("%s: unable to map carrier structures,"
    195  1.13    dante 			" error = %d\n", sc->sc_dev.dv_xname, error);
    196  1.13    dante 		return (error);
    197  1.13    dante 	}
    198  1.13    dante 
    199  1.13    dante 	/*
    200  1.13    dante          * Create and load the DMA map used for the control blocks.
    201  1.13    dante          */
    202  1.13    dante 	if ((error = bus_dmamap_create(sc->sc_dmat,
    203  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 1,
    204  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 0, BUS_DMA_NOWAIT,
    205  1.13    dante 			&sc->sc_dmamap_carrier)) != 0) {
    206  1.13    dante 		printf("%s: unable to create carriers DMA map,"
    207  1.13    dante 			" error = %d\n", sc->sc_dev.dv_xname, error);
    208  1.13    dante 		return (error);
    209  1.13    dante 	}
    210  1.13    dante 	if ((error = bus_dmamap_load(sc->sc_dmat,
    211  1.13    dante 			sc->sc_dmamap_carrier, sc->sc_control->carriers,
    212  1.13    dante 			ADW_CARRIER_SIZE * ADW_MAX_CARRIER, NULL,
    213  1.13    dante 			BUS_DMA_NOWAIT)) != 0) {
    214  1.13    dante 		printf("%s: unable to load carriers DMA map,"
    215  1.13    dante 			" error = %d\n", sc->sc_dev.dv_xname, error);
    216  1.13    dante 		return (error);
    217  1.13    dante 	}
    218  1.13    dante 
    219  1.13    dante 	error = bus_dmamap_create(sc->sc_dmat, ADW_CARRIER_SIZE* ADW_MAX_CARRIER,
    220  1.13    dante 			1, ADW_CARRIER_SIZE * ADW_MAX_CARRIER,
    221  1.13    dante 			0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
    222  1.13    dante 			&sc->sc_control->dmamap_xfer);
    223  1.13    dante 	if (error) {
    224  1.13    dante 		printf("%s: unable to create Carrier DMA map, error = %d\n",
    225  1.13    dante 		       sc->sc_dev.dv_xname, error);
    226  1.13    dante 		return (error);
    227  1.13    dante 	}
    228  1.13    dante 
    229   1.1    dante 	return (0);
    230   1.1    dante }
    231   1.1    dante 
    232   1.1    dante 
    233   1.1    dante /*
    234  1.13    dante  * Create a set of Carriers and add them to the free list.  Called once
    235  1.13    dante  * by adw_init().  We return the number of Carriers successfully created.
    236  1.13    dante  */
    237  1.13    dante static int
    238  1.13    dante adw_create_carriers(sc)
    239  1.13    dante 	ADW_SOFTC	*sc;
    240  1.13    dante {
    241  1.13    dante 	ADW_CARRIER	*carr;
    242  1.13    dante 	u_int32_t	carr_next = NULL;
    243  1.13    dante 	int		i, error;
    244  1.13    dante 
    245  1.13    dante 	for(i=0; i < ADW_MAX_CARRIER; i++) {
    246  1.13    dante 		carr = (ADW_CARRIER *)(((u_int8_t *)sc->sc_control->carriers) +
    247  1.13    dante 				(ADW_CARRIER_SIZE * i));
    248  1.13    dante 		if ((error = adw_init_carrier(sc, carr)) != 0) {
    249  1.13    dante 			printf("%s: unable to initialize carrier, error = %d\n",
    250  1.13    dante 			       sc->sc_dev.dv_xname, error);
    251  1.13    dante 			return (i);
    252  1.13    dante 		}
    253  1.13    dante 		carr->next_vpa = carr_next;
    254  1.13    dante 		carr_next = carr->carr_pa;
    255  1.13    dante carr->id = i;
    256  1.13    dante 	}
    257  1.13    dante 	sc->carr_freelist = carr;
    258  1.13    dante 	return (i);
    259  1.13    dante }
    260  1.13    dante 
    261  1.13    dante 
    262  1.13    dante static int
    263  1.13    dante adw_init_carrier(sc, carr)
    264  1.13    dante 	ADW_SOFTC	*sc;
    265  1.13    dante 	ADW_CARRIER	*carr;
    266  1.13    dante {
    267  1.13    dante 	u_int32_t	carr_pa;
    268  1.13    dante 	int		/*error, */hashnum;
    269  1.13    dante 
    270  1.13    dante 	/*
    271  1.13    dante          * Create the DMA map for all of the Carriers.
    272  1.13    dante          */
    273  1.13    dante /*	error = bus_dmamap_create(sc->sc_dmat, ADW_CARRIER_SIZE,
    274  1.13    dante 			1, ADW_CARRIER_SIZE,
    275  1.13    dante 			0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
    276  1.13    dante 			&carr->dmamap_xfer);
    277  1.13    dante 	if (error) {
    278  1.13    dante 		printf("%s: unable to create Carrier DMA map, error = %d\n",
    279  1.13    dante 		       sc->sc_dev.dv_xname, error);
    280  1.13    dante 		return (error);
    281  1.13    dante 	}
    282  1.13    dante */
    283  1.13    dante 	/*
    284  1.13    dante 	 * put in the phystokv hash table
    285  1.13    dante 	 * Never gets taken out.
    286  1.13    dante 	 */
    287  1.13    dante 	carr_pa = ADW_CARRIER_ADDR(sc, carr);
    288  1.13    dante 	carr->carr_pa = carr_pa;
    289  1.13    dante 	hashnum = CARRIER_HASH(carr_pa);
    290  1.13    dante 	carr->nexthash = sc->sc_carrhash[hashnum];
    291  1.13    dante 	sc->sc_carrhash[hashnum] = carr;
    292  1.13    dante 
    293  1.13    dante 	return(0);
    294  1.13    dante }
    295  1.13    dante 
    296  1.13    dante 
    297  1.13    dante /*
    298  1.13    dante  * Given a physical address, find the Carrier that it corresponds to.
    299  1.13    dante  */
    300  1.13    dante ADW_CARRIER *
    301  1.13    dante adw_carrier_phys_kv(sc, carr_phys)
    302  1.13    dante 	ADW_SOFTC	*sc;
    303  1.13    dante 	u_int32_t	carr_phys;
    304  1.13    dante {
    305  1.13    dante 	int hashnum = CARRIER_HASH(carr_phys);
    306  1.13    dante 	ADW_CARRIER *carr = sc->sc_carrhash[hashnum];
    307  1.13    dante 
    308  1.13    dante 	while (carr) {
    309  1.13    dante 		if (carr->carr_pa == carr_phys)
    310  1.13    dante 			break;
    311  1.13    dante 		carr = carr->nexthash;
    312  1.13    dante 	}
    313  1.13    dante 	return (carr);
    314  1.13    dante }
    315  1.13    dante 
    316  1.13    dante 
    317  1.13    dante /*
    318   1.1    dante  * Create a set of ccbs and add them to the free list.  Called once
    319   1.1    dante  * by adw_init().  We return the number of CCBs successfully created.
    320   1.1    dante  */
    321   1.1    dante static int
    322   1.1    dante adw_create_ccbs(sc, ccbstore, count)
    323   1.1    dante 	ADW_SOFTC      *sc;
    324   1.1    dante 	ADW_CCB        *ccbstore;
    325   1.1    dante 	int             count;
    326   1.1    dante {
    327   1.1    dante 	ADW_CCB        *ccb;
    328   1.1    dante 	int             i, error;
    329   1.1    dante 
    330   1.1    dante 	for (i = 0; i < count; i++) {
    331   1.1    dante 		ccb = &ccbstore[i];
    332   1.1    dante 		if ((error = adw_init_ccb(sc, ccb)) != 0) {
    333   1.1    dante 			printf("%s: unable to initialize ccb, error = %d\n",
    334   1.1    dante 			       sc->sc_dev.dv_xname, error);
    335   1.1    dante 			return (i);
    336   1.1    dante 		}
    337   1.1    dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    338   1.1    dante 	}
    339   1.1    dante 
    340   1.1    dante 	return (i);
    341   1.1    dante }
    342   1.1    dante 
    343   1.1    dante 
    344   1.1    dante /*
    345   1.1    dante  * A ccb is put onto the free list.
    346   1.1    dante  */
    347   1.1    dante static void
    348   1.1    dante adw_free_ccb(sc, ccb)
    349   1.1    dante 	ADW_SOFTC      *sc;
    350   1.1    dante 	ADW_CCB        *ccb;
    351   1.1    dante {
    352   1.1    dante 	int             s;
    353   1.1    dante 
    354   1.1    dante 	s = splbio();
    355   1.1    dante 
    356   1.1    dante 	adw_reset_ccb(ccb);
    357   1.1    dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    358   1.1    dante 
    359   1.1    dante 	/*
    360   1.1    dante          * If there were none, wake anybody waiting for one to come free,
    361   1.1    dante          * starting with queued entries.
    362   1.1    dante          */
    363   1.1    dante 	if (ccb->chain.tqe_next == 0)
    364   1.1    dante 		wakeup(&sc->sc_free_ccb);
    365   1.1    dante 
    366   1.1    dante 	splx(s);
    367   1.1    dante }
    368   1.1    dante 
    369   1.1    dante 
    370   1.1    dante static void
    371   1.1    dante adw_reset_ccb(ccb)
    372   1.1    dante 	ADW_CCB        *ccb;
    373   1.1    dante {
    374   1.1    dante 
    375   1.1    dante 	ccb->flags = 0;
    376   1.1    dante }
    377   1.1    dante 
    378   1.1    dante 
    379   1.1    dante static int
    380   1.1    dante adw_init_ccb(sc, ccb)
    381   1.1    dante 	ADW_SOFTC      *sc;
    382   1.1    dante 	ADW_CCB        *ccb;
    383   1.1    dante {
    384   1.7    dante 	int	hashnum, error;
    385   1.1    dante 
    386   1.1    dante 	/*
    387   1.1    dante          * Create the DMA map for this CCB.
    388   1.1    dante          */
    389   1.1    dante 	error = bus_dmamap_create(sc->sc_dmat,
    390   1.1    dante 				  (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    391   1.1    dante 			 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    392   1.1    dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    393   1.1    dante 	if (error) {
    394  1.13    dante 		printf("%s: unable to create CCB DMA map, error = %d\n",
    395   1.1    dante 		       sc->sc_dev.dv_xname, error);
    396   1.1    dante 		return (error);
    397   1.1    dante 	}
    398   1.7    dante 
    399   1.7    dante 	/*
    400   1.7    dante 	 * put in the phystokv hash table
    401   1.7    dante 	 * Never gets taken out.
    402   1.7    dante 	 */
    403   1.7    dante 	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    404   1.7    dante 	    ADW_CCB_OFF(ccb);
    405   1.7    dante 	hashnum = CCB_HASH(ccb->hashkey);
    406   1.7    dante 	ccb->nexthash = sc->sc_ccbhash[hashnum];
    407   1.7    dante 	sc->sc_ccbhash[hashnum] = ccb;
    408   1.1    dante 	adw_reset_ccb(ccb);
    409   1.1    dante 	return (0);
    410   1.1    dante }
    411   1.1    dante 
    412   1.1    dante 
    413   1.1    dante /*
    414   1.1    dante  * Get a free ccb
    415   1.1    dante  *
    416   1.1    dante  * If there are none, see if we can allocate a new one
    417   1.1    dante  */
    418   1.1    dante static ADW_CCB *
    419   1.1    dante adw_get_ccb(sc, flags)
    420   1.1    dante 	ADW_SOFTC      *sc;
    421   1.1    dante 	int             flags;
    422   1.1    dante {
    423   1.1    dante 	ADW_CCB        *ccb = 0;
    424   1.1    dante 	int             s;
    425   1.1    dante 
    426   1.1    dante 	s = splbio();
    427   1.1    dante 
    428   1.1    dante 	/*
    429   1.1    dante          * If we can and have to, sleep waiting for one to come free
    430   1.1    dante          * but only if we can't allocate a new one.
    431   1.1    dante          */
    432   1.1    dante 	for (;;) {
    433   1.1    dante 		ccb = sc->sc_free_ccb.tqh_first;
    434   1.1    dante 		if (ccb) {
    435   1.1    dante 			TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    436   1.1    dante 			break;
    437   1.1    dante 		}
    438  1.12  thorpej 		if ((flags & XS_CTL_NOSLEEP) != 0)
    439   1.1    dante 			goto out;
    440   1.1    dante 
    441   1.1    dante 		tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
    442   1.1    dante 	}
    443   1.1    dante 
    444   1.1    dante 	ccb->flags |= CCB_ALLOC;
    445   1.1    dante 
    446   1.1    dante out:
    447   1.1    dante 	splx(s);
    448   1.1    dante 	return (ccb);
    449   1.1    dante }
    450   1.1    dante 
    451   1.1    dante 
    452   1.1    dante /*
    453   1.7    dante  * Given a physical address, find the ccb that it corresponds to.
    454   1.7    dante  */
    455   1.7    dante ADW_CCB *
    456   1.7    dante adw_ccb_phys_kv(sc, ccb_phys)
    457   1.7    dante 	ADW_SOFTC	*sc;
    458   1.9  thorpej 	u_int32_t	ccb_phys;
    459   1.7    dante {
    460   1.7    dante 	int hashnum = CCB_HASH(ccb_phys);
    461   1.7    dante 	ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
    462   1.7    dante 
    463   1.7    dante 	while (ccb) {
    464   1.7    dante 		if (ccb->hashkey == ccb_phys)
    465   1.7    dante 			break;
    466   1.7    dante 		ccb = ccb->nexthash;
    467   1.7    dante 	}
    468   1.7    dante 	return (ccb);
    469   1.7    dante }
    470   1.7    dante 
    471   1.7    dante 
    472   1.7    dante /*
    473   1.1    dante  * Queue a CCB to be sent to the controller, and send it if possible.
    474   1.1    dante  */
    475  1.13    dante static int
    476  1.13    dante adw_queue_ccb(sc, ccb, retry)
    477   1.1    dante 	ADW_SOFTC      *sc;
    478   1.1    dante 	ADW_CCB        *ccb;
    479  1.13    dante 	int		retry;
    480   1.1    dante {
    481  1.13    dante 	int		errcode;
    482   1.1    dante 
    483  1.13    dante 	if(!retry)
    484  1.13    dante 		TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    485  1.17  thorpej 
    486  1.17  thorpej 	errcode = ADW_SUCCESS;
    487   1.1    dante 
    488  1.13    dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    489   1.1    dante 
    490  1.13    dante 		errcode = AdvExeScsiQueue(sc, &ccb->scsiq);
    491  1.13    dante 		switch(errcode) {
    492  1.13    dante 		case ADW_SUCCESS:
    493  1.13    dante 			break;
    494   1.1    dante 
    495  1.13    dante 		case ADW_BUSY:
    496  1.13    dante 			printf("ADW_BUSY\n");
    497  1.13    dante 			return(ADW_BUSY);
    498  1.13    dante 
    499  1.13    dante 		case ADW_ERROR:
    500  1.13    dante 			printf("ADW_ERROR\n");
    501  1.13    dante 			TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    502  1.13    dante 			return(ADW_ERROR);
    503  1.13    dante 		}
    504  1.11    dante 
    505   1.1    dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    506   1.1    dante 
    507  1.12  thorpej 		if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
    508  1.15  thorpej 			callout_reset(&ccb->xs->xs_callout,
    509  1.15  thorpej 			    (ccb->timeout * hz) / 1000, adw_timeout, ccb);
    510   1.1    dante 	}
    511  1.13    dante 
    512  1.13    dante 	return(errcode);
    513   1.1    dante }
    514   1.1    dante 
    515   1.1    dante 
    516   1.1    dante /******************************************************************************/
    517   1.7    dante /*                           SCSI layer interfacing routines                  */
    518   1.1    dante /******************************************************************************/
    519   1.1    dante 
    520   1.1    dante 
    521   1.1    dante int
    522   1.1    dante adw_init(sc)
    523   1.1    dante 	ADW_SOFTC      *sc;
    524   1.1    dante {
    525   1.2    dante 	u_int16_t       warn_code;
    526   1.1    dante 
    527   1.1    dante 
    528   1.1    dante 	sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
    529   1.2    dante 		ADW_LIB_VERSION_MINOR;
    530   1.1    dante 	sc->cfg.chip_version =
    531   1.1    dante 		ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
    532   1.1    dante 
    533   1.1    dante 	/*
    534   1.1    dante 	 * Reset the chip to start and allow register writes.
    535   1.1    dante 	 */
    536   1.1    dante 	if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
    537   1.1    dante 		panic("adw_init: adw_find_signature failed");
    538   1.2    dante 	} else {
    539   1.1    dante 		AdvResetChip(sc->sc_iot, sc->sc_ioh);
    540   1.1    dante 
    541  1.16    dante 		switch(sc->chip_type) {
    542  1.16    dante 		case ADV_CHIP_ASC3550:
    543  1.16    dante 			warn_code = AdvInitFrom3550EEP(sc);
    544  1.16    dante 			break;
    545  1.16    dante 
    546  1.16    dante 		case ADV_CHIP_ASC38C0800:
    547  1.16    dante 			warn_code = AdvInitFrom38C0800EEP(sc);
    548  1.16    dante 			break;
    549  1.16    dante 
    550  1.16    dante 		case ADV_CHIP_ASC38C1600:
    551  1.16    dante 			warn_code = AdvInitFrom38C1600EEP(sc);
    552  1.16    dante 			break;
    553  1.16    dante 
    554  1.16    dante 		default:
    555  1.16    dante 			return -1;
    556  1.16    dante 		}
    557  1.13    dante 
    558   1.2    dante 		if (warn_code & ASC_WARN_EEPROM_CHKSUM)
    559   1.1    dante 			printf("%s: Bad checksum found. "
    560   1.2    dante 			       "Setting default values\n",
    561   1.2    dante 			       sc->sc_dev.dv_xname);
    562   1.2    dante 		if (warn_code & ASC_WARN_EEPROM_TERMINATION)
    563   1.1    dante 			printf("%s: Bad bus termination setting."
    564   1.2    dante 			       "Using automatic termination.\n",
    565   1.2    dante 			       sc->sc_dev.dv_xname);
    566   1.1    dante 	}
    567   1.1    dante 
    568  1.13    dante 	sc->isr_callback = (ADW_CALLBACK) adw_isr_callback;
    569  1.13    dante 	sc->async_callback = (ADW_CALLBACK) adw_async_callback;
    570   1.1    dante 
    571  1.16    dante 	return 0;
    572   1.1    dante }
    573   1.1    dante 
    574   1.1    dante 
    575   1.1    dante void
    576   1.1    dante adw_attach(sc)
    577   1.1    dante 	ADW_SOFTC      *sc;
    578   1.1    dante {
    579   1.1    dante 	int             i, error;
    580   1.1    dante 
    581   1.1    dante 
    582  1.13    dante 	TAILQ_INIT(&sc->sc_free_ccb);
    583  1.13    dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    584  1.13    dante 	TAILQ_INIT(&sc->sc_queue);
    585  1.13    dante 
    586  1.13    dante 
    587  1.13    dante 	/*
    588  1.13    dante          * Allocate the Control Blocks.
    589  1.13    dante          */
    590  1.13    dante 	error = adw_alloc_controls(sc);
    591  1.13    dante 	if (error)
    592  1.13    dante 		return; /* (error) */ ;
    593  1.13    dante 
    594  1.13    dante 	bzero(sc->sc_control, sizeof(struct adw_control));
    595  1.13    dante 
    596  1.13    dante 	/*
    597  1.13    dante 	 * Create and initialize the Control Blocks.
    598  1.13    dante 	 */
    599  1.13    dante 	i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
    600  1.13    dante 	if (i == 0) {
    601  1.13    dante 		printf("%s: unable to create Control Blocks\n",
    602  1.13    dante 		       sc->sc_dev.dv_xname);
    603  1.13    dante 		return; /* (ENOMEM) */ ;
    604  1.13    dante 	} else if (i != ADW_MAX_CCB) {
    605  1.13    dante 		printf("%s: WARNING: only %d of %d Control Blocks"
    606  1.13    dante 		       " created\n",
    607  1.13    dante 		       sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
    608  1.13    dante 	}
    609  1.13    dante 
    610  1.13    dante 	/*
    611  1.13    dante 	 * Create and initialize the Carriers.
    612  1.13    dante 	 */
    613  1.13    dante 	error = adw_alloc_carriers(sc);
    614  1.13    dante 	if (error)
    615  1.13    dante 		return; /* (error) */ ;
    616  1.13    dante 
    617  1.13    dante 	bzero(sc->sc_control->carriers, ADW_CARRIER_SIZE * ADW_MAX_CARRIER);
    618  1.13    dante 
    619  1.13    dante 	i = adw_create_carriers(sc);
    620  1.13    dante 	if (i == 0) {
    621  1.13    dante 		printf("%s: unable to create Carriers\n",
    622  1.13    dante 		       sc->sc_dev.dv_xname);
    623  1.13    dante 		return; /* (ENOMEM) */ ;
    624  1.13    dante 	} else if (i != ADW_MAX_CARRIER) {
    625  1.13    dante 		printf("%s: WARNING: only %d of %d Carriers created\n",
    626  1.13    dante 		       sc->sc_dev.dv_xname, i, ADW_MAX_CARRIER);
    627  1.13    dante 	}
    628  1.13    dante 
    629  1.13    dante 
    630   1.1    dante 	/*
    631  1.16    dante 	 * Initialize the adapter
    632   1.1    dante 	 */
    633  1.16    dante 	switch(sc->chip_type) {
    634  1.16    dante 	case ADV_CHIP_ASC3550:
    635  1.16    dante 		error = AdvInitAsc3550Driver(sc);
    636  1.16    dante 		break;
    637  1.16    dante 
    638  1.16    dante 	case ADV_CHIP_ASC38C0800:
    639  1.16    dante 		error = AdvInitAsc38C0800Driver(sc);
    640  1.16    dante 		break;
    641  1.16    dante 
    642  1.16    dante 	case ADV_CHIP_ASC38C1600:
    643  1.16    dante 		error = AdvInitAsc38C1600Driver(sc);
    644  1.16    dante 		break;
    645  1.16    dante 
    646  1.16    dante 	default:
    647  1.16    dante 		return;
    648  1.16    dante 	}
    649  1.16    dante 
    650  1.13    dante 	switch (error) {
    651   1.2    dante 	case ASC_IERR_MCODE_CHKSUM:
    652   1.2    dante 		panic("%s: Microcode checksum error",
    653   1.2    dante 		      sc->sc_dev.dv_xname);
    654   1.2    dante 		break;
    655   1.2    dante 
    656   1.2    dante 	case ASC_IERR_ILLEGAL_CONNECTION:
    657   1.2    dante 		panic("%s: All three connectors are in use",
    658   1.2    dante 		      sc->sc_dev.dv_xname);
    659   1.2    dante 		break;
    660   1.2    dante 
    661   1.2    dante 	case ASC_IERR_REVERSED_CABLE:
    662   1.2    dante 		panic("%s: Cable is reversed",
    663   1.2    dante 		      sc->sc_dev.dv_xname);
    664   1.2    dante 		break;
    665   1.2    dante 
    666   1.2    dante 	case ASC_IERR_SINGLE_END_DEVICE:
    667   1.2    dante 		panic("%s: single-ended device is attached to"
    668   1.2    dante 		      " one of the connectors",
    669   1.2    dante 		      sc->sc_dev.dv_xname);
    670   1.2    dante 		break;
    671  1.13    dante 
    672  1.13    dante 	case ASC_IERR_NO_CARRIER:
    673  1.13    dante 		panic("%s: no carrier",
    674  1.13    dante 		      sc->sc_dev.dv_xname);
    675  1.13    dante 		break;
    676  1.13    dante 
    677  1.13    dante 	case ASC_WARN_BUSRESET_ERROR:
    678  1.13    dante 		printf("%s: WARNING: Bus Reset Error\n",
    679  1.13    dante 		      sc->sc_dev.dv_xname);
    680  1.13    dante 		break;
    681   1.1    dante 	}
    682   1.1    dante 
    683   1.4  thorpej 	/*
    684   1.4  thorpej 	 * Fill in the adapter.
    685   1.4  thorpej 	 */
    686   1.4  thorpej 	sc->sc_adapter.scsipi_cmd = adw_scsi_cmd;
    687   1.4  thorpej 	sc->sc_adapter.scsipi_minphys = adwminphys;
    688   1.1    dante 
    689   1.1    dante 	/*
    690   1.1    dante          * fill in the prototype scsipi_link.
    691   1.1    dante          */
    692   1.1    dante 	sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
    693   1.1    dante 	sc->sc_link.adapter_softc = sc;
    694   1.1    dante 	sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
    695   1.4  thorpej 	sc->sc_link.adapter = &sc->sc_adapter;
    696   1.1    dante 	sc->sc_link.device = &adw_dev;
    697   1.1    dante 	sc->sc_link.openings = 4;
    698   1.1    dante 	sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID;
    699   1.5   mjacob 	sc->sc_link.scsipi_scsi.max_lun = 7;
    700   1.1    dante 	sc->sc_link.type = BUS_SCSI;
    701   1.1    dante 
    702   1.1    dante 
    703   1.1    dante 	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
    704   1.1    dante }
    705   1.1    dante 
    706   1.1    dante 
    707   1.1    dante static void
    708   1.1    dante adwminphys(bp)
    709   1.1    dante 	struct buf     *bp;
    710   1.1    dante {
    711   1.1    dante 
    712   1.1    dante 	if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
    713   1.1    dante 		bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
    714   1.1    dante 	minphys(bp);
    715   1.1    dante }
    716   1.1    dante 
    717   1.1    dante 
    718   1.1    dante /*
    719   1.2    dante  * start a scsi operation given the command and the data address.
    720   1.2    dante  * Also needs the unit, target and lu.
    721   1.1    dante  */
    722   1.1    dante static int
    723   1.1    dante adw_scsi_cmd(xs)
    724   1.1    dante 	struct scsipi_xfer *xs;
    725   1.1    dante {
    726   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    727   1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    728   1.1    dante 	ADW_CCB        *ccb;
    729  1.14  thorpej 	int             s, fromqueue = 1, dontqueue = 0, nowait = 0, retry = 0;
    730  1.14  thorpej 	int		flags;
    731   1.1    dante 
    732   1.1    dante 	s = splbio();		/* protect the queue */
    733   1.1    dante 
    734   1.1    dante 	/*
    735   1.1    dante          * If we're running the queue from adw_done(), we've been
    736   1.1    dante          * called with the first queue entry as our argument.
    737   1.1    dante          */
    738   1.6  thorpej 	if (xs == TAILQ_FIRST(&sc->sc_queue)) {
    739   1.6  thorpej 		TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    740   1.1    dante 		fromqueue = 1;
    741  1.14  thorpej 		nowait = 1;
    742   1.1    dante 	} else {
    743   1.1    dante 
    744   1.1    dante 		/* Polled requests can't be queued for later. */
    745  1.12  thorpej 		dontqueue = xs->xs_control & XS_CTL_POLL;
    746   1.1    dante 
    747   1.1    dante 		/*
    748   1.1    dante                  * If there are jobs in the queue, run them first.
    749   1.1    dante                  */
    750   1.6  thorpej 		if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
    751   1.1    dante 			/*
    752   1.1    dante                          * If we can't queue, we have to abort, since
    753   1.1    dante                          * we have to preserve order.
    754   1.1    dante                          */
    755   1.1    dante 			if (dontqueue) {
    756   1.1    dante 				splx(s);
    757   1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    758   1.1    dante 				return (TRY_AGAIN_LATER);
    759   1.1    dante 			}
    760   1.1    dante 			/*
    761   1.1    dante                          * Swap with the first queue entry.
    762   1.1    dante                          */
    763   1.6  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    764   1.6  thorpej 			xs = TAILQ_FIRST(&sc->sc_queue);
    765   1.6  thorpej 			TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    766   1.1    dante 			fromqueue = 1;
    767   1.1    dante 		}
    768   1.1    dante 	}
    769   1.1    dante 
    770   1.1    dante 
    771   1.1    dante 	/*
    772   1.1    dante          * get a ccb to use. If the transfer
    773   1.1    dante          * is from a buf (possibly from interrupt time)
    774   1.1    dante          * then we can't allow it to sleep
    775   1.1    dante          */
    776   1.1    dante 
    777  1.14  thorpej 	flags = xs->xs_control;
    778  1.14  thorpej 	if (nowait)
    779  1.14  thorpej 		flags |= XS_CTL_NOSLEEP;
    780  1.14  thorpej 	if ((ccb = adw_get_ccb(sc, flags)) == NULL) {
    781   1.1    dante 		/*
    782   1.1    dante                  * If we can't queue, we lose.
    783   1.1    dante                  */
    784   1.1    dante 		if (dontqueue) {
    785   1.1    dante 			splx(s);
    786   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    787   1.1    dante 			return (TRY_AGAIN_LATER);
    788   1.1    dante 		}
    789   1.1    dante 		/*
    790   1.1    dante                  * Stuff ourselves into the queue, in front
    791   1.1    dante                  * if we came off in the first place.
    792   1.1    dante                  */
    793   1.6  thorpej 		if (fromqueue)
    794   1.6  thorpej 			TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
    795   1.6  thorpej 		else
    796   1.6  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    797   1.1    dante 		splx(s);
    798   1.1    dante 		return (SUCCESSFULLY_QUEUED);
    799   1.1    dante 	}
    800   1.1    dante 	splx(s);		/* done playing with the queue */
    801   1.1    dante 
    802   1.1    dante 	ccb->xs = xs;
    803   1.1    dante 	ccb->timeout = xs->timeout;
    804   1.1    dante 
    805  1.14  thorpej 	if (adw_build_req(xs, ccb, flags)) {
    806  1.13    dante retryagain:
    807  1.13    dante 		s = splbio();
    808  1.13    dante 		retry = adw_queue_ccb(sc, ccb, retry);
    809  1.13    dante 		splx(s);
    810  1.13    dante 
    811  1.13    dante 		switch(retry) {
    812  1.13    dante 		case ADW_BUSY:
    813  1.13    dante 			goto retryagain;
    814  1.13    dante 
    815  1.13    dante 		case ADW_ERROR:
    816  1.13    dante 			xs->error = XS_DRIVER_STUFFUP;
    817  1.13    dante 			return (COMPLETE);
    818  1.13    dante 
    819  1.13    dante 		}
    820   1.1    dante 
    821   1.1    dante 		/*
    822   1.1    dante 	         * Usually return SUCCESSFULLY QUEUED
    823   1.1    dante 	         */
    824  1.12  thorpej 		if ((xs->xs_control & XS_CTL_POLL) == 0)
    825   1.1    dante 			return (SUCCESSFULLY_QUEUED);
    826   1.1    dante 
    827   1.1    dante 		/*
    828   1.1    dante 	         * If we can't use interrupts, poll on completion
    829   1.1    dante 	         */
    830   1.1    dante 		if (adw_poll(sc, xs, ccb->timeout)) {
    831   1.1    dante 			adw_timeout(ccb);
    832   1.1    dante 			if (adw_poll(sc, xs, ccb->timeout))
    833   1.1    dante 				adw_timeout(ccb);
    834   1.1    dante 		}
    835   1.1    dante 	}
    836   1.2    dante 	return (COMPLETE);
    837   1.1    dante }
    838   1.1    dante 
    839   1.1    dante 
    840   1.1    dante /*
    841   1.1    dante  * Build a request structure for the Wide Boards.
    842   1.1    dante  */
    843   1.1    dante static int
    844  1.14  thorpej adw_build_req(xs, ccb, flags)
    845   1.2    dante 	struct scsipi_xfer *xs;
    846   1.2    dante 	ADW_CCB        *ccb;
    847  1.14  thorpej 	int		flags;
    848   1.1    dante {
    849   1.2    dante 	struct scsipi_link *sc_link = xs->sc_link;
    850   1.2    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    851   1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    852   1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    853   1.2    dante 	int             error;
    854   1.1    dante 
    855   1.1    dante 	scsiqp = &ccb->scsiq;
    856   1.1    dante 	bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
    857   1.1    dante 
    858   1.1    dante 	/*
    859   1.7    dante 	 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
    860   1.7    dante 	 * physical CCB structure.
    861   1.1    dante 	 */
    862  1.10  thorpej 	scsiqp->ccb_ptr = ccb->hashkey;
    863   1.1    dante 
    864   1.1    dante 	/*
    865   1.1    dante 	 * Build the ADW_SCSI_REQ_Q request.
    866   1.1    dante 	 */
    867   1.1    dante 
    868   1.1    dante 	/*
    869   1.1    dante 	 * Set CDB length and copy it to the request structure.
    870  1.16    dante 	 * For wide  boards a CDB length maximum of 16 bytes
    871  1.16    dante 	 * is supported.
    872   1.1    dante 	 */
    873  1.16    dante 	bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)?
    874  1.16    dante 			xs->cmdlen : 12 );
    875  1.16    dante 	if(xs->cmdlen > 12)
    876  1.16    dante 		bcopy(&(xs->cmd[12]),  &scsiqp->cdb16, xs->cmdlen - 12);
    877   1.1    dante 
    878   1.1    dante 	scsiqp->target_id = sc_link->scsipi_scsi.target;
    879   1.1    dante 	scsiqp->target_lun = sc_link->scsipi_scsi.lun;
    880   1.1    dante 
    881   1.7    dante 	scsiqp->vsense_addr = &ccb->scsi_sense;
    882  1.13    dante 	scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    883  1.13    dante 			ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
    884  1.13    dante /*	scsiqp->sense_addr = ccb->hashkey +
    885  1.10  thorpej 	    offsetof(struct adw_ccb, scsi_sense);
    886  1.13    dante */	scsiqp->sense_len = sizeof(struct scsipi_sense_data);
    887   1.1    dante 
    888   1.1    dante 	/*
    889   1.1    dante 	 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
    890   1.1    dante 	 */
    891   1.1    dante 	if (xs->datalen) {
    892   1.1    dante 		/*
    893   1.1    dante                  * Map the DMA transfer.
    894   1.1    dante                  */
    895   1.1    dante #ifdef TFS
    896  1.12  thorpej 		if (xs->xs_control & SCSI_DATA_UIO) {
    897   1.1    dante 			error = bus_dmamap_load_uio(dmat,
    898   1.2    dante 				ccb->dmamap_xfer, (struct uio *) xs->data,
    899  1.14  thorpej 				(flags & XS_CTL_NOSLEEP) ?
    900  1.12  thorpej 				BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    901   1.1    dante 		} else
    902  1.13    dante #endif		/* TFS */
    903   1.1    dante 		{
    904   1.1    dante 			error = bus_dmamap_load(dmat,
    905   1.2    dante 			      ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
    906  1.14  thorpej 				(flags & XS_CTL_NOSLEEP) ?
    907  1.12  thorpej 				BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
    908   1.1    dante 		}
    909   1.1    dante 
    910   1.1    dante 		if (error) {
    911   1.1    dante 			if (error == EFBIG) {
    912   1.1    dante 				printf("%s: adw_scsi_cmd, more than %d dma"
    913   1.1    dante 				       " segments\n",
    914   1.1    dante 				       sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
    915   1.1    dante 			} else {
    916   1.1    dante 				printf("%s: adw_scsi_cmd, error %d loading"
    917   1.1    dante 				       " dma map\n",
    918   1.1    dante 				       sc->sc_dev.dv_xname, error);
    919   1.1    dante 			}
    920   1.1    dante 
    921   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    922   1.1    dante 			adw_free_ccb(sc, ccb);
    923   1.1    dante 			return (0);
    924   1.1    dante 		}
    925   1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    926   1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    927  1.13    dante 				(xs->xs_control & XS_CTL_DATA_IN) ?
    928  1.13    dante 				BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
    929   1.1    dante 
    930   1.1    dante 		/*
    931   1.1    dante 		 * Build scatter-gather list.
    932   1.1    dante 		 */
    933   1.1    dante 		scsiqp->data_cnt = xs->datalen;
    934   1.7    dante 		scsiqp->vdata_addr = xs->data;
    935   1.1    dante 		scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
    936   1.7    dante 		bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
    937   1.7    dante 		adw_build_sglist(ccb, scsiqp, ccb->sg_block);
    938   1.1    dante 	} else {
    939   1.1    dante 		/*
    940   1.1    dante                  * No data xfer, use non S/G values.
    941   1.1    dante                  */
    942   1.1    dante 		scsiqp->data_cnt = 0;
    943   1.1    dante 		scsiqp->vdata_addr = 0;
    944   1.1    dante 		scsiqp->data_addr = 0;
    945   1.1    dante 	}
    946   1.1    dante 
    947   1.1    dante 	return (1);
    948   1.1    dante }
    949   1.1    dante 
    950   1.1    dante 
    951   1.1    dante /*
    952   1.1    dante  * Build scatter-gather list for Wide Boards.
    953   1.1    dante  */
    954   1.1    dante static void
    955   1.7    dante adw_build_sglist(ccb, scsiqp, sg_block)
    956   1.2    dante 	ADW_CCB        *ccb;
    957   1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    958   1.7    dante 	ADW_SG_BLOCK   *sg_block;
    959   1.1    dante {
    960   1.9  thorpej 	u_long          sg_block_next_addr;	/* block and its next */
    961   1.9  thorpej 	u_int32_t       sg_block_physical_addr;
    962  1.13    dante 	int             i;	/* how many SG entries */
    963   1.1    dante 	bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
    964   1.2    dante 	int             sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
    965   1.1    dante 
    966   1.1    dante 
    967   1.9  thorpej 	sg_block_next_addr = (u_long) sg_block;	/* allow math operation */
    968  1.10  thorpej 	sg_block_physical_addr = ccb->hashkey +
    969  1.10  thorpej 	    offsetof(struct adw_ccb, sg_block[0]);
    970   1.1    dante 	scsiqp->sg_real_addr = sg_block_physical_addr;
    971   1.1    dante 
    972   1.1    dante 	/*
    973   1.1    dante 	 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
    974   1.1    dante 	 * then split the request into multiple sg-list blocks.
    975   1.1    dante 	 */
    976   1.1    dante 
    977   1.2    dante 	do {
    978   1.2    dante 		for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
    979   1.1    dante 			sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
    980   1.1    dante 			sg_block->sg_list[i].sg_count = sg_list->ds_len;
    981   1.1    dante 
    982   1.2    dante 			if (--sg_elem_cnt == 0) {
    983   1.1    dante 				/* last entry, get out */
    984  1.13    dante 				sg_block->sg_cnt = i + i;
    985   1.2    dante 				sg_block->sg_ptr = NULL; /* next link = NULL */
    986   1.1    dante 				return;
    987   1.1    dante 			}
    988   1.1    dante 			sg_list++;
    989   1.1    dante 		}
    990   1.1    dante 		sg_block_next_addr += sizeof(ADW_SG_BLOCK);
    991   1.1    dante 		sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
    992   1.1    dante 
    993  1.13    dante 		sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
    994   1.9  thorpej 		sg_block->sg_ptr = sg_block_physical_addr;
    995   1.2    dante 		sg_block = (ADW_SG_BLOCK *) sg_block_next_addr;	/* virt. addr */
    996  1.10  thorpej 	} while (1);
    997   1.1    dante }
    998   1.1    dante 
    999   1.1    dante 
   1000   1.1    dante int
   1001   1.1    dante adw_intr(arg)
   1002   1.1    dante 	void           *arg;
   1003   1.1    dante {
   1004   1.1    dante 	ADW_SOFTC      *sc = arg;
   1005   1.1    dante 	struct scsipi_xfer *xs;
   1006   1.1    dante 
   1007   1.1    dante 
   1008  1.13    dante 	if(AdvISR(sc) != ADW_FALSE) {
   1009  1.13    dante 		/*
   1010  1.13    dante 	         * If there are queue entries in the software queue, try to
   1011  1.13    dante 	         * run the first one.  We should be more or less guaranteed
   1012  1.13    dante 	         * to succeed, since we just freed a CCB.
   1013  1.13    dante 	         *
   1014  1.13    dante 	         * NOTE: adw_scsi_cmd() relies on our calling it with
   1015  1.13    dante 	         * the first entry in the queue.
   1016  1.13    dante 	         */
   1017  1.13    dante 		if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
   1018  1.13    dante 			(void) adw_scsi_cmd(xs);
   1019  1.16    dante 
   1020  1.16    dante 		return (1);
   1021  1.13    dante 	}
   1022   1.1    dante 
   1023  1.16    dante 	return (0);
   1024   1.1    dante }
   1025   1.1    dante 
   1026   1.1    dante 
   1027   1.1    dante /*
   1028   1.1    dante  * Poll a particular unit, looking for a particular xs
   1029   1.1    dante  */
   1030   1.1    dante static int
   1031   1.1    dante adw_poll(sc, xs, count)
   1032   1.1    dante 	ADW_SOFTC      *sc;
   1033   1.1    dante 	struct scsipi_xfer *xs;
   1034   1.1    dante 	int             count;
   1035   1.1    dante {
   1036   1.1    dante 
   1037   1.1    dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
   1038   1.1    dante 	while (count) {
   1039   1.1    dante 		adw_intr(sc);
   1040  1.12  thorpej 		if (xs->xs_status & XS_STS_DONE)
   1041   1.1    dante 			return (0);
   1042   1.1    dante 		delay(1000);	/* only happens in boot so ok */
   1043   1.1    dante 		count--;
   1044   1.1    dante 	}
   1045   1.1    dante 	return (1);
   1046   1.1    dante }
   1047   1.1    dante 
   1048   1.1    dante 
   1049   1.1    dante static void
   1050   1.1    dante adw_timeout(arg)
   1051   1.1    dante 	void           *arg;
   1052   1.1    dante {
   1053   1.1    dante 	ADW_CCB        *ccb = arg;
   1054   1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
   1055   1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
   1056   1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
   1057   1.1    dante 	int             s;
   1058   1.1    dante 
   1059   1.1    dante 	scsi_print_addr(sc_link);
   1060   1.1    dante 	printf("timed out");
   1061   1.1    dante 
   1062   1.1    dante 	s = splbio();
   1063   1.1    dante 
   1064   1.1    dante 	/*
   1065   1.1    dante          * If it has been through before, then a previous abort has failed,
   1066   1.1    dante          * don't try abort again, reset the bus instead.
   1067   1.1    dante          */
   1068  1.11    dante 	if (ccb->flags & CCB_ABORTED) {
   1069  1.11    dante 	/*
   1070  1.11    dante 	 * Abort Timed Out
   1071  1.11    dante 	 * Lets try resetting the bus!
   1072  1.11    dante 	 */
   1073  1.11    dante 		printf(" AGAIN. Resetting SCSI Bus\n");
   1074  1.11    dante 		ccb->flags &= ~CCB_ABORTED;
   1075  1.11    dante 		/* AdvResetSCSIBus() will call sbreset_callback() */
   1076   1.1    dante 		AdvResetSCSIBus(sc);
   1077   1.1    dante 	} else {
   1078  1.11    dante 	/*
   1079  1.11    dante 	 * Abort the operation that has timed out
   1080  1.11    dante 	 */
   1081   1.1    dante 		printf("\n");
   1082  1.11    dante 		xs->error = XS_TIMEOUT;
   1083  1.11    dante 		ccb->flags |= CCB_ABORTING;
   1084  1.11    dante 		/* ADW_ABORT_CCB() will implicitly call isr_callback() */
   1085   1.1    dante 		ADW_ABORT_CCB(sc, ccb);
   1086   1.1    dante 	}
   1087   1.1    dante 
   1088   1.1    dante 	splx(s);
   1089   1.1    dante }
   1090   1.1    dante 
   1091   1.1    dante 
   1092   1.1    dante /******************************************************************************/
   1093   1.7    dante /*                           WIDE boards Interrupt callbacks                  */
   1094   1.1    dante /******************************************************************************/
   1095   1.1    dante 
   1096   1.1    dante 
   1097   1.1    dante /*
   1098  1.13    dante  * adw__isr_callback() - Second Level Interrupt Handler called by AdvISR()
   1099   1.1    dante  *
   1100   1.1    dante  * Interrupt callback function for the Wide SCSI Adv Library.
   1101   1.1    dante  */
   1102   1.1    dante static void
   1103  1.13    dante adw_isr_callback(sc, scsiq)
   1104   1.1    dante 	ADW_SOFTC      *sc;
   1105   1.1    dante 	ADW_SCSI_REQ_Q *scsiq;
   1106   1.1    dante {
   1107   1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
   1108   1.7    dante 	ADW_CCB        *ccb;
   1109   1.7    dante 	struct scsipi_xfer *xs;
   1110   1.1    dante 	struct scsipi_sense_data *s1, *s2;
   1111  1.13    dante //	int		 s;
   1112   1.1    dante 
   1113   1.7    dante 
   1114   1.7    dante 	ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
   1115  1.11    dante 
   1116  1.15  thorpej 	callout_stop(&ccb->xs->xs_callout);
   1117  1.11    dante 
   1118  1.13    dante /*	if(ccb->flags & CCB_ABORTING) {
   1119  1.11    dante 		printf("Retrying request\n");
   1120  1.11    dante 		ccb->flags &= ~CCB_ABORTING;
   1121  1.11    dante 		ccb->flags |= CCB_ABORTED;
   1122  1.11    dante 		s = splbio();
   1123  1.11    dante 		adw_queue_ccb(sc, ccb);
   1124  1.11    dante 		splx(s);
   1125  1.11    dante 		return;
   1126  1.11    dante 	}
   1127  1.13    dante */
   1128   1.7    dante 	xs = ccb->xs;
   1129   1.1    dante 
   1130   1.1    dante 	/*
   1131   1.1    dante          * If we were a data transfer, unload the map that described
   1132   1.1    dante          * the data buffer.
   1133   1.1    dante          */
   1134   1.1    dante 	if (xs->datalen) {
   1135   1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
   1136   1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
   1137  1.12  thorpej 			 (xs->xs_control & XS_CTL_DATA_IN) ?
   1138  1.12  thorpej 			 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   1139   1.1    dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
   1140   1.1    dante 	}
   1141   1.1    dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
   1142   1.1    dante 		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
   1143   1.1    dante 		Debugger();
   1144   1.1    dante 		return;
   1145   1.1    dante 	}
   1146   1.1    dante 	/*
   1147   1.1    dante 	 * Check for an underrun condition.
   1148   1.1    dante 	 */
   1149   1.2    dante 	/*
   1150   1.2    dante 	 * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
   1151   1.2    dante 	 * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
   1152   1.2    dante 	 * scsiqp->data_cnt); underrun = ASC_TRUE; }
   1153   1.2    dante 	 */
   1154   1.1    dante 	/*
   1155   1.1    dante 	 * 'done_status' contains the command's ending status.
   1156   1.1    dante 	 */
   1157   1.1    dante 	switch (scsiq->done_status) {
   1158   1.1    dante 	case QD_NO_ERROR:
   1159   1.1    dante 		switch (scsiq->host_status) {
   1160   1.1    dante 		case QHSTA_NO_ERROR:
   1161   1.1    dante 			xs->error = XS_NOERROR;
   1162   1.1    dante 			xs->resid = 0;
   1163   1.1    dante 			break;
   1164   1.1    dante 		default:
   1165   1.1    dante 			/* QHSTA error occurred. */
   1166   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
   1167   1.1    dante 			break;
   1168   1.1    dante 		}
   1169  1.13    dante 		break;
   1170   1.1    dante 
   1171   1.1    dante 	case QD_WITH_ERROR:
   1172   1.1    dante 		switch (scsiq->host_status) {
   1173   1.1    dante 		case QHSTA_NO_ERROR:
   1174  1.11    dante 			switch(scsiq->scsi_status) {
   1175  1.11    dante 			case SS_CHK_CONDITION:
   1176  1.11    dante 			case SS_CMD_TERMINATED:
   1177   1.1    dante 				s1 = &ccb->scsi_sense;
   1178   1.1    dante 				s2 = &xs->sense.scsi_sense;
   1179   1.1    dante 				*s2 = *s1;
   1180   1.1    dante 				xs->error = XS_SENSE;
   1181  1.11    dante 				break;
   1182  1.11    dante 			case SS_TARGET_BUSY:
   1183  1.11    dante 			case SS_RSERV_CONFLICT:
   1184  1.11    dante 			case SS_QUEUE_FULL:
   1185  1.11    dante 				xs->error = XS_DRIVER_STUFFUP;
   1186  1.11    dante 				break;
   1187  1.11    dante 			case SS_CONDITION_MET:
   1188  1.11    dante 			case SS_INTERMID:
   1189  1.11    dante 			case SS_INTERMID_COND_MET:
   1190   1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
   1191  1.11    dante 				break;
   1192  1.11    dante 			case SS_GOOD:
   1193  1.11    dante 				break;
   1194   1.1    dante 			}
   1195   1.1    dante 			break;
   1196   1.1    dante 
   1197  1.11    dante 		case QHSTA_M_SEL_TIMEOUT:
   1198  1.11    dante 			xs->error = XS_DRIVER_STUFFUP;
   1199  1.11    dante 			break;
   1200  1.11    dante 
   1201   1.1    dante 		default:
   1202   1.1    dante 			/* Some other QHSTA error occurred. */
   1203   1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
   1204   1.1    dante 			break;
   1205   1.1    dante 		}
   1206   1.1    dante 		break;
   1207   1.1    dante 
   1208   1.1    dante 	case QD_ABORTED_BY_HOST:
   1209  1.11    dante 		xs->error = XS_DRIVER_STUFFUP;
   1210  1.11    dante 		break;
   1211  1.11    dante 
   1212   1.1    dante 	default:
   1213   1.1    dante 		xs->error = XS_DRIVER_STUFFUP;
   1214   1.1    dante 		break;
   1215   1.1    dante 	}
   1216   1.1    dante 
   1217   1.1    dante 	adw_free_ccb(sc, ccb);
   1218  1.12  thorpej 	xs->xs_status |= XS_STS_DONE;
   1219   1.1    dante 	scsipi_done(xs);
   1220  1.11    dante }
   1221  1.11    dante 
   1222  1.11    dante 
   1223  1.13    dante /*
   1224  1.13    dante  * adv_async_callback() - Adv Library asynchronous event callback function.
   1225  1.13    dante  */
   1226  1.11    dante static void
   1227  1.13    dante adw_async_callback(sc, code)
   1228  1.11    dante 	ADW_SOFTC	*sc;
   1229  1.13    dante 	u_int8_t	code;
   1230  1.11    dante {
   1231  1.13    dante 	switch (code) {
   1232  1.13    dante 	case ADV_ASYNC_SCSI_BUS_RESET_DET:
   1233  1.13    dante 		/*
   1234  1.13    dante 		 * The firmware detected a SCSI Bus reset.
   1235  1.13    dante 		 */
   1236  1.13    dante 		break;
   1237  1.13    dante 
   1238  1.13    dante 	case ADV_ASYNC_RDMA_FAILURE:
   1239  1.13    dante 		/*
   1240  1.13    dante 		 * Handle RDMA failure by resetting the SCSI Bus and
   1241  1.13    dante 		 * possibly the chip if it is unresponsive. Log the error
   1242  1.13    dante 		 * with a unique code.
   1243  1.13    dante 		 */
   1244  1.13    dante 		AdvResetSCSIBus(sc);
   1245  1.13    dante 		break;
   1246  1.13    dante 
   1247  1.13    dante 	case ADV_HOST_SCSI_BUS_RESET:
   1248  1.13    dante                /*
   1249  1.13    dante                 * Host generated SCSI bus reset occurred.
   1250  1.13    dante                 */
   1251  1.13    dante               break;
   1252  1.13    dante 
   1253  1.13    dante 	default:
   1254  1.13    dante 		break;
   1255  1.13    dante 	}
   1256   1.1    dante }
   1257