adw.c revision 1.2 1 1.2 dante /* $NetBSD: adw.c,v 1.2 1998/09/26 19:54:22 dante Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.1 dante * Generic driver for the Advanced Systems Inc. SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.1 dante * This product includes software developed by the NetBSD
22 1.1 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.1 dante #include <sys/kernel.h>
44 1.1 dante #include <sys/errno.h>
45 1.1 dante #include <sys/ioctl.h>
46 1.1 dante #include <sys/device.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/buf.h>
49 1.1 dante #include <sys/proc.h>
50 1.1 dante #include <sys/user.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <vm/vm.h>
56 1.1 dante #include <vm/vm_param.h>
57 1.1 dante #include <vm/pmap.h>
58 1.1 dante
59 1.1 dante #include <dev/scsipi/scsi_all.h>
60 1.1 dante #include <dev/scsipi/scsipi_all.h>
61 1.1 dante #include <dev/scsipi/scsiconf.h>
62 1.1 dante
63 1.1 dante #include <dev/ic/adwlib.h>
64 1.1 dante #include <dev/ic/adw.h>
65 1.1 dante
66 1.1 dante #ifndef DDB
67 1.1 dante #define Debugger() panic("should call debugger here (adv.c)")
68 1.2 dante #endif /* ! DDB */
69 1.1 dante
70 1.1 dante /******************************************************************************/
71 1.1 dante
72 1.1 dante
73 1.1 dante static void adw_enqueue __P((ADW_SOFTC *, struct scsipi_xfer *, int));
74 1.1 dante static struct scsipi_xfer *adw_dequeue __P((ADW_SOFTC *));
75 1.1 dante
76 1.1 dante static int adw_alloc_ccbs __P((ADW_SOFTC *));
77 1.1 dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
78 1.1 dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
79 1.1 dante static void adw_reset_ccb __P((ADW_CCB *));
80 1.1 dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
81 1.1 dante static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int));
82 1.1 dante static void adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *));
83 1.1 dante static void adw_start_ccbs __P((ADW_SOFTC *));
84 1.1 dante
85 1.1 dante static int adw_scsi_cmd __P((struct scsipi_xfer *));
86 1.1 dante static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *));
87 1.2 dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *));
88 1.1 dante static void adwminphys __P((struct buf *));
89 1.1 dante static void adw_wide_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
90 1.1 dante
91 1.1 dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
92 1.1 dante static void adw_timeout __P((void *));
93 1.1 dante static void adw_watchdog __P((void *));
94 1.1 dante
95 1.1 dante
96 1.1 dante /******************************************************************************/
97 1.1 dante
98 1.1 dante
99 1.1 dante struct scsipi_adapter adw_switch =
100 1.1 dante {
101 1.1 dante adw_scsi_cmd, /* called to start/enqueue a SCSI command */
102 1.1 dante adwminphys, /* to limit the transfer to max device can do */
103 1.1 dante 0, /* IT SEEMS IT IS NOT USED YET */
104 1.1 dante 0, /* as above... */
105 1.1 dante };
106 1.1 dante
107 1.1 dante
108 1.1 dante /* the below structure is so we have a default dev struct for out link struct */
109 1.1 dante struct scsipi_device adw_dev =
110 1.1 dante {
111 1.1 dante NULL, /* Use default error handler */
112 1.1 dante NULL, /* have a queue, served by this */
113 1.1 dante NULL, /* have no async handler */
114 1.1 dante NULL, /* Use default 'done' routine */
115 1.1 dante };
116 1.1 dante
117 1.1 dante
118 1.1 dante #define ADW_ABORT_TIMEOUT 10000 /* time to wait for abort (mSec) */
119 1.1 dante #define ADW_WATCH_TIMEOUT 10000 /* time to wait for watchdog (mSec) */
120 1.1 dante
121 1.1 dante
122 1.1 dante /******************************************************************************/
123 1.2 dante /* scsipi_xfer queue routines */
124 1.1 dante /******************************************************************************/
125 1.1 dante
126 1.1 dante /*
127 1.1 dante * Insert a scsipi_xfer into the software queue. We overload xs->free_list
128 1.1 dante * to avoid having to allocate additional resources (since we're used
129 1.1 dante * only during resource shortages anyhow.
130 1.1 dante */
131 1.1 dante static void
132 1.1 dante adw_enqueue(sc, xs, infront)
133 1.1 dante ADW_SOFTC *sc;
134 1.1 dante struct scsipi_xfer *xs;
135 1.1 dante int infront;
136 1.1 dante {
137 1.1 dante
138 1.1 dante if (infront || sc->sc_queue.lh_first == NULL) {
139 1.1 dante if (sc->sc_queue.lh_first == NULL)
140 1.1 dante sc->sc_queuelast = xs;
141 1.1 dante LIST_INSERT_HEAD(&sc->sc_queue, xs, free_list);
142 1.1 dante return;
143 1.1 dante }
144 1.1 dante LIST_INSERT_AFTER(sc->sc_queuelast, xs, free_list);
145 1.1 dante sc->sc_queuelast = xs;
146 1.1 dante }
147 1.1 dante
148 1.1 dante
149 1.1 dante /*
150 1.1 dante * Pull a scsipi_xfer off the front of the software queue.
151 1.1 dante */
152 1.1 dante static struct scsipi_xfer *
153 1.1 dante adw_dequeue(sc)
154 1.1 dante ADW_SOFTC *sc;
155 1.1 dante {
156 1.1 dante struct scsipi_xfer *xs;
157 1.1 dante
158 1.1 dante xs = sc->sc_queue.lh_first;
159 1.1 dante LIST_REMOVE(xs, free_list);
160 1.1 dante
161 1.1 dante if (sc->sc_queue.lh_first == NULL)
162 1.1 dante sc->sc_queuelast = NULL;
163 1.1 dante
164 1.1 dante return (xs);
165 1.1 dante }
166 1.1 dante
167 1.1 dante
168 1.1 dante /******************************************************************************/
169 1.2 dante /* Control Blocks routines */
170 1.1 dante /******************************************************************************/
171 1.1 dante
172 1.1 dante
173 1.1 dante static int
174 1.1 dante adw_alloc_ccbs(sc)
175 1.1 dante ADW_SOFTC *sc;
176 1.1 dante {
177 1.1 dante bus_dma_segment_t seg;
178 1.1 dante int error, rseg;
179 1.1 dante
180 1.1 dante /*
181 1.1 dante * Allocate the control blocks.
182 1.1 dante */
183 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
184 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
185 1.1 dante printf("%s: unable to allocate control structures,"
186 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
187 1.1 dante return (error);
188 1.1 dante }
189 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
190 1.1 dante sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
191 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
192 1.1 dante printf("%s: unable to map control structures, error = %d\n",
193 1.1 dante sc->sc_dev.dv_xname, error);
194 1.1 dante return (error);
195 1.1 dante }
196 1.1 dante /*
197 1.1 dante * Create and load the DMA map used for the control blocks.
198 1.1 dante */
199 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
200 1.1 dante 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
201 1.1 dante &sc->sc_dmamap_control)) != 0) {
202 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
203 1.1 dante sc->sc_dev.dv_xname, error);
204 1.1 dante return (error);
205 1.1 dante }
206 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
207 1.1 dante sc->sc_control, sizeof(struct adw_control), NULL,
208 1.1 dante BUS_DMA_NOWAIT)) != 0) {
209 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
210 1.1 dante sc->sc_dev.dv_xname, error);
211 1.1 dante return (error);
212 1.1 dante }
213 1.1 dante return (0);
214 1.1 dante }
215 1.1 dante
216 1.1 dante
217 1.1 dante /*
218 1.1 dante * Create a set of ccbs and add them to the free list. Called once
219 1.1 dante * by adw_init(). We return the number of CCBs successfully created.
220 1.1 dante */
221 1.1 dante static int
222 1.1 dante adw_create_ccbs(sc, ccbstore, count)
223 1.1 dante ADW_SOFTC *sc;
224 1.1 dante ADW_CCB *ccbstore;
225 1.1 dante int count;
226 1.1 dante {
227 1.1 dante ADW_CCB *ccb;
228 1.1 dante int i, error;
229 1.1 dante
230 1.1 dante bzero(ccbstore, sizeof(ADW_CCB) * count);
231 1.1 dante for (i = 0; i < count; i++) {
232 1.1 dante ccb = &ccbstore[i];
233 1.1 dante if ((error = adw_init_ccb(sc, ccb)) != 0) {
234 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
235 1.1 dante sc->sc_dev.dv_xname, error);
236 1.1 dante return (i);
237 1.1 dante }
238 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
239 1.1 dante }
240 1.1 dante
241 1.1 dante return (i);
242 1.1 dante }
243 1.1 dante
244 1.1 dante
245 1.1 dante /*
246 1.1 dante * A ccb is put onto the free list.
247 1.1 dante */
248 1.1 dante static void
249 1.1 dante adw_free_ccb(sc, ccb)
250 1.1 dante ADW_SOFTC *sc;
251 1.1 dante ADW_CCB *ccb;
252 1.1 dante {
253 1.1 dante int s;
254 1.1 dante
255 1.1 dante s = splbio();
256 1.1 dante
257 1.1 dante adw_reset_ccb(ccb);
258 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
259 1.1 dante
260 1.1 dante /*
261 1.1 dante * If there were none, wake anybody waiting for one to come free,
262 1.1 dante * starting with queued entries.
263 1.1 dante */
264 1.1 dante if (ccb->chain.tqe_next == 0)
265 1.1 dante wakeup(&sc->sc_free_ccb);
266 1.1 dante
267 1.1 dante splx(s);
268 1.1 dante }
269 1.1 dante
270 1.1 dante
271 1.1 dante static void
272 1.1 dante adw_reset_ccb(ccb)
273 1.1 dante ADW_CCB *ccb;
274 1.1 dante {
275 1.1 dante
276 1.1 dante ccb->flags = 0;
277 1.1 dante }
278 1.1 dante
279 1.1 dante
280 1.1 dante static int
281 1.1 dante adw_init_ccb(sc, ccb)
282 1.1 dante ADW_SOFTC *sc;
283 1.1 dante ADW_CCB *ccb;
284 1.1 dante {
285 1.1 dante int error;
286 1.1 dante
287 1.1 dante /*
288 1.1 dante * Create the DMA map for this CCB.
289 1.1 dante */
290 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
291 1.1 dante (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
292 1.1 dante ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
293 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
294 1.1 dante if (error) {
295 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
296 1.1 dante sc->sc_dev.dv_xname, error);
297 1.1 dante return (error);
298 1.1 dante }
299 1.1 dante adw_reset_ccb(ccb);
300 1.1 dante return (0);
301 1.1 dante }
302 1.1 dante
303 1.1 dante
304 1.1 dante /*
305 1.1 dante * Get a free ccb
306 1.1 dante *
307 1.1 dante * If there are none, see if we can allocate a new one
308 1.1 dante */
309 1.1 dante static ADW_CCB *
310 1.1 dante adw_get_ccb(sc, flags)
311 1.1 dante ADW_SOFTC *sc;
312 1.1 dante int flags;
313 1.1 dante {
314 1.1 dante ADW_CCB *ccb = 0;
315 1.1 dante int s;
316 1.1 dante
317 1.1 dante s = splbio();
318 1.1 dante
319 1.1 dante /*
320 1.1 dante * If we can and have to, sleep waiting for one to come free
321 1.1 dante * but only if we can't allocate a new one.
322 1.1 dante */
323 1.1 dante for (;;) {
324 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
325 1.1 dante if (ccb) {
326 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
327 1.1 dante break;
328 1.1 dante }
329 1.1 dante if ((flags & SCSI_NOSLEEP) != 0)
330 1.1 dante goto out;
331 1.1 dante
332 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
333 1.1 dante }
334 1.1 dante
335 1.1 dante ccb->flags |= CCB_ALLOC;
336 1.1 dante
337 1.1 dante out:
338 1.1 dante splx(s);
339 1.1 dante return (ccb);
340 1.1 dante }
341 1.1 dante
342 1.1 dante
343 1.1 dante /*
344 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
345 1.1 dante */
346 1.1 dante static void
347 1.1 dante adw_queue_ccb(sc, ccb)
348 1.1 dante ADW_SOFTC *sc;
349 1.1 dante ADW_CCB *ccb;
350 1.1 dante {
351 1.1 dante
352 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
353 1.1 dante
354 1.1 dante adw_start_ccbs(sc);
355 1.1 dante }
356 1.1 dante
357 1.1 dante
358 1.1 dante static void
359 1.1 dante adw_start_ccbs(sc)
360 1.1 dante ADW_SOFTC *sc;
361 1.1 dante {
362 1.1 dante ADW_CCB *ccb;
363 1.1 dante
364 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
365 1.1 dante if (ccb->flags & CCB_WATCHDOG)
366 1.1 dante untimeout(adw_watchdog, ccb);
367 1.1 dante
368 1.1 dante if (AdvExeScsiQueue(sc, &ccb->scsiq) == ADW_BUSY) {
369 1.1 dante ccb->flags |= CCB_WATCHDOG;
370 1.1 dante timeout(adw_watchdog, ccb,
371 1.1 dante (ADW_WATCH_TIMEOUT * hz) / 1000);
372 1.1 dante break;
373 1.1 dante }
374 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
375 1.1 dante
376 1.1 dante if ((ccb->xs->flags & SCSI_POLL) == 0)
377 1.1 dante timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000);
378 1.1 dante }
379 1.1 dante }
380 1.1 dante
381 1.1 dante
382 1.1 dante /******************************************************************************/
383 1.2 dante /* SCSI layer interfacing routines */
384 1.1 dante /******************************************************************************/
385 1.1 dante
386 1.1 dante
387 1.1 dante int
388 1.1 dante adw_init(sc)
389 1.1 dante ADW_SOFTC *sc;
390 1.1 dante {
391 1.2 dante u_int16_t warn_code;
392 1.1 dante
393 1.1 dante
394 1.1 dante sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
395 1.2 dante ADW_LIB_VERSION_MINOR;
396 1.1 dante sc->cfg.chip_version =
397 1.1 dante ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
398 1.1 dante
399 1.1 dante /*
400 1.1 dante * Reset the chip to start and allow register writes.
401 1.1 dante */
402 1.1 dante if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
403 1.1 dante panic("adw_init: adw_find_signature failed");
404 1.2 dante } else {
405 1.1 dante AdvResetChip(sc->sc_iot, sc->sc_ioh);
406 1.1 dante
407 1.1 dante warn_code = AdvInitFromEEP(sc);
408 1.2 dante if (warn_code & ASC_WARN_EEPROM_CHKSUM)
409 1.1 dante printf("%s: Bad checksum found. "
410 1.2 dante "Setting default values\n",
411 1.2 dante sc->sc_dev.dv_xname);
412 1.2 dante if (warn_code & ASC_WARN_EEPROM_TERMINATION)
413 1.1 dante printf("%s: Bad bus termination setting."
414 1.2 dante "Using automatic termination.\n",
415 1.2 dante sc->sc_dev.dv_xname);
416 1.1 dante
417 1.1 dante /*
418 1.1 dante * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
419 1.1 dante * Resets should be performed.
420 1.1 dante */
421 1.1 dante if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
422 1.1 dante AdvResetSCSIBus(sc);
423 1.1 dante }
424 1.1 dante
425 1.1 dante sc->isr_callback = (ulong) adw_wide_isr_callback;
426 1.1 dante
427 1.1 dante return (0);
428 1.1 dante }
429 1.1 dante
430 1.1 dante
431 1.1 dante void
432 1.1 dante adw_attach(sc)
433 1.1 dante ADW_SOFTC *sc;
434 1.1 dante {
435 1.1 dante int i, error;
436 1.1 dante
437 1.1 dante
438 1.1 dante /*
439 1.1 dante * Initialize the ASC3550.
440 1.1 dante */
441 1.2 dante switch (AdvInitAsc3550Driver(sc)) {
442 1.2 dante case ASC_IERR_MCODE_CHKSUM:
443 1.2 dante panic("%s: Microcode checksum error",
444 1.2 dante sc->sc_dev.dv_xname);
445 1.2 dante break;
446 1.2 dante
447 1.2 dante case ASC_IERR_ILLEGAL_CONNECTION:
448 1.2 dante panic("%s: All three connectors are in use",
449 1.2 dante sc->sc_dev.dv_xname);
450 1.2 dante break;
451 1.2 dante
452 1.2 dante case ASC_IERR_REVERSED_CABLE:
453 1.2 dante panic("%s: Cable is reversed",
454 1.2 dante sc->sc_dev.dv_xname);
455 1.2 dante break;
456 1.2 dante
457 1.2 dante case ASC_IERR_SINGLE_END_DEVICE:
458 1.2 dante panic("%s: single-ended device is attached to"
459 1.2 dante " one of the connectors",
460 1.2 dante sc->sc_dev.dv_xname);
461 1.2 dante break;
462 1.1 dante }
463 1.1 dante
464 1.1 dante
465 1.1 dante /*
466 1.1 dante * fill in the prototype scsipi_link.
467 1.1 dante */
468 1.1 dante sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
469 1.1 dante sc->sc_link.adapter_softc = sc;
470 1.1 dante sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
471 1.1 dante sc->sc_link.adapter = &adw_switch;
472 1.1 dante sc->sc_link.device = &adw_dev;
473 1.1 dante sc->sc_link.openings = 4;
474 1.1 dante sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID;
475 1.1 dante sc->sc_link.type = BUS_SCSI;
476 1.1 dante
477 1.1 dante
478 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
479 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
480 1.1 dante LIST_INIT(&sc->sc_queue);
481 1.1 dante
482 1.1 dante
483 1.1 dante /*
484 1.1 dante * Allocate the Control Blocks.
485 1.1 dante */
486 1.1 dante error = adw_alloc_ccbs(sc);
487 1.1 dante if (error)
488 1.1 dante return; /* (error) */ ;
489 1.1 dante
490 1.1 dante /*
491 1.1 dante * Create and initialize the Control Blocks.
492 1.1 dante */
493 1.1 dante i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
494 1.1 dante if (i == 0) {
495 1.1 dante printf("%s: unable to create control blocks\n",
496 1.1 dante sc->sc_dev.dv_xname);
497 1.1 dante return; /* (ENOMEM) */ ;
498 1.1 dante } else if (i != ADW_MAX_CCB) {
499 1.1 dante printf("%s: WARNING: only %d of %d control blocks"
500 1.2 dante " created\n",
501 1.2 dante sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
502 1.1 dante }
503 1.1 dante config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
504 1.1 dante }
505 1.1 dante
506 1.1 dante
507 1.1 dante static void
508 1.1 dante adwminphys(bp)
509 1.1 dante struct buf *bp;
510 1.1 dante {
511 1.1 dante
512 1.1 dante if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
513 1.1 dante bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
514 1.1 dante minphys(bp);
515 1.1 dante }
516 1.1 dante
517 1.1 dante
518 1.1 dante /*
519 1.2 dante * start a scsi operation given the command and the data address.
520 1.2 dante * Also needs the unit, target and lu.
521 1.1 dante */
522 1.1 dante static int
523 1.1 dante adw_scsi_cmd(xs)
524 1.1 dante struct scsipi_xfer *xs;
525 1.1 dante {
526 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
527 1.1 dante ADW_SOFTC *sc = sc_link->adapter_softc;
528 1.1 dante ADW_CCB *ccb;
529 1.1 dante int s, fromqueue = 1, dontqueue = 0;
530 1.1 dante
531 1.1 dante s = splbio(); /* protect the queue */
532 1.1 dante
533 1.1 dante /*
534 1.1 dante * If we're running the queue from adw_done(), we've been
535 1.1 dante * called with the first queue entry as our argument.
536 1.1 dante */
537 1.1 dante if (xs == sc->sc_queue.lh_first) {
538 1.1 dante xs = adw_dequeue(sc);
539 1.1 dante fromqueue = 1;
540 1.1 dante } else {
541 1.1 dante
542 1.1 dante /* Polled requests can't be queued for later. */
543 1.1 dante dontqueue = xs->flags & SCSI_POLL;
544 1.1 dante
545 1.1 dante /*
546 1.1 dante * If there are jobs in the queue, run them first.
547 1.1 dante */
548 1.1 dante if (sc->sc_queue.lh_first != NULL) {
549 1.1 dante /*
550 1.1 dante * If we can't queue, we have to abort, since
551 1.1 dante * we have to preserve order.
552 1.1 dante */
553 1.1 dante if (dontqueue) {
554 1.1 dante splx(s);
555 1.1 dante xs->error = XS_DRIVER_STUFFUP;
556 1.1 dante return (TRY_AGAIN_LATER);
557 1.1 dante }
558 1.1 dante /*
559 1.1 dante * Swap with the first queue entry.
560 1.1 dante */
561 1.1 dante adw_enqueue(sc, xs, 0);
562 1.1 dante xs = adw_dequeue(sc);
563 1.1 dante fromqueue = 1;
564 1.1 dante }
565 1.1 dante }
566 1.1 dante
567 1.1 dante
568 1.1 dante /*
569 1.1 dante * get a ccb to use. If the transfer
570 1.1 dante * is from a buf (possibly from interrupt time)
571 1.1 dante * then we can't allow it to sleep
572 1.1 dante */
573 1.1 dante
574 1.1 dante if ((ccb = adw_get_ccb(sc, xs->flags)) == NULL) {
575 1.1 dante /*
576 1.1 dante * If we can't queue, we lose.
577 1.1 dante */
578 1.1 dante if (dontqueue) {
579 1.1 dante splx(s);
580 1.1 dante xs->error = XS_DRIVER_STUFFUP;
581 1.1 dante return (TRY_AGAIN_LATER);
582 1.1 dante }
583 1.1 dante /*
584 1.1 dante * Stuff ourselves into the queue, in front
585 1.1 dante * if we came off in the first place.
586 1.1 dante */
587 1.1 dante adw_enqueue(sc, xs, fromqueue);
588 1.1 dante splx(s);
589 1.1 dante return (SUCCESSFULLY_QUEUED);
590 1.1 dante }
591 1.1 dante splx(s); /* done playing with the queue */
592 1.1 dante
593 1.1 dante ccb->xs = xs;
594 1.1 dante ccb->timeout = xs->timeout;
595 1.1 dante
596 1.2 dante if (adw_build_req(xs, ccb)) {
597 1.1 dante s = splbio();
598 1.1 dante adw_queue_ccb(sc, ccb);
599 1.1 dante splx(s);
600 1.1 dante
601 1.1 dante /*
602 1.1 dante * Usually return SUCCESSFULLY QUEUED
603 1.1 dante */
604 1.1 dante if ((xs->flags & SCSI_POLL) == 0)
605 1.1 dante return (SUCCESSFULLY_QUEUED);
606 1.1 dante
607 1.1 dante /*
608 1.1 dante * If we can't use interrupts, poll on completion
609 1.1 dante */
610 1.1 dante if (adw_poll(sc, xs, ccb->timeout)) {
611 1.1 dante adw_timeout(ccb);
612 1.1 dante if (adw_poll(sc, xs, ccb->timeout))
613 1.1 dante adw_timeout(ccb);
614 1.1 dante }
615 1.1 dante }
616 1.2 dante return (COMPLETE);
617 1.1 dante }
618 1.1 dante
619 1.1 dante
620 1.1 dante /*
621 1.1 dante * Build a request structure for the Wide Boards.
622 1.1 dante */
623 1.1 dante static int
624 1.1 dante adw_build_req(xs, ccb)
625 1.2 dante struct scsipi_xfer *xs;
626 1.2 dante ADW_CCB *ccb;
627 1.1 dante {
628 1.2 dante struct scsipi_link *sc_link = xs->sc_link;
629 1.2 dante ADW_SOFTC *sc = sc_link->adapter_softc;
630 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
631 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
632 1.2 dante int error;
633 1.1 dante
634 1.1 dante scsiqp = &ccb->scsiq;
635 1.1 dante bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
636 1.1 dante
637 1.1 dante /*
638 1.1 dante * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the CCB structure.
639 1.1 dante */
640 1.1 dante scsiqp->ccb_ptr = (ulong) ccb;
641 1.1 dante
642 1.1 dante
643 1.1 dante /*
644 1.1 dante * Build the ADW_SCSI_REQ_Q request.
645 1.1 dante */
646 1.1 dante
647 1.1 dante /*
648 1.1 dante * Set CDB length and copy it to the request structure.
649 1.1 dante */
650 1.1 dante bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen);
651 1.1 dante
652 1.1 dante scsiqp->target_id = sc_link->scsipi_scsi.target;
653 1.1 dante scsiqp->target_lun = sc_link->scsipi_scsi.lun;
654 1.1 dante
655 1.2 dante scsiqp->vsense_addr = (ulong) & ccb->scsi_sense;
656 1.1 dante scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
657 1.1 dante ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
658 1.1 dante scsiqp->sense_len = sizeof(struct scsipi_sense_data);
659 1.1 dante
660 1.1 dante /*
661 1.1 dante * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
662 1.1 dante */
663 1.1 dante if (xs->datalen) {
664 1.1 dante /*
665 1.1 dante * Map the DMA transfer.
666 1.1 dante */
667 1.1 dante #ifdef TFS
668 1.1 dante if (xs->flags & SCSI_DATA_UIO) {
669 1.1 dante error = bus_dmamap_load_uio(dmat,
670 1.2 dante ccb->dmamap_xfer, (struct uio *) xs->data,
671 1.2 dante (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
672 1.2 dante BUS_DMA_WAITOK);
673 1.1 dante } else
674 1.1 dante #endif /* TFS */
675 1.1 dante {
676 1.1 dante error = bus_dmamap_load(dmat,
677 1.2 dante ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
678 1.2 dante (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
679 1.2 dante BUS_DMA_WAITOK);
680 1.1 dante }
681 1.1 dante
682 1.1 dante if (error) {
683 1.1 dante if (error == EFBIG) {
684 1.1 dante printf("%s: adw_scsi_cmd, more than %d dma"
685 1.1 dante " segments\n",
686 1.1 dante sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
687 1.1 dante } else {
688 1.1 dante printf("%s: adw_scsi_cmd, error %d loading"
689 1.1 dante " dma map\n",
690 1.1 dante sc->sc_dev.dv_xname, error);
691 1.1 dante }
692 1.1 dante
693 1.1 dante xs->error = XS_DRIVER_STUFFUP;
694 1.1 dante adw_free_ccb(sc, ccb);
695 1.1 dante return (0);
696 1.1 dante }
697 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
698 1.1 dante ccb->dmamap_xfer->dm_mapsize,
699 1.2 dante (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
700 1.1 dante BUS_DMASYNC_PREWRITE);
701 1.1 dante
702 1.1 dante /*
703 1.1 dante * Build scatter-gather list.
704 1.1 dante */
705 1.1 dante scsiqp->data_cnt = xs->datalen;
706 1.1 dante scsiqp->vdata_addr = (ulong) xs->data;
707 1.1 dante scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
708 1.1 dante scsiqp->sg_list_ptr = &ccb->sg_block[0];
709 1.2 dante bzero(scsiqp->sg_list_ptr,
710 1.2 dante sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
711 1.1 dante adw_build_sglist(ccb, scsiqp);
712 1.1 dante } else {
713 1.1 dante /*
714 1.1 dante * No data xfer, use non S/G values.
715 1.1 dante */
716 1.1 dante scsiqp->data_cnt = 0;
717 1.1 dante scsiqp->vdata_addr = 0;
718 1.1 dante scsiqp->data_addr = 0;
719 1.1 dante scsiqp->sg_list_ptr = NULL;
720 1.1 dante }
721 1.1 dante
722 1.1 dante return (1);
723 1.1 dante }
724 1.1 dante
725 1.1 dante
726 1.1 dante /*
727 1.1 dante * Build scatter-gather list for Wide Boards.
728 1.1 dante */
729 1.1 dante static void
730 1.1 dante adw_build_sglist(ccb, scsiqp)
731 1.2 dante ADW_CCB *ccb;
732 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
733 1.1 dante {
734 1.1 dante struct scsipi_xfer *xs = ccb->xs;
735 1.2 dante ADW_SOFTC *sc = xs->sc_link->adapter_softc;
736 1.2 dante ADW_SG_BLOCK *sg_block = scsiqp->sg_list_ptr;
737 1.2 dante ulong sg_block_next_addr; /* block and its next */
738 1.2 dante ulong sg_block_physical_addr;
739 1.2 dante int sg_block_index, i; /* how many SG entries */
740 1.1 dante bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
741 1.2 dante int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
742 1.1 dante
743 1.1 dante
744 1.1 dante sg_block_next_addr = (ulong) sg_block; /* allow math operation */
745 1.1 dante sg_block_physical_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
746 1.1 dante ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, sg_block[0]);
747 1.1 dante scsiqp->sg_real_addr = sg_block_physical_addr;
748 1.1 dante
749 1.1 dante /*
750 1.1 dante * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
751 1.1 dante * then split the request into multiple sg-list blocks.
752 1.1 dante */
753 1.1 dante
754 1.1 dante sg_block_index = 0;
755 1.2 dante do {
756 1.1 dante sg_block->first_entry_no = sg_block_index;
757 1.2 dante for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
758 1.1 dante sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
759 1.1 dante sg_block->sg_list[i].sg_count = sg_list->ds_len;
760 1.1 dante
761 1.2 dante if (--sg_elem_cnt == 0) {
762 1.1 dante /* last entry, get out */
763 1.1 dante scsiqp->sg_entry_cnt = sg_block_index + i + 1;
764 1.1 dante sg_block->last_entry_no = sg_block_index + i;
765 1.2 dante sg_block->sg_ptr = NULL; /* next link = NULL */
766 1.1 dante return;
767 1.1 dante }
768 1.1 dante sg_list++;
769 1.1 dante }
770 1.1 dante sg_block_next_addr += sizeof(ADW_SG_BLOCK);
771 1.1 dante sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
772 1.1 dante
773 1.1 dante sg_block_index += NO_OF_SG_PER_BLOCK;
774 1.1 dante sg_block->sg_ptr = (ADW_SG_BLOCK *) sg_block_physical_addr;
775 1.1 dante sg_block->last_entry_no = sg_block_index - 1;
776 1.2 dante sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
777 1.1 dante }
778 1.1 dante while (1);
779 1.1 dante }
780 1.1 dante
781 1.1 dante
782 1.1 dante int
783 1.1 dante adw_intr(arg)
784 1.1 dante void *arg;
785 1.1 dante {
786 1.1 dante ADW_SOFTC *sc = arg;
787 1.1 dante struct scsipi_xfer *xs;
788 1.1 dante
789 1.1 dante
790 1.1 dante AdvISR(sc);
791 1.1 dante
792 1.1 dante /*
793 1.1 dante * If there are queue entries in the software queue, try to
794 1.1 dante * run the first one. We should be more or less guaranteed
795 1.1 dante * to succeed, since we just freed a CCB.
796 1.1 dante *
797 1.1 dante * NOTE: adw_scsi_cmd() relies on our calling it with
798 1.1 dante * the first entry in the queue.
799 1.1 dante */
800 1.1 dante if ((xs = sc->sc_queue.lh_first) != NULL)
801 1.1 dante (void) adw_scsi_cmd(xs);
802 1.1 dante
803 1.1 dante return (1);
804 1.1 dante }
805 1.1 dante
806 1.1 dante
807 1.1 dante /*
808 1.1 dante * Poll a particular unit, looking for a particular xs
809 1.1 dante */
810 1.1 dante static int
811 1.1 dante adw_poll(sc, xs, count)
812 1.1 dante ADW_SOFTC *sc;
813 1.1 dante struct scsipi_xfer *xs;
814 1.1 dante int count;
815 1.1 dante {
816 1.1 dante
817 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
818 1.1 dante while (count) {
819 1.1 dante adw_intr(sc);
820 1.1 dante if (xs->flags & ITSDONE)
821 1.1 dante return (0);
822 1.1 dante delay(1000); /* only happens in boot so ok */
823 1.1 dante count--;
824 1.1 dante }
825 1.1 dante return (1);
826 1.1 dante }
827 1.1 dante
828 1.1 dante
829 1.1 dante static void
830 1.1 dante adw_timeout(arg)
831 1.1 dante void *arg;
832 1.1 dante {
833 1.1 dante ADW_CCB *ccb = arg;
834 1.1 dante struct scsipi_xfer *xs = ccb->xs;
835 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
836 1.1 dante ADW_SOFTC *sc = sc_link->adapter_softc;
837 1.1 dante int s;
838 1.1 dante
839 1.1 dante scsi_print_addr(sc_link);
840 1.1 dante printf("timed out");
841 1.1 dante
842 1.1 dante s = splbio();
843 1.1 dante
844 1.1 dante /*
845 1.1 dante * If it has been through before, then a previous abort has failed,
846 1.1 dante * don't try abort again, reset the bus instead.
847 1.1 dante */
848 1.1 dante if (ccb->flags & CCB_ABORT) {
849 1.1 dante /* abort timed out */
850 1.1 dante printf(" AGAIN. Resetting Bus\n");
851 1.1 dante /* Lets try resetting the bus! */
852 1.1 dante AdvResetSCSIBus(sc);
853 1.1 dante ccb->timeout = ADW_ABORT_TIMEOUT;
854 1.1 dante adw_queue_ccb(sc, ccb);
855 1.1 dante } else {
856 1.1 dante /* abort the operation that has timed out */
857 1.1 dante printf("\n");
858 1.1 dante ADW_ABORT_CCB(sc, ccb);
859 1.1 dante xs->error = XS_TIMEOUT;
860 1.1 dante ccb->timeout = ADW_ABORT_TIMEOUT;
861 1.1 dante ccb->flags |= CCB_ABORT;
862 1.1 dante adw_queue_ccb(sc, ccb);
863 1.1 dante }
864 1.1 dante
865 1.1 dante splx(s);
866 1.1 dante }
867 1.1 dante
868 1.1 dante
869 1.1 dante static void
870 1.1 dante adw_watchdog(arg)
871 1.1 dante void *arg;
872 1.1 dante {
873 1.1 dante ADW_CCB *ccb = arg;
874 1.1 dante struct scsipi_xfer *xs = ccb->xs;
875 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
876 1.1 dante ADW_SOFTC *sc = sc_link->adapter_softc;
877 1.1 dante int s;
878 1.1 dante
879 1.1 dante s = splbio();
880 1.1 dante
881 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
882 1.1 dante adw_start_ccbs(sc);
883 1.1 dante
884 1.1 dante splx(s);
885 1.1 dante }
886 1.1 dante
887 1.1 dante
888 1.1 dante /******************************************************************************/
889 1.2 dante /* NARROW and WIDE boards Interrupt callbacks */
890 1.1 dante /******************************************************************************/
891 1.1 dante
892 1.1 dante
893 1.1 dante /*
894 1.1 dante * adw_wide_isr_callback() - Second Level Interrupt Handler called by AdvISR()
895 1.1 dante *
896 1.1 dante * Interrupt callback function for the Wide SCSI Adv Library.
897 1.1 dante */
898 1.1 dante static void
899 1.1 dante adw_wide_isr_callback(sc, scsiq)
900 1.1 dante ADW_SOFTC *sc;
901 1.1 dante ADW_SCSI_REQ_Q *scsiq;
902 1.1 dante {
903 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
904 1.2 dante ADW_CCB *ccb = (ADW_CCB *) scsiq->ccb_ptr;
905 1.2 dante struct scsipi_xfer *xs = ccb->xs;
906 1.1 dante struct scsipi_sense_data *s1, *s2;
907 1.2 dante //int underrun = ASC_FALSE;
908 1.1 dante
909 1.1 dante
910 1.1 dante untimeout(adw_timeout, ccb);
911 1.1 dante
912 1.1 dante /*
913 1.1 dante * If we were a data transfer, unload the map that described
914 1.1 dante * the data buffer.
915 1.1 dante */
916 1.1 dante if (xs->datalen) {
917 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
918 1.1 dante ccb->dmamap_xfer->dm_mapsize,
919 1.1 dante (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
920 1.1 dante BUS_DMASYNC_POSTWRITE);
921 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
922 1.1 dante }
923 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
924 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
925 1.1 dante Debugger();
926 1.1 dante return;
927 1.1 dante }
928 1.1 dante /*
929 1.1 dante * Check for an underrun condition.
930 1.1 dante */
931 1.2 dante /*
932 1.2 dante * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
933 1.2 dante * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
934 1.2 dante * scsiqp->data_cnt); underrun = ASC_TRUE; }
935 1.2 dante */
936 1.1 dante /*
937 1.1 dante * 'done_status' contains the command's ending status.
938 1.1 dante */
939 1.1 dante switch (scsiq->done_status) {
940 1.1 dante case QD_NO_ERROR:
941 1.1 dante switch (scsiq->host_status) {
942 1.1 dante case QHSTA_NO_ERROR:
943 1.1 dante xs->error = XS_NOERROR;
944 1.1 dante xs->resid = 0;
945 1.1 dante break;
946 1.1 dante default:
947 1.1 dante /* QHSTA error occurred. */
948 1.1 dante xs->error = XS_DRIVER_STUFFUP;
949 1.1 dante break;
950 1.1 dante }
951 1.1 dante /*
952 1.1 dante * If there was an underrun without any other error,
953 1.1 dante * set DID_ERROR to indicate the underrun error.
954 1.1 dante *
955 1.1 dante * Note: There is no way yet to indicate the number
956 1.1 dante * of underrun bytes.
957 1.1 dante */
958 1.2 dante /*
959 1.2 dante * if (xs->error == XS_NOERROR && underrun == ASC_TRUE) {
960 1.2 dante * scp->result = HOST_BYTE(DID_UNDERRUN); }
961 1.2 dante */ break;
962 1.1 dante
963 1.1 dante case QD_WITH_ERROR:
964 1.1 dante switch (scsiq->host_status) {
965 1.1 dante case QHSTA_NO_ERROR:
966 1.1 dante if (scsiq->scsi_status == SS_CHK_CONDITION) {
967 1.1 dante s1 = &ccb->scsi_sense;
968 1.1 dante s2 = &xs->sense.scsi_sense;
969 1.1 dante *s2 = *s1;
970 1.1 dante xs->error = XS_SENSE;
971 1.1 dante } else {
972 1.1 dante xs->error = XS_DRIVER_STUFFUP;
973 1.1 dante }
974 1.1 dante break;
975 1.1 dante
976 1.1 dante default:
977 1.1 dante /* Some other QHSTA error occurred. */
978 1.1 dante xs->error = XS_DRIVER_STUFFUP;
979 1.1 dante break;
980 1.1 dante }
981 1.1 dante break;
982 1.1 dante
983 1.1 dante case QD_ABORTED_BY_HOST:
984 1.1 dante default:
985 1.1 dante xs->error = XS_DRIVER_STUFFUP;
986 1.1 dante break;
987 1.1 dante }
988 1.1 dante
989 1.1 dante
990 1.1 dante adw_free_ccb(sc, ccb);
991 1.1 dante xs->flags |= ITSDONE;
992 1.1 dante scsipi_done(xs);
993 1.1 dante }
994