adw.c revision 1.55 1 1.55 uwe /* $NetBSD: adw.c,v 1.55 2019/10/06 01:04:49 uwe Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.1 dante * Generic driver for the Advanced Systems Inc. SCSI controllers
5 1.1 dante *
6 1.13 dante * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.1 dante * This product includes software developed by the NetBSD
22 1.1 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.36 lukem
40 1.36 lukem #include <sys/cdefs.h>
41 1.55 uwe __KERNEL_RCSID(0, "$NetBSD: adw.c,v 1.55 2019/10/06 01:04:49 uwe Exp $");
42 1.1 dante
43 1.1 dante #include <sys/param.h>
44 1.1 dante #include <sys/systm.h>
45 1.15 thorpej #include <sys/callout.h>
46 1.1 dante #include <sys/kernel.h>
47 1.1 dante #include <sys/errno.h>
48 1.1 dante #include <sys/ioctl.h>
49 1.1 dante #include <sys/device.h>
50 1.1 dante #include <sys/malloc.h>
51 1.1 dante #include <sys/buf.h>
52 1.1 dante #include <sys/proc.h>
53 1.1 dante
54 1.48 ad #include <sys/bus.h>
55 1.48 ad #include <sys/intr.h>
56 1.1 dante
57 1.1 dante #include <dev/scsipi/scsi_all.h>
58 1.1 dante #include <dev/scsipi/scsipi_all.h>
59 1.1 dante #include <dev/scsipi/scsiconf.h>
60 1.1 dante
61 1.1 dante #include <dev/ic/adwlib.h>
62 1.22 dante #include <dev/ic/adwmcode.h>
63 1.1 dante #include <dev/ic/adw.h>
64 1.1 dante
65 1.1 dante #ifndef DDB
66 1.11 dante #define Debugger() panic("should call debugger here (adw.c)")
67 1.2 dante #endif /* ! DDB */
68 1.1 dante
69 1.1 dante /******************************************************************************/
70 1.1 dante
71 1.1 dante
72 1.30 lukem static int adw_alloc_controls(ADW_SOFTC *);
73 1.30 lukem static int adw_alloc_carriers(ADW_SOFTC *);
74 1.30 lukem static int adw_create_ccbs(ADW_SOFTC *, ADW_CCB *, int);
75 1.30 lukem static void adw_free_ccb(ADW_SOFTC *, ADW_CCB *);
76 1.30 lukem static void adw_reset_ccb(ADW_CCB *);
77 1.30 lukem static int adw_init_ccb(ADW_SOFTC *, ADW_CCB *);
78 1.30 lukem static ADW_CCB *adw_get_ccb(ADW_SOFTC *);
79 1.30 lukem static int adw_queue_ccb(ADW_SOFTC *, ADW_CCB *);
80 1.30 lukem
81 1.30 lukem static void adw_scsipi_request(struct scsipi_channel *,
82 1.30 lukem scsipi_adapter_req_t, void *);
83 1.30 lukem static int adw_build_req(ADW_SOFTC *, ADW_CCB *);
84 1.30 lukem static void adw_build_sglist(ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *);
85 1.30 lukem static void adwminphys(struct buf *);
86 1.30 lukem static void adw_isr_callback(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
87 1.30 lukem static void adw_async_callback(ADW_SOFTC *, u_int8_t);
88 1.30 lukem
89 1.30 lukem static void adw_print_info(ADW_SOFTC *, int);
90 1.30 lukem
91 1.30 lukem static int adw_poll(ADW_SOFTC *, struct scsipi_xfer *, int);
92 1.30 lukem static void adw_timeout(void *);
93 1.30 lukem static void adw_reset_bus(ADW_SOFTC *);
94 1.1 dante
95 1.1 dante
96 1.1 dante /******************************************************************************/
97 1.22 dante /* DMA Mapping for Control Blocks */
98 1.1 dante /******************************************************************************/
99 1.1 dante
100 1.1 dante
101 1.1 dante static int
102 1.30 lukem adw_alloc_controls(ADW_SOFTC *sc)
103 1.1 dante {
104 1.1 dante bus_dma_segment_t seg;
105 1.1 dante int error, rseg;
106 1.1 dante
107 1.1 dante /*
108 1.13 dante * Allocate the control structure.
109 1.1 dante */
110 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
111 1.54 msaitoh PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
112 1.54 msaitoh aprint_error_dev(sc->sc_dev, "unable to allocate control "
113 1.54 msaitoh "structures, error = %d\n", error);
114 1.1 dante return (error);
115 1.1 dante }
116 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
117 1.54 msaitoh sizeof(struct adw_control), (void **) & sc->sc_control,
118 1.54 msaitoh BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
119 1.54 msaitoh aprint_error_dev(sc->sc_dev,
120 1.54 msaitoh "unable to map control structures, error = %d\n", error);
121 1.1 dante return (error);
122 1.1 dante }
123 1.13 dante
124 1.1 dante /*
125 1.1 dante * Create and load the DMA map used for the control blocks.
126 1.1 dante */
127 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
128 1.54 msaitoh 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
129 1.54 msaitoh &sc->sc_dmamap_control)) != 0) {
130 1.54 msaitoh aprint_error_dev(sc->sc_dev,
131 1.54 msaitoh "unable to create control DMA map, error = %d\n", error);
132 1.1 dante return (error);
133 1.1 dante }
134 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
135 1.54 msaitoh sc->sc_control, sizeof(struct adw_control), NULL,
136 1.54 msaitoh BUS_DMA_NOWAIT)) != 0) {
137 1.54 msaitoh aprint_error_dev(sc->sc_dev,
138 1.54 msaitoh "unable to load control DMA map, error = %d\n", error);
139 1.1 dante return (error);
140 1.1 dante }
141 1.13 dante
142 1.13 dante return (0);
143 1.13 dante }
144 1.13 dante
145 1.13 dante
146 1.13 dante static int
147 1.30 lukem adw_alloc_carriers(ADW_SOFTC *sc)
148 1.13 dante {
149 1.13 dante bus_dma_segment_t seg;
150 1.13 dante int error, rseg;
151 1.13 dante
152 1.13 dante /*
153 1.13 dante * Allocate the control structure.
154 1.13 dante */
155 1.19 dante sc->sc_control->carriers = malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
156 1.13 dante M_DEVBUF, M_WAITOK);
157 1.13 dante if(!sc->sc_control->carriers) {
158 1.52 chs aprint_error_dev(sc->sc_dev,
159 1.49 cegger "malloc() failed in allocating carrier structures\n");
160 1.18 thorpej return (ENOMEM);
161 1.13 dante }
162 1.13 dante
163 1.13 dante if ((error = bus_dmamem_alloc(sc->sc_dmat,
164 1.54 msaitoh sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
165 1.54 msaitoh 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
166 1.54 msaitoh aprint_error_dev(sc->sc_dev, "unable to allocate carrier "
167 1.54 msaitoh "structures, error = %d\n", error);
168 1.13 dante return (error);
169 1.13 dante }
170 1.13 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
171 1.54 msaitoh sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
172 1.54 msaitoh (void **)&sc->sc_control->carriers,
173 1.54 msaitoh BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
174 1.54 msaitoh aprint_error_dev(sc->sc_dev,
175 1.54 msaitoh "unable to map carrier structures, error = %d\n", error);
176 1.13 dante return (error);
177 1.13 dante }
178 1.13 dante
179 1.13 dante /*
180 1.13 dante * Create and load the DMA map used for the control blocks.
181 1.13 dante */
182 1.13 dante if ((error = bus_dmamap_create(sc->sc_dmat,
183 1.54 msaitoh sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1,
184 1.54 msaitoh sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT,
185 1.54 msaitoh &sc->sc_dmamap_carrier)) != 0) {
186 1.54 msaitoh aprint_error_dev(sc->sc_dev,
187 1.54 msaitoh "unable to create carriers DMA map, error = %d\n", error);
188 1.13 dante return (error);
189 1.13 dante }
190 1.54 msaitoh if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_carrier,
191 1.54 msaitoh sc->sc_control->carriers, sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
192 1.54 msaitoh NULL, BUS_DMA_NOWAIT)) != 0) {
193 1.54 msaitoh aprint_error_dev(sc->sc_dev,
194 1.54 msaitoh "unable to load carriers DMA map, error = %d\n", error);
195 1.13 dante return (error);
196 1.13 dante }
197 1.13 dante
198 1.1 dante return (0);
199 1.1 dante }
200 1.1 dante
201 1.1 dante
202 1.22 dante /******************************************************************************/
203 1.22 dante /* Control Blocks routines */
204 1.22 dante /******************************************************************************/
205 1.13 dante
206 1.13 dante
207 1.13 dante /*
208 1.1 dante * Create a set of ccbs and add them to the free list. Called once
209 1.1 dante * by adw_init(). We return the number of CCBs successfully created.
210 1.1 dante */
211 1.1 dante static int
212 1.30 lukem adw_create_ccbs(ADW_SOFTC *sc, ADW_CCB *ccbstore, int count)
213 1.1 dante {
214 1.1 dante ADW_CCB *ccb;
215 1.1 dante int i, error;
216 1.1 dante
217 1.1 dante for (i = 0; i < count; i++) {
218 1.1 dante ccb = &ccbstore[i];
219 1.1 dante if ((error = adw_init_ccb(sc, ccb)) != 0) {
220 1.54 msaitoh aprint_error_dev(sc->sc_dev,
221 1.54 msaitoh "unable to initialize ccb, error = %d\n", error);
222 1.1 dante return (i);
223 1.1 dante }
224 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
225 1.1 dante }
226 1.1 dante
227 1.1 dante return (i);
228 1.1 dante }
229 1.1 dante
230 1.1 dante
231 1.1 dante /*
232 1.1 dante * A ccb is put onto the free list.
233 1.1 dante */
234 1.1 dante static void
235 1.30 lukem adw_free_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
236 1.1 dante {
237 1.1 dante int s;
238 1.1 dante
239 1.1 dante s = splbio();
240 1.1 dante
241 1.1 dante adw_reset_ccb(ccb);
242 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
243 1.1 dante
244 1.1 dante splx(s);
245 1.1 dante }
246 1.1 dante
247 1.1 dante
248 1.1 dante static void
249 1.30 lukem adw_reset_ccb(ADW_CCB *ccb)
250 1.1 dante {
251 1.1 dante
252 1.1 dante ccb->flags = 0;
253 1.1 dante }
254 1.1 dante
255 1.1 dante
256 1.1 dante static int
257 1.30 lukem adw_init_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
258 1.1 dante {
259 1.7 dante int hashnum, error;
260 1.1 dante
261 1.1 dante /*
262 1.1 dante * Create the DMA map for this CCB.
263 1.1 dante */
264 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
265 1.54 msaitoh (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, ADW_MAX_SG_LIST,
266 1.54 msaitoh (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 0,
267 1.54 msaitoh BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
268 1.1 dante if (error) {
269 1.54 msaitoh aprint_error_dev(sc->sc_dev,
270 1.54 msaitoh "unable to create CCB DMA map, error = %d\n", error);
271 1.1 dante return (error);
272 1.1 dante }
273 1.7 dante
274 1.7 dante /*
275 1.7 dante * put in the phystokv hash table
276 1.7 dante * Never gets taken out.
277 1.7 dante */
278 1.35 briggs ccb->hashkey = htole32(sc->sc_dmamap_control->dm_segs[0].ds_addr +
279 1.35 briggs ADW_CCB_OFF(ccb));
280 1.7 dante hashnum = CCB_HASH(ccb->hashkey);
281 1.7 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
282 1.7 dante sc->sc_ccbhash[hashnum] = ccb;
283 1.1 dante adw_reset_ccb(ccb);
284 1.1 dante return (0);
285 1.1 dante }
286 1.1 dante
287 1.1 dante
288 1.1 dante /*
289 1.1 dante * Get a free ccb
290 1.1 dante *
291 1.1 dante * If there are none, see if we can allocate a new one
292 1.1 dante */
293 1.1 dante static ADW_CCB *
294 1.30 lukem adw_get_ccb(ADW_SOFTC *sc)
295 1.1 dante {
296 1.1 dante ADW_CCB *ccb = 0;
297 1.1 dante int s;
298 1.1 dante
299 1.1 dante s = splbio();
300 1.1 dante
301 1.29 bouyer ccb = sc->sc_free_ccb.tqh_first;
302 1.29 bouyer if (ccb != NULL) {
303 1.29 bouyer TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
304 1.29 bouyer ccb->flags |= CCB_ALLOC;
305 1.1 dante }
306 1.1 dante splx(s);
307 1.1 dante return (ccb);
308 1.1 dante }
309 1.1 dante
310 1.1 dante
311 1.1 dante /*
312 1.7 dante * Given a physical address, find the ccb that it corresponds to.
313 1.7 dante */
314 1.7 dante ADW_CCB *
315 1.30 lukem adw_ccb_phys_kv(ADW_SOFTC *sc, u_int32_t ccb_phys)
316 1.7 dante {
317 1.7 dante int hashnum = CCB_HASH(ccb_phys);
318 1.7 dante ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
319 1.7 dante
320 1.7 dante while (ccb) {
321 1.7 dante if (ccb->hashkey == ccb_phys)
322 1.7 dante break;
323 1.7 dante ccb = ccb->nexthash;
324 1.7 dante }
325 1.7 dante return (ccb);
326 1.7 dante }
327 1.7 dante
328 1.7 dante
329 1.7 dante /*
330 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
331 1.1 dante */
332 1.13 dante static int
333 1.30 lukem adw_queue_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
334 1.1 dante {
335 1.19 dante int errcode = ADW_SUCCESS;
336 1.1 dante
337 1.29 bouyer TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
338 1.1 dante
339 1.13 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
340 1.1 dante
341 1.29 bouyer TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
342 1.22 dante errcode = AdwExeScsiQueue(sc, &ccb->scsiq);
343 1.13 dante switch(errcode) {
344 1.13 dante case ADW_SUCCESS:
345 1.13 dante break;
346 1.1 dante
347 1.13 dante case ADW_BUSY:
348 1.13 dante printf("ADW_BUSY\n");
349 1.13 dante return(ADW_BUSY);
350 1.13 dante
351 1.13 dante case ADW_ERROR:
352 1.13 dante printf("ADW_ERROR\n");
353 1.13 dante return(ADW_ERROR);
354 1.13 dante }
355 1.11 dante
356 1.19 dante TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain);
357 1.1 dante
358 1.12 thorpej if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
359 1.15 thorpej callout_reset(&ccb->xs->xs_callout,
360 1.38 bouyer mstohz(ccb->timeout), adw_timeout, ccb);
361 1.1 dante }
362 1.13 dante
363 1.13 dante return(errcode);
364 1.1 dante }
365 1.1 dante
366 1.1 dante
367 1.1 dante /******************************************************************************/
368 1.22 dante /* SCSI layer interfacing routines */
369 1.1 dante /******************************************************************************/
370 1.1 dante
371 1.1 dante
372 1.1 dante int
373 1.30 lukem adw_init(ADW_SOFTC *sc)
374 1.1 dante {
375 1.2 dante u_int16_t warn_code;
376 1.1 dante
377 1.1 dante
378 1.1 dante sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
379 1.2 dante ADW_LIB_VERSION_MINOR;
380 1.1 dante sc->cfg.chip_version =
381 1.1 dante ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
382 1.1 dante
383 1.1 dante /*
384 1.1 dante * Reset the chip to start and allow register writes.
385 1.1 dante */
386 1.1 dante if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
387 1.1 dante panic("adw_init: adw_find_signature failed");
388 1.2 dante } else {
389 1.22 dante AdwResetChip(sc->sc_iot, sc->sc_ioh);
390 1.1 dante
391 1.23 dante warn_code = AdwInitFromEEPROM(sc);
392 1.13 dante
393 1.22 dante if (warn_code & ADW_WARN_EEPROM_CHKSUM)
394 1.52 chs aprint_error_dev(sc->sc_dev, "Bad checksum found. "
395 1.54 msaitoh "Setting default values\n");
396 1.22 dante if (warn_code & ADW_WARN_EEPROM_TERMINATION)
397 1.54 msaitoh aprint_error_dev(sc->sc_dev, "Bad bus termination "
398 1.54 msaitoh "setting. Using automatic termination.\n");
399 1.1 dante }
400 1.1 dante
401 1.55 uwe sc->isr_callback = adw_isr_callback;
402 1.55 uwe sc->async_callback = adw_async_callback;
403 1.1 dante
404 1.16 dante return 0;
405 1.1 dante }
406 1.1 dante
407 1.1 dante
408 1.1 dante void
409 1.30 lukem adw_attach(ADW_SOFTC *sc)
410 1.1 dante {
411 1.29 bouyer struct scsipi_adapter *adapt = &sc->sc_adapter;
412 1.29 bouyer struct scsipi_channel *chan = &sc->sc_channel;
413 1.29 bouyer int ncontrols, error;
414 1.1 dante
415 1.13 dante TAILQ_INIT(&sc->sc_free_ccb);
416 1.13 dante TAILQ_INIT(&sc->sc_waiting_ccb);
417 1.19 dante TAILQ_INIT(&sc->sc_pending_ccb);
418 1.13 dante
419 1.13 dante /*
420 1.13 dante * Allocate the Control Blocks.
421 1.13 dante */
422 1.13 dante error = adw_alloc_controls(sc);
423 1.13 dante if (error)
424 1.13 dante return; /* (error) */ ;
425 1.13 dante
426 1.32 thorpej memset(sc->sc_control, 0, sizeof(struct adw_control));
427 1.13 dante
428 1.13 dante /*
429 1.13 dante * Create and initialize the Control Blocks.
430 1.13 dante */
431 1.29 bouyer ncontrols = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
432 1.29 bouyer if (ncontrols == 0) {
433 1.53 msaitoh aprint_error_dev(sc->sc_dev,
434 1.53 msaitoh "unable to create Control Blocks\n");
435 1.13 dante return; /* (ENOMEM) */ ;
436 1.29 bouyer } else if (ncontrols != ADW_MAX_CCB) {
437 1.53 msaitoh aprint_error_dev(sc->sc_dev,
438 1.53 msaitoh "WARNING: only %d of %d Control Blocks created\n",
439 1.49 cegger ncontrols, ADW_MAX_CCB);
440 1.13 dante }
441 1.13 dante
442 1.13 dante /*
443 1.13 dante * Create and initialize the Carriers.
444 1.13 dante */
445 1.13 dante error = adw_alloc_carriers(sc);
446 1.13 dante if (error)
447 1.13 dante return; /* (error) */ ;
448 1.13 dante
449 1.21 dante /*
450 1.21 dante * Zero's the freeze_device status
451 1.21 dante */
452 1.32 thorpej memset(sc->sc_freeze_dev, 0, sizeof(sc->sc_freeze_dev));
453 1.13 dante
454 1.1 dante /*
455 1.16 dante * Initialize the adapter
456 1.1 dante */
457 1.23 dante switch (AdwInitDriver(sc)) {
458 1.22 dante case ADW_IERR_BIST_PRE_TEST:
459 1.19 dante panic("%s: BIST pre-test error",
460 1.52 chs device_xname(sc->sc_dev));
461 1.19 dante break;
462 1.19 dante
463 1.22 dante case ADW_IERR_BIST_RAM_TEST:
464 1.19 dante panic("%s: BIST RAM test error",
465 1.52 chs device_xname(sc->sc_dev));
466 1.19 dante break;
467 1.19 dante
468 1.22 dante case ADW_IERR_MCODE_CHKSUM:
469 1.2 dante panic("%s: Microcode checksum error",
470 1.52 chs device_xname(sc->sc_dev));
471 1.2 dante break;
472 1.2 dante
473 1.22 dante case ADW_IERR_ILLEGAL_CONNECTION:
474 1.2 dante panic("%s: All three connectors are in use",
475 1.52 chs device_xname(sc->sc_dev));
476 1.2 dante break;
477 1.2 dante
478 1.22 dante case ADW_IERR_REVERSED_CABLE:
479 1.2 dante panic("%s: Cable is reversed",
480 1.52 chs device_xname(sc->sc_dev));
481 1.2 dante break;
482 1.2 dante
483 1.22 dante case ADW_IERR_HVD_DEVICE:
484 1.19 dante panic("%s: HVD attached to LVD connector",
485 1.52 chs device_xname(sc->sc_dev));
486 1.19 dante break;
487 1.19 dante
488 1.22 dante case ADW_IERR_SINGLE_END_DEVICE:
489 1.2 dante panic("%s: single-ended device is attached to"
490 1.2 dante " one of the connectors",
491 1.52 chs device_xname(sc->sc_dev));
492 1.2 dante break;
493 1.13 dante
494 1.22 dante case ADW_IERR_NO_CARRIER:
495 1.22 dante panic("%s: unable to create Carriers",
496 1.52 chs device_xname(sc->sc_dev));
497 1.13 dante break;
498 1.13 dante
499 1.22 dante case ADW_WARN_BUSRESET_ERROR:
500 1.52 chs aprint_error_dev(sc->sc_dev, "WARNING: Bus Reset Error\n");
501 1.13 dante break;
502 1.1 dante }
503 1.1 dante
504 1.4 thorpej /*
505 1.29 bouyer * Fill in the scsipi_adapter.
506 1.4 thorpej */
507 1.29 bouyer memset(adapt, 0, sizeof(*adapt));
508 1.52 chs adapt->adapt_dev = sc->sc_dev;
509 1.29 bouyer adapt->adapt_nchannels = 1;
510 1.29 bouyer adapt->adapt_openings = ncontrols;
511 1.29 bouyer adapt->adapt_max_periph = adapt->adapt_openings;
512 1.29 bouyer adapt->adapt_request = adw_scsipi_request;
513 1.29 bouyer adapt->adapt_minphys = adwminphys;
514 1.1 dante
515 1.1 dante /*
516 1.29 bouyer * Fill in the scsipi_channel.
517 1.29 bouyer */
518 1.29 bouyer memset(chan, 0, sizeof(*chan));
519 1.45 perry chan->chan_adapter = adapt;
520 1.29 bouyer chan->chan_bustype = &scsi_bustype;
521 1.29 bouyer chan->chan_channel = 0;
522 1.29 bouyer chan->chan_ntargets = ADW_MAX_TID + 1;
523 1.41 mycroft chan->chan_nluns = 8;
524 1.29 bouyer chan->chan_id = sc->chip_scsi_id;
525 1.1 dante
526 1.52 chs config_found(sc->sc_dev, &sc->sc_channel, scsiprint);
527 1.1 dante }
528 1.1 dante
529 1.1 dante
530 1.1 dante static void
531 1.30 lukem adwminphys(struct buf *bp)
532 1.1 dante {
533 1.1 dante
534 1.1 dante if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
535 1.1 dante bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
536 1.1 dante minphys(bp);
537 1.1 dante }
538 1.1 dante
539 1.1 dante
540 1.1 dante /*
541 1.2 dante * start a scsi operation given the command and the data address.
542 1.2 dante * Also needs the unit, target and lu.
543 1.1 dante */
544 1.29 bouyer static void
545 1.30 lukem adw_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
546 1.30 lukem void *arg)
547 1.29 bouyer {
548 1.1 dante struct scsipi_xfer *xs;
549 1.52 chs ADW_SOFTC *sc = device_private(chan->chan_adapter->adapt_dev);
550 1.1 dante ADW_CCB *ccb;
551 1.29 bouyer int s, retry;
552 1.1 dante
553 1.29 bouyer switch (req) {
554 1.29 bouyer case ADAPTER_REQ_RUN_XFER:
555 1.29 bouyer xs = arg;
556 1.1 dante
557 1.29 bouyer /*
558 1.29 bouyer * get a ccb to use. If the transfer
559 1.29 bouyer * is from a buf (possibly from interrupt time)
560 1.29 bouyer * then we can't allow it to sleep
561 1.29 bouyer */
562 1.1 dante
563 1.29 bouyer ccb = adw_get_ccb(sc);
564 1.29 bouyer #ifdef DIAGNOSTIC
565 1.1 dante /*
566 1.29 bouyer * This should never happen as we track the resources
567 1.29 bouyer * in the mid-layer.
568 1.1 dante */
569 1.29 bouyer if (ccb == NULL) {
570 1.29 bouyer scsipi_printaddr(xs->xs_periph);
571 1.29 bouyer printf("unable to allocate ccb\n");
572 1.29 bouyer panic("adw_scsipi_request");
573 1.1 dante }
574 1.29 bouyer #endif
575 1.1 dante
576 1.29 bouyer ccb->xs = xs;
577 1.29 bouyer ccb->timeout = xs->timeout;
578 1.1 dante
579 1.29 bouyer if (adw_build_req(sc, ccb)) {
580 1.29 bouyer s = splbio();
581 1.29 bouyer retry = adw_queue_ccb(sc, ccb);
582 1.1 dante splx(s);
583 1.1 dante
584 1.29 bouyer switch(retry) {
585 1.29 bouyer case ADW_BUSY:
586 1.29 bouyer xs->error = XS_RESOURCE_SHORTAGE;
587 1.29 bouyer adw_free_ccb(sc, ccb);
588 1.29 bouyer scsipi_done(xs);
589 1.29 bouyer return;
590 1.1 dante
591 1.29 bouyer case ADW_ERROR:
592 1.29 bouyer xs->error = XS_DRIVER_STUFFUP;
593 1.29 bouyer adw_free_ccb(sc, ccb);
594 1.29 bouyer scsipi_done(xs);
595 1.29 bouyer return;
596 1.29 bouyer }
597 1.29 bouyer if ((xs->xs_control & XS_CTL_POLL) == 0)
598 1.29 bouyer return;
599 1.29 bouyer /*
600 1.29 bouyer * Not allowed to use interrupts, poll for completion.
601 1.29 bouyer */
602 1.29 bouyer if (adw_poll(sc, xs, ccb->timeout)) {
603 1.29 bouyer adw_timeout(ccb);
604 1.29 bouyer if (adw_poll(sc, xs, ccb->timeout))
605 1.29 bouyer adw_timeout(ccb);
606 1.29 bouyer }
607 1.13 dante }
608 1.29 bouyer return;
609 1.1 dante
610 1.29 bouyer case ADAPTER_REQ_GROW_RESOURCES:
611 1.29 bouyer /* XXX Not supported. */
612 1.29 bouyer return;
613 1.1 dante
614 1.29 bouyer case ADAPTER_REQ_SET_XFER_MODE:
615 1.45 perry /* XXX XXX XXX */
616 1.29 bouyer return;
617 1.1 dante }
618 1.1 dante }
619 1.1 dante
620 1.1 dante
621 1.1 dante /*
622 1.1 dante * Build a request structure for the Wide Boards.
623 1.1 dante */
624 1.1 dante static int
625 1.30 lukem adw_build_req(ADW_SOFTC *sc, ADW_CCB *ccb)
626 1.1 dante {
627 1.29 bouyer struct scsipi_xfer *xs = ccb->xs;
628 1.29 bouyer struct scsipi_periph *periph = xs->xs_periph;
629 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
630 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
631 1.2 dante int error;
632 1.1 dante
633 1.1 dante scsiqp = &ccb->scsiq;
634 1.32 thorpej memset(scsiqp, 0, sizeof(ADW_SCSI_REQ_Q));
635 1.1 dante
636 1.1 dante /*
637 1.7 dante * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
638 1.7 dante * physical CCB structure.
639 1.1 dante */
640 1.10 thorpej scsiqp->ccb_ptr = ccb->hashkey;
641 1.1 dante
642 1.1 dante /*
643 1.1 dante * Build the ADW_SCSI_REQ_Q request.
644 1.1 dante */
645 1.1 dante
646 1.1 dante /*
647 1.1 dante * Set CDB length and copy it to the request structure.
648 1.16 dante * For wide boards a CDB length maximum of 16 bytes
649 1.16 dante * is supported.
650 1.1 dante */
651 1.31 thorpej memcpy(&scsiqp->cdb, xs->cmd, ((scsiqp->cdb_len = xs->cmdlen) <= 12)?
652 1.16 dante xs->cmdlen : 12 );
653 1.16 dante if(xs->cmdlen > 12)
654 1.31 thorpej memcpy(&scsiqp->cdb16, &(xs->cmd[12]), xs->cmdlen - 12);
655 1.1 dante
656 1.29 bouyer scsiqp->target_id = periph->periph_target;
657 1.29 bouyer scsiqp->target_lun = periph->periph_lun;
658 1.1 dante
659 1.7 dante scsiqp->vsense_addr = &ccb->scsi_sense;
660 1.35 briggs scsiqp->sense_addr = htole32(sc->sc_dmamap_control->dm_segs[0].ds_addr +
661 1.35 briggs ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense));
662 1.44 thorpej scsiqp->sense_len = sizeof(struct scsi_sense_data);
663 1.1 dante
664 1.1 dante /*
665 1.1 dante * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
666 1.1 dante */
667 1.1 dante if (xs->datalen) {
668 1.1 dante /*
669 1.1 dante * Map the DMA transfer.
670 1.1 dante */
671 1.1 dante #ifdef TFS
672 1.12 thorpej if (xs->xs_control & SCSI_DATA_UIO) {
673 1.29 bouyer error = bus_dmamap_load_uio(dmat,
674 1.29 bouyer ccb->dmamap_xfer, (struct uio *) xs->data,
675 1.29 bouyer ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
676 1.33 thorpej BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
677 1.33 thorpej ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
678 1.33 thorpej BUS_DMA_WRITE));
679 1.1 dante } else
680 1.13 dante #endif /* TFS */
681 1.1 dante {
682 1.29 bouyer error = bus_dmamap_load(dmat,
683 1.29 bouyer ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
684 1.29 bouyer ((xs->xs_control & XS_CTL_NOSLEEP) ?
685 1.29 bouyer BUS_DMA_NOWAIT : BUS_DMA_WAITOK) |
686 1.33 thorpej BUS_DMA_STREAMING |
687 1.33 thorpej ((xs->xs_control & XS_CTL_DATA_IN) ?
688 1.33 thorpej BUS_DMA_READ : BUS_DMA_WRITE));
689 1.1 dante }
690 1.1 dante
691 1.29 bouyer switch (error) {
692 1.29 bouyer case 0:
693 1.29 bouyer break;
694 1.29 bouyer case ENOMEM:
695 1.29 bouyer case EAGAIN:
696 1.29 bouyer xs->error = XS_RESOURCE_SHORTAGE;
697 1.45 perry goto out_bad;
698 1.1 dante
699 1.29 bouyer default:
700 1.1 dante xs->error = XS_DRIVER_STUFFUP;
701 1.54 msaitoh aprint_error_dev(sc->sc_dev,
702 1.54 msaitoh "error %d loading DMA map\n", error);
703 1.29 bouyer out_bad:
704 1.1 dante adw_free_ccb(sc, ccb);
705 1.29 bouyer scsipi_done(xs);
706 1.29 bouyer return(0);
707 1.1 dante }
708 1.29 bouyer
709 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
710 1.29 bouyer ccb->dmamap_xfer->dm_mapsize,
711 1.29 bouyer (xs->xs_control & XS_CTL_DATA_IN) ?
712 1.29 bouyer BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
713 1.1 dante
714 1.1 dante /*
715 1.1 dante * Build scatter-gather list.
716 1.1 dante */
717 1.35 briggs scsiqp->data_cnt = htole32(xs->datalen);
718 1.7 dante scsiqp->vdata_addr = xs->data;
719 1.35 briggs scsiqp->data_addr = htole32(ccb->dmamap_xfer->dm_segs[0].ds_addr);
720 1.32 thorpej memset(ccb->sg_block, 0,
721 1.32 thorpej sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
722 1.7 dante adw_build_sglist(ccb, scsiqp, ccb->sg_block);
723 1.1 dante } else {
724 1.1 dante /*
725 1.1 dante * No data xfer, use non S/G values.
726 1.1 dante */
727 1.1 dante scsiqp->data_cnt = 0;
728 1.1 dante scsiqp->vdata_addr = 0;
729 1.1 dante scsiqp->data_addr = 0;
730 1.1 dante }
731 1.1 dante
732 1.1 dante return (1);
733 1.1 dante }
734 1.1 dante
735 1.1 dante
736 1.1 dante /*
737 1.1 dante * Build scatter-gather list for Wide Boards.
738 1.1 dante */
739 1.1 dante static void
740 1.30 lukem adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block)
741 1.1 dante {
742 1.9 thorpej u_long sg_block_next_addr; /* block and its next */
743 1.9 thorpej u_int32_t sg_block_physical_addr;
744 1.13 dante int i; /* how many SG entries */
745 1.1 dante bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
746 1.2 dante int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
747 1.1 dante
748 1.1 dante
749 1.9 thorpej sg_block_next_addr = (u_long) sg_block; /* allow math operation */
750 1.35 briggs sg_block_physical_addr = le32toh(ccb->hashkey) +
751 1.10 thorpej offsetof(struct adw_ccb, sg_block[0]);
752 1.35 briggs scsiqp->sg_real_addr = htole32(sg_block_physical_addr);
753 1.1 dante
754 1.1 dante /*
755 1.40 wiz * If there are more than NO_OF_SG_PER_BLOCK DMA segments (hw sg-list)
756 1.1 dante * then split the request into multiple sg-list blocks.
757 1.1 dante */
758 1.1 dante
759 1.2 dante do {
760 1.2 dante for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
761 1.35 briggs sg_block->sg_list[i].sg_addr = htole32(sg_list->ds_addr);
762 1.35 briggs sg_block->sg_list[i].sg_count = htole32(sg_list->ds_len);
763 1.1 dante
764 1.2 dante if (--sg_elem_cnt == 0) {
765 1.1 dante /* last entry, get out */
766 1.27 hpeyerl sg_block->sg_cnt = i + 1;
767 1.42 fvdl sg_block->sg_ptr = 0; /* next link = NULL */
768 1.1 dante return;
769 1.1 dante }
770 1.1 dante sg_list++;
771 1.1 dante }
772 1.1 dante sg_block_next_addr += sizeof(ADW_SG_BLOCK);
773 1.1 dante sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
774 1.1 dante
775 1.13 dante sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
776 1.35 briggs sg_block->sg_ptr = htole32(sg_block_physical_addr);
777 1.2 dante sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
778 1.10 thorpej } while (1);
779 1.1 dante }
780 1.1 dante
781 1.1 dante
782 1.22 dante /******************************************************************************/
783 1.22 dante /* Interrupts and TimeOut routines */
784 1.22 dante /******************************************************************************/
785 1.22 dante
786 1.22 dante
787 1.1 dante int
788 1.30 lukem adw_intr(void *arg)
789 1.1 dante {
790 1.1 dante ADW_SOFTC *sc = arg;
791 1.1 dante
792 1.1 dante
793 1.22 dante if(AdwISR(sc) != ADW_FALSE) {
794 1.16 dante return (1);
795 1.13 dante }
796 1.1 dante
797 1.16 dante return (0);
798 1.1 dante }
799 1.1 dante
800 1.1 dante
801 1.1 dante /*
802 1.1 dante * Poll a particular unit, looking for a particular xs
803 1.1 dante */
804 1.1 dante static int
805 1.30 lukem adw_poll(ADW_SOFTC *sc, struct scsipi_xfer *xs, int count)
806 1.1 dante {
807 1.1 dante
808 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
809 1.1 dante while (count) {
810 1.1 dante adw_intr(sc);
811 1.12 thorpej if (xs->xs_status & XS_STS_DONE)
812 1.1 dante return (0);
813 1.1 dante delay(1000); /* only happens in boot so ok */
814 1.1 dante count--;
815 1.1 dante }
816 1.1 dante return (1);
817 1.1 dante }
818 1.1 dante
819 1.1 dante
820 1.1 dante static void
821 1.30 lukem adw_timeout(void *arg)
822 1.1 dante {
823 1.1 dante ADW_CCB *ccb = arg;
824 1.1 dante struct scsipi_xfer *xs = ccb->xs;
825 1.29 bouyer struct scsipi_periph *periph = xs->xs_periph;
826 1.29 bouyer ADW_SOFTC *sc =
827 1.52 chs device_private(periph->periph_channel->chan_adapter->adapt_dev);
828 1.1 dante int s;
829 1.1 dante
830 1.29 bouyer scsipi_printaddr(periph);
831 1.1 dante printf("timed out");
832 1.1 dante
833 1.1 dante s = splbio();
834 1.1 dante
835 1.11 dante if (ccb->flags & CCB_ABORTED) {
836 1.11 dante /*
837 1.11 dante * Abort Timed Out
838 1.19 dante *
839 1.20 dante * No more opportunities. Lets try resetting the bus and
840 1.20 dante * reinitialize the host adapter.
841 1.11 dante */
842 1.19 dante callout_stop(&xs->xs_callout);
843 1.11 dante printf(" AGAIN. Resetting SCSI Bus\n");
844 1.22 dante adw_reset_bus(sc);
845 1.19 dante splx(s);
846 1.19 dante return;
847 1.19 dante } else if (ccb->flags & CCB_ABORTING) {
848 1.19 dante /*
849 1.20 dante * Abort the operation that has timed out.
850 1.19 dante *
851 1.19 dante * Second opportunity.
852 1.19 dante */
853 1.19 dante printf("\n");
854 1.19 dante xs->error = XS_TIMEOUT;
855 1.19 dante ccb->flags |= CCB_ABORTED;
856 1.19 dante #if 0
857 1.19 dante /*
858 1.19 dante * - XXX - 3.3a microcode is BROKEN!!!
859 1.19 dante *
860 1.19 dante * We cannot abort a CCB, so we can only hope the command
861 1.19 dante * get completed before the next timeout, otherwise a
862 1.19 dante * Bus Reset will arrive inexorably.
863 1.19 dante */
864 1.19 dante /*
865 1.19 dante * ADW_ABORT_CCB() makes the board to generate an interrupt
866 1.19 dante *
867 1.19 dante * - XXX - The above assertion MUST be verified (and this
868 1.19 dante * code changed as well [callout_*()]), when the
869 1.19 dante * ADW_ABORT_CCB will be working again
870 1.19 dante */
871 1.19 dante ADW_ABORT_CCB(sc, ccb);
872 1.19 dante #endif
873 1.19 dante /*
874 1.19 dante * waiting for multishot callout_reset() let's restart it
875 1.43 wiz * by hand so the next time a timeout event will occur
876 1.19 dante * we will reset the bus.
877 1.19 dante */
878 1.19 dante callout_reset(&xs->xs_callout,
879 1.38 bouyer mstohz(ccb->timeout), adw_timeout, ccb);
880 1.1 dante } else {
881 1.11 dante /*
882 1.20 dante * Abort the operation that has timed out.
883 1.19 dante *
884 1.19 dante * First opportunity.
885 1.11 dante */
886 1.1 dante printf("\n");
887 1.11 dante xs->error = XS_TIMEOUT;
888 1.11 dante ccb->flags |= CCB_ABORTING;
889 1.19 dante #if 0
890 1.19 dante /*
891 1.19 dante * - XXX - 3.3a microcode is BROKEN!!!
892 1.19 dante *
893 1.19 dante * We cannot abort a CCB, so we can only hope the command
894 1.19 dante * get completed before the next 2 timeout, otherwise a
895 1.19 dante * Bus Reset will arrive inexorably.
896 1.19 dante */
897 1.19 dante /*
898 1.19 dante * ADW_ABORT_CCB() makes the board to generate an interrupt
899 1.19 dante *
900 1.19 dante * - XXX - The above assertion MUST be verified (and this
901 1.19 dante * code changed as well [callout_*()]), when the
902 1.19 dante * ADW_ABORT_CCB will be working again
903 1.19 dante */
904 1.1 dante ADW_ABORT_CCB(sc, ccb);
905 1.19 dante #endif
906 1.19 dante /*
907 1.19 dante * waiting for multishot callout_reset() let's restart it
908 1.20 dante * by hand so to give a second opportunity to the command
909 1.20 dante * which timed-out.
910 1.19 dante */
911 1.19 dante callout_reset(&xs->xs_callout,
912 1.38 bouyer mstohz(ccb->timeout), adw_timeout, ccb);
913 1.1 dante }
914 1.1 dante
915 1.1 dante splx(s);
916 1.1 dante }
917 1.1 dante
918 1.1 dante
919 1.21 dante static void
920 1.30 lukem adw_reset_bus(ADW_SOFTC *sc)
921 1.21 dante {
922 1.21 dante ADW_CCB *ccb;
923 1.21 dante int s;
924 1.29 bouyer struct scsipi_xfer *xs;
925 1.21 dante
926 1.21 dante s = splbio();
927 1.22 dante AdwResetSCSIBus(sc);
928 1.21 dante while((ccb = TAILQ_LAST(&sc->sc_pending_ccb,
929 1.21 dante adw_pending_ccb)) != NULL) {
930 1.21 dante callout_stop(&ccb->xs->xs_callout);
931 1.21 dante TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
932 1.29 bouyer xs = ccb->xs;
933 1.29 bouyer adw_free_ccb(sc, ccb);
934 1.29 bouyer xs->error = XS_RESOURCE_SHORTAGE;
935 1.29 bouyer scsipi_done(xs);
936 1.21 dante }
937 1.21 dante splx(s);
938 1.21 dante }
939 1.21 dante
940 1.21 dante
941 1.1 dante /******************************************************************************/
942 1.19 dante /* Host Adapter and Peripherals Information Routines */
943 1.19 dante /******************************************************************************/
944 1.19 dante
945 1.19 dante
946 1.19 dante static void
947 1.30 lukem adw_print_info(ADW_SOFTC *sc, int tid)
948 1.19 dante {
949 1.19 dante bus_space_tag_t iot = sc->sc_iot;
950 1.19 dante bus_space_handle_t ioh = sc->sc_ioh;
951 1.19 dante u_int16_t wdtr_able, wdtr_done, wdtr;
952 1.19 dante u_int16_t sdtr_able, sdtr_done, sdtr, period;
953 1.20 dante static int wdtr_reneg = 0, sdtr_reneg = 0;
954 1.20 dante
955 1.20 dante if (tid == 0){
956 1.20 dante wdtr_reneg = sdtr_reneg = 0;
957 1.20 dante }
958 1.19 dante
959 1.52 chs printf("%s: target %d ", device_xname(sc->sc_dev), tid);
960 1.19 dante
961 1.22 dante ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, wdtr_able);
962 1.19 dante if(wdtr_able & ADW_TID_TO_TIDMASK(tid)) {
963 1.22 dante ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, wdtr_done);
964 1.22 dante ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE +
965 1.19 dante (2 * tid), wdtr);
966 1.19 dante printf("using %d-bits wide, ", (wdtr & 0x8000)? 16 : 8);
967 1.19 dante if((wdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0)
968 1.19 dante wdtr_reneg = 1;
969 1.19 dante } else {
970 1.19 dante printf("wide transfers disabled, ");
971 1.19 dante }
972 1.19 dante
973 1.22 dante ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
974 1.19 dante if(sdtr_able & ADW_TID_TO_TIDMASK(tid)) {
975 1.22 dante ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, sdtr_done);
976 1.22 dante ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE +
977 1.19 dante (2 * tid), sdtr);
978 1.19 dante sdtr &= ~0x8000;
979 1.19 dante if((sdtr & 0x1F) != 0) {
980 1.19 dante if((sdtr & 0x1F00) == 0x1100){
981 1.19 dante printf("80.0 MHz");
982 1.19 dante } else if((sdtr & 0x1F00) == 0x1000){
983 1.19 dante printf("40.0 MHz");
984 1.19 dante } else {
985 1.19 dante /* <= 20.0 MHz */
986 1.19 dante period = (((sdtr >> 8) * 25) + 50)/4;
987 1.19 dante if(period == 0) {
988 1.19 dante /* Should never happen. */
989 1.19 dante printf("? MHz");
990 1.19 dante } else {
991 1.19 dante printf("%d.%d MHz", 250/period,
992 1.19 dante ADW_TENTHS(250, period));
993 1.19 dante }
994 1.19 dante }
995 1.19 dante printf(" synchronous transfers\n");
996 1.19 dante } else {
997 1.19 dante printf("asynchronous transfers\n");
998 1.19 dante }
999 1.19 dante if((sdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0)
1000 1.19 dante sdtr_reneg = 1;
1001 1.19 dante } else {
1002 1.19 dante printf("synchronous transfers disabled\n");
1003 1.19 dante }
1004 1.19 dante
1005 1.19 dante if(wdtr_reneg || sdtr_reneg) {
1006 1.52 chs printf("%s: target %d %s", device_xname(sc->sc_dev), tid,
1007 1.19 dante (wdtr_reneg)? ((sdtr_reneg)? "wide/sync" : "wide") :
1008 1.19 dante ((sdtr_reneg)? "sync" : "") );
1009 1.19 dante printf(" renegotiation pending before next command.\n");
1010 1.19 dante }
1011 1.45 perry }
1012 1.19 dante
1013 1.19 dante
1014 1.19 dante /******************************************************************************/
1015 1.19 dante /* WIDE boards Interrupt callbacks */
1016 1.1 dante /******************************************************************************/
1017 1.1 dante
1018 1.1 dante
1019 1.1 dante /*
1020 1.22 dante * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR()
1021 1.1 dante *
1022 1.1 dante * Interrupt callback function for the Wide SCSI Adv Library.
1023 1.19 dante *
1024 1.19 dante * Notice:
1025 1.22 dante * Interrupts are disabled by the caller (AdwISR() function), and will be
1026 1.19 dante * enabled at the end of the caller.
1027 1.1 dante */
1028 1.1 dante static void
1029 1.30 lukem adw_isr_callback(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq)
1030 1.1 dante {
1031 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
1032 1.7 dante ADW_CCB *ccb;
1033 1.7 dante struct scsipi_xfer *xs;
1034 1.44 thorpej struct scsi_sense_data *s1, *s2;
1035 1.1 dante
1036 1.7 dante
1037 1.7 dante ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1038 1.11 dante
1039 1.15 thorpej callout_stop(&ccb->xs->xs_callout);
1040 1.11 dante
1041 1.7 dante xs = ccb->xs;
1042 1.1 dante
1043 1.1 dante /*
1044 1.1 dante * If we were a data transfer, unload the map that described
1045 1.1 dante * the data buffer.
1046 1.1 dante */
1047 1.1 dante if (xs->datalen) {
1048 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
1049 1.1 dante ccb->dmamap_xfer->dm_mapsize,
1050 1.12 thorpej (xs->xs_control & XS_CTL_DATA_IN) ?
1051 1.12 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1052 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
1053 1.1 dante }
1054 1.20 dante
1055 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
1056 1.52 chs aprint_error_dev(sc->sc_dev, "exiting ccb not allocated!\n");
1057 1.1 dante Debugger();
1058 1.1 dante return;
1059 1.1 dante }
1060 1.20 dante
1061 1.1 dante /*
1062 1.1 dante * 'done_status' contains the command's ending status.
1063 1.43 wiz * 'host_status' contains the host adapter status.
1064 1.20 dante * 'scsi_status' contains the scsi peripheral status.
1065 1.1 dante */
1066 1.21 dante if ((scsiq->host_status == QHSTA_NO_ERROR) &&
1067 1.21 dante ((scsiq->done_status == QD_NO_ERROR) ||
1068 1.22 dante (scsiq->done_status == QD_WITH_ERROR))) {
1069 1.34 dante switch (scsiq->scsi_status) {
1070 1.21 dante case SCSI_STATUS_GOOD:
1071 1.21 dante if ((scsiq->cdb[0] == INQUIRY) &&
1072 1.21 dante (scsiq->target_lun == 0)) {
1073 1.21 dante adw_print_info(sc, scsiq->target_id);
1074 1.21 dante }
1075 1.21 dante xs->error = XS_NOERROR;
1076 1.35 briggs xs->resid = le32toh(scsiq->data_cnt);
1077 1.21 dante sc->sc_freeze_dev[scsiq->target_id] = 0;
1078 1.21 dante break;
1079 1.21 dante
1080 1.21 dante case SCSI_STATUS_CHECK_CONDITION:
1081 1.21 dante case SCSI_STATUS_CMD_TERMINATED:
1082 1.21 dante s1 = &ccb->scsi_sense;
1083 1.21 dante s2 = &xs->sense.scsi_sense;
1084 1.21 dante *s2 = *s1;
1085 1.21 dante xs->error = XS_SENSE;
1086 1.21 dante sc->sc_freeze_dev[scsiq->target_id] = 1;
1087 1.21 dante break;
1088 1.21 dante
1089 1.21 dante default:
1090 1.21 dante xs->error = XS_BUSY;
1091 1.21 dante sc->sc_freeze_dev[scsiq->target_id] = 1;
1092 1.21 dante break;
1093 1.20 dante }
1094 1.21 dante } else if (scsiq->done_status == QD_ABORTED_BY_HOST) {
1095 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1096 1.21 dante } else {
1097 1.21 dante switch (scsiq->host_status) {
1098 1.21 dante case QHSTA_M_SEL_TIMEOUT:
1099 1.21 dante xs->error = XS_SELTIMEOUT;
1100 1.21 dante break;
1101 1.21 dante
1102 1.21 dante case QHSTA_M_SXFR_OFF_UFLW:
1103 1.21 dante case QHSTA_M_SXFR_OFF_OFLW:
1104 1.21 dante case QHSTA_M_DATA_OVER_RUN:
1105 1.54 msaitoh aprint_error_dev(sc->sc_dev,
1106 1.54 msaitoh "Overrun/Overflow/Underflow condition\n");
1107 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1108 1.21 dante break;
1109 1.21 dante
1110 1.21 dante case QHSTA_M_SXFR_DESELECTED:
1111 1.21 dante case QHSTA_M_UNEXPECTED_BUS_FREE:
1112 1.52 chs aprint_error_dev(sc->sc_dev, "Unexpected BUS free\n");
1113 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1114 1.21 dante break;
1115 1.21 dante
1116 1.21 dante case QHSTA_M_SCSI_BUS_RESET:
1117 1.21 dante case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1118 1.52 chs aprint_error_dev(sc->sc_dev, "BUS Reset\n");
1119 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1120 1.21 dante break;
1121 1.1 dante
1122 1.21 dante case QHSTA_M_BUS_DEVICE_RESET:
1123 1.52 chs aprint_error_dev(sc->sc_dev, "Device Reset\n");
1124 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1125 1.21 dante break;
1126 1.20 dante
1127 1.21 dante case QHSTA_M_QUEUE_ABORTED:
1128 1.52 chs aprint_error_dev(sc->sc_dev, "Queue Aborted\n");
1129 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1130 1.1 dante break;
1131 1.1 dante
1132 1.20 dante case QHSTA_M_SXFR_SDMA_ERR:
1133 1.21 dante case QHSTA_M_SXFR_SXFR_PERR:
1134 1.21 dante case QHSTA_M_RDMA_PERR:
1135 1.20 dante /*
1136 1.21 dante * DMA Error. This should *NEVER* happen!
1137 1.20 dante *
1138 1.20 dante * Lets try resetting the bus and reinitialize
1139 1.20 dante * the host adapter.
1140 1.20 dante */
1141 1.54 msaitoh aprint_error_dev(sc->sc_dev,
1142 1.54 msaitoh "DMA Error. Reseting bus\n");
1143 1.22 dante TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1144 1.22 dante adw_reset_bus(sc);
1145 1.21 dante xs->error = XS_BUSY;
1146 1.22 dante goto done;
1147 1.45 perry
1148 1.21 dante case QHSTA_M_WTM_TIMEOUT:
1149 1.21 dante case QHSTA_M_SXFR_WD_TMO:
1150 1.21 dante /* The SCSI bus hung in a phase */
1151 1.21 dante printf("%s: Watch Dog timer expired. Reseting bus\n",
1152 1.52 chs device_xname(sc->sc_dev));
1153 1.22 dante TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1154 1.22 dante adw_reset_bus(sc);
1155 1.21 dante xs->error = XS_BUSY;
1156 1.22 dante goto done;
1157 1.21 dante
1158 1.21 dante case QHSTA_M_SXFR_XFR_PH_ERR:
1159 1.52 chs aprint_error_dev(sc->sc_dev, "Transfer Error\n");
1160 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1161 1.21 dante break;
1162 1.21 dante
1163 1.21 dante case QHSTA_M_BAD_CMPL_STATUS_IN:
1164 1.21 dante /* No command complete after a status message */
1165 1.21 dante printf("%s: Bad Completion Status\n",
1166 1.52 chs device_xname(sc->sc_dev));
1167 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1168 1.21 dante break;
1169 1.21 dante
1170 1.21 dante case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1171 1.52 chs aprint_error_dev(sc->sc_dev, "Auto Sense Failed\n");
1172 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1173 1.21 dante break;
1174 1.21 dante
1175 1.21 dante case QHSTA_M_INVALID_DEVICE:
1176 1.52 chs aprint_error_dev(sc->sc_dev, "Invalid Device\n");
1177 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1178 1.21 dante break;
1179 1.11 dante
1180 1.21 dante case QHSTA_M_NO_AUTO_REQ_SENSE:
1181 1.21 dante /*
1182 1.21 dante * User didn't request sense, but we got a
1183 1.21 dante * check condition.
1184 1.21 dante */
1185 1.54 msaitoh aprint_error_dev(sc->sc_dev,
1186 1.54 msaitoh "Unexpected Check Condition\n");
1187 1.1 dante xs->error = XS_DRIVER_STUFFUP;
1188 1.1 dante break;
1189 1.1 dante
1190 1.21 dante case QHSTA_M_SXFR_UNKNOWN_ERROR:
1191 1.52 chs aprint_error_dev(sc->sc_dev, "Unknown Error\n");
1192 1.21 dante xs->error = XS_DRIVER_STUFFUP;
1193 1.21 dante break;
1194 1.11 dante
1195 1.21 dante default:
1196 1.21 dante panic("%s: Unhandled Host Status Error %x",
1197 1.52 chs device_xname(sc->sc_dev), scsiq->host_status);
1198 1.21 dante }
1199 1.1 dante }
1200 1.1 dante
1201 1.19 dante TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1202 1.22 dante done: adw_free_ccb(sc, ccb);
1203 1.1 dante scsipi_done(xs);
1204 1.11 dante }
1205 1.11 dante
1206 1.11 dante
1207 1.13 dante /*
1208 1.22 dante * adw_async_callback() - Adv Library asynchronous event callback function.
1209 1.13 dante */
1210 1.11 dante static void
1211 1.30 lukem adw_async_callback(ADW_SOFTC *sc, u_int8_t code)
1212 1.11 dante {
1213 1.13 dante switch (code) {
1214 1.13 dante case ADV_ASYNC_SCSI_BUS_RESET_DET:
1215 1.21 dante /* The firmware detected a SCSI Bus reset. */
1216 1.54 msaitoh printf("%s: SCSI Bus reset detected\n",
1217 1.54 msaitoh device_xname(sc->sc_dev));
1218 1.13 dante break;
1219 1.13 dante
1220 1.13 dante case ADV_ASYNC_RDMA_FAILURE:
1221 1.13 dante /*
1222 1.13 dante * Handle RDMA failure by resetting the SCSI Bus and
1223 1.19 dante * possibly the chip if it is unresponsive.
1224 1.13 dante */
1225 1.20 dante printf("%s: RDMA failure. Resetting the SCSI Bus and"
1226 1.52 chs " the adapter\n", device_xname(sc->sc_dev));
1227 1.22 dante AdwResetSCSIBus(sc);
1228 1.13 dante break;
1229 1.13 dante
1230 1.13 dante case ADV_HOST_SCSI_BUS_RESET:
1231 1.21 dante /* Host generated SCSI bus reset occurred. */
1232 1.19 dante printf("%s: Host generated SCSI bus reset occurred\n",
1233 1.52 chs device_xname(sc->sc_dev));
1234 1.19 dante break;
1235 1.19 dante
1236 1.19 dante case ADV_ASYNC_CARRIER_READY_FAILURE:
1237 1.21 dante /* Carrier Ready failure. */
1238 1.54 msaitoh printf("%s: Carrier Ready failure!\n",
1239 1.54 msaitoh device_xname(sc->sc_dev));
1240 1.19 dante break;
1241 1.13 dante
1242 1.13 dante default:
1243 1.13 dante break;
1244 1.13 dante }
1245 1.1 dante }
1246