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adw.c revision 1.6
      1  1.6  thorpej /* $NetBSD: adw.c,v 1.6 1998/12/09 08:47:18 thorpej Exp $	 */
      2  1.1    dante 
      3  1.1    dante /*
      4  1.1    dante  * Generic driver for the Advanced Systems Inc. SCSI controllers
      5  1.1    dante  *
      6  1.1    dante  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      7  1.1    dante  * All rights reserved.
      8  1.1    dante  *
      9  1.1    dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
     10  1.1    dante  *
     11  1.1    dante  * Redistribution and use in source and binary forms, with or without
     12  1.1    dante  * modification, are permitted provided that the following conditions
     13  1.1    dante  * are met:
     14  1.1    dante  * 1. Redistributions of source code must retain the above copyright
     15  1.1    dante  *    notice, this list of conditions and the following disclaimer.
     16  1.1    dante  * 2. Redistributions in binary form must reproduce the above copyright
     17  1.1    dante  *    notice, this list of conditions and the following disclaimer in the
     18  1.1    dante  *    documentation and/or other materials provided with the distribution.
     19  1.1    dante  * 3. All advertising materials mentioning features or use of this software
     20  1.1    dante  *    must display the following acknowledgement:
     21  1.1    dante  *        This product includes software developed by the NetBSD
     22  1.1    dante  *        Foundation, Inc. and its contributors.
     23  1.1    dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24  1.1    dante  *    contributors may be used to endorse or promote products derived
     25  1.1    dante  *    from this software without specific prior written permission.
     26  1.1    dante  *
     27  1.1    dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28  1.1    dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29  1.1    dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30  1.1    dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31  1.1    dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32  1.1    dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33  1.1    dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34  1.1    dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35  1.1    dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36  1.1    dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37  1.1    dante  * POSSIBILITY OF SUCH DAMAGE.
     38  1.1    dante  */
     39  1.1    dante 
     40  1.1    dante #include <sys/types.h>
     41  1.1    dante #include <sys/param.h>
     42  1.1    dante #include <sys/systm.h>
     43  1.1    dante #include <sys/kernel.h>
     44  1.1    dante #include <sys/errno.h>
     45  1.1    dante #include <sys/ioctl.h>
     46  1.1    dante #include <sys/device.h>
     47  1.1    dante #include <sys/malloc.h>
     48  1.1    dante #include <sys/buf.h>
     49  1.1    dante #include <sys/proc.h>
     50  1.1    dante #include <sys/user.h>
     51  1.1    dante 
     52  1.1    dante #include <machine/bus.h>
     53  1.1    dante #include <machine/intr.h>
     54  1.1    dante 
     55  1.1    dante #include <vm/vm.h>
     56  1.1    dante #include <vm/vm_param.h>
     57  1.1    dante #include <vm/pmap.h>
     58  1.1    dante 
     59  1.1    dante #include <dev/scsipi/scsi_all.h>
     60  1.1    dante #include <dev/scsipi/scsipi_all.h>
     61  1.1    dante #include <dev/scsipi/scsiconf.h>
     62  1.1    dante 
     63  1.1    dante #include <dev/ic/adwlib.h>
     64  1.1    dante #include <dev/ic/adw.h>
     65  1.1    dante 
     66  1.1    dante #ifndef DDB
     67  1.1    dante #define	Debugger()	panic("should call debugger here (adv.c)")
     68  1.2    dante #endif				/* ! DDB */
     69  1.1    dante 
     70  1.1    dante /******************************************************************************/
     71  1.1    dante 
     72  1.1    dante 
     73  1.1    dante static int adw_alloc_ccbs __P((ADW_SOFTC *));
     74  1.1    dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
     75  1.1    dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
     76  1.1    dante static void adw_reset_ccb __P((ADW_CCB *));
     77  1.1    dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
     78  1.1    dante static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int));
     79  1.1    dante static void adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *));
     80  1.1    dante static void adw_start_ccbs __P((ADW_SOFTC *));
     81  1.1    dante 
     82  1.1    dante static int adw_scsi_cmd __P((struct scsipi_xfer *));
     83  1.1    dante static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *));
     84  1.2    dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *));
     85  1.1    dante static void adwminphys __P((struct buf *));
     86  1.1    dante static void adw_wide_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
     87  1.1    dante 
     88  1.1    dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
     89  1.1    dante static void adw_timeout __P((void *));
     90  1.1    dante static void adw_watchdog __P((void *));
     91  1.1    dante 
     92  1.1    dante 
     93  1.1    dante /******************************************************************************/
     94  1.1    dante 
     95  1.1    dante 
     96  1.1    dante /* the below structure is so we have a default dev struct for out link struct */
     97  1.1    dante struct scsipi_device adw_dev =
     98  1.1    dante {
     99  1.1    dante 	NULL,			/* Use default error handler */
    100  1.1    dante 	NULL,			/* have a queue, served by this */
    101  1.1    dante 	NULL,			/* have no async handler */
    102  1.1    dante 	NULL,			/* Use default 'done' routine */
    103  1.1    dante };
    104  1.1    dante 
    105  1.1    dante 
    106  1.1    dante #define ADW_ABORT_TIMEOUT       10000	/* time to wait for abort (mSec) */
    107  1.1    dante #define ADW_WATCH_TIMEOUT       10000	/* time to wait for watchdog (mSec) */
    108  1.1    dante 
    109  1.1    dante 
    110  1.1    dante /******************************************************************************/
    111  1.2    dante /* Control Blocks routines                        */
    112  1.1    dante /******************************************************************************/
    113  1.1    dante 
    114  1.1    dante 
    115  1.1    dante static int
    116  1.1    dante adw_alloc_ccbs(sc)
    117  1.1    dante 	ADW_SOFTC      *sc;
    118  1.1    dante {
    119  1.1    dante 	bus_dma_segment_t seg;
    120  1.1    dante 	int             error, rseg;
    121  1.1    dante 
    122  1.1    dante 	/*
    123  1.1    dante          * Allocate the control blocks.
    124  1.1    dante          */
    125  1.1    dante 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
    126  1.1    dante 			   NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    127  1.1    dante 		printf("%s: unable to allocate control structures,"
    128  1.1    dante 		       " error = %d\n", sc->sc_dev.dv_xname, error);
    129  1.1    dante 		return (error);
    130  1.1    dante 	}
    131  1.1    dante 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    132  1.1    dante 		   sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
    133  1.1    dante 				 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
    134  1.1    dante 		printf("%s: unable to map control structures, error = %d\n",
    135  1.1    dante 		       sc->sc_dev.dv_xname, error);
    136  1.1    dante 		return (error);
    137  1.1    dante 	}
    138  1.1    dante 	/*
    139  1.1    dante          * Create and load the DMA map used for the control blocks.
    140  1.1    dante          */
    141  1.1    dante 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
    142  1.1    dante 			   1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
    143  1.1    dante 				       &sc->sc_dmamap_control)) != 0) {
    144  1.1    dante 		printf("%s: unable to create control DMA map, error = %d\n",
    145  1.1    dante 		       sc->sc_dev.dv_xname, error);
    146  1.1    dante 		return (error);
    147  1.1    dante 	}
    148  1.1    dante 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
    149  1.1    dante 			   sc->sc_control, sizeof(struct adw_control), NULL,
    150  1.1    dante 				     BUS_DMA_NOWAIT)) != 0) {
    151  1.1    dante 		printf("%s: unable to load control DMA map, error = %d\n",
    152  1.1    dante 		       sc->sc_dev.dv_xname, error);
    153  1.1    dante 		return (error);
    154  1.1    dante 	}
    155  1.1    dante 	return (0);
    156  1.1    dante }
    157  1.1    dante 
    158  1.1    dante 
    159  1.1    dante /*
    160  1.1    dante  * Create a set of ccbs and add them to the free list.  Called once
    161  1.1    dante  * by adw_init().  We return the number of CCBs successfully created.
    162  1.1    dante  */
    163  1.1    dante static int
    164  1.1    dante adw_create_ccbs(sc, ccbstore, count)
    165  1.1    dante 	ADW_SOFTC      *sc;
    166  1.1    dante 	ADW_CCB        *ccbstore;
    167  1.1    dante 	int             count;
    168  1.1    dante {
    169  1.1    dante 	ADW_CCB        *ccb;
    170  1.1    dante 	int             i, error;
    171  1.1    dante 
    172  1.1    dante 	bzero(ccbstore, sizeof(ADW_CCB) * count);
    173  1.1    dante 	for (i = 0; i < count; i++) {
    174  1.1    dante 		ccb = &ccbstore[i];
    175  1.1    dante 		if ((error = adw_init_ccb(sc, ccb)) != 0) {
    176  1.1    dante 			printf("%s: unable to initialize ccb, error = %d\n",
    177  1.1    dante 			       sc->sc_dev.dv_xname, error);
    178  1.1    dante 			return (i);
    179  1.1    dante 		}
    180  1.1    dante 		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
    181  1.1    dante 	}
    182  1.1    dante 
    183  1.1    dante 	return (i);
    184  1.1    dante }
    185  1.1    dante 
    186  1.1    dante 
    187  1.1    dante /*
    188  1.1    dante  * A ccb is put onto the free list.
    189  1.1    dante  */
    190  1.1    dante static void
    191  1.1    dante adw_free_ccb(sc, ccb)
    192  1.1    dante 	ADW_SOFTC      *sc;
    193  1.1    dante 	ADW_CCB        *ccb;
    194  1.1    dante {
    195  1.1    dante 	int             s;
    196  1.1    dante 
    197  1.1    dante 	s = splbio();
    198  1.1    dante 
    199  1.1    dante 	adw_reset_ccb(ccb);
    200  1.1    dante 	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
    201  1.1    dante 
    202  1.1    dante 	/*
    203  1.1    dante          * If there were none, wake anybody waiting for one to come free,
    204  1.1    dante          * starting with queued entries.
    205  1.1    dante          */
    206  1.1    dante 	if (ccb->chain.tqe_next == 0)
    207  1.1    dante 		wakeup(&sc->sc_free_ccb);
    208  1.1    dante 
    209  1.1    dante 	splx(s);
    210  1.1    dante }
    211  1.1    dante 
    212  1.1    dante 
    213  1.1    dante static void
    214  1.1    dante adw_reset_ccb(ccb)
    215  1.1    dante 	ADW_CCB        *ccb;
    216  1.1    dante {
    217  1.1    dante 
    218  1.1    dante 	ccb->flags = 0;
    219  1.1    dante }
    220  1.1    dante 
    221  1.1    dante 
    222  1.1    dante static int
    223  1.1    dante adw_init_ccb(sc, ccb)
    224  1.1    dante 	ADW_SOFTC      *sc;
    225  1.1    dante 	ADW_CCB        *ccb;
    226  1.1    dante {
    227  1.1    dante 	int             error;
    228  1.1    dante 
    229  1.1    dante 	/*
    230  1.1    dante          * Create the DMA map for this CCB.
    231  1.1    dante          */
    232  1.1    dante 	error = bus_dmamap_create(sc->sc_dmat,
    233  1.1    dante 				  (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    234  1.1    dante 			 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
    235  1.1    dante 		   0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
    236  1.1    dante 	if (error) {
    237  1.1    dante 		printf("%s: unable to create DMA map, error = %d\n",
    238  1.1    dante 		       sc->sc_dev.dv_xname, error);
    239  1.1    dante 		return (error);
    240  1.1    dante 	}
    241  1.1    dante 	adw_reset_ccb(ccb);
    242  1.1    dante 	return (0);
    243  1.1    dante }
    244  1.1    dante 
    245  1.1    dante 
    246  1.1    dante /*
    247  1.1    dante  * Get a free ccb
    248  1.1    dante  *
    249  1.1    dante  * If there are none, see if we can allocate a new one
    250  1.1    dante  */
    251  1.1    dante static ADW_CCB *
    252  1.1    dante adw_get_ccb(sc, flags)
    253  1.1    dante 	ADW_SOFTC      *sc;
    254  1.1    dante 	int             flags;
    255  1.1    dante {
    256  1.1    dante 	ADW_CCB        *ccb = 0;
    257  1.1    dante 	int             s;
    258  1.1    dante 
    259  1.1    dante 	s = splbio();
    260  1.1    dante 
    261  1.1    dante 	/*
    262  1.1    dante          * If we can and have to, sleep waiting for one to come free
    263  1.1    dante          * but only if we can't allocate a new one.
    264  1.1    dante          */
    265  1.1    dante 	for (;;) {
    266  1.1    dante 		ccb = sc->sc_free_ccb.tqh_first;
    267  1.1    dante 		if (ccb) {
    268  1.1    dante 			TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
    269  1.1    dante 			break;
    270  1.1    dante 		}
    271  1.1    dante 		if ((flags & SCSI_NOSLEEP) != 0)
    272  1.1    dante 			goto out;
    273  1.1    dante 
    274  1.1    dante 		tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
    275  1.1    dante 	}
    276  1.1    dante 
    277  1.1    dante 	ccb->flags |= CCB_ALLOC;
    278  1.1    dante 
    279  1.1    dante out:
    280  1.1    dante 	splx(s);
    281  1.1    dante 	return (ccb);
    282  1.1    dante }
    283  1.1    dante 
    284  1.1    dante 
    285  1.1    dante /*
    286  1.1    dante  * Queue a CCB to be sent to the controller, and send it if possible.
    287  1.1    dante  */
    288  1.1    dante static void
    289  1.1    dante adw_queue_ccb(sc, ccb)
    290  1.1    dante 	ADW_SOFTC      *sc;
    291  1.1    dante 	ADW_CCB        *ccb;
    292  1.1    dante {
    293  1.1    dante 
    294  1.1    dante 	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
    295  1.1    dante 
    296  1.1    dante 	adw_start_ccbs(sc);
    297  1.1    dante }
    298  1.1    dante 
    299  1.1    dante 
    300  1.1    dante static void
    301  1.1    dante adw_start_ccbs(sc)
    302  1.1    dante 	ADW_SOFTC      *sc;
    303  1.1    dante {
    304  1.1    dante 	ADW_CCB        *ccb;
    305  1.1    dante 
    306  1.1    dante 	while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
    307  1.1    dante 		if (ccb->flags & CCB_WATCHDOG)
    308  1.1    dante 			untimeout(adw_watchdog, ccb);
    309  1.1    dante 
    310  1.1    dante 		if (AdvExeScsiQueue(sc, &ccb->scsiq) == ADW_BUSY) {
    311  1.1    dante 			ccb->flags |= CCB_WATCHDOG;
    312  1.1    dante 			timeout(adw_watchdog, ccb,
    313  1.1    dante 				(ADW_WATCH_TIMEOUT * hz) / 1000);
    314  1.1    dante 			break;
    315  1.1    dante 		}
    316  1.1    dante 		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
    317  1.1    dante 
    318  1.1    dante 		if ((ccb->xs->flags & SCSI_POLL) == 0)
    319  1.1    dante 			timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000);
    320  1.1    dante 	}
    321  1.1    dante }
    322  1.1    dante 
    323  1.1    dante 
    324  1.1    dante /******************************************************************************/
    325  1.2    dante /* SCSI layer interfacing routines                    */
    326  1.1    dante /******************************************************************************/
    327  1.1    dante 
    328  1.1    dante 
    329  1.1    dante int
    330  1.1    dante adw_init(sc)
    331  1.1    dante 	ADW_SOFTC      *sc;
    332  1.1    dante {
    333  1.2    dante 	u_int16_t       warn_code;
    334  1.1    dante 
    335  1.1    dante 
    336  1.1    dante 	sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
    337  1.2    dante 		ADW_LIB_VERSION_MINOR;
    338  1.1    dante 	sc->cfg.chip_version =
    339  1.1    dante 		ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
    340  1.1    dante 
    341  1.1    dante 	/*
    342  1.1    dante 	 * Reset the chip to start and allow register writes.
    343  1.1    dante 	 */
    344  1.1    dante 	if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
    345  1.1    dante 		panic("adw_init: adw_find_signature failed");
    346  1.2    dante 	} else {
    347  1.1    dante 		AdvResetChip(sc->sc_iot, sc->sc_ioh);
    348  1.1    dante 
    349  1.1    dante 		warn_code = AdvInitFromEEP(sc);
    350  1.2    dante 		if (warn_code & ASC_WARN_EEPROM_CHKSUM)
    351  1.1    dante 			printf("%s: Bad checksum found. "
    352  1.2    dante 			       "Setting default values\n",
    353  1.2    dante 			       sc->sc_dev.dv_xname);
    354  1.2    dante 		if (warn_code & ASC_WARN_EEPROM_TERMINATION)
    355  1.1    dante 			printf("%s: Bad bus termination setting."
    356  1.2    dante 			       "Using automatic termination.\n",
    357  1.2    dante 			       sc->sc_dev.dv_xname);
    358  1.1    dante 
    359  1.1    dante 		/*
    360  1.1    dante 		 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
    361  1.1    dante 		 * Resets should be performed.
    362  1.1    dante 		 */
    363  1.1    dante 		if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
    364  1.1    dante 			AdvResetSCSIBus(sc);
    365  1.1    dante 	}
    366  1.1    dante 
    367  1.1    dante 	sc->isr_callback = (ulong) adw_wide_isr_callback;
    368  1.1    dante 
    369  1.1    dante 	return (0);
    370  1.1    dante }
    371  1.1    dante 
    372  1.1    dante 
    373  1.1    dante void
    374  1.1    dante adw_attach(sc)
    375  1.1    dante 	ADW_SOFTC      *sc;
    376  1.1    dante {
    377  1.1    dante 	int             i, error;
    378  1.1    dante 
    379  1.1    dante 
    380  1.1    dante 	/*
    381  1.1    dante 	 * Initialize the ASC3550.
    382  1.1    dante 	 */
    383  1.2    dante 	switch (AdvInitAsc3550Driver(sc)) {
    384  1.2    dante 	case ASC_IERR_MCODE_CHKSUM:
    385  1.2    dante 		panic("%s: Microcode checksum error",
    386  1.2    dante 		      sc->sc_dev.dv_xname);
    387  1.2    dante 		break;
    388  1.2    dante 
    389  1.2    dante 	case ASC_IERR_ILLEGAL_CONNECTION:
    390  1.2    dante 		panic("%s: All three connectors are in use",
    391  1.2    dante 		      sc->sc_dev.dv_xname);
    392  1.2    dante 		break;
    393  1.2    dante 
    394  1.2    dante 	case ASC_IERR_REVERSED_CABLE:
    395  1.2    dante 		panic("%s: Cable is reversed",
    396  1.2    dante 		      sc->sc_dev.dv_xname);
    397  1.2    dante 		break;
    398  1.2    dante 
    399  1.2    dante 	case ASC_IERR_SINGLE_END_DEVICE:
    400  1.2    dante 		panic("%s: single-ended device is attached to"
    401  1.2    dante 		      " one of the connectors",
    402  1.2    dante 		      sc->sc_dev.dv_xname);
    403  1.2    dante 		break;
    404  1.1    dante 	}
    405  1.1    dante 
    406  1.4  thorpej 	/*
    407  1.4  thorpej 	 * Fill in the adapter.
    408  1.4  thorpej 	 */
    409  1.4  thorpej 	sc->sc_adapter.scsipi_cmd = adw_scsi_cmd;
    410  1.4  thorpej 	sc->sc_adapter.scsipi_minphys = adwminphys;
    411  1.1    dante 
    412  1.1    dante 	/*
    413  1.1    dante          * fill in the prototype scsipi_link.
    414  1.1    dante          */
    415  1.1    dante 	sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
    416  1.1    dante 	sc->sc_link.adapter_softc = sc;
    417  1.1    dante 	sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
    418  1.4  thorpej 	sc->sc_link.adapter = &sc->sc_adapter;
    419  1.1    dante 	sc->sc_link.device = &adw_dev;
    420  1.1    dante 	sc->sc_link.openings = 4;
    421  1.1    dante 	sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID;
    422  1.5   mjacob 	sc->sc_link.scsipi_scsi.max_lun = 7;
    423  1.1    dante 	sc->sc_link.type = BUS_SCSI;
    424  1.1    dante 
    425  1.1    dante 
    426  1.1    dante 	TAILQ_INIT(&sc->sc_free_ccb);
    427  1.1    dante 	TAILQ_INIT(&sc->sc_waiting_ccb);
    428  1.6  thorpej 	TAILQ_INIT(&sc->sc_queue);
    429  1.1    dante 
    430  1.1    dante 
    431  1.1    dante 	/*
    432  1.1    dante          * Allocate the Control Blocks.
    433  1.1    dante          */
    434  1.1    dante 	error = adw_alloc_ccbs(sc);
    435  1.1    dante 	if (error)
    436  1.1    dante 		return; /* (error) */ ;
    437  1.1    dante 
    438  1.1    dante 	/*
    439  1.1    dante 	 * Create and initialize the Control Blocks.
    440  1.1    dante 	 */
    441  1.1    dante 	i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
    442  1.1    dante 	if (i == 0) {
    443  1.1    dante 		printf("%s: unable to create control blocks\n",
    444  1.1    dante 		       sc->sc_dev.dv_xname);
    445  1.1    dante 		return; /* (ENOMEM) */ ;
    446  1.1    dante 	} else if (i != ADW_MAX_CCB) {
    447  1.1    dante 		printf("%s: WARNING: only %d of %d control blocks"
    448  1.2    dante 		       " created\n",
    449  1.2    dante 		       sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
    450  1.1    dante 	}
    451  1.1    dante 	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
    452  1.1    dante }
    453  1.1    dante 
    454  1.1    dante 
    455  1.1    dante static void
    456  1.1    dante adwminphys(bp)
    457  1.1    dante 	struct buf     *bp;
    458  1.1    dante {
    459  1.1    dante 
    460  1.1    dante 	if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
    461  1.1    dante 		bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
    462  1.1    dante 	minphys(bp);
    463  1.1    dante }
    464  1.1    dante 
    465  1.1    dante 
    466  1.1    dante /*
    467  1.2    dante  * start a scsi operation given the command and the data address.
    468  1.2    dante  * Also needs the unit, target and lu.
    469  1.1    dante  */
    470  1.1    dante static int
    471  1.1    dante adw_scsi_cmd(xs)
    472  1.1    dante 	struct scsipi_xfer *xs;
    473  1.1    dante {
    474  1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    475  1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    476  1.1    dante 	ADW_CCB        *ccb;
    477  1.1    dante 	int             s, fromqueue = 1, dontqueue = 0;
    478  1.1    dante 
    479  1.1    dante 	s = splbio();		/* protect the queue */
    480  1.1    dante 
    481  1.1    dante 	/*
    482  1.1    dante          * If we're running the queue from adw_done(), we've been
    483  1.1    dante          * called with the first queue entry as our argument.
    484  1.1    dante          */
    485  1.6  thorpej 	if (xs == TAILQ_FIRST(&sc->sc_queue)) {
    486  1.6  thorpej 		TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    487  1.1    dante 		fromqueue = 1;
    488  1.1    dante 	} else {
    489  1.1    dante 
    490  1.1    dante 		/* Polled requests can't be queued for later. */
    491  1.1    dante 		dontqueue = xs->flags & SCSI_POLL;
    492  1.1    dante 
    493  1.1    dante 		/*
    494  1.1    dante                  * If there are jobs in the queue, run them first.
    495  1.1    dante                  */
    496  1.6  thorpej 		if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
    497  1.1    dante 			/*
    498  1.1    dante                          * If we can't queue, we have to abort, since
    499  1.1    dante                          * we have to preserve order.
    500  1.1    dante                          */
    501  1.1    dante 			if (dontqueue) {
    502  1.1    dante 				splx(s);
    503  1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    504  1.1    dante 				return (TRY_AGAIN_LATER);
    505  1.1    dante 			}
    506  1.1    dante 			/*
    507  1.1    dante                          * Swap with the first queue entry.
    508  1.1    dante                          */
    509  1.6  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    510  1.6  thorpej 			xs = TAILQ_FIRST(&sc->sc_queue);
    511  1.6  thorpej 			TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
    512  1.1    dante 			fromqueue = 1;
    513  1.1    dante 		}
    514  1.1    dante 	}
    515  1.1    dante 
    516  1.1    dante 
    517  1.1    dante 	/*
    518  1.1    dante          * get a ccb to use. If the transfer
    519  1.1    dante          * is from a buf (possibly from interrupt time)
    520  1.1    dante          * then we can't allow it to sleep
    521  1.1    dante          */
    522  1.1    dante 
    523  1.1    dante 	if ((ccb = adw_get_ccb(sc, xs->flags)) == NULL) {
    524  1.1    dante 		/*
    525  1.1    dante                  * If we can't queue, we lose.
    526  1.1    dante                  */
    527  1.1    dante 		if (dontqueue) {
    528  1.1    dante 			splx(s);
    529  1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    530  1.1    dante 			return (TRY_AGAIN_LATER);
    531  1.1    dante 		}
    532  1.1    dante 		/*
    533  1.1    dante                  * Stuff ourselves into the queue, in front
    534  1.1    dante                  * if we came off in the first place.
    535  1.1    dante                  */
    536  1.6  thorpej 		if (fromqueue)
    537  1.6  thorpej 			TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
    538  1.6  thorpej 		else
    539  1.6  thorpej 			TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
    540  1.1    dante 		splx(s);
    541  1.1    dante 		return (SUCCESSFULLY_QUEUED);
    542  1.1    dante 	}
    543  1.1    dante 	splx(s);		/* done playing with the queue */
    544  1.1    dante 
    545  1.1    dante 	ccb->xs = xs;
    546  1.1    dante 	ccb->timeout = xs->timeout;
    547  1.1    dante 
    548  1.2    dante 	if (adw_build_req(xs, ccb)) {
    549  1.1    dante 		s = splbio();
    550  1.1    dante 		adw_queue_ccb(sc, ccb);
    551  1.1    dante 		splx(s);
    552  1.1    dante 
    553  1.1    dante 		/*
    554  1.1    dante 	         * Usually return SUCCESSFULLY QUEUED
    555  1.1    dante 	         */
    556  1.1    dante 		if ((xs->flags & SCSI_POLL) == 0)
    557  1.1    dante 			return (SUCCESSFULLY_QUEUED);
    558  1.1    dante 
    559  1.1    dante 		/*
    560  1.1    dante 	         * If we can't use interrupts, poll on completion
    561  1.1    dante 	         */
    562  1.1    dante 		if (adw_poll(sc, xs, ccb->timeout)) {
    563  1.1    dante 			adw_timeout(ccb);
    564  1.1    dante 			if (adw_poll(sc, xs, ccb->timeout))
    565  1.1    dante 				adw_timeout(ccb);
    566  1.1    dante 		}
    567  1.1    dante 	}
    568  1.2    dante 	return (COMPLETE);
    569  1.1    dante }
    570  1.1    dante 
    571  1.1    dante 
    572  1.1    dante /*
    573  1.1    dante  * Build a request structure for the Wide Boards.
    574  1.1    dante  */
    575  1.1    dante static int
    576  1.1    dante adw_build_req(xs, ccb)
    577  1.2    dante 	struct scsipi_xfer *xs;
    578  1.2    dante 	ADW_CCB        *ccb;
    579  1.1    dante {
    580  1.2    dante 	struct scsipi_link *sc_link = xs->sc_link;
    581  1.2    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    582  1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    583  1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    584  1.2    dante 	int             error;
    585  1.1    dante 
    586  1.1    dante 	scsiqp = &ccb->scsiq;
    587  1.1    dante 	bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
    588  1.1    dante 
    589  1.1    dante 	/*
    590  1.1    dante 	 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the CCB structure.
    591  1.1    dante 	 */
    592  1.1    dante 	scsiqp->ccb_ptr = (ulong) ccb;
    593  1.1    dante 
    594  1.1    dante 
    595  1.1    dante 	/*
    596  1.1    dante 	 * Build the ADW_SCSI_REQ_Q request.
    597  1.1    dante 	 */
    598  1.1    dante 
    599  1.1    dante 	/*
    600  1.1    dante 	 * Set CDB length and copy it to the request structure.
    601  1.1    dante 	 */
    602  1.1    dante 	bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen);
    603  1.1    dante 
    604  1.1    dante 	scsiqp->target_id = sc_link->scsipi_scsi.target;
    605  1.1    dante 	scsiqp->target_lun = sc_link->scsipi_scsi.lun;
    606  1.1    dante 
    607  1.2    dante 	scsiqp->vsense_addr = (ulong) & ccb->scsi_sense;
    608  1.1    dante 	scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    609  1.1    dante 		ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
    610  1.1    dante 	scsiqp->sense_len = sizeof(struct scsipi_sense_data);
    611  1.1    dante 
    612  1.1    dante 	/*
    613  1.1    dante 	 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
    614  1.1    dante 	 */
    615  1.1    dante 	if (xs->datalen) {
    616  1.1    dante 		/*
    617  1.1    dante                  * Map the DMA transfer.
    618  1.1    dante                  */
    619  1.1    dante #ifdef TFS
    620  1.1    dante 		if (xs->flags & SCSI_DATA_UIO) {
    621  1.1    dante 			error = bus_dmamap_load_uio(dmat,
    622  1.2    dante 				ccb->dmamap_xfer, (struct uio *) xs->data,
    623  1.2    dante 				(xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
    624  1.2    dante 					BUS_DMA_WAITOK);
    625  1.1    dante 		} else
    626  1.1    dante #endif				/* TFS */
    627  1.1    dante 		{
    628  1.1    dante 			error = bus_dmamap_load(dmat,
    629  1.2    dante 			      ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
    630  1.2    dante 				(xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
    631  1.2    dante 					BUS_DMA_WAITOK);
    632  1.1    dante 		}
    633  1.1    dante 
    634  1.1    dante 		if (error) {
    635  1.1    dante 			if (error == EFBIG) {
    636  1.1    dante 				printf("%s: adw_scsi_cmd, more than %d dma"
    637  1.1    dante 				       " segments\n",
    638  1.1    dante 				       sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
    639  1.1    dante 			} else {
    640  1.1    dante 				printf("%s: adw_scsi_cmd, error %d loading"
    641  1.1    dante 				       " dma map\n",
    642  1.1    dante 				       sc->sc_dev.dv_xname, error);
    643  1.1    dante 			}
    644  1.1    dante 
    645  1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    646  1.1    dante 			adw_free_ccb(sc, ccb);
    647  1.1    dante 			return (0);
    648  1.1    dante 		}
    649  1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    650  1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    651  1.2    dante 			  (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
    652  1.1    dante 				BUS_DMASYNC_PREWRITE);
    653  1.1    dante 
    654  1.1    dante 		/*
    655  1.1    dante 		 * Build scatter-gather list.
    656  1.1    dante 		 */
    657  1.1    dante 		scsiqp->data_cnt = xs->datalen;
    658  1.1    dante 		scsiqp->vdata_addr = (ulong) xs->data;
    659  1.1    dante 		scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
    660  1.1    dante 		scsiqp->sg_list_ptr = &ccb->sg_block[0];
    661  1.2    dante 		bzero(scsiqp->sg_list_ptr,
    662  1.2    dante 				sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
    663  1.1    dante 		adw_build_sglist(ccb, scsiqp);
    664  1.1    dante 	} else {
    665  1.1    dante 		/*
    666  1.1    dante                  * No data xfer, use non S/G values.
    667  1.1    dante                  */
    668  1.1    dante 		scsiqp->data_cnt = 0;
    669  1.1    dante 		scsiqp->vdata_addr = 0;
    670  1.1    dante 		scsiqp->data_addr = 0;
    671  1.1    dante 		scsiqp->sg_list_ptr = NULL;
    672  1.1    dante 	}
    673  1.1    dante 
    674  1.1    dante 	return (1);
    675  1.1    dante }
    676  1.1    dante 
    677  1.1    dante 
    678  1.1    dante /*
    679  1.1    dante  * Build scatter-gather list for Wide Boards.
    680  1.1    dante  */
    681  1.1    dante static void
    682  1.1    dante adw_build_sglist(ccb, scsiqp)
    683  1.2    dante 	ADW_CCB        *ccb;
    684  1.2    dante 	ADW_SCSI_REQ_Q *scsiqp;
    685  1.1    dante {
    686  1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    687  1.2    dante 	ADW_SOFTC      *sc = xs->sc_link->adapter_softc;
    688  1.2    dante 	ADW_SG_BLOCK   *sg_block = scsiqp->sg_list_ptr;
    689  1.2    dante 	ulong           sg_block_next_addr;	/* block and its next */
    690  1.2    dante 	ulong           sg_block_physical_addr;
    691  1.2    dante 	int             sg_block_index, i;	/* how many SG entries */
    692  1.1    dante 	bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
    693  1.2    dante 	int             sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
    694  1.1    dante 
    695  1.1    dante 
    696  1.1    dante 	sg_block_next_addr = (ulong) sg_block;	/* allow math operation */
    697  1.1    dante 	sg_block_physical_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
    698  1.1    dante 		ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, sg_block[0]);
    699  1.1    dante 	scsiqp->sg_real_addr = sg_block_physical_addr;
    700  1.1    dante 
    701  1.1    dante 	/*
    702  1.1    dante 	 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
    703  1.1    dante 	 * then split the request into multiple sg-list blocks.
    704  1.1    dante 	 */
    705  1.1    dante 
    706  1.1    dante 	sg_block_index = 0;
    707  1.2    dante 	do {
    708  1.1    dante 		sg_block->first_entry_no = sg_block_index;
    709  1.2    dante 		for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
    710  1.1    dante 			sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
    711  1.1    dante 			sg_block->sg_list[i].sg_count = sg_list->ds_len;
    712  1.1    dante 
    713  1.2    dante 			if (--sg_elem_cnt == 0) {
    714  1.1    dante 				/* last entry, get out */
    715  1.1    dante 				scsiqp->sg_entry_cnt = sg_block_index + i + 1;
    716  1.1    dante 				sg_block->last_entry_no = sg_block_index + i;
    717  1.2    dante 				sg_block->sg_ptr = NULL; /* next link = NULL */
    718  1.1    dante 				return;
    719  1.1    dante 			}
    720  1.1    dante 			sg_list++;
    721  1.1    dante 		}
    722  1.1    dante 		sg_block_next_addr += sizeof(ADW_SG_BLOCK);
    723  1.1    dante 		sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
    724  1.1    dante 
    725  1.1    dante 		sg_block_index += NO_OF_SG_PER_BLOCK;
    726  1.1    dante 		sg_block->sg_ptr = (ADW_SG_BLOCK *) sg_block_physical_addr;
    727  1.1    dante 		sg_block->last_entry_no = sg_block_index - 1;
    728  1.2    dante 		sg_block = (ADW_SG_BLOCK *) sg_block_next_addr;	/* virt. addr */
    729  1.1    dante 	}
    730  1.1    dante 	while (1);
    731  1.1    dante }
    732  1.1    dante 
    733  1.1    dante 
    734  1.1    dante int
    735  1.1    dante adw_intr(arg)
    736  1.1    dante 	void           *arg;
    737  1.1    dante {
    738  1.1    dante 	ADW_SOFTC      *sc = arg;
    739  1.1    dante 	struct scsipi_xfer *xs;
    740  1.1    dante 
    741  1.1    dante 
    742  1.1    dante 	AdvISR(sc);
    743  1.1    dante 
    744  1.1    dante 	/*
    745  1.1    dante          * If there are queue entries in the software queue, try to
    746  1.1    dante          * run the first one.  We should be more or less guaranteed
    747  1.1    dante          * to succeed, since we just freed a CCB.
    748  1.1    dante          *
    749  1.1    dante          * NOTE: adw_scsi_cmd() relies on our calling it with
    750  1.1    dante          * the first entry in the queue.
    751  1.1    dante          */
    752  1.6  thorpej 	if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
    753  1.1    dante 		(void) adw_scsi_cmd(xs);
    754  1.1    dante 
    755  1.1    dante 	return (1);
    756  1.1    dante }
    757  1.1    dante 
    758  1.1    dante 
    759  1.1    dante /*
    760  1.1    dante  * Poll a particular unit, looking for a particular xs
    761  1.1    dante  */
    762  1.1    dante static int
    763  1.1    dante adw_poll(sc, xs, count)
    764  1.1    dante 	ADW_SOFTC      *sc;
    765  1.1    dante 	struct scsipi_xfer *xs;
    766  1.1    dante 	int             count;
    767  1.1    dante {
    768  1.1    dante 
    769  1.1    dante 	/* timeouts are in msec, so we loop in 1000 usec cycles */
    770  1.1    dante 	while (count) {
    771  1.1    dante 		adw_intr(sc);
    772  1.1    dante 		if (xs->flags & ITSDONE)
    773  1.1    dante 			return (0);
    774  1.1    dante 		delay(1000);	/* only happens in boot so ok */
    775  1.1    dante 		count--;
    776  1.1    dante 	}
    777  1.1    dante 	return (1);
    778  1.1    dante }
    779  1.1    dante 
    780  1.1    dante 
    781  1.1    dante static void
    782  1.1    dante adw_timeout(arg)
    783  1.1    dante 	void           *arg;
    784  1.1    dante {
    785  1.1    dante 	ADW_CCB        *ccb = arg;
    786  1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    787  1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    788  1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    789  1.1    dante 	int             s;
    790  1.1    dante 
    791  1.1    dante 	scsi_print_addr(sc_link);
    792  1.1    dante 	printf("timed out");
    793  1.1    dante 
    794  1.1    dante 	s = splbio();
    795  1.1    dante 
    796  1.1    dante 	/*
    797  1.1    dante          * If it has been through before, then a previous abort has failed,
    798  1.1    dante          * don't try abort again, reset the bus instead.
    799  1.1    dante          */
    800  1.1    dante 	if (ccb->flags & CCB_ABORT) {
    801  1.1    dante 		/* abort timed out */
    802  1.1    dante 		printf(" AGAIN. Resetting Bus\n");
    803  1.1    dante 		/* Lets try resetting the bus! */
    804  1.1    dante 		AdvResetSCSIBus(sc);
    805  1.1    dante 		ccb->timeout = ADW_ABORT_TIMEOUT;
    806  1.1    dante 		adw_queue_ccb(sc, ccb);
    807  1.1    dante 	} else {
    808  1.1    dante 		/* abort the operation that has timed out */
    809  1.1    dante 		printf("\n");
    810  1.1    dante 		ADW_ABORT_CCB(sc, ccb);
    811  1.1    dante 		xs->error = XS_TIMEOUT;
    812  1.1    dante 		ccb->timeout = ADW_ABORT_TIMEOUT;
    813  1.1    dante 		ccb->flags |= CCB_ABORT;
    814  1.1    dante 		adw_queue_ccb(sc, ccb);
    815  1.1    dante 	}
    816  1.1    dante 
    817  1.1    dante 	splx(s);
    818  1.1    dante }
    819  1.1    dante 
    820  1.1    dante 
    821  1.1    dante static void
    822  1.1    dante adw_watchdog(arg)
    823  1.1    dante 	void           *arg;
    824  1.1    dante {
    825  1.1    dante 	ADW_CCB        *ccb = arg;
    826  1.1    dante 	struct scsipi_xfer *xs = ccb->xs;
    827  1.1    dante 	struct scsipi_link *sc_link = xs->sc_link;
    828  1.1    dante 	ADW_SOFTC      *sc = sc_link->adapter_softc;
    829  1.1    dante 	int             s;
    830  1.1    dante 
    831  1.1    dante 	s = splbio();
    832  1.1    dante 
    833  1.1    dante 	ccb->flags &= ~CCB_WATCHDOG;
    834  1.1    dante 	adw_start_ccbs(sc);
    835  1.1    dante 
    836  1.1    dante 	splx(s);
    837  1.1    dante }
    838  1.1    dante 
    839  1.1    dante 
    840  1.1    dante /******************************************************************************/
    841  1.2    dante /* NARROW and WIDE boards Interrupt callbacks                */
    842  1.1    dante /******************************************************************************/
    843  1.1    dante 
    844  1.1    dante 
    845  1.1    dante /*
    846  1.1    dante  * adw_wide_isr_callback() - Second Level Interrupt Handler called by AdvISR()
    847  1.1    dante  *
    848  1.1    dante  * Interrupt callback function for the Wide SCSI Adv Library.
    849  1.1    dante  */
    850  1.1    dante static void
    851  1.1    dante adw_wide_isr_callback(sc, scsiq)
    852  1.1    dante 	ADW_SOFTC      *sc;
    853  1.1    dante 	ADW_SCSI_REQ_Q *scsiq;
    854  1.1    dante {
    855  1.2    dante 	bus_dma_tag_t   dmat = sc->sc_dmat;
    856  1.2    dante 	ADW_CCB        *ccb = (ADW_CCB *) scsiq->ccb_ptr;
    857  1.2    dante 	struct scsipi_xfer *xs = ccb->xs;
    858  1.1    dante 	struct scsipi_sense_data *s1, *s2;
    859  1.2    dante 	//int           underrun = ASC_FALSE;
    860  1.1    dante 
    861  1.1    dante 
    862  1.1    dante 	untimeout(adw_timeout, ccb);
    863  1.1    dante 
    864  1.1    dante 	/*
    865  1.1    dante          * If we were a data transfer, unload the map that described
    866  1.1    dante          * the data buffer.
    867  1.1    dante          */
    868  1.1    dante 	if (xs->datalen) {
    869  1.1    dante 		bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
    870  1.1    dante 				ccb->dmamap_xfer->dm_mapsize,
    871  1.1    dante 			 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
    872  1.1    dante 				BUS_DMASYNC_POSTWRITE);
    873  1.1    dante 		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
    874  1.1    dante 	}
    875  1.1    dante 	if ((ccb->flags & CCB_ALLOC) == 0) {
    876  1.1    dante 		printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
    877  1.1    dante 		Debugger();
    878  1.1    dante 		return;
    879  1.1    dante 	}
    880  1.1    dante 	/*
    881  1.1    dante 	 * Check for an underrun condition.
    882  1.1    dante 	 */
    883  1.2    dante 	/*
    884  1.2    dante 	 * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
    885  1.2    dante 	 * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
    886  1.2    dante 	 * scsiqp->data_cnt); underrun = ASC_TRUE; }
    887  1.2    dante 	 */
    888  1.1    dante 	/*
    889  1.1    dante 	 * 'done_status' contains the command's ending status.
    890  1.1    dante 	 */
    891  1.1    dante 	switch (scsiq->done_status) {
    892  1.1    dante 	case QD_NO_ERROR:
    893  1.1    dante 		switch (scsiq->host_status) {
    894  1.1    dante 		case QHSTA_NO_ERROR:
    895  1.1    dante 			xs->error = XS_NOERROR;
    896  1.1    dante 			xs->resid = 0;
    897  1.1    dante 			break;
    898  1.1    dante 		default:
    899  1.1    dante 			/* QHSTA error occurred. */
    900  1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    901  1.1    dante 			break;
    902  1.1    dante 		}
    903  1.1    dante 		/*
    904  1.1    dante 		 * If there was an underrun without any other error,
    905  1.1    dante 		 * set DID_ERROR to indicate the underrun error.
    906  1.1    dante 		 *
    907  1.1    dante 		 * Note: There is no way yet to indicate the number
    908  1.1    dante 		 * of underrun bytes.
    909  1.1    dante 		 */
    910  1.2    dante 		/*
    911  1.2    dante 		 * if (xs->error == XS_NOERROR && underrun == ASC_TRUE) {
    912  1.2    dante 		 * scp->result = HOST_BYTE(DID_UNDERRUN); }
    913  1.2    dante 		 */ break;
    914  1.1    dante 
    915  1.1    dante 	case QD_WITH_ERROR:
    916  1.1    dante 		switch (scsiq->host_status) {
    917  1.1    dante 		case QHSTA_NO_ERROR:
    918  1.1    dante 			if (scsiq->scsi_status == SS_CHK_CONDITION) {
    919  1.1    dante 				s1 = &ccb->scsi_sense;
    920  1.1    dante 				s2 = &xs->sense.scsi_sense;
    921  1.1    dante 				*s2 = *s1;
    922  1.1    dante 				xs->error = XS_SENSE;
    923  1.1    dante 			} else {
    924  1.1    dante 				xs->error = XS_DRIVER_STUFFUP;
    925  1.1    dante 			}
    926  1.1    dante 			break;
    927  1.1    dante 
    928  1.1    dante 		default:
    929  1.1    dante 			/* Some other QHSTA error occurred. */
    930  1.1    dante 			xs->error = XS_DRIVER_STUFFUP;
    931  1.1    dante 			break;
    932  1.1    dante 		}
    933  1.1    dante 		break;
    934  1.1    dante 
    935  1.1    dante 	case QD_ABORTED_BY_HOST:
    936  1.1    dante 	default:
    937  1.1    dante 		xs->error = XS_DRIVER_STUFFUP;
    938  1.1    dante 		break;
    939  1.1    dante 	}
    940  1.1    dante 
    941  1.1    dante 
    942  1.1    dante 	adw_free_ccb(sc, ccb);
    943  1.1    dante 	xs->flags |= ITSDONE;
    944  1.1    dante 	scsipi_done(xs);
    945  1.1    dante }
    946