adw.c revision 1.7 1 1.7 dante /* $NetBSD: adw.c,v 1.7 1999/02/23 20:18:16 dante Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.1 dante * Generic driver for the Advanced Systems Inc. SCSI controllers
5 1.1 dante *
6 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 1.1 dante * All rights reserved.
8 1.1 dante *
9 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 1.1 dante *
11 1.1 dante * Redistribution and use in source and binary forms, with or without
12 1.1 dante * modification, are permitted provided that the following conditions
13 1.1 dante * are met:
14 1.1 dante * 1. Redistributions of source code must retain the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer.
16 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dante * notice, this list of conditions and the following disclaimer in the
18 1.1 dante * documentation and/or other materials provided with the distribution.
19 1.1 dante * 3. All advertising materials mentioning features or use of this software
20 1.1 dante * must display the following acknowledgement:
21 1.1 dante * This product includes software developed by the NetBSD
22 1.1 dante * Foundation, Inc. and its contributors.
23 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 dante * contributors may be used to endorse or promote products derived
25 1.1 dante * from this software without specific prior written permission.
26 1.1 dante *
27 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
38 1.1 dante */
39 1.1 dante
40 1.1 dante #include <sys/types.h>
41 1.1 dante #include <sys/param.h>
42 1.1 dante #include <sys/systm.h>
43 1.1 dante #include <sys/kernel.h>
44 1.1 dante #include <sys/errno.h>
45 1.1 dante #include <sys/ioctl.h>
46 1.1 dante #include <sys/device.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/buf.h>
49 1.1 dante #include <sys/proc.h>
50 1.1 dante #include <sys/user.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <vm/vm.h>
56 1.1 dante #include <vm/vm_param.h>
57 1.1 dante #include <vm/pmap.h>
58 1.1 dante
59 1.1 dante #include <dev/scsipi/scsi_all.h>
60 1.1 dante #include <dev/scsipi/scsipi_all.h>
61 1.1 dante #include <dev/scsipi/scsiconf.h>
62 1.1 dante
63 1.1 dante #include <dev/ic/adwlib.h>
64 1.1 dante #include <dev/ic/adw.h>
65 1.1 dante
66 1.1 dante #ifndef DDB
67 1.1 dante #define Debugger() panic("should call debugger here (adv.c)")
68 1.2 dante #endif /* ! DDB */
69 1.1 dante
70 1.1 dante /******************************************************************************/
71 1.1 dante
72 1.1 dante
73 1.1 dante static int adw_alloc_ccbs __P((ADW_SOFTC *));
74 1.1 dante static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int));
75 1.1 dante static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *));
76 1.1 dante static void adw_reset_ccb __P((ADW_CCB *));
77 1.1 dante static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *));
78 1.1 dante static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int));
79 1.1 dante static void adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *));
80 1.1 dante static void adw_start_ccbs __P((ADW_SOFTC *));
81 1.1 dante
82 1.1 dante static int adw_scsi_cmd __P((struct scsipi_xfer *));
83 1.1 dante static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *));
84 1.7 dante static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *));
85 1.1 dante static void adwminphys __P((struct buf *));
86 1.1 dante static void adw_wide_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
87 1.1 dante
88 1.1 dante static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int));
89 1.1 dante static void adw_timeout __P((void *));
90 1.1 dante static void adw_watchdog __P((void *));
91 1.1 dante
92 1.1 dante
93 1.1 dante /******************************************************************************/
94 1.1 dante
95 1.1 dante
96 1.1 dante /* the below structure is so we have a default dev struct for out link struct */
97 1.1 dante struct scsipi_device adw_dev =
98 1.1 dante {
99 1.1 dante NULL, /* Use default error handler */
100 1.1 dante NULL, /* have a queue, served by this */
101 1.1 dante NULL, /* have no async handler */
102 1.1 dante NULL, /* Use default 'done' routine */
103 1.1 dante };
104 1.1 dante
105 1.1 dante
106 1.1 dante #define ADW_ABORT_TIMEOUT 10000 /* time to wait for abort (mSec) */
107 1.1 dante #define ADW_WATCH_TIMEOUT 10000 /* time to wait for watchdog (mSec) */
108 1.1 dante
109 1.1 dante
110 1.1 dante /******************************************************************************/
111 1.7 dante /* Control Blocks routines */
112 1.1 dante /******************************************************************************/
113 1.1 dante
114 1.1 dante
115 1.1 dante static int
116 1.1 dante adw_alloc_ccbs(sc)
117 1.1 dante ADW_SOFTC *sc;
118 1.1 dante {
119 1.1 dante bus_dma_segment_t seg;
120 1.1 dante int error, rseg;
121 1.1 dante
122 1.1 dante /*
123 1.1 dante * Allocate the control blocks.
124 1.1 dante */
125 1.1 dante if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
126 1.1 dante NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
127 1.1 dante printf("%s: unable to allocate control structures,"
128 1.1 dante " error = %d\n", sc->sc_dev.dv_xname, error);
129 1.1 dante return (error);
130 1.1 dante }
131 1.1 dante if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
132 1.1 dante sizeof(struct adw_control), (caddr_t *) & sc->sc_control,
133 1.1 dante BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
134 1.1 dante printf("%s: unable to map control structures, error = %d\n",
135 1.1 dante sc->sc_dev.dv_xname, error);
136 1.1 dante return (error);
137 1.1 dante }
138 1.1 dante /*
139 1.1 dante * Create and load the DMA map used for the control blocks.
140 1.1 dante */
141 1.1 dante if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
142 1.1 dante 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
143 1.1 dante &sc->sc_dmamap_control)) != 0) {
144 1.1 dante printf("%s: unable to create control DMA map, error = %d\n",
145 1.1 dante sc->sc_dev.dv_xname, error);
146 1.1 dante return (error);
147 1.1 dante }
148 1.1 dante if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
149 1.1 dante sc->sc_control, sizeof(struct adw_control), NULL,
150 1.1 dante BUS_DMA_NOWAIT)) != 0) {
151 1.1 dante printf("%s: unable to load control DMA map, error = %d\n",
152 1.1 dante sc->sc_dev.dv_xname, error);
153 1.1 dante return (error);
154 1.1 dante }
155 1.1 dante return (0);
156 1.1 dante }
157 1.1 dante
158 1.1 dante
159 1.1 dante /*
160 1.1 dante * Create a set of ccbs and add them to the free list. Called once
161 1.1 dante * by adw_init(). We return the number of CCBs successfully created.
162 1.1 dante */
163 1.1 dante static int
164 1.1 dante adw_create_ccbs(sc, ccbstore, count)
165 1.1 dante ADW_SOFTC *sc;
166 1.1 dante ADW_CCB *ccbstore;
167 1.1 dante int count;
168 1.1 dante {
169 1.1 dante ADW_CCB *ccb;
170 1.1 dante int i, error;
171 1.1 dante
172 1.1 dante bzero(ccbstore, sizeof(ADW_CCB) * count);
173 1.1 dante for (i = 0; i < count; i++) {
174 1.1 dante ccb = &ccbstore[i];
175 1.1 dante if ((error = adw_init_ccb(sc, ccb)) != 0) {
176 1.1 dante printf("%s: unable to initialize ccb, error = %d\n",
177 1.1 dante sc->sc_dev.dv_xname, error);
178 1.1 dante return (i);
179 1.1 dante }
180 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
181 1.1 dante }
182 1.1 dante
183 1.1 dante return (i);
184 1.1 dante }
185 1.1 dante
186 1.1 dante
187 1.1 dante /*
188 1.1 dante * A ccb is put onto the free list.
189 1.1 dante */
190 1.1 dante static void
191 1.1 dante adw_free_ccb(sc, ccb)
192 1.1 dante ADW_SOFTC *sc;
193 1.1 dante ADW_CCB *ccb;
194 1.1 dante {
195 1.1 dante int s;
196 1.1 dante
197 1.1 dante s = splbio();
198 1.1 dante
199 1.1 dante adw_reset_ccb(ccb);
200 1.1 dante TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
201 1.1 dante
202 1.1 dante /*
203 1.1 dante * If there were none, wake anybody waiting for one to come free,
204 1.1 dante * starting with queued entries.
205 1.1 dante */
206 1.1 dante if (ccb->chain.tqe_next == 0)
207 1.1 dante wakeup(&sc->sc_free_ccb);
208 1.1 dante
209 1.1 dante splx(s);
210 1.1 dante }
211 1.1 dante
212 1.1 dante
213 1.1 dante static void
214 1.1 dante adw_reset_ccb(ccb)
215 1.1 dante ADW_CCB *ccb;
216 1.1 dante {
217 1.1 dante
218 1.1 dante ccb->flags = 0;
219 1.1 dante }
220 1.1 dante
221 1.1 dante
222 1.1 dante static int
223 1.1 dante adw_init_ccb(sc, ccb)
224 1.1 dante ADW_SOFTC *sc;
225 1.1 dante ADW_CCB *ccb;
226 1.1 dante {
227 1.7 dante int hashnum, error;
228 1.1 dante
229 1.1 dante /*
230 1.1 dante * Create the DMA map for this CCB.
231 1.1 dante */
232 1.1 dante error = bus_dmamap_create(sc->sc_dmat,
233 1.1 dante (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
234 1.1 dante ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
235 1.1 dante 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
236 1.1 dante if (error) {
237 1.1 dante printf("%s: unable to create DMA map, error = %d\n",
238 1.1 dante sc->sc_dev.dv_xname, error);
239 1.1 dante return (error);
240 1.1 dante }
241 1.7 dante
242 1.7 dante /*
243 1.7 dante * put in the phystokv hash table
244 1.7 dante * Never gets taken out.
245 1.7 dante */
246 1.7 dante ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
247 1.7 dante ADW_CCB_OFF(ccb);
248 1.7 dante hashnum = CCB_HASH(ccb->hashkey);
249 1.7 dante ccb->nexthash = sc->sc_ccbhash[hashnum];
250 1.7 dante sc->sc_ccbhash[hashnum] = ccb;
251 1.1 dante adw_reset_ccb(ccb);
252 1.1 dante return (0);
253 1.1 dante }
254 1.1 dante
255 1.1 dante
256 1.1 dante /*
257 1.1 dante * Get a free ccb
258 1.1 dante *
259 1.1 dante * If there are none, see if we can allocate a new one
260 1.1 dante */
261 1.1 dante static ADW_CCB *
262 1.1 dante adw_get_ccb(sc, flags)
263 1.1 dante ADW_SOFTC *sc;
264 1.1 dante int flags;
265 1.1 dante {
266 1.1 dante ADW_CCB *ccb = 0;
267 1.1 dante int s;
268 1.1 dante
269 1.1 dante s = splbio();
270 1.1 dante
271 1.1 dante /*
272 1.1 dante * If we can and have to, sleep waiting for one to come free
273 1.1 dante * but only if we can't allocate a new one.
274 1.1 dante */
275 1.1 dante for (;;) {
276 1.1 dante ccb = sc->sc_free_ccb.tqh_first;
277 1.1 dante if (ccb) {
278 1.1 dante TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
279 1.1 dante break;
280 1.1 dante }
281 1.1 dante if ((flags & SCSI_NOSLEEP) != 0)
282 1.1 dante goto out;
283 1.1 dante
284 1.1 dante tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0);
285 1.1 dante }
286 1.1 dante
287 1.1 dante ccb->flags |= CCB_ALLOC;
288 1.1 dante
289 1.1 dante out:
290 1.1 dante splx(s);
291 1.1 dante return (ccb);
292 1.1 dante }
293 1.1 dante
294 1.1 dante
295 1.1 dante /*
296 1.7 dante * Given a physical address, find the ccb that it corresponds to.
297 1.7 dante */
298 1.7 dante ADW_CCB *
299 1.7 dante adw_ccb_phys_kv(sc, ccb_phys)
300 1.7 dante ADW_SOFTC *sc;
301 1.7 dante u_long ccb_phys;
302 1.7 dante {
303 1.7 dante int hashnum = CCB_HASH(ccb_phys);
304 1.7 dante ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
305 1.7 dante
306 1.7 dante while (ccb) {
307 1.7 dante if (ccb->hashkey == ccb_phys)
308 1.7 dante break;
309 1.7 dante ccb = ccb->nexthash;
310 1.7 dante }
311 1.7 dante return (ccb);
312 1.7 dante }
313 1.7 dante
314 1.7 dante
315 1.7 dante /*
316 1.1 dante * Queue a CCB to be sent to the controller, and send it if possible.
317 1.1 dante */
318 1.1 dante static void
319 1.1 dante adw_queue_ccb(sc, ccb)
320 1.1 dante ADW_SOFTC *sc;
321 1.1 dante ADW_CCB *ccb;
322 1.1 dante {
323 1.1 dante
324 1.1 dante TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
325 1.1 dante
326 1.1 dante adw_start_ccbs(sc);
327 1.1 dante }
328 1.1 dante
329 1.1 dante
330 1.1 dante static void
331 1.1 dante adw_start_ccbs(sc)
332 1.1 dante ADW_SOFTC *sc;
333 1.1 dante {
334 1.1 dante ADW_CCB *ccb;
335 1.1 dante
336 1.1 dante while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
337 1.1 dante if (ccb->flags & CCB_WATCHDOG)
338 1.1 dante untimeout(adw_watchdog, ccb);
339 1.1 dante
340 1.1 dante if (AdvExeScsiQueue(sc, &ccb->scsiq) == ADW_BUSY) {
341 1.1 dante ccb->flags |= CCB_WATCHDOG;
342 1.1 dante timeout(adw_watchdog, ccb,
343 1.1 dante (ADW_WATCH_TIMEOUT * hz) / 1000);
344 1.1 dante break;
345 1.1 dante }
346 1.1 dante TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
347 1.1 dante
348 1.1 dante if ((ccb->xs->flags & SCSI_POLL) == 0)
349 1.1 dante timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000);
350 1.1 dante }
351 1.1 dante }
352 1.1 dante
353 1.1 dante
354 1.1 dante /******************************************************************************/
355 1.7 dante /* SCSI layer interfacing routines */
356 1.1 dante /******************************************************************************/
357 1.1 dante
358 1.1 dante
359 1.1 dante int
360 1.1 dante adw_init(sc)
361 1.1 dante ADW_SOFTC *sc;
362 1.1 dante {
363 1.2 dante u_int16_t warn_code;
364 1.1 dante
365 1.1 dante
366 1.1 dante sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
367 1.2 dante ADW_LIB_VERSION_MINOR;
368 1.1 dante sc->cfg.chip_version =
369 1.1 dante ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
370 1.1 dante
371 1.1 dante /*
372 1.1 dante * Reset the chip to start and allow register writes.
373 1.1 dante */
374 1.1 dante if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
375 1.1 dante panic("adw_init: adw_find_signature failed");
376 1.2 dante } else {
377 1.1 dante AdvResetChip(sc->sc_iot, sc->sc_ioh);
378 1.1 dante
379 1.1 dante warn_code = AdvInitFromEEP(sc);
380 1.2 dante if (warn_code & ASC_WARN_EEPROM_CHKSUM)
381 1.1 dante printf("%s: Bad checksum found. "
382 1.2 dante "Setting default values\n",
383 1.2 dante sc->sc_dev.dv_xname);
384 1.2 dante if (warn_code & ASC_WARN_EEPROM_TERMINATION)
385 1.1 dante printf("%s: Bad bus termination setting."
386 1.2 dante "Using automatic termination.\n",
387 1.2 dante sc->sc_dev.dv_xname);
388 1.1 dante
389 1.1 dante /*
390 1.1 dante * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
391 1.1 dante * Resets should be performed.
392 1.1 dante */
393 1.1 dante if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
394 1.1 dante AdvResetSCSIBus(sc);
395 1.1 dante }
396 1.1 dante
397 1.1 dante sc->isr_callback = (ulong) adw_wide_isr_callback;
398 1.1 dante
399 1.1 dante return (0);
400 1.1 dante }
401 1.1 dante
402 1.1 dante
403 1.1 dante void
404 1.1 dante adw_attach(sc)
405 1.1 dante ADW_SOFTC *sc;
406 1.1 dante {
407 1.1 dante int i, error;
408 1.1 dante
409 1.1 dante
410 1.1 dante /*
411 1.1 dante * Initialize the ASC3550.
412 1.1 dante */
413 1.2 dante switch (AdvInitAsc3550Driver(sc)) {
414 1.2 dante case ASC_IERR_MCODE_CHKSUM:
415 1.2 dante panic("%s: Microcode checksum error",
416 1.2 dante sc->sc_dev.dv_xname);
417 1.2 dante break;
418 1.2 dante
419 1.2 dante case ASC_IERR_ILLEGAL_CONNECTION:
420 1.2 dante panic("%s: All three connectors are in use",
421 1.2 dante sc->sc_dev.dv_xname);
422 1.2 dante break;
423 1.2 dante
424 1.2 dante case ASC_IERR_REVERSED_CABLE:
425 1.2 dante panic("%s: Cable is reversed",
426 1.2 dante sc->sc_dev.dv_xname);
427 1.2 dante break;
428 1.2 dante
429 1.2 dante case ASC_IERR_SINGLE_END_DEVICE:
430 1.2 dante panic("%s: single-ended device is attached to"
431 1.2 dante " one of the connectors",
432 1.2 dante sc->sc_dev.dv_xname);
433 1.2 dante break;
434 1.1 dante }
435 1.1 dante
436 1.4 thorpej /*
437 1.4 thorpej * Fill in the adapter.
438 1.4 thorpej */
439 1.4 thorpej sc->sc_adapter.scsipi_cmd = adw_scsi_cmd;
440 1.4 thorpej sc->sc_adapter.scsipi_minphys = adwminphys;
441 1.1 dante
442 1.1 dante /*
443 1.1 dante * fill in the prototype scsipi_link.
444 1.1 dante */
445 1.1 dante sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
446 1.1 dante sc->sc_link.adapter_softc = sc;
447 1.1 dante sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id;
448 1.4 thorpej sc->sc_link.adapter = &sc->sc_adapter;
449 1.1 dante sc->sc_link.device = &adw_dev;
450 1.1 dante sc->sc_link.openings = 4;
451 1.1 dante sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID;
452 1.5 mjacob sc->sc_link.scsipi_scsi.max_lun = 7;
453 1.1 dante sc->sc_link.type = BUS_SCSI;
454 1.1 dante
455 1.1 dante
456 1.1 dante TAILQ_INIT(&sc->sc_free_ccb);
457 1.1 dante TAILQ_INIT(&sc->sc_waiting_ccb);
458 1.6 thorpej TAILQ_INIT(&sc->sc_queue);
459 1.1 dante
460 1.1 dante
461 1.1 dante /*
462 1.1 dante * Allocate the Control Blocks.
463 1.1 dante */
464 1.1 dante error = adw_alloc_ccbs(sc);
465 1.1 dante if (error)
466 1.1 dante return; /* (error) */ ;
467 1.1 dante
468 1.1 dante /*
469 1.1 dante * Create and initialize the Control Blocks.
470 1.1 dante */
471 1.1 dante i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
472 1.1 dante if (i == 0) {
473 1.1 dante printf("%s: unable to create control blocks\n",
474 1.1 dante sc->sc_dev.dv_xname);
475 1.1 dante return; /* (ENOMEM) */ ;
476 1.1 dante } else if (i != ADW_MAX_CCB) {
477 1.1 dante printf("%s: WARNING: only %d of %d control blocks"
478 1.2 dante " created\n",
479 1.2 dante sc->sc_dev.dv_xname, i, ADW_MAX_CCB);
480 1.1 dante }
481 1.1 dante config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
482 1.1 dante }
483 1.1 dante
484 1.1 dante
485 1.1 dante static void
486 1.1 dante adwminphys(bp)
487 1.1 dante struct buf *bp;
488 1.1 dante {
489 1.1 dante
490 1.1 dante if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
491 1.1 dante bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
492 1.1 dante minphys(bp);
493 1.1 dante }
494 1.1 dante
495 1.1 dante
496 1.1 dante /*
497 1.2 dante * start a scsi operation given the command and the data address.
498 1.2 dante * Also needs the unit, target and lu.
499 1.1 dante */
500 1.1 dante static int
501 1.1 dante adw_scsi_cmd(xs)
502 1.1 dante struct scsipi_xfer *xs;
503 1.1 dante {
504 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
505 1.1 dante ADW_SOFTC *sc = sc_link->adapter_softc;
506 1.1 dante ADW_CCB *ccb;
507 1.1 dante int s, fromqueue = 1, dontqueue = 0;
508 1.1 dante
509 1.1 dante s = splbio(); /* protect the queue */
510 1.1 dante
511 1.1 dante /*
512 1.1 dante * If we're running the queue from adw_done(), we've been
513 1.1 dante * called with the first queue entry as our argument.
514 1.1 dante */
515 1.6 thorpej if (xs == TAILQ_FIRST(&sc->sc_queue)) {
516 1.6 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
517 1.1 dante fromqueue = 1;
518 1.1 dante } else {
519 1.1 dante
520 1.1 dante /* Polled requests can't be queued for later. */
521 1.1 dante dontqueue = xs->flags & SCSI_POLL;
522 1.1 dante
523 1.1 dante /*
524 1.1 dante * If there are jobs in the queue, run them first.
525 1.1 dante */
526 1.6 thorpej if (TAILQ_FIRST(&sc->sc_queue) != NULL) {
527 1.1 dante /*
528 1.1 dante * If we can't queue, we have to abort, since
529 1.1 dante * we have to preserve order.
530 1.1 dante */
531 1.1 dante if (dontqueue) {
532 1.1 dante splx(s);
533 1.1 dante xs->error = XS_DRIVER_STUFFUP;
534 1.1 dante return (TRY_AGAIN_LATER);
535 1.1 dante }
536 1.1 dante /*
537 1.1 dante * Swap with the first queue entry.
538 1.1 dante */
539 1.6 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
540 1.6 thorpej xs = TAILQ_FIRST(&sc->sc_queue);
541 1.6 thorpej TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q);
542 1.1 dante fromqueue = 1;
543 1.1 dante }
544 1.1 dante }
545 1.1 dante
546 1.1 dante
547 1.1 dante /*
548 1.1 dante * get a ccb to use. If the transfer
549 1.1 dante * is from a buf (possibly from interrupt time)
550 1.1 dante * then we can't allow it to sleep
551 1.1 dante */
552 1.1 dante
553 1.1 dante if ((ccb = adw_get_ccb(sc, xs->flags)) == NULL) {
554 1.1 dante /*
555 1.1 dante * If we can't queue, we lose.
556 1.1 dante */
557 1.1 dante if (dontqueue) {
558 1.1 dante splx(s);
559 1.1 dante xs->error = XS_DRIVER_STUFFUP;
560 1.1 dante return (TRY_AGAIN_LATER);
561 1.1 dante }
562 1.1 dante /*
563 1.1 dante * Stuff ourselves into the queue, in front
564 1.1 dante * if we came off in the first place.
565 1.1 dante */
566 1.6 thorpej if (fromqueue)
567 1.6 thorpej TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q);
568 1.6 thorpej else
569 1.6 thorpej TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q);
570 1.1 dante splx(s);
571 1.1 dante return (SUCCESSFULLY_QUEUED);
572 1.1 dante }
573 1.1 dante splx(s); /* done playing with the queue */
574 1.1 dante
575 1.1 dante ccb->xs = xs;
576 1.1 dante ccb->timeout = xs->timeout;
577 1.1 dante
578 1.2 dante if (adw_build_req(xs, ccb)) {
579 1.1 dante s = splbio();
580 1.1 dante adw_queue_ccb(sc, ccb);
581 1.1 dante splx(s);
582 1.1 dante
583 1.1 dante /*
584 1.1 dante * Usually return SUCCESSFULLY QUEUED
585 1.1 dante */
586 1.1 dante if ((xs->flags & SCSI_POLL) == 0)
587 1.1 dante return (SUCCESSFULLY_QUEUED);
588 1.1 dante
589 1.1 dante /*
590 1.1 dante * If we can't use interrupts, poll on completion
591 1.1 dante */
592 1.1 dante if (adw_poll(sc, xs, ccb->timeout)) {
593 1.1 dante adw_timeout(ccb);
594 1.1 dante if (adw_poll(sc, xs, ccb->timeout))
595 1.1 dante adw_timeout(ccb);
596 1.1 dante }
597 1.1 dante }
598 1.2 dante return (COMPLETE);
599 1.1 dante }
600 1.1 dante
601 1.1 dante
602 1.1 dante /*
603 1.1 dante * Build a request structure for the Wide Boards.
604 1.1 dante */
605 1.1 dante static int
606 1.1 dante adw_build_req(xs, ccb)
607 1.2 dante struct scsipi_xfer *xs;
608 1.2 dante ADW_CCB *ccb;
609 1.1 dante {
610 1.2 dante struct scsipi_link *sc_link = xs->sc_link;
611 1.2 dante ADW_SOFTC *sc = sc_link->adapter_softc;
612 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
613 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
614 1.2 dante int error;
615 1.1 dante
616 1.1 dante scsiqp = &ccb->scsiq;
617 1.1 dante bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q));
618 1.1 dante
619 1.1 dante /*
620 1.7 dante * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
621 1.7 dante * physical CCB structure.
622 1.1 dante */
623 1.7 dante scsiqp->ccb_ptr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
624 1.7 dante ADW_CCB_OFF(ccb);
625 1.1 dante
626 1.1 dante
627 1.1 dante /*
628 1.1 dante * Build the ADW_SCSI_REQ_Q request.
629 1.1 dante */
630 1.1 dante
631 1.1 dante /*
632 1.1 dante * Set CDB length and copy it to the request structure.
633 1.1 dante */
634 1.1 dante bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen);
635 1.1 dante
636 1.1 dante scsiqp->target_id = sc_link->scsipi_scsi.target;
637 1.1 dante scsiqp->target_lun = sc_link->scsipi_scsi.lun;
638 1.1 dante
639 1.7 dante scsiqp->vsense_addr = &ccb->scsi_sense;
640 1.1 dante scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
641 1.1 dante ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense);
642 1.1 dante scsiqp->sense_len = sizeof(struct scsipi_sense_data);
643 1.1 dante
644 1.1 dante /*
645 1.1 dante * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
646 1.1 dante */
647 1.1 dante if (xs->datalen) {
648 1.1 dante /*
649 1.1 dante * Map the DMA transfer.
650 1.1 dante */
651 1.1 dante #ifdef TFS
652 1.1 dante if (xs->flags & SCSI_DATA_UIO) {
653 1.1 dante error = bus_dmamap_load_uio(dmat,
654 1.2 dante ccb->dmamap_xfer, (struct uio *) xs->data,
655 1.2 dante (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
656 1.2 dante BUS_DMA_WAITOK);
657 1.1 dante } else
658 1.1 dante #endif /* TFS */
659 1.1 dante {
660 1.1 dante error = bus_dmamap_load(dmat,
661 1.2 dante ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
662 1.2 dante (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
663 1.2 dante BUS_DMA_WAITOK);
664 1.1 dante }
665 1.1 dante
666 1.1 dante if (error) {
667 1.1 dante if (error == EFBIG) {
668 1.1 dante printf("%s: adw_scsi_cmd, more than %d dma"
669 1.1 dante " segments\n",
670 1.1 dante sc->sc_dev.dv_xname, ADW_MAX_SG_LIST);
671 1.1 dante } else {
672 1.1 dante printf("%s: adw_scsi_cmd, error %d loading"
673 1.1 dante " dma map\n",
674 1.1 dante sc->sc_dev.dv_xname, error);
675 1.1 dante }
676 1.1 dante
677 1.1 dante xs->error = XS_DRIVER_STUFFUP;
678 1.1 dante adw_free_ccb(sc, ccb);
679 1.1 dante return (0);
680 1.1 dante }
681 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
682 1.1 dante ccb->dmamap_xfer->dm_mapsize,
683 1.2 dante (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
684 1.1 dante BUS_DMASYNC_PREWRITE);
685 1.1 dante
686 1.1 dante /*
687 1.1 dante * Build scatter-gather list.
688 1.1 dante */
689 1.1 dante scsiqp->data_cnt = xs->datalen;
690 1.7 dante scsiqp->vdata_addr = xs->data;
691 1.1 dante scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr;
692 1.7 dante bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
693 1.7 dante adw_build_sglist(ccb, scsiqp, ccb->sg_block);
694 1.1 dante } else {
695 1.1 dante /*
696 1.1 dante * No data xfer, use non S/G values.
697 1.1 dante */
698 1.1 dante scsiqp->data_cnt = 0;
699 1.1 dante scsiqp->vdata_addr = 0;
700 1.1 dante scsiqp->data_addr = 0;
701 1.1 dante }
702 1.1 dante
703 1.1 dante return (1);
704 1.1 dante }
705 1.1 dante
706 1.1 dante
707 1.1 dante /*
708 1.1 dante * Build scatter-gather list for Wide Boards.
709 1.1 dante */
710 1.1 dante static void
711 1.7 dante adw_build_sglist(ccb, scsiqp, sg_block)
712 1.2 dante ADW_CCB *ccb;
713 1.2 dante ADW_SCSI_REQ_Q *scsiqp;
714 1.7 dante ADW_SG_BLOCK *sg_block;
715 1.1 dante {
716 1.1 dante struct scsipi_xfer *xs = ccb->xs;
717 1.2 dante ADW_SOFTC *sc = xs->sc_link->adapter_softc;
718 1.2 dante ulong sg_block_next_addr; /* block and its next */
719 1.2 dante ulong sg_block_physical_addr;
720 1.2 dante int sg_block_index, i; /* how many SG entries */
721 1.1 dante bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
722 1.2 dante int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
723 1.1 dante
724 1.1 dante
725 1.1 dante sg_block_next_addr = (ulong) sg_block; /* allow math operation */
726 1.1 dante sg_block_physical_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
727 1.1 dante ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, sg_block[0]);
728 1.1 dante scsiqp->sg_real_addr = sg_block_physical_addr;
729 1.1 dante
730 1.1 dante /*
731 1.1 dante * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list)
732 1.1 dante * then split the request into multiple sg-list blocks.
733 1.1 dante */
734 1.1 dante
735 1.1 dante sg_block_index = 0;
736 1.2 dante do {
737 1.1 dante sg_block->first_entry_no = sg_block_index;
738 1.2 dante for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
739 1.1 dante sg_block->sg_list[i].sg_addr = sg_list->ds_addr;
740 1.1 dante sg_block->sg_list[i].sg_count = sg_list->ds_len;
741 1.1 dante
742 1.2 dante if (--sg_elem_cnt == 0) {
743 1.1 dante /* last entry, get out */
744 1.1 dante scsiqp->sg_entry_cnt = sg_block_index + i + 1;
745 1.1 dante sg_block->last_entry_no = sg_block_index + i;
746 1.2 dante sg_block->sg_ptr = NULL; /* next link = NULL */
747 1.1 dante return;
748 1.1 dante }
749 1.1 dante sg_list++;
750 1.1 dante }
751 1.1 dante sg_block_next_addr += sizeof(ADW_SG_BLOCK);
752 1.1 dante sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
753 1.1 dante
754 1.1 dante sg_block_index += NO_OF_SG_PER_BLOCK;
755 1.1 dante sg_block->sg_ptr = (ADW_SG_BLOCK *) sg_block_physical_addr;
756 1.1 dante sg_block->last_entry_no = sg_block_index - 1;
757 1.2 dante sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
758 1.1 dante }
759 1.1 dante while (1);
760 1.1 dante }
761 1.1 dante
762 1.1 dante
763 1.1 dante int
764 1.1 dante adw_intr(arg)
765 1.1 dante void *arg;
766 1.1 dante {
767 1.1 dante ADW_SOFTC *sc = arg;
768 1.1 dante struct scsipi_xfer *xs;
769 1.1 dante
770 1.1 dante
771 1.1 dante AdvISR(sc);
772 1.1 dante
773 1.1 dante /*
774 1.1 dante * If there are queue entries in the software queue, try to
775 1.1 dante * run the first one. We should be more or less guaranteed
776 1.1 dante * to succeed, since we just freed a CCB.
777 1.1 dante *
778 1.1 dante * NOTE: adw_scsi_cmd() relies on our calling it with
779 1.1 dante * the first entry in the queue.
780 1.1 dante */
781 1.6 thorpej if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL)
782 1.1 dante (void) adw_scsi_cmd(xs);
783 1.1 dante
784 1.1 dante return (1);
785 1.1 dante }
786 1.1 dante
787 1.1 dante
788 1.1 dante /*
789 1.1 dante * Poll a particular unit, looking for a particular xs
790 1.1 dante */
791 1.1 dante static int
792 1.1 dante adw_poll(sc, xs, count)
793 1.1 dante ADW_SOFTC *sc;
794 1.1 dante struct scsipi_xfer *xs;
795 1.1 dante int count;
796 1.1 dante {
797 1.1 dante
798 1.1 dante /* timeouts are in msec, so we loop in 1000 usec cycles */
799 1.1 dante while (count) {
800 1.1 dante adw_intr(sc);
801 1.1 dante if (xs->flags & ITSDONE)
802 1.1 dante return (0);
803 1.1 dante delay(1000); /* only happens in boot so ok */
804 1.1 dante count--;
805 1.1 dante }
806 1.1 dante return (1);
807 1.1 dante }
808 1.1 dante
809 1.1 dante
810 1.1 dante static void
811 1.1 dante adw_timeout(arg)
812 1.1 dante void *arg;
813 1.1 dante {
814 1.1 dante ADW_CCB *ccb = arg;
815 1.1 dante struct scsipi_xfer *xs = ccb->xs;
816 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
817 1.1 dante ADW_SOFTC *sc = sc_link->adapter_softc;
818 1.1 dante int s;
819 1.1 dante
820 1.1 dante scsi_print_addr(sc_link);
821 1.1 dante printf("timed out");
822 1.1 dante
823 1.1 dante s = splbio();
824 1.1 dante
825 1.1 dante /*
826 1.1 dante * If it has been through before, then a previous abort has failed,
827 1.1 dante * don't try abort again, reset the bus instead.
828 1.1 dante */
829 1.1 dante if (ccb->flags & CCB_ABORT) {
830 1.1 dante /* abort timed out */
831 1.1 dante printf(" AGAIN. Resetting Bus\n");
832 1.1 dante /* Lets try resetting the bus! */
833 1.1 dante AdvResetSCSIBus(sc);
834 1.1 dante ccb->timeout = ADW_ABORT_TIMEOUT;
835 1.1 dante adw_queue_ccb(sc, ccb);
836 1.1 dante } else {
837 1.1 dante /* abort the operation that has timed out */
838 1.1 dante printf("\n");
839 1.1 dante ADW_ABORT_CCB(sc, ccb);
840 1.1 dante xs->error = XS_TIMEOUT;
841 1.1 dante ccb->timeout = ADW_ABORT_TIMEOUT;
842 1.1 dante ccb->flags |= CCB_ABORT;
843 1.1 dante adw_queue_ccb(sc, ccb);
844 1.1 dante }
845 1.1 dante
846 1.1 dante splx(s);
847 1.1 dante }
848 1.1 dante
849 1.1 dante
850 1.1 dante static void
851 1.1 dante adw_watchdog(arg)
852 1.1 dante void *arg;
853 1.1 dante {
854 1.1 dante ADW_CCB *ccb = arg;
855 1.1 dante struct scsipi_xfer *xs = ccb->xs;
856 1.1 dante struct scsipi_link *sc_link = xs->sc_link;
857 1.1 dante ADW_SOFTC *sc = sc_link->adapter_softc;
858 1.1 dante int s;
859 1.1 dante
860 1.1 dante s = splbio();
861 1.1 dante
862 1.1 dante ccb->flags &= ~CCB_WATCHDOG;
863 1.1 dante adw_start_ccbs(sc);
864 1.1 dante
865 1.1 dante splx(s);
866 1.1 dante }
867 1.1 dante
868 1.1 dante
869 1.1 dante /******************************************************************************/
870 1.7 dante /* WIDE boards Interrupt callbacks */
871 1.1 dante /******************************************************************************/
872 1.1 dante
873 1.1 dante
874 1.1 dante /*
875 1.1 dante * adw_wide_isr_callback() - Second Level Interrupt Handler called by AdvISR()
876 1.1 dante *
877 1.1 dante * Interrupt callback function for the Wide SCSI Adv Library.
878 1.1 dante */
879 1.1 dante static void
880 1.1 dante adw_wide_isr_callback(sc, scsiq)
881 1.1 dante ADW_SOFTC *sc;
882 1.1 dante ADW_SCSI_REQ_Q *scsiq;
883 1.1 dante {
884 1.2 dante bus_dma_tag_t dmat = sc->sc_dmat;
885 1.7 dante ADW_CCB *ccb;
886 1.7 dante struct scsipi_xfer *xs;
887 1.1 dante struct scsipi_sense_data *s1, *s2;
888 1.2 dante //int underrun = ASC_FALSE;
889 1.1 dante
890 1.7 dante
891 1.7 dante ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
892 1.7 dante xs = ccb->xs;
893 1.1 dante
894 1.1 dante untimeout(adw_timeout, ccb);
895 1.1 dante
896 1.1 dante /*
897 1.1 dante * If we were a data transfer, unload the map that described
898 1.1 dante * the data buffer.
899 1.1 dante */
900 1.1 dante if (xs->datalen) {
901 1.1 dante bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
902 1.1 dante ccb->dmamap_xfer->dm_mapsize,
903 1.1 dante (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
904 1.1 dante BUS_DMASYNC_POSTWRITE);
905 1.1 dante bus_dmamap_unload(dmat, ccb->dmamap_xfer);
906 1.1 dante }
907 1.1 dante if ((ccb->flags & CCB_ALLOC) == 0) {
908 1.1 dante printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
909 1.1 dante Debugger();
910 1.1 dante return;
911 1.1 dante }
912 1.1 dante /*
913 1.1 dante * Check for an underrun condition.
914 1.1 dante */
915 1.2 dante /*
916 1.2 dante * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) {
917 1.2 dante * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n",
918 1.2 dante * scsiqp->data_cnt); underrun = ASC_TRUE; }
919 1.2 dante */
920 1.1 dante /*
921 1.1 dante * 'done_status' contains the command's ending status.
922 1.1 dante */
923 1.1 dante switch (scsiq->done_status) {
924 1.1 dante case QD_NO_ERROR:
925 1.1 dante switch (scsiq->host_status) {
926 1.1 dante case QHSTA_NO_ERROR:
927 1.1 dante xs->error = XS_NOERROR;
928 1.1 dante xs->resid = 0;
929 1.1 dante break;
930 1.1 dante default:
931 1.1 dante /* QHSTA error occurred. */
932 1.1 dante xs->error = XS_DRIVER_STUFFUP;
933 1.1 dante break;
934 1.1 dante }
935 1.1 dante /*
936 1.1 dante * If there was an underrun without any other error,
937 1.1 dante * set DID_ERROR to indicate the underrun error.
938 1.1 dante *
939 1.1 dante * Note: There is no way yet to indicate the number
940 1.1 dante * of underrun bytes.
941 1.1 dante */
942 1.2 dante /*
943 1.2 dante * if (xs->error == XS_NOERROR && underrun == ASC_TRUE) {
944 1.2 dante * scp->result = HOST_BYTE(DID_UNDERRUN); }
945 1.2 dante */ break;
946 1.1 dante
947 1.1 dante case QD_WITH_ERROR:
948 1.1 dante switch (scsiq->host_status) {
949 1.1 dante case QHSTA_NO_ERROR:
950 1.1 dante if (scsiq->scsi_status == SS_CHK_CONDITION) {
951 1.1 dante s1 = &ccb->scsi_sense;
952 1.1 dante s2 = &xs->sense.scsi_sense;
953 1.1 dante *s2 = *s1;
954 1.1 dante xs->error = XS_SENSE;
955 1.1 dante } else {
956 1.1 dante xs->error = XS_DRIVER_STUFFUP;
957 1.1 dante }
958 1.1 dante break;
959 1.1 dante
960 1.1 dante default:
961 1.1 dante /* Some other QHSTA error occurred. */
962 1.1 dante xs->error = XS_DRIVER_STUFFUP;
963 1.1 dante break;
964 1.1 dante }
965 1.1 dante break;
966 1.1 dante
967 1.1 dante case QD_ABORTED_BY_HOST:
968 1.1 dante default:
969 1.1 dante xs->error = XS_DRIVER_STUFFUP;
970 1.1 dante break;
971 1.1 dante }
972 1.1 dante
973 1.1 dante
974 1.1 dante adw_free_ccb(sc, ccb);
975 1.1 dante xs->flags |= ITSDONE;
976 1.1 dante scsipi_done(xs);
977 1.1 dante }
978