adw.c revision 1.23
1 /* $NetBSD: adw.c,v 1.23 2000/05/27 18:24:50 dante Exp $ */ 2 3 /* 4 * Generic driver for the Advanced Systems Inc. SCSI controllers 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/buf.h> 50 #include <sys/proc.h> 51 #include <sys/user.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <vm/vm.h> 57 #include <vm/vm_param.h> 58 #include <vm/pmap.h> 59 60 #include <dev/scsipi/scsi_all.h> 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsiconf.h> 63 64 #include <dev/ic/adwlib.h> 65 #include <dev/ic/adwmcode.h> 66 #include <dev/ic/adw.h> 67 68 #ifndef DDB 69 #define Debugger() panic("should call debugger here (adw.c)") 70 #endif /* ! DDB */ 71 72 /******************************************************************************/ 73 74 75 static int adw_alloc_controls __P((ADW_SOFTC *)); 76 static int adw_alloc_carriers __P((ADW_SOFTC *)); 77 static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int)); 78 static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *)); 79 static void adw_reset_ccb __P((ADW_CCB *)); 80 static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *)); 81 static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int)); 82 static int adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *, int)); 83 84 static int adw_scsi_cmd __P((struct scsipi_xfer *)); 85 static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *, int)); 86 static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *)); 87 static void adwminphys __P((struct buf *)); 88 static void adw_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 89 static void adw_async_callback __P((ADW_SOFTC *, u_int8_t)); 90 91 static void adw_print_info __P((ADW_SOFTC *, int)); 92 93 static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int)); 94 static void adw_timeout __P((void *)); 95 static void adw_reset_bus __P((ADW_SOFTC *)); 96 97 98 /******************************************************************************/ 99 100 101 /* the below structure is so we have a default dev struct for our link struct */ 102 struct scsipi_device adw_dev = 103 { 104 NULL, /* Use default error handler */ 105 NULL, /* have a queue, served by this */ 106 NULL, /* have no async handler */ 107 NULL, /* Use default 'done' routine */ 108 }; 109 110 111 /******************************************************************************/ 112 /* DMA Mapping for Control Blocks */ 113 /******************************************************************************/ 114 115 116 static int 117 adw_alloc_controls(sc) 118 ADW_SOFTC *sc; 119 { 120 bus_dma_segment_t seg; 121 int error, rseg; 122 123 /* 124 * Allocate the control structure. 125 */ 126 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control), 127 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 128 printf("%s: unable to allocate control structures," 129 " error = %d\n", sc->sc_dev.dv_xname, error); 130 return (error); 131 } 132 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 133 sizeof(struct adw_control), (caddr_t *) & sc->sc_control, 134 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 135 printf("%s: unable to map control structures, error = %d\n", 136 sc->sc_dev.dv_xname, error); 137 return (error); 138 } 139 140 /* 141 * Create and load the DMA map used for the control blocks. 142 */ 143 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control), 144 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT, 145 &sc->sc_dmamap_control)) != 0) { 146 printf("%s: unable to create control DMA map, error = %d\n", 147 sc->sc_dev.dv_xname, error); 148 return (error); 149 } 150 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control, 151 sc->sc_control, sizeof(struct adw_control), NULL, 152 BUS_DMA_NOWAIT)) != 0) { 153 printf("%s: unable to load control DMA map, error = %d\n", 154 sc->sc_dev.dv_xname, error); 155 return (error); 156 } 157 158 return (0); 159 } 160 161 162 static int 163 adw_alloc_carriers(sc) 164 ADW_SOFTC *sc; 165 { 166 bus_dma_segment_t seg; 167 int error, rseg; 168 169 /* 170 * Allocate the control structure. 171 */ 172 sc->sc_control->carriers = malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 173 M_DEVBUF, M_WAITOK); 174 if(!sc->sc_control->carriers) { 175 printf("%s: malloc() failed in allocating carrier structures\n", 176 sc->sc_dev.dv_xname); 177 return (ENOMEM); 178 } 179 180 if ((error = bus_dmamem_alloc(sc->sc_dmat, 181 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 182 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 183 printf("%s: unable to allocate carrier structures," 184 " error = %d\n", sc->sc_dev.dv_xname, error); 185 return (error); 186 } 187 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 188 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 189 (caddr_t *) &sc->sc_control->carriers, 190 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 191 printf("%s: unable to map carrier structures," 192 " error = %d\n", sc->sc_dev.dv_xname, error); 193 return (error); 194 } 195 196 /* 197 * Create and load the DMA map used for the control blocks. 198 */ 199 if ((error = bus_dmamap_create(sc->sc_dmat, 200 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, 201 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, 202 &sc->sc_dmamap_carrier)) != 0) { 203 printf("%s: unable to create carriers DMA map," 204 " error = %d\n", sc->sc_dev.dv_xname, error); 205 return (error); 206 } 207 if ((error = bus_dmamap_load(sc->sc_dmat, 208 sc->sc_dmamap_carrier, sc->sc_control->carriers, 209 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, 210 BUS_DMA_NOWAIT)) != 0) { 211 printf("%s: unable to load carriers DMA map," 212 " error = %d\n", sc->sc_dev.dv_xname, error); 213 return (error); 214 } 215 216 return (0); 217 } 218 219 220 /******************************************************************************/ 221 /* Control Blocks routines */ 222 /******************************************************************************/ 223 224 225 /* 226 * Create a set of ccbs and add them to the free list. Called once 227 * by adw_init(). We return the number of CCBs successfully created. 228 */ 229 static int 230 adw_create_ccbs(sc, ccbstore, count) 231 ADW_SOFTC *sc; 232 ADW_CCB *ccbstore; 233 int count; 234 { 235 ADW_CCB *ccb; 236 int i, error; 237 238 for (i = 0; i < count; i++) { 239 ccb = &ccbstore[i]; 240 if ((error = adw_init_ccb(sc, ccb)) != 0) { 241 printf("%s: unable to initialize ccb, error = %d\n", 242 sc->sc_dev.dv_xname, error); 243 return (i); 244 } 245 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain); 246 } 247 248 return (i); 249 } 250 251 252 /* 253 * A ccb is put onto the free list. 254 */ 255 static void 256 adw_free_ccb(sc, ccb) 257 ADW_SOFTC *sc; 258 ADW_CCB *ccb; 259 { 260 int s; 261 262 s = splbio(); 263 264 adw_reset_ccb(ccb); 265 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain); 266 267 /* 268 * If there were none, wake anybody waiting for one to come free, 269 * starting with queued entries. 270 */ 271 if (ccb->chain.tqe_next == 0) 272 wakeup(&sc->sc_free_ccb); 273 274 splx(s); 275 } 276 277 278 static void 279 adw_reset_ccb(ccb) 280 ADW_CCB *ccb; 281 { 282 283 ccb->flags = 0; 284 } 285 286 287 static int 288 adw_init_ccb(sc, ccb) 289 ADW_SOFTC *sc; 290 ADW_CCB *ccb; 291 { 292 int hashnum, error; 293 294 /* 295 * Create the DMA map for this CCB. 296 */ 297 error = bus_dmamap_create(sc->sc_dmat, 298 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 299 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 300 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer); 301 if (error) { 302 printf("%s: unable to create CCB DMA map, error = %d\n", 303 sc->sc_dev.dv_xname, error); 304 return (error); 305 } 306 307 /* 308 * put in the phystokv hash table 309 * Never gets taken out. 310 */ 311 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr + 312 ADW_CCB_OFF(ccb); 313 hashnum = CCB_HASH(ccb->hashkey); 314 ccb->nexthash = sc->sc_ccbhash[hashnum]; 315 sc->sc_ccbhash[hashnum] = ccb; 316 adw_reset_ccb(ccb); 317 return (0); 318 } 319 320 321 /* 322 * Get a free ccb 323 * 324 * If there are none, see if we can allocate a new one 325 */ 326 static ADW_CCB * 327 adw_get_ccb(sc, flags) 328 ADW_SOFTC *sc; 329 int flags; 330 { 331 ADW_CCB *ccb = 0; 332 int s; 333 334 s = splbio(); 335 336 /* 337 * If we can and have to, sleep waiting for one to come free 338 * but only if we can't allocate a new one. 339 */ 340 for (;;) { 341 ccb = sc->sc_free_ccb.tqh_first; 342 if (ccb) { 343 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain); 344 break; 345 } 346 if ((flags & XS_CTL_NOSLEEP) != 0) 347 goto out; 348 349 tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0); 350 } 351 352 ccb->flags |= CCB_ALLOC; 353 354 out: 355 splx(s); 356 return (ccb); 357 } 358 359 360 /* 361 * Given a physical address, find the ccb that it corresponds to. 362 */ 363 ADW_CCB * 364 adw_ccb_phys_kv(sc, ccb_phys) 365 ADW_SOFTC *sc; 366 u_int32_t ccb_phys; 367 { 368 int hashnum = CCB_HASH(ccb_phys); 369 ADW_CCB *ccb = sc->sc_ccbhash[hashnum]; 370 371 while (ccb) { 372 if (ccb->hashkey == ccb_phys) 373 break; 374 ccb = ccb->nexthash; 375 } 376 return (ccb); 377 } 378 379 380 /* 381 * Queue a CCB to be sent to the controller, and send it if possible. 382 */ 383 static int 384 adw_queue_ccb(sc, ccb, retry) 385 ADW_SOFTC *sc; 386 ADW_CCB *ccb; 387 int retry; 388 { 389 int errcode = ADW_SUCCESS; 390 391 if(!retry) { 392 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); 393 } 394 395 while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) { 396 397 errcode = AdwExeScsiQueue(sc, &ccb->scsiq); 398 switch(errcode) { 399 case ADW_SUCCESS: 400 break; 401 402 case ADW_BUSY: 403 printf("ADW_BUSY\n"); 404 return(ADW_BUSY); 405 406 case ADW_ERROR: 407 printf("ADW_ERROR\n"); 408 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 409 return(ADW_ERROR); 410 } 411 412 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 413 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); 414 415 if ((ccb->xs->xs_control & XS_CTL_POLL) == 0) 416 callout_reset(&ccb->xs->xs_callout, 417 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 418 } 419 420 return(errcode); 421 } 422 423 424 /******************************************************************************/ 425 /* SCSI layer interfacing routines */ 426 /******************************************************************************/ 427 428 429 int 430 adw_init(sc) 431 ADW_SOFTC *sc; 432 { 433 u_int16_t warn_code; 434 435 436 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | 437 ADW_LIB_VERSION_MINOR; 438 sc->cfg.chip_version = 439 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); 440 441 /* 442 * Reset the chip to start and allow register writes. 443 */ 444 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { 445 panic("adw_init: adw_find_signature failed"); 446 } else { 447 AdwResetChip(sc->sc_iot, sc->sc_ioh); 448 449 warn_code = AdwInitFromEEPROM(sc); 450 451 if (warn_code & ADW_WARN_EEPROM_CHKSUM) 452 printf("%s: Bad checksum found. " 453 "Setting default values\n", 454 sc->sc_dev.dv_xname); 455 if (warn_code & ADW_WARN_EEPROM_TERMINATION) 456 printf("%s: Bad bus termination setting." 457 "Using automatic termination.\n", 458 sc->sc_dev.dv_xname); 459 } 460 461 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; 462 sc->async_callback = (ADW_CALLBACK) adw_async_callback; 463 464 return 0; 465 } 466 467 468 void 469 adw_attach(sc) 470 ADW_SOFTC *sc; 471 { 472 int i, error; 473 474 475 TAILQ_INIT(&sc->sc_free_ccb); 476 TAILQ_INIT(&sc->sc_waiting_ccb); 477 TAILQ_INIT(&sc->sc_pending_ccb); 478 TAILQ_INIT(&sc->sc_queue); 479 480 481 /* 482 * Allocate the Control Blocks. 483 */ 484 error = adw_alloc_controls(sc); 485 if (error) 486 return; /* (error) */ ; 487 488 bzero(sc->sc_control, sizeof(struct adw_control)); 489 490 /* 491 * Create and initialize the Control Blocks. 492 */ 493 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB); 494 if (i == 0) { 495 printf("%s: unable to create Control Blocks\n", 496 sc->sc_dev.dv_xname); 497 return; /* (ENOMEM) */ ; 498 } else if (i != ADW_MAX_CCB) { 499 printf("%s: WARNING: only %d of %d Control Blocks" 500 " created\n", 501 sc->sc_dev.dv_xname, i, ADW_MAX_CCB); 502 } 503 504 /* 505 * Create and initialize the Carriers. 506 */ 507 error = adw_alloc_carriers(sc); 508 if (error) 509 return; /* (error) */ ; 510 511 /* 512 * Zero's the freeze_device status 513 */ 514 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 515 516 /* 517 * Initialize the adapter 518 */ 519 switch (AdwInitDriver(sc)) { 520 case ADW_IERR_BIST_PRE_TEST: 521 panic("%s: BIST pre-test error", 522 sc->sc_dev.dv_xname); 523 break; 524 525 case ADW_IERR_BIST_RAM_TEST: 526 panic("%s: BIST RAM test error", 527 sc->sc_dev.dv_xname); 528 break; 529 530 case ADW_IERR_MCODE_CHKSUM: 531 panic("%s: Microcode checksum error", 532 sc->sc_dev.dv_xname); 533 break; 534 535 case ADW_IERR_ILLEGAL_CONNECTION: 536 panic("%s: All three connectors are in use", 537 sc->sc_dev.dv_xname); 538 break; 539 540 case ADW_IERR_REVERSED_CABLE: 541 panic("%s: Cable is reversed", 542 sc->sc_dev.dv_xname); 543 break; 544 545 case ADW_IERR_HVD_DEVICE: 546 panic("%s: HVD attached to LVD connector", 547 sc->sc_dev.dv_xname); 548 break; 549 550 case ADW_IERR_SINGLE_END_DEVICE: 551 panic("%s: single-ended device is attached to" 552 " one of the connectors", 553 sc->sc_dev.dv_xname); 554 break; 555 556 case ADW_IERR_NO_CARRIER: 557 panic("%s: unable to create Carriers", 558 sc->sc_dev.dv_xname); 559 break; 560 561 case ADW_WARN_BUSRESET_ERROR: 562 printf("%s: WARNING: Bus Reset Error\n", 563 sc->sc_dev.dv_xname); 564 break; 565 } 566 567 /* 568 * Fill in the adapter. 569 */ 570 sc->sc_adapter.scsipi_cmd = adw_scsi_cmd; 571 sc->sc_adapter.scsipi_minphys = adwminphys; 572 573 /* 574 * fill in the prototype scsipi_link. 575 */ 576 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 577 sc->sc_link.adapter_softc = sc; 578 sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id; 579 sc->sc_link.adapter = &sc->sc_adapter; 580 sc->sc_link.device = &adw_dev; 581 sc->sc_link.openings = 4; 582 sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID; 583 sc->sc_link.scsipi_scsi.max_lun = 7; 584 sc->sc_link.type = BUS_SCSI; 585 586 587 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 588 } 589 590 591 static void 592 adwminphys(bp) 593 struct buf *bp; 594 { 595 596 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE)) 597 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE); 598 minphys(bp); 599 } 600 601 602 /* 603 * start a scsi operation given the command and the data address. 604 * Also needs the unit, target and lu. 605 */ 606 static int 607 adw_scsi_cmd(xs) 608 struct scsipi_xfer *xs; 609 { 610 struct scsipi_link *sc_link = xs->sc_link; 611 ADW_SOFTC *sc = sc_link->adapter_softc; 612 ADW_CCB *ccb; 613 int s, fromqueue = 1, dontqueue = 0, nowait = 0, retry = 0; 614 int flags; 615 616 s = splbio(); /* protect the queue */ 617 618 /* 619 * If we're running the queue from adw_done(), we've been 620 * called with the first queue entry as our argument. 621 */ 622 if (xs == TAILQ_FIRST(&sc->sc_queue)) { 623 if(sc->sc_freeze_dev[xs->sc_link->scsipi_scsi.target]) { 624 splx(s); 625 return (TRY_AGAIN_LATER); 626 } 627 628 TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q); 629 fromqueue = 1; 630 nowait = 1; 631 } else { 632 if(sc->sc_freeze_dev[xs->sc_link->scsipi_scsi.target]) { 633 splx(s); 634 xs->error = XS_DRIVER_STUFFUP; 635 return (TRY_AGAIN_LATER); 636 } 637 638 /* Polled requests can't be queued for later. */ 639 dontqueue = xs->xs_control & XS_CTL_POLL; 640 641 /* 642 * If there are jobs in the queue, run them first. 643 */ 644 if (TAILQ_FIRST(&sc->sc_queue) != NULL) { 645 /* 646 * If we can't queue, we have to abort, since 647 * we have to preserve order. 648 */ 649 if (dontqueue) { 650 splx(s); 651 xs->error = XS_DRIVER_STUFFUP; 652 return (TRY_AGAIN_LATER); 653 } 654 /* 655 * Swap with the first queue entry. 656 */ 657 TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q); 658 xs = TAILQ_FIRST(&sc->sc_queue); 659 TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q); 660 fromqueue = 1; 661 } 662 } 663 664 665 /* 666 * get a ccb to use. If the transfer 667 * is from a buf (possibly from interrupt time) 668 * then we can't allow it to sleep 669 */ 670 671 flags = xs->xs_control; 672 if (nowait) 673 flags |= XS_CTL_NOSLEEP; 674 if ((ccb = adw_get_ccb(sc, flags)) == NULL) { 675 /* 676 * If we can't queue, we lose. 677 */ 678 if (dontqueue) { 679 splx(s); 680 xs->error = XS_DRIVER_STUFFUP; 681 return (TRY_AGAIN_LATER); 682 } 683 /* 684 * Stuff ourselves into the queue, in front 685 * if we came off in the first place. 686 */ 687 if (fromqueue) 688 TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q); 689 else 690 TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q); 691 splx(s); 692 return (SUCCESSFULLY_QUEUED); 693 } 694 splx(s); /* done playing with the queue */ 695 696 ccb->xs = xs; 697 ccb->timeout = xs->timeout; 698 699 if (adw_build_req(xs, ccb, flags)) { 700 retryagain: 701 s = splbio(); 702 retry = adw_queue_ccb(sc, ccb, retry); 703 splx(s); 704 705 switch(retry) { 706 case ADW_BUSY: 707 goto retryagain; 708 709 case ADW_ERROR: 710 xs->error = XS_DRIVER_STUFFUP; 711 return (COMPLETE); 712 } 713 714 /* 715 * Usually return SUCCESSFULLY QUEUED 716 */ 717 if ((xs->xs_control & XS_CTL_POLL) == 0) 718 return (SUCCESSFULLY_QUEUED); 719 720 /* 721 * If we can't use interrupts, poll on completion 722 */ 723 if (adw_poll(sc, xs, ccb->timeout)) { 724 adw_timeout(ccb); 725 if (adw_poll(sc, xs, ccb->timeout)) 726 adw_timeout(ccb); 727 } 728 } 729 return (COMPLETE); 730 } 731 732 733 /* 734 * Build a request structure for the Wide Boards. 735 */ 736 static int 737 adw_build_req(xs, ccb, flags) 738 struct scsipi_xfer *xs; 739 ADW_CCB *ccb; 740 int flags; 741 { 742 struct scsipi_link *sc_link = xs->sc_link; 743 ADW_SOFTC *sc = sc_link->adapter_softc; 744 bus_dma_tag_t dmat = sc->sc_dmat; 745 ADW_SCSI_REQ_Q *scsiqp; 746 int error; 747 748 scsiqp = &ccb->scsiq; 749 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); 750 751 /* 752 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the 753 * physical CCB structure. 754 */ 755 scsiqp->ccb_ptr = ccb->hashkey; 756 757 /* 758 * Build the ADW_SCSI_REQ_Q request. 759 */ 760 761 /* 762 * Set CDB length and copy it to the request structure. 763 * For wide boards a CDB length maximum of 16 bytes 764 * is supported. 765 */ 766 bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)? 767 xs->cmdlen : 12 ); 768 if(xs->cmdlen > 12) 769 bcopy(&(xs->cmd[12]), &scsiqp->cdb16, xs->cmdlen - 12); 770 771 scsiqp->target_id = sc_link->scsipi_scsi.target; 772 scsiqp->target_lun = sc_link->scsipi_scsi.lun; 773 774 scsiqp->vsense_addr = &ccb->scsi_sense; 775 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 776 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); 777 scsiqp->sense_len = sizeof(struct scsipi_sense_data); 778 779 /* 780 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. 781 */ 782 if (xs->datalen) { 783 /* 784 * Map the DMA transfer. 785 */ 786 #ifdef TFS 787 if (xs->xs_control & SCSI_DATA_UIO) { 788 error = bus_dmamap_load_uio(dmat, 789 ccb->dmamap_xfer, (struct uio *) xs->data, 790 (flags & XS_CTL_NOSLEEP) ? 791 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 792 } else 793 #endif /* TFS */ 794 { 795 error = bus_dmamap_load(dmat, 796 ccb->dmamap_xfer, xs->data, xs->datalen, NULL, 797 (flags & XS_CTL_NOSLEEP) ? 798 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 799 } 800 801 if (error) { 802 if (error == EFBIG) { 803 printf("%s: adw_scsi_cmd, more than %d dma" 804 " segments\n", 805 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST); 806 } else { 807 printf("%s: adw_scsi_cmd, error %d loading" 808 " dma map\n", 809 sc->sc_dev.dv_xname, error); 810 } 811 812 xs->error = XS_DRIVER_STUFFUP; 813 adw_free_ccb(sc, ccb); 814 return (0); 815 } 816 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, 817 ccb->dmamap_xfer->dm_mapsize, 818 (xs->xs_control & XS_CTL_DATA_IN) ? 819 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 820 821 /* 822 * Build scatter-gather list. 823 */ 824 scsiqp->data_cnt = xs->datalen; 825 scsiqp->vdata_addr = xs->data; 826 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; 827 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); 828 adw_build_sglist(ccb, scsiqp, ccb->sg_block); 829 } else { 830 /* 831 * No data xfer, use non S/G values. 832 */ 833 scsiqp->data_cnt = 0; 834 scsiqp->vdata_addr = 0; 835 scsiqp->data_addr = 0; 836 } 837 838 return (1); 839 } 840 841 842 /* 843 * Build scatter-gather list for Wide Boards. 844 */ 845 static void 846 adw_build_sglist(ccb, scsiqp, sg_block) 847 ADW_CCB *ccb; 848 ADW_SCSI_REQ_Q *scsiqp; 849 ADW_SG_BLOCK *sg_block; 850 { 851 u_long sg_block_next_addr; /* block and its next */ 852 u_int32_t sg_block_physical_addr; 853 int i; /* how many SG entries */ 854 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; 855 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; 856 857 858 sg_block_next_addr = (u_long) sg_block; /* allow math operation */ 859 sg_block_physical_addr = ccb->hashkey + 860 offsetof(struct adw_ccb, sg_block[0]); 861 scsiqp->sg_real_addr = sg_block_physical_addr; 862 863 /* 864 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list) 865 * then split the request into multiple sg-list blocks. 866 */ 867 868 do { 869 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 870 sg_block->sg_list[i].sg_addr = sg_list->ds_addr; 871 sg_block->sg_list[i].sg_count = sg_list->ds_len; 872 873 if (--sg_elem_cnt == 0) { 874 /* last entry, get out */ 875 sg_block->sg_cnt = i + i; 876 sg_block->sg_ptr = NULL; /* next link = NULL */ 877 return; 878 } 879 sg_list++; 880 } 881 sg_block_next_addr += sizeof(ADW_SG_BLOCK); 882 sg_block_physical_addr += sizeof(ADW_SG_BLOCK); 883 884 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 885 sg_block->sg_ptr = sg_block_physical_addr; 886 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ 887 } while (1); 888 } 889 890 891 /******************************************************************************/ 892 /* Interrupts and TimeOut routines */ 893 /******************************************************************************/ 894 895 896 int 897 adw_intr(arg) 898 void *arg; 899 { 900 ADW_SOFTC *sc = arg; 901 struct scsipi_xfer *xs; 902 903 904 if(AdwISR(sc) != ADW_FALSE) { 905 /* 906 * If there are queue entries in the software queue, try to 907 * run the first one. We should be more or less guaranteed 908 * to succeed, since we just freed a CCB. 909 * 910 * NOTE: adw_scsi_cmd() relies on our calling it with 911 * the first entry in the queue. 912 */ 913 if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL) 914 (void) adw_scsi_cmd(xs); 915 916 return (1); 917 } 918 919 return (0); 920 } 921 922 923 /* 924 * Poll a particular unit, looking for a particular xs 925 */ 926 static int 927 adw_poll(sc, xs, count) 928 ADW_SOFTC *sc; 929 struct scsipi_xfer *xs; 930 int count; 931 { 932 933 /* timeouts are in msec, so we loop in 1000 usec cycles */ 934 while (count) { 935 adw_intr(sc); 936 if (xs->xs_status & XS_STS_DONE) 937 return (0); 938 delay(1000); /* only happens in boot so ok */ 939 count--; 940 } 941 return (1); 942 } 943 944 945 static void 946 adw_timeout(arg) 947 void *arg; 948 { 949 ADW_CCB *ccb = arg; 950 struct scsipi_xfer *xs = ccb->xs; 951 struct scsipi_link *sc_link = xs->sc_link; 952 ADW_SOFTC *sc = sc_link->adapter_softc; 953 int s; 954 955 scsi_print_addr(sc_link); 956 printf("timed out"); 957 958 s = splbio(); 959 960 if (ccb->flags & CCB_ABORTED) { 961 /* 962 * Abort Timed Out 963 * 964 * No more opportunities. Lets try resetting the bus and 965 * reinitialize the host adapter. 966 */ 967 callout_stop(&xs->xs_callout); 968 printf(" AGAIN. Resetting SCSI Bus\n"); 969 adw_reset_bus(sc); 970 splx(s); 971 return; 972 } else if (ccb->flags & CCB_ABORTING) { 973 /* 974 * Abort the operation that has timed out. 975 * 976 * Second opportunity. 977 */ 978 printf("\n"); 979 xs->error = XS_TIMEOUT; 980 ccb->flags |= CCB_ABORTED; 981 #if 0 982 /* 983 * - XXX - 3.3a microcode is BROKEN!!! 984 * 985 * We cannot abort a CCB, so we can only hope the command 986 * get completed before the next timeout, otherwise a 987 * Bus Reset will arrive inexorably. 988 */ 989 /* 990 * ADW_ABORT_CCB() makes the board to generate an interrupt 991 * 992 * - XXX - The above assertion MUST be verified (and this 993 * code changed as well [callout_*()]), when the 994 * ADW_ABORT_CCB will be working again 995 */ 996 ADW_ABORT_CCB(sc, ccb); 997 #endif 998 /* 999 * waiting for multishot callout_reset() let's restart it 1000 * by hand so the next time a timeout event will occour 1001 * we will reset the bus. 1002 */ 1003 callout_reset(&xs->xs_callout, 1004 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 1005 } else { 1006 /* 1007 * Abort the operation that has timed out. 1008 * 1009 * First opportunity. 1010 */ 1011 printf("\n"); 1012 xs->error = XS_TIMEOUT; 1013 ccb->flags |= CCB_ABORTING; 1014 #if 0 1015 /* 1016 * - XXX - 3.3a microcode is BROKEN!!! 1017 * 1018 * We cannot abort a CCB, so we can only hope the command 1019 * get completed before the next 2 timeout, otherwise a 1020 * Bus Reset will arrive inexorably. 1021 */ 1022 /* 1023 * ADW_ABORT_CCB() makes the board to generate an interrupt 1024 * 1025 * - XXX - The above assertion MUST be verified (and this 1026 * code changed as well [callout_*()]), when the 1027 * ADW_ABORT_CCB will be working again 1028 */ 1029 ADW_ABORT_CCB(sc, ccb); 1030 #endif 1031 /* 1032 * waiting for multishot callout_reset() let's restart it 1033 * by hand so to give a second opportunity to the command 1034 * which timed-out. 1035 */ 1036 callout_reset(&xs->xs_callout, 1037 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 1038 } 1039 1040 splx(s); 1041 } 1042 1043 1044 static void 1045 adw_reset_bus(sc) 1046 ADW_SOFTC *sc; 1047 { 1048 ADW_CCB *ccb; 1049 int s; 1050 1051 s = splbio(); 1052 AdwResetSCSIBus(sc); 1053 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, 1054 adw_pending_ccb)) != NULL) { 1055 callout_stop(&ccb->xs->xs_callout); 1056 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1057 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); 1058 } 1059 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); 1060 splx(s); 1061 } 1062 1063 1064 /******************************************************************************/ 1065 /* Host Adapter and Peripherals Information Routines */ 1066 /******************************************************************************/ 1067 1068 1069 static void 1070 adw_print_info(sc, tid) 1071 ADW_SOFTC *sc; 1072 int tid; 1073 { 1074 bus_space_tag_t iot = sc->sc_iot; 1075 bus_space_handle_t ioh = sc->sc_ioh; 1076 u_int16_t wdtr_able, wdtr_done, wdtr; 1077 u_int16_t sdtr_able, sdtr_done, sdtr, period; 1078 static int wdtr_reneg = 0, sdtr_reneg = 0; 1079 1080 if (tid == 0){ 1081 wdtr_reneg = sdtr_reneg = 0; 1082 } 1083 1084 printf("%s: target %d ", sc->sc_dev.dv_xname, tid); 1085 1086 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, wdtr_able); 1087 if(wdtr_able & ADW_TID_TO_TIDMASK(tid)) { 1088 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, wdtr_done); 1089 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + 1090 (2 * tid), wdtr); 1091 printf("using %d-bits wide, ", (wdtr & 0x8000)? 16 : 8); 1092 if((wdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) 1093 wdtr_reneg = 1; 1094 } else { 1095 printf("wide transfers disabled, "); 1096 } 1097 1098 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1099 if(sdtr_able & ADW_TID_TO_TIDMASK(tid)) { 1100 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, sdtr_done); 1101 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + 1102 (2 * tid), sdtr); 1103 sdtr &= ~0x8000; 1104 if((sdtr & 0x1F) != 0) { 1105 if((sdtr & 0x1F00) == 0x1100){ 1106 printf("80.0 MHz"); 1107 } else if((sdtr & 0x1F00) == 0x1000){ 1108 printf("40.0 MHz"); 1109 } else { 1110 /* <= 20.0 MHz */ 1111 period = (((sdtr >> 8) * 25) + 50)/4; 1112 if(period == 0) { 1113 /* Should never happen. */ 1114 printf("? MHz"); 1115 } else { 1116 printf("%d.%d MHz", 250/period, 1117 ADW_TENTHS(250, period)); 1118 } 1119 } 1120 printf(" synchronous transfers\n"); 1121 } else { 1122 printf("asynchronous transfers\n"); 1123 } 1124 if((sdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) 1125 sdtr_reneg = 1; 1126 } else { 1127 printf("synchronous transfers disabled\n"); 1128 } 1129 1130 if(wdtr_reneg || sdtr_reneg) { 1131 printf("%s: target %d %s", sc->sc_dev.dv_xname, tid, 1132 (wdtr_reneg)? ((sdtr_reneg)? "wide/sync" : "wide") : 1133 ((sdtr_reneg)? "sync" : "") ); 1134 printf(" renegotiation pending before next command.\n"); 1135 } 1136 } 1137 1138 1139 /******************************************************************************/ 1140 /* WIDE boards Interrupt callbacks */ 1141 /******************************************************************************/ 1142 1143 1144 /* 1145 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() 1146 * 1147 * Interrupt callback function for the Wide SCSI Adv Library. 1148 * 1149 * Notice: 1150 * Interrupts are disabled by the caller (AdwISR() function), and will be 1151 * enabled at the end of the caller. 1152 */ 1153 static void 1154 adw_isr_callback(sc, scsiq) 1155 ADW_SOFTC *sc; 1156 ADW_SCSI_REQ_Q *scsiq; 1157 { 1158 bus_dma_tag_t dmat = sc->sc_dmat; 1159 ADW_CCB *ccb; 1160 struct scsipi_xfer *xs; 1161 struct scsipi_sense_data *s1, *s2; 1162 1163 1164 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1165 1166 callout_stop(&ccb->xs->xs_callout); 1167 1168 xs = ccb->xs; 1169 1170 /* 1171 * If we were a data transfer, unload the map that described 1172 * the data buffer. 1173 */ 1174 if (xs->datalen) { 1175 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, 1176 ccb->dmamap_xfer->dm_mapsize, 1177 (xs->xs_control & XS_CTL_DATA_IN) ? 1178 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1179 bus_dmamap_unload(dmat, ccb->dmamap_xfer); 1180 } 1181 1182 if ((ccb->flags & CCB_ALLOC) == 0) { 1183 printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname); 1184 Debugger(); 1185 return; 1186 } 1187 1188 /* 1189 * 'done_status' contains the command's ending status. 1190 * 'host_status' conatins the host adapter status. 1191 * 'scsi_status' contains the scsi peripheral status. 1192 */ 1193 if ((scsiq->host_status == QHSTA_NO_ERROR) && 1194 ((scsiq->done_status == QD_NO_ERROR) || 1195 (scsiq->done_status == QD_WITH_ERROR))) { 1196 switch (scsiq->host_status) { 1197 case SCSI_STATUS_GOOD: 1198 if ((scsiq->cdb[0] == INQUIRY) && 1199 (scsiq->target_lun == 0)) { 1200 adw_print_info(sc, scsiq->target_id); 1201 } 1202 xs->error = XS_NOERROR; 1203 xs->resid = scsiq->data_cnt; 1204 sc->sc_freeze_dev[scsiq->target_id] = 0; 1205 break; 1206 1207 case SCSI_STATUS_CHECK_CONDITION: 1208 case SCSI_STATUS_CMD_TERMINATED: 1209 s1 = &ccb->scsi_sense; 1210 s2 = &xs->sense.scsi_sense; 1211 *s2 = *s1; 1212 xs->error = XS_SENSE; 1213 sc->sc_freeze_dev[scsiq->target_id] = 1; 1214 break; 1215 1216 default: 1217 xs->error = XS_BUSY; 1218 sc->sc_freeze_dev[scsiq->target_id] = 1; 1219 break; 1220 } 1221 } else if (scsiq->done_status == QD_ABORTED_BY_HOST) { 1222 xs->error = XS_DRIVER_STUFFUP; 1223 } else { 1224 switch (scsiq->host_status) { 1225 case QHSTA_M_SEL_TIMEOUT: 1226 xs->error = XS_SELTIMEOUT; 1227 break; 1228 1229 case QHSTA_M_SXFR_OFF_UFLW: 1230 case QHSTA_M_SXFR_OFF_OFLW: 1231 case QHSTA_M_DATA_OVER_RUN: 1232 printf("%s: Overrun/Overflow/Underflow condition\n", 1233 sc->sc_dev.dv_xname); 1234 xs->error = XS_DRIVER_STUFFUP; 1235 break; 1236 1237 case QHSTA_M_SXFR_DESELECTED: 1238 case QHSTA_M_UNEXPECTED_BUS_FREE: 1239 printf("%s: Unexpected BUS free\n",sc->sc_dev.dv_xname); 1240 xs->error = XS_DRIVER_STUFFUP; 1241 break; 1242 1243 case QHSTA_M_SCSI_BUS_RESET: 1244 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1245 printf("%s: BUS Reset\n", sc->sc_dev.dv_xname); 1246 xs->error = XS_DRIVER_STUFFUP; 1247 break; 1248 1249 case QHSTA_M_BUS_DEVICE_RESET: 1250 printf("%s: Device Reset\n", sc->sc_dev.dv_xname); 1251 xs->error = XS_DRIVER_STUFFUP; 1252 break; 1253 1254 case QHSTA_M_QUEUE_ABORTED: 1255 printf("%s: Queue Aborted\n", sc->sc_dev.dv_xname); 1256 xs->error = XS_DRIVER_STUFFUP; 1257 break; 1258 1259 case QHSTA_M_SXFR_SDMA_ERR: 1260 case QHSTA_M_SXFR_SXFR_PERR: 1261 case QHSTA_M_RDMA_PERR: 1262 /* 1263 * DMA Error. This should *NEVER* happen! 1264 * 1265 * Lets try resetting the bus and reinitialize 1266 * the host adapter. 1267 */ 1268 printf("%s: DMA Error. Reseting bus\n", 1269 sc->sc_dev.dv_xname); 1270 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1271 adw_reset_bus(sc); 1272 xs->error = XS_BUSY; 1273 goto done; 1274 1275 case QHSTA_M_WTM_TIMEOUT: 1276 case QHSTA_M_SXFR_WD_TMO: 1277 /* The SCSI bus hung in a phase */ 1278 printf("%s: Watch Dog timer expired. Reseting bus\n", 1279 sc->sc_dev.dv_xname); 1280 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1281 adw_reset_bus(sc); 1282 xs->error = XS_BUSY; 1283 goto done; 1284 1285 case QHSTA_M_SXFR_XFR_PH_ERR: 1286 printf("%s: Transfer Error\n", sc->sc_dev.dv_xname); 1287 xs->error = XS_DRIVER_STUFFUP; 1288 break; 1289 1290 case QHSTA_M_BAD_CMPL_STATUS_IN: 1291 /* No command complete after a status message */ 1292 printf("%s: Bad Completion Status\n", 1293 sc->sc_dev.dv_xname); 1294 xs->error = XS_DRIVER_STUFFUP; 1295 break; 1296 1297 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1298 printf("%s: Auto Sense Failed\n", sc->sc_dev.dv_xname); 1299 xs->error = XS_DRIVER_STUFFUP; 1300 break; 1301 1302 case QHSTA_M_INVALID_DEVICE: 1303 printf("%s: Invalid Device\n", sc->sc_dev.dv_xname); 1304 xs->error = XS_DRIVER_STUFFUP; 1305 break; 1306 1307 case QHSTA_M_NO_AUTO_REQ_SENSE: 1308 /* 1309 * User didn't request sense, but we got a 1310 * check condition. 1311 */ 1312 printf("%s: Unexpected Check Condition\n", 1313 sc->sc_dev.dv_xname); 1314 xs->error = XS_DRIVER_STUFFUP; 1315 break; 1316 1317 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1318 printf("%s: Unknown Error\n", sc->sc_dev.dv_xname); 1319 xs->error = XS_DRIVER_STUFFUP; 1320 break; 1321 1322 default: 1323 panic("%s: Unhandled Host Status Error %x", 1324 sc->sc_dev.dv_xname, scsiq->host_status); 1325 } 1326 } 1327 1328 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1329 done: adw_free_ccb(sc, ccb); 1330 xs->xs_status |= XS_STS_DONE; 1331 scsipi_done(xs); 1332 } 1333 1334 1335 /* 1336 * adw_async_callback() - Adv Library asynchronous event callback function. 1337 */ 1338 static void 1339 adw_async_callback(sc, code) 1340 ADW_SOFTC *sc; 1341 u_int8_t code; 1342 { 1343 switch (code) { 1344 case ADV_ASYNC_SCSI_BUS_RESET_DET: 1345 /* The firmware detected a SCSI Bus reset. */ 1346 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); 1347 break; 1348 1349 case ADV_ASYNC_RDMA_FAILURE: 1350 /* 1351 * Handle RDMA failure by resetting the SCSI Bus and 1352 * possibly the chip if it is unresponsive. 1353 */ 1354 printf("%s: RDMA failure. Resetting the SCSI Bus and" 1355 " the adapter\n", sc->sc_dev.dv_xname); 1356 AdwResetSCSIBus(sc); 1357 break; 1358 1359 case ADV_HOST_SCSI_BUS_RESET: 1360 /* Host generated SCSI bus reset occurred. */ 1361 printf("%s: Host generated SCSI bus reset occurred\n", 1362 sc->sc_dev.dv_xname); 1363 break; 1364 1365 case ADV_ASYNC_CARRIER_READY_FAILURE: 1366 /* Carrier Ready failure. */ 1367 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); 1368 break; 1369 1370 default: 1371 break; 1372 } 1373 } 1374
Indexes created Tue Sep 23 07:09:52 GMT 2025