adw.c revision 1.26
1 /* $NetBSD: adw.c,v 1.26 2000/11/14 18:21:00 thorpej Exp $ */ 2 3 /* 4 * Generic driver for the Advanced Systems Inc. SCSI controllers 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/buf.h> 50 #include <sys/proc.h> 51 #include <sys/user.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/ic/adwlib.h> 63 #include <dev/ic/adwmcode.h> 64 #include <dev/ic/adw.h> 65 66 #ifndef DDB 67 #define Debugger() panic("should call debugger here (adw.c)") 68 #endif /* ! DDB */ 69 70 /******************************************************************************/ 71 72 73 static int adw_alloc_controls __P((ADW_SOFTC *)); 74 static int adw_alloc_carriers __P((ADW_SOFTC *)); 75 static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int)); 76 static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *)); 77 static void adw_reset_ccb __P((ADW_CCB *)); 78 static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *)); 79 static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int)); 80 static int adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *, int)); 81 82 static int adw_scsi_cmd __P((struct scsipi_xfer *)); 83 static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *, int)); 84 static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *)); 85 static void adwminphys __P((struct buf *)); 86 static void adw_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 87 static void adw_async_callback __P((ADW_SOFTC *, u_int8_t)); 88 89 static void adw_print_info __P((ADW_SOFTC *, int)); 90 91 static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int)); 92 static void adw_timeout __P((void *)); 93 static void adw_reset_bus __P((ADW_SOFTC *)); 94 95 96 /******************************************************************************/ 97 98 99 /* the below structure is so we have a default dev struct for our link struct */ 100 struct scsipi_device adw_dev = 101 { 102 NULL, /* Use default error handler */ 103 NULL, /* have a queue, served by this */ 104 NULL, /* have no async handler */ 105 NULL, /* Use default 'done' routine */ 106 }; 107 108 109 /******************************************************************************/ 110 /* DMA Mapping for Control Blocks */ 111 /******************************************************************************/ 112 113 114 static int 115 adw_alloc_controls(sc) 116 ADW_SOFTC *sc; 117 { 118 bus_dma_segment_t seg; 119 int error, rseg; 120 121 /* 122 * Allocate the control structure. 123 */ 124 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control), 125 PAGE_SIZE, 0, &seg, 1, &rseg, 126 BUS_DMA_NOWAIT)) != 0) { 127 printf("%s: unable to allocate control structures," 128 " error = %d\n", sc->sc_dev.dv_xname, error); 129 return (error); 130 } 131 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 132 sizeof(struct adw_control), (caddr_t *) & sc->sc_control, 133 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 134 printf("%s: unable to map control structures, error = %d\n", 135 sc->sc_dev.dv_xname, error); 136 return (error); 137 } 138 139 /* 140 * Create and load the DMA map used for the control blocks. 141 */ 142 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control), 143 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT, 144 &sc->sc_dmamap_control)) != 0) { 145 printf("%s: unable to create control DMA map, error = %d\n", 146 sc->sc_dev.dv_xname, error); 147 return (error); 148 } 149 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control, 150 sc->sc_control, sizeof(struct adw_control), NULL, 151 BUS_DMA_NOWAIT)) != 0) { 152 printf("%s: unable to load control DMA map, error = %d\n", 153 sc->sc_dev.dv_xname, error); 154 return (error); 155 } 156 157 return (0); 158 } 159 160 161 static int 162 adw_alloc_carriers(sc) 163 ADW_SOFTC *sc; 164 { 165 bus_dma_segment_t seg; 166 int error, rseg; 167 168 /* 169 * Allocate the control structure. 170 */ 171 sc->sc_control->carriers = malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 172 M_DEVBUF, M_WAITOK); 173 if(!sc->sc_control->carriers) { 174 printf("%s: malloc() failed in allocating carrier structures\n", 175 sc->sc_dev.dv_xname); 176 return (ENOMEM); 177 } 178 179 if ((error = bus_dmamem_alloc(sc->sc_dmat, 180 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 181 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 182 printf("%s: unable to allocate carrier structures," 183 " error = %d\n", sc->sc_dev.dv_xname, error); 184 return (error); 185 } 186 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 187 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 188 (caddr_t *) &sc->sc_control->carriers, 189 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 190 printf("%s: unable to map carrier structures," 191 " error = %d\n", sc->sc_dev.dv_xname, error); 192 return (error); 193 } 194 195 /* 196 * Create and load the DMA map used for the control blocks. 197 */ 198 if ((error = bus_dmamap_create(sc->sc_dmat, 199 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, 200 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, 201 &sc->sc_dmamap_carrier)) != 0) { 202 printf("%s: unable to create carriers DMA map," 203 " error = %d\n", sc->sc_dev.dv_xname, error); 204 return (error); 205 } 206 if ((error = bus_dmamap_load(sc->sc_dmat, 207 sc->sc_dmamap_carrier, sc->sc_control->carriers, 208 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, 209 BUS_DMA_NOWAIT)) != 0) { 210 printf("%s: unable to load carriers DMA map," 211 " error = %d\n", sc->sc_dev.dv_xname, error); 212 return (error); 213 } 214 215 return (0); 216 } 217 218 219 /******************************************************************************/ 220 /* Control Blocks routines */ 221 /******************************************************************************/ 222 223 224 /* 225 * Create a set of ccbs and add them to the free list. Called once 226 * by adw_init(). We return the number of CCBs successfully created. 227 */ 228 static int 229 adw_create_ccbs(sc, ccbstore, count) 230 ADW_SOFTC *sc; 231 ADW_CCB *ccbstore; 232 int count; 233 { 234 ADW_CCB *ccb; 235 int i, error; 236 237 for (i = 0; i < count; i++) { 238 ccb = &ccbstore[i]; 239 if ((error = adw_init_ccb(sc, ccb)) != 0) { 240 printf("%s: unable to initialize ccb, error = %d\n", 241 sc->sc_dev.dv_xname, error); 242 return (i); 243 } 244 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain); 245 } 246 247 return (i); 248 } 249 250 251 /* 252 * A ccb is put onto the free list. 253 */ 254 static void 255 adw_free_ccb(sc, ccb) 256 ADW_SOFTC *sc; 257 ADW_CCB *ccb; 258 { 259 int s; 260 261 s = splbio(); 262 263 adw_reset_ccb(ccb); 264 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain); 265 266 /* 267 * If there were none, wake anybody waiting for one to come free, 268 * starting with queued entries. 269 */ 270 if (ccb->chain.tqe_next == 0) 271 wakeup(&sc->sc_free_ccb); 272 273 splx(s); 274 } 275 276 277 static void 278 adw_reset_ccb(ccb) 279 ADW_CCB *ccb; 280 { 281 282 ccb->flags = 0; 283 } 284 285 286 static int 287 adw_init_ccb(sc, ccb) 288 ADW_SOFTC *sc; 289 ADW_CCB *ccb; 290 { 291 int hashnum, error; 292 293 /* 294 * Create the DMA map for this CCB. 295 */ 296 error = bus_dmamap_create(sc->sc_dmat, 297 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 298 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 299 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer); 300 if (error) { 301 printf("%s: unable to create CCB DMA map, error = %d\n", 302 sc->sc_dev.dv_xname, error); 303 return (error); 304 } 305 306 /* 307 * put in the phystokv hash table 308 * Never gets taken out. 309 */ 310 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr + 311 ADW_CCB_OFF(ccb); 312 hashnum = CCB_HASH(ccb->hashkey); 313 ccb->nexthash = sc->sc_ccbhash[hashnum]; 314 sc->sc_ccbhash[hashnum] = ccb; 315 adw_reset_ccb(ccb); 316 return (0); 317 } 318 319 320 /* 321 * Get a free ccb 322 * 323 * If there are none, see if we can allocate a new one 324 */ 325 static ADW_CCB * 326 adw_get_ccb(sc, flags) 327 ADW_SOFTC *sc; 328 int flags; 329 { 330 ADW_CCB *ccb = 0; 331 int s; 332 333 s = splbio(); 334 335 /* 336 * If we can and have to, sleep waiting for one to come free 337 * but only if we can't allocate a new one. 338 */ 339 for (;;) { 340 ccb = sc->sc_free_ccb.tqh_first; 341 if (ccb) { 342 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain); 343 break; 344 } 345 if ((flags & XS_CTL_NOSLEEP) != 0) 346 goto out; 347 348 tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0); 349 } 350 351 ccb->flags |= CCB_ALLOC; 352 353 out: 354 splx(s); 355 return (ccb); 356 } 357 358 359 /* 360 * Given a physical address, find the ccb that it corresponds to. 361 */ 362 ADW_CCB * 363 adw_ccb_phys_kv(sc, ccb_phys) 364 ADW_SOFTC *sc; 365 u_int32_t ccb_phys; 366 { 367 int hashnum = CCB_HASH(ccb_phys); 368 ADW_CCB *ccb = sc->sc_ccbhash[hashnum]; 369 370 while (ccb) { 371 if (ccb->hashkey == ccb_phys) 372 break; 373 ccb = ccb->nexthash; 374 } 375 return (ccb); 376 } 377 378 379 /* 380 * Queue a CCB to be sent to the controller, and send it if possible. 381 */ 382 static int 383 adw_queue_ccb(sc, ccb, retry) 384 ADW_SOFTC *sc; 385 ADW_CCB *ccb; 386 int retry; 387 { 388 int errcode = ADW_SUCCESS; 389 390 if(!retry) { 391 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); 392 } 393 394 while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) { 395 396 errcode = AdwExeScsiQueue(sc, &ccb->scsiq); 397 switch(errcode) { 398 case ADW_SUCCESS: 399 break; 400 401 case ADW_BUSY: 402 printf("ADW_BUSY\n"); 403 return(ADW_BUSY); 404 405 case ADW_ERROR: 406 printf("ADW_ERROR\n"); 407 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 408 return(ADW_ERROR); 409 } 410 411 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 412 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); 413 414 if ((ccb->xs->xs_control & XS_CTL_POLL) == 0) 415 callout_reset(&ccb->xs->xs_callout, 416 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 417 } 418 419 return(errcode); 420 } 421 422 423 /******************************************************************************/ 424 /* SCSI layer interfacing routines */ 425 /******************************************************************************/ 426 427 428 int 429 adw_init(sc) 430 ADW_SOFTC *sc; 431 { 432 u_int16_t warn_code; 433 434 435 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | 436 ADW_LIB_VERSION_MINOR; 437 sc->cfg.chip_version = 438 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); 439 440 /* 441 * Reset the chip to start and allow register writes. 442 */ 443 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { 444 panic("adw_init: adw_find_signature failed"); 445 } else { 446 AdwResetChip(sc->sc_iot, sc->sc_ioh); 447 448 warn_code = AdwInitFromEEPROM(sc); 449 450 if (warn_code & ADW_WARN_EEPROM_CHKSUM) 451 printf("%s: Bad checksum found. " 452 "Setting default values\n", 453 sc->sc_dev.dv_xname); 454 if (warn_code & ADW_WARN_EEPROM_TERMINATION) 455 printf("%s: Bad bus termination setting." 456 "Using automatic termination.\n", 457 sc->sc_dev.dv_xname); 458 } 459 460 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; 461 sc->async_callback = (ADW_CALLBACK) adw_async_callback; 462 463 return 0; 464 } 465 466 467 void 468 adw_attach(sc) 469 ADW_SOFTC *sc; 470 { 471 int i, error; 472 473 474 TAILQ_INIT(&sc->sc_free_ccb); 475 TAILQ_INIT(&sc->sc_waiting_ccb); 476 TAILQ_INIT(&sc->sc_pending_ccb); 477 TAILQ_INIT(&sc->sc_queue); 478 479 480 /* 481 * Allocate the Control Blocks. 482 */ 483 error = adw_alloc_controls(sc); 484 if (error) 485 return; /* (error) */ ; 486 487 bzero(sc->sc_control, sizeof(struct adw_control)); 488 489 /* 490 * Create and initialize the Control Blocks. 491 */ 492 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB); 493 if (i == 0) { 494 printf("%s: unable to create Control Blocks\n", 495 sc->sc_dev.dv_xname); 496 return; /* (ENOMEM) */ ; 497 } else if (i != ADW_MAX_CCB) { 498 printf("%s: WARNING: only %d of %d Control Blocks" 499 " created\n", 500 sc->sc_dev.dv_xname, i, ADW_MAX_CCB); 501 } 502 503 /* 504 * Create and initialize the Carriers. 505 */ 506 error = adw_alloc_carriers(sc); 507 if (error) 508 return; /* (error) */ ; 509 510 /* 511 * Zero's the freeze_device status 512 */ 513 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 514 515 /* 516 * Initialize the adapter 517 */ 518 switch (AdwInitDriver(sc)) { 519 case ADW_IERR_BIST_PRE_TEST: 520 panic("%s: BIST pre-test error", 521 sc->sc_dev.dv_xname); 522 break; 523 524 case ADW_IERR_BIST_RAM_TEST: 525 panic("%s: BIST RAM test error", 526 sc->sc_dev.dv_xname); 527 break; 528 529 case ADW_IERR_MCODE_CHKSUM: 530 panic("%s: Microcode checksum error", 531 sc->sc_dev.dv_xname); 532 break; 533 534 case ADW_IERR_ILLEGAL_CONNECTION: 535 panic("%s: All three connectors are in use", 536 sc->sc_dev.dv_xname); 537 break; 538 539 case ADW_IERR_REVERSED_CABLE: 540 panic("%s: Cable is reversed", 541 sc->sc_dev.dv_xname); 542 break; 543 544 case ADW_IERR_HVD_DEVICE: 545 panic("%s: HVD attached to LVD connector", 546 sc->sc_dev.dv_xname); 547 break; 548 549 case ADW_IERR_SINGLE_END_DEVICE: 550 panic("%s: single-ended device is attached to" 551 " one of the connectors", 552 sc->sc_dev.dv_xname); 553 break; 554 555 case ADW_IERR_NO_CARRIER: 556 panic("%s: unable to create Carriers", 557 sc->sc_dev.dv_xname); 558 break; 559 560 case ADW_WARN_BUSRESET_ERROR: 561 printf("%s: WARNING: Bus Reset Error\n", 562 sc->sc_dev.dv_xname); 563 break; 564 } 565 566 /* 567 * Fill in the adapter. 568 */ 569 sc->sc_adapter.scsipi_cmd = adw_scsi_cmd; 570 sc->sc_adapter.scsipi_minphys = adwminphys; 571 572 /* 573 * fill in the prototype scsipi_link. 574 */ 575 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 576 sc->sc_link.adapter_softc = sc; 577 sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id; 578 sc->sc_link.adapter = &sc->sc_adapter; 579 sc->sc_link.device = &adw_dev; 580 sc->sc_link.openings = 4; 581 sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID; 582 sc->sc_link.scsipi_scsi.max_lun = 7; 583 sc->sc_link.type = BUS_SCSI; 584 585 586 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 587 } 588 589 590 static void 591 adwminphys(bp) 592 struct buf *bp; 593 { 594 595 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE)) 596 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE); 597 minphys(bp); 598 } 599 600 601 /* 602 * start a scsi operation given the command and the data address. 603 * Also needs the unit, target and lu. 604 */ 605 static int 606 adw_scsi_cmd(xs) 607 struct scsipi_xfer *xs; 608 { 609 struct scsipi_link *sc_link = xs->sc_link; 610 ADW_SOFTC *sc = sc_link->adapter_softc; 611 ADW_CCB *ccb; 612 int s, fromqueue = 1, dontqueue = 0, nowait = 0, retry = 0; 613 int flags; 614 615 s = splbio(); /* protect the queue */ 616 617 /* 618 * If we're running the queue from adw_done(), we've been 619 * called with the first queue entry as our argument. 620 */ 621 if (xs == TAILQ_FIRST(&sc->sc_queue)) { 622 if(sc->sc_freeze_dev[xs->sc_link->scsipi_scsi.target]) { 623 splx(s); 624 return (TRY_AGAIN_LATER); 625 } 626 627 TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q); 628 fromqueue = 1; 629 nowait = 1; 630 } else { 631 if(sc->sc_freeze_dev[xs->sc_link->scsipi_scsi.target]) { 632 splx(s); 633 xs->error = XS_DRIVER_STUFFUP; 634 return (TRY_AGAIN_LATER); 635 } 636 637 /* Polled requests can't be queued for later. */ 638 dontqueue = xs->xs_control & XS_CTL_POLL; 639 640 /* 641 * If there are jobs in the queue, run them first. 642 */ 643 if (TAILQ_FIRST(&sc->sc_queue) != NULL) { 644 /* 645 * If we can't queue, we have to abort, since 646 * we have to preserve order. 647 */ 648 if (dontqueue) { 649 splx(s); 650 xs->error = XS_DRIVER_STUFFUP; 651 return (TRY_AGAIN_LATER); 652 } 653 /* 654 * Swap with the first queue entry. 655 */ 656 TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q); 657 xs = TAILQ_FIRST(&sc->sc_queue); 658 TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q); 659 fromqueue = 1; 660 } 661 } 662 663 664 /* 665 * get a ccb to use. If the transfer 666 * is from a buf (possibly from interrupt time) 667 * then we can't allow it to sleep 668 */ 669 670 flags = xs->xs_control; 671 if (nowait) 672 flags |= XS_CTL_NOSLEEP; 673 if ((ccb = adw_get_ccb(sc, flags)) == NULL) { 674 /* 675 * If we can't queue, we lose. 676 */ 677 if (dontqueue) { 678 splx(s); 679 xs->error = XS_DRIVER_STUFFUP; 680 return (TRY_AGAIN_LATER); 681 } 682 /* 683 * Stuff ourselves into the queue, in front 684 * if we came off in the first place. 685 */ 686 if (fromqueue) 687 TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q); 688 else 689 TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q); 690 splx(s); 691 return (SUCCESSFULLY_QUEUED); 692 } 693 splx(s); /* done playing with the queue */ 694 695 ccb->xs = xs; 696 ccb->timeout = xs->timeout; 697 698 if (adw_build_req(xs, ccb, flags)) { 699 retryagain: 700 s = splbio(); 701 retry = adw_queue_ccb(sc, ccb, retry); 702 splx(s); 703 704 switch(retry) { 705 case ADW_BUSY: 706 goto retryagain; 707 708 case ADW_ERROR: 709 xs->error = XS_DRIVER_STUFFUP; 710 return (COMPLETE); 711 } 712 713 /* 714 * Usually return SUCCESSFULLY QUEUED 715 */ 716 if ((xs->xs_control & XS_CTL_POLL) == 0) 717 return (SUCCESSFULLY_QUEUED); 718 719 /* 720 * If we can't use interrupts, poll on completion 721 */ 722 if (adw_poll(sc, xs, ccb->timeout)) { 723 adw_timeout(ccb); 724 if (adw_poll(sc, xs, ccb->timeout)) 725 adw_timeout(ccb); 726 } 727 } 728 return (COMPLETE); 729 } 730 731 732 /* 733 * Build a request structure for the Wide Boards. 734 */ 735 static int 736 adw_build_req(xs, ccb, flags) 737 struct scsipi_xfer *xs; 738 ADW_CCB *ccb; 739 int flags; 740 { 741 struct scsipi_link *sc_link = xs->sc_link; 742 ADW_SOFTC *sc = sc_link->adapter_softc; 743 bus_dma_tag_t dmat = sc->sc_dmat; 744 ADW_SCSI_REQ_Q *scsiqp; 745 int error; 746 747 scsiqp = &ccb->scsiq; 748 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); 749 750 /* 751 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the 752 * physical CCB structure. 753 */ 754 scsiqp->ccb_ptr = ccb->hashkey; 755 756 /* 757 * Build the ADW_SCSI_REQ_Q request. 758 */ 759 760 /* 761 * Set CDB length and copy it to the request structure. 762 * For wide boards a CDB length maximum of 16 bytes 763 * is supported. 764 */ 765 bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)? 766 xs->cmdlen : 12 ); 767 if(xs->cmdlen > 12) 768 bcopy(&(xs->cmd[12]), &scsiqp->cdb16, xs->cmdlen - 12); 769 770 scsiqp->target_id = sc_link->scsipi_scsi.target; 771 scsiqp->target_lun = sc_link->scsipi_scsi.lun; 772 773 scsiqp->vsense_addr = &ccb->scsi_sense; 774 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 775 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); 776 scsiqp->sense_len = sizeof(struct scsipi_sense_data); 777 778 /* 779 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. 780 */ 781 if (xs->datalen) { 782 /* 783 * Map the DMA transfer. 784 */ 785 #ifdef TFS 786 if (xs->xs_control & SCSI_DATA_UIO) { 787 error = bus_dmamap_load_uio(dmat, 788 ccb->dmamap_xfer, (struct uio *) xs->data, 789 (flags & XS_CTL_NOSLEEP) ? 790 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 791 } else 792 #endif /* TFS */ 793 { 794 error = bus_dmamap_load(dmat, 795 ccb->dmamap_xfer, xs->data, xs->datalen, NULL, 796 (flags & XS_CTL_NOSLEEP) ? 797 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 798 } 799 800 if (error) { 801 if (error == EFBIG) { 802 printf("%s: adw_scsi_cmd, more than %d dma" 803 " segments\n", 804 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST); 805 } else { 806 printf("%s: adw_scsi_cmd, error %d loading" 807 " dma map\n", 808 sc->sc_dev.dv_xname, error); 809 } 810 811 xs->error = XS_DRIVER_STUFFUP; 812 adw_free_ccb(sc, ccb); 813 return (0); 814 } 815 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, 816 ccb->dmamap_xfer->dm_mapsize, 817 (xs->xs_control & XS_CTL_DATA_IN) ? 818 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 819 820 /* 821 * Build scatter-gather list. 822 */ 823 scsiqp->data_cnt = xs->datalen; 824 scsiqp->vdata_addr = xs->data; 825 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; 826 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); 827 adw_build_sglist(ccb, scsiqp, ccb->sg_block); 828 } else { 829 /* 830 * No data xfer, use non S/G values. 831 */ 832 scsiqp->data_cnt = 0; 833 scsiqp->vdata_addr = 0; 834 scsiqp->data_addr = 0; 835 } 836 837 return (1); 838 } 839 840 841 /* 842 * Build scatter-gather list for Wide Boards. 843 */ 844 static void 845 adw_build_sglist(ccb, scsiqp, sg_block) 846 ADW_CCB *ccb; 847 ADW_SCSI_REQ_Q *scsiqp; 848 ADW_SG_BLOCK *sg_block; 849 { 850 u_long sg_block_next_addr; /* block and its next */ 851 u_int32_t sg_block_physical_addr; 852 int i; /* how many SG entries */ 853 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; 854 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; 855 856 857 sg_block_next_addr = (u_long) sg_block; /* allow math operation */ 858 sg_block_physical_addr = ccb->hashkey + 859 offsetof(struct adw_ccb, sg_block[0]); 860 scsiqp->sg_real_addr = sg_block_physical_addr; 861 862 /* 863 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list) 864 * then split the request into multiple sg-list blocks. 865 */ 866 867 do { 868 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 869 sg_block->sg_list[i].sg_addr = sg_list->ds_addr; 870 sg_block->sg_list[i].sg_count = sg_list->ds_len; 871 872 if (--sg_elem_cnt == 0) { 873 /* last entry, get out */ 874 sg_block->sg_cnt = i + i; 875 sg_block->sg_ptr = NULL; /* next link = NULL */ 876 return; 877 } 878 sg_list++; 879 } 880 sg_block_next_addr += sizeof(ADW_SG_BLOCK); 881 sg_block_physical_addr += sizeof(ADW_SG_BLOCK); 882 883 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 884 sg_block->sg_ptr = sg_block_physical_addr; 885 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ 886 } while (1); 887 } 888 889 890 /******************************************************************************/ 891 /* Interrupts and TimeOut routines */ 892 /******************************************************************************/ 893 894 895 int 896 adw_intr(arg) 897 void *arg; 898 { 899 ADW_SOFTC *sc = arg; 900 struct scsipi_xfer *xs; 901 902 903 if(AdwISR(sc) != ADW_FALSE) { 904 /* 905 * If there are queue entries in the software queue, try to 906 * run the first one. We should be more or less guaranteed 907 * to succeed, since we just freed a CCB. 908 * 909 * NOTE: adw_scsi_cmd() relies on our calling it with 910 * the first entry in the queue. 911 */ 912 if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL) 913 (void) adw_scsi_cmd(xs); 914 915 return (1); 916 } 917 918 return (0); 919 } 920 921 922 /* 923 * Poll a particular unit, looking for a particular xs 924 */ 925 static int 926 adw_poll(sc, xs, count) 927 ADW_SOFTC *sc; 928 struct scsipi_xfer *xs; 929 int count; 930 { 931 932 /* timeouts are in msec, so we loop in 1000 usec cycles */ 933 while (count) { 934 adw_intr(sc); 935 if (xs->xs_status & XS_STS_DONE) 936 return (0); 937 delay(1000); /* only happens in boot so ok */ 938 count--; 939 } 940 return (1); 941 } 942 943 944 static void 945 adw_timeout(arg) 946 void *arg; 947 { 948 ADW_CCB *ccb = arg; 949 struct scsipi_xfer *xs = ccb->xs; 950 struct scsipi_link *sc_link = xs->sc_link; 951 ADW_SOFTC *sc = sc_link->adapter_softc; 952 int s; 953 954 scsi_print_addr(sc_link); 955 printf("timed out"); 956 957 s = splbio(); 958 959 if (ccb->flags & CCB_ABORTED) { 960 /* 961 * Abort Timed Out 962 * 963 * No more opportunities. Lets try resetting the bus and 964 * reinitialize the host adapter. 965 */ 966 callout_stop(&xs->xs_callout); 967 printf(" AGAIN. Resetting SCSI Bus\n"); 968 adw_reset_bus(sc); 969 splx(s); 970 return; 971 } else if (ccb->flags & CCB_ABORTING) { 972 /* 973 * Abort the operation that has timed out. 974 * 975 * Second opportunity. 976 */ 977 printf("\n"); 978 xs->error = XS_TIMEOUT; 979 ccb->flags |= CCB_ABORTED; 980 #if 0 981 /* 982 * - XXX - 3.3a microcode is BROKEN!!! 983 * 984 * We cannot abort a CCB, so we can only hope the command 985 * get completed before the next timeout, otherwise a 986 * Bus Reset will arrive inexorably. 987 */ 988 /* 989 * ADW_ABORT_CCB() makes the board to generate an interrupt 990 * 991 * - XXX - The above assertion MUST be verified (and this 992 * code changed as well [callout_*()]), when the 993 * ADW_ABORT_CCB will be working again 994 */ 995 ADW_ABORT_CCB(sc, ccb); 996 #endif 997 /* 998 * waiting for multishot callout_reset() let's restart it 999 * by hand so the next time a timeout event will occour 1000 * we will reset the bus. 1001 */ 1002 callout_reset(&xs->xs_callout, 1003 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 1004 } else { 1005 /* 1006 * Abort the operation that has timed out. 1007 * 1008 * First opportunity. 1009 */ 1010 printf("\n"); 1011 xs->error = XS_TIMEOUT; 1012 ccb->flags |= CCB_ABORTING; 1013 #if 0 1014 /* 1015 * - XXX - 3.3a microcode is BROKEN!!! 1016 * 1017 * We cannot abort a CCB, so we can only hope the command 1018 * get completed before the next 2 timeout, otherwise a 1019 * Bus Reset will arrive inexorably. 1020 */ 1021 /* 1022 * ADW_ABORT_CCB() makes the board to generate an interrupt 1023 * 1024 * - XXX - The above assertion MUST be verified (and this 1025 * code changed as well [callout_*()]), when the 1026 * ADW_ABORT_CCB will be working again 1027 */ 1028 ADW_ABORT_CCB(sc, ccb); 1029 #endif 1030 /* 1031 * waiting for multishot callout_reset() let's restart it 1032 * by hand so to give a second opportunity to the command 1033 * which timed-out. 1034 */ 1035 callout_reset(&xs->xs_callout, 1036 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 1037 } 1038 1039 splx(s); 1040 } 1041 1042 1043 static void 1044 adw_reset_bus(sc) 1045 ADW_SOFTC *sc; 1046 { 1047 ADW_CCB *ccb; 1048 int s; 1049 1050 s = splbio(); 1051 AdwResetSCSIBus(sc); 1052 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, 1053 adw_pending_ccb)) != NULL) { 1054 callout_stop(&ccb->xs->xs_callout); 1055 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1056 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); 1057 } 1058 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); 1059 splx(s); 1060 } 1061 1062 1063 /******************************************************************************/ 1064 /* Host Adapter and Peripherals Information Routines */ 1065 /******************************************************************************/ 1066 1067 1068 static void 1069 adw_print_info(sc, tid) 1070 ADW_SOFTC *sc; 1071 int tid; 1072 { 1073 bus_space_tag_t iot = sc->sc_iot; 1074 bus_space_handle_t ioh = sc->sc_ioh; 1075 u_int16_t wdtr_able, wdtr_done, wdtr; 1076 u_int16_t sdtr_able, sdtr_done, sdtr, period; 1077 static int wdtr_reneg = 0, sdtr_reneg = 0; 1078 1079 if (tid == 0){ 1080 wdtr_reneg = sdtr_reneg = 0; 1081 } 1082 1083 printf("%s: target %d ", sc->sc_dev.dv_xname, tid); 1084 1085 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, wdtr_able); 1086 if(wdtr_able & ADW_TID_TO_TIDMASK(tid)) { 1087 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, wdtr_done); 1088 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + 1089 (2 * tid), wdtr); 1090 printf("using %d-bits wide, ", (wdtr & 0x8000)? 16 : 8); 1091 if((wdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) 1092 wdtr_reneg = 1; 1093 } else { 1094 printf("wide transfers disabled, "); 1095 } 1096 1097 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1098 if(sdtr_able & ADW_TID_TO_TIDMASK(tid)) { 1099 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, sdtr_done); 1100 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + 1101 (2 * tid), sdtr); 1102 sdtr &= ~0x8000; 1103 if((sdtr & 0x1F) != 0) { 1104 if((sdtr & 0x1F00) == 0x1100){ 1105 printf("80.0 MHz"); 1106 } else if((sdtr & 0x1F00) == 0x1000){ 1107 printf("40.0 MHz"); 1108 } else { 1109 /* <= 20.0 MHz */ 1110 period = (((sdtr >> 8) * 25) + 50)/4; 1111 if(period == 0) { 1112 /* Should never happen. */ 1113 printf("? MHz"); 1114 } else { 1115 printf("%d.%d MHz", 250/period, 1116 ADW_TENTHS(250, period)); 1117 } 1118 } 1119 printf(" synchronous transfers\n"); 1120 } else { 1121 printf("asynchronous transfers\n"); 1122 } 1123 if((sdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) 1124 sdtr_reneg = 1; 1125 } else { 1126 printf("synchronous transfers disabled\n"); 1127 } 1128 1129 if(wdtr_reneg || sdtr_reneg) { 1130 printf("%s: target %d %s", sc->sc_dev.dv_xname, tid, 1131 (wdtr_reneg)? ((sdtr_reneg)? "wide/sync" : "wide") : 1132 ((sdtr_reneg)? "sync" : "") ); 1133 printf(" renegotiation pending before next command.\n"); 1134 } 1135 } 1136 1137 1138 /******************************************************************************/ 1139 /* WIDE boards Interrupt callbacks */ 1140 /******************************************************************************/ 1141 1142 1143 /* 1144 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() 1145 * 1146 * Interrupt callback function for the Wide SCSI Adv Library. 1147 * 1148 * Notice: 1149 * Interrupts are disabled by the caller (AdwISR() function), and will be 1150 * enabled at the end of the caller. 1151 */ 1152 static void 1153 adw_isr_callback(sc, scsiq) 1154 ADW_SOFTC *sc; 1155 ADW_SCSI_REQ_Q *scsiq; 1156 { 1157 bus_dma_tag_t dmat = sc->sc_dmat; 1158 ADW_CCB *ccb; 1159 struct scsipi_xfer *xs; 1160 struct scsipi_sense_data *s1, *s2; 1161 1162 1163 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1164 1165 callout_stop(&ccb->xs->xs_callout); 1166 1167 xs = ccb->xs; 1168 1169 /* 1170 * If we were a data transfer, unload the map that described 1171 * the data buffer. 1172 */ 1173 if (xs->datalen) { 1174 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, 1175 ccb->dmamap_xfer->dm_mapsize, 1176 (xs->xs_control & XS_CTL_DATA_IN) ? 1177 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1178 bus_dmamap_unload(dmat, ccb->dmamap_xfer); 1179 } 1180 1181 if ((ccb->flags & CCB_ALLOC) == 0) { 1182 printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname); 1183 Debugger(); 1184 return; 1185 } 1186 1187 /* 1188 * 'done_status' contains the command's ending status. 1189 * 'host_status' conatins the host adapter status. 1190 * 'scsi_status' contains the scsi peripheral status. 1191 */ 1192 if ((scsiq->host_status == QHSTA_NO_ERROR) && 1193 ((scsiq->done_status == QD_NO_ERROR) || 1194 (scsiq->done_status == QD_WITH_ERROR))) { 1195 switch (scsiq->host_status) { 1196 case SCSI_STATUS_GOOD: 1197 if ((scsiq->cdb[0] == INQUIRY) && 1198 (scsiq->target_lun == 0)) { 1199 adw_print_info(sc, scsiq->target_id); 1200 } 1201 xs->error = XS_NOERROR; 1202 xs->resid = scsiq->data_cnt; 1203 sc->sc_freeze_dev[scsiq->target_id] = 0; 1204 break; 1205 1206 case SCSI_STATUS_CHECK_CONDITION: 1207 case SCSI_STATUS_CMD_TERMINATED: 1208 s1 = &ccb->scsi_sense; 1209 s2 = &xs->sense.scsi_sense; 1210 *s2 = *s1; 1211 xs->error = XS_SENSE; 1212 sc->sc_freeze_dev[scsiq->target_id] = 1; 1213 break; 1214 1215 default: 1216 xs->error = XS_BUSY; 1217 sc->sc_freeze_dev[scsiq->target_id] = 1; 1218 break; 1219 } 1220 } else if (scsiq->done_status == QD_ABORTED_BY_HOST) { 1221 xs->error = XS_DRIVER_STUFFUP; 1222 } else { 1223 switch (scsiq->host_status) { 1224 case QHSTA_M_SEL_TIMEOUT: 1225 xs->error = XS_SELTIMEOUT; 1226 break; 1227 1228 case QHSTA_M_SXFR_OFF_UFLW: 1229 case QHSTA_M_SXFR_OFF_OFLW: 1230 case QHSTA_M_DATA_OVER_RUN: 1231 printf("%s: Overrun/Overflow/Underflow condition\n", 1232 sc->sc_dev.dv_xname); 1233 xs->error = XS_DRIVER_STUFFUP; 1234 break; 1235 1236 case QHSTA_M_SXFR_DESELECTED: 1237 case QHSTA_M_UNEXPECTED_BUS_FREE: 1238 printf("%s: Unexpected BUS free\n",sc->sc_dev.dv_xname); 1239 xs->error = XS_DRIVER_STUFFUP; 1240 break; 1241 1242 case QHSTA_M_SCSI_BUS_RESET: 1243 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1244 printf("%s: BUS Reset\n", sc->sc_dev.dv_xname); 1245 xs->error = XS_DRIVER_STUFFUP; 1246 break; 1247 1248 case QHSTA_M_BUS_DEVICE_RESET: 1249 printf("%s: Device Reset\n", sc->sc_dev.dv_xname); 1250 xs->error = XS_DRIVER_STUFFUP; 1251 break; 1252 1253 case QHSTA_M_QUEUE_ABORTED: 1254 printf("%s: Queue Aborted\n", sc->sc_dev.dv_xname); 1255 xs->error = XS_DRIVER_STUFFUP; 1256 break; 1257 1258 case QHSTA_M_SXFR_SDMA_ERR: 1259 case QHSTA_M_SXFR_SXFR_PERR: 1260 case QHSTA_M_RDMA_PERR: 1261 /* 1262 * DMA Error. This should *NEVER* happen! 1263 * 1264 * Lets try resetting the bus and reinitialize 1265 * the host adapter. 1266 */ 1267 printf("%s: DMA Error. Reseting bus\n", 1268 sc->sc_dev.dv_xname); 1269 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1270 adw_reset_bus(sc); 1271 xs->error = XS_BUSY; 1272 goto done; 1273 1274 case QHSTA_M_WTM_TIMEOUT: 1275 case QHSTA_M_SXFR_WD_TMO: 1276 /* The SCSI bus hung in a phase */ 1277 printf("%s: Watch Dog timer expired. Reseting bus\n", 1278 sc->sc_dev.dv_xname); 1279 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1280 adw_reset_bus(sc); 1281 xs->error = XS_BUSY; 1282 goto done; 1283 1284 case QHSTA_M_SXFR_XFR_PH_ERR: 1285 printf("%s: Transfer Error\n", sc->sc_dev.dv_xname); 1286 xs->error = XS_DRIVER_STUFFUP; 1287 break; 1288 1289 case QHSTA_M_BAD_CMPL_STATUS_IN: 1290 /* No command complete after a status message */ 1291 printf("%s: Bad Completion Status\n", 1292 sc->sc_dev.dv_xname); 1293 xs->error = XS_DRIVER_STUFFUP; 1294 break; 1295 1296 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1297 printf("%s: Auto Sense Failed\n", sc->sc_dev.dv_xname); 1298 xs->error = XS_DRIVER_STUFFUP; 1299 break; 1300 1301 case QHSTA_M_INVALID_DEVICE: 1302 printf("%s: Invalid Device\n", sc->sc_dev.dv_xname); 1303 xs->error = XS_DRIVER_STUFFUP; 1304 break; 1305 1306 case QHSTA_M_NO_AUTO_REQ_SENSE: 1307 /* 1308 * User didn't request sense, but we got a 1309 * check condition. 1310 */ 1311 printf("%s: Unexpected Check Condition\n", 1312 sc->sc_dev.dv_xname); 1313 xs->error = XS_DRIVER_STUFFUP; 1314 break; 1315 1316 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1317 printf("%s: Unknown Error\n", sc->sc_dev.dv_xname); 1318 xs->error = XS_DRIVER_STUFFUP; 1319 break; 1320 1321 default: 1322 panic("%s: Unhandled Host Status Error %x", 1323 sc->sc_dev.dv_xname, scsiq->host_status); 1324 } 1325 } 1326 1327 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1328 done: adw_free_ccb(sc, ccb); 1329 xs->xs_status |= XS_STS_DONE; 1330 scsipi_done(xs); 1331 } 1332 1333 1334 /* 1335 * adw_async_callback() - Adv Library asynchronous event callback function. 1336 */ 1337 static void 1338 adw_async_callback(sc, code) 1339 ADW_SOFTC *sc; 1340 u_int8_t code; 1341 { 1342 switch (code) { 1343 case ADV_ASYNC_SCSI_BUS_RESET_DET: 1344 /* The firmware detected a SCSI Bus reset. */ 1345 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); 1346 break; 1347 1348 case ADV_ASYNC_RDMA_FAILURE: 1349 /* 1350 * Handle RDMA failure by resetting the SCSI Bus and 1351 * possibly the chip if it is unresponsive. 1352 */ 1353 printf("%s: RDMA failure. Resetting the SCSI Bus and" 1354 " the adapter\n", sc->sc_dev.dv_xname); 1355 AdwResetSCSIBus(sc); 1356 break; 1357 1358 case ADV_HOST_SCSI_BUS_RESET: 1359 /* Host generated SCSI bus reset occurred. */ 1360 printf("%s: Host generated SCSI bus reset occurred\n", 1361 sc->sc_dev.dv_xname); 1362 break; 1363 1364 case ADV_ASYNC_CARRIER_READY_FAILURE: 1365 /* Carrier Ready failure. */ 1366 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); 1367 break; 1368 1369 default: 1370 break; 1371 } 1372 } 1373
Indexes created Tue Sep 23 02:09:52 GMT 2025