adwlib.c revision 1.11
1 /* $NetBSD: adwlib.c,v 1.11 2000/05/08 17:21:34 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_param.h> 73 #include <vm/pmap.h> 74 75 #include <dev/ic/adwlib.h> 76 #include <dev/ic/adw.h> 77 #include <dev/ic/adwmcode.h> 78 79 80 /* Static Functions */ 81 82 static u_int16_t AdvGet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 83 ADW_EEP_3550_CONFIG *)); 84 static u_int16_t AdvGet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_EEP_38C0800_CONFIG *)); 86 static u_int16_t AdvGet38C1600EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 87 ADW_EEP_38C1600_CONFIG *)); 88 static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 89 static void AdvWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 90 static void AdvSet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 91 ADW_EEP_3550_CONFIG *)); 92 static void AdvSet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 93 ADW_EEP_38C0800_CONFIG *)); 94 static void AdvSet38C1600EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 95 ADW_EEP_38C1600_CONFIG *)); 96 static void AdvInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 97 98 static void AdvSleepMilliSecond __P((u_int32_t)); 99 static void AdvDelayMicroSecond __P((u_int32_t)); 100 101 102 /* 103 * EEPROM Configuration. 104 * 105 * All drivers should use this structure to set the default EEPROM 106 * configuration. The BIOS now uses this structure when it is built. 107 * Additional structure information can be found in advlib.h where 108 * the structure is defined. 109 */ 110 static ADW_EEP_3550_CONFIG 111 Default_3550_EEPROM_Config = { 112 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 113 0x0000, /* cfg_msw */ 114 0xFFFF, /* disc_enable */ 115 0xFFFF, /* wdtr_able */ 116 0xFFFF, /* sdtr_able */ 117 0xFFFF, /* start_motor */ 118 0xFFFF, /* tagqng_able */ 119 0xFFFF, /* bios_scan */ 120 0, /* scam_tolerant */ 121 7, /* adapter_scsi_id */ 122 0, /* bios_boot_delay */ 123 3, /* scsi_reset_delay */ 124 0, /* bios_id_lun */ 125 0, /* termination */ 126 0, /* reserved1 */ 127 0xFFE7, /* bios_ctrl */ 128 0xFFFF, /* ultra_able */ 129 0, /* reserved2 */ 130 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 131 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 132 0, /* dvc_cntl */ 133 0, /* bug_fix */ 134 0, /* serial_number_word1 */ 135 0, /* serial_number_word2 */ 136 0, /* serial_number_word3 */ 137 0, /* check_sum */ 138 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */ 139 0, /* dvc_err_code */ 140 0, /* adv_err_code */ 141 0, /* adv_err_addr */ 142 0, /* saved_dvc_err_code */ 143 0, /* saved_adv_err_code */ 144 0, /* saved_adv_err_addr */ 145 0 /* num_of_err */ 146 }; 147 148 static ADW_EEP_38C0800_CONFIG 149 Default_38C0800_EEPROM_Config = { 150 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 151 0x0000, /* 01 cfg_msw */ 152 0xFFFF, /* 02 disc_enable */ 153 0xFFFF, /* 03 wdtr_able */ 154 0x4444, /* 04 sdtr_speed1 */ 155 0xFFFF, /* 05 start_motor */ 156 0xFFFF, /* 06 tagqng_able */ 157 0xFFFF, /* 07 bios_scan */ 158 0, /* 08 scam_tolerant */ 159 7, /* 09 adapter_scsi_id */ 160 0, /* bios_boot_delay */ 161 3, /* 10 scsi_reset_delay */ 162 0, /* bios_id_lun */ 163 0, /* 11 termination_se */ 164 0, /* termination_lvd */ 165 0xFFE7, /* 12 bios_ctrl */ 166 0x4444, /* 13 sdtr_speed2 */ 167 0x4444, /* 14 sdtr_speed3 */ 168 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 169 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 170 0, /* 16 dvc_cntl */ 171 0x4444, /* 17 sdtr_speed4 */ 172 0, /* 18 serial_number_word1 */ 173 0, /* 19 serial_number_word2 */ 174 0, /* 20 serial_number_word3 */ 175 0, /* 21 check_sum */ 176 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 177 0, /* 30 dvc_err_code */ 178 0, /* 31 adv_err_code */ 179 0, /* 32 adv_err_addr */ 180 0, /* 33 saved_dvc_err_code */ 181 0, /* 34 saved_adv_err_code */ 182 0, /* 35 saved_adv_err_addr */ 183 0, /* 36 reserved */ 184 0, /* 37 reserved */ 185 0, /* 38 reserved */ 186 0, /* 39 reserved */ 187 0, /* 40 reserved */ 188 0, /* 41 reserved */ 189 0, /* 42 reserved */ 190 0, /* 43 reserved */ 191 0, /* 44 reserved */ 192 0, /* 45 reserved */ 193 0, /* 46 reserved */ 194 0, /* 47 reserved */ 195 0, /* 48 reserved */ 196 0, /* 49 reserved */ 197 0, /* 50 reserved */ 198 0, /* 51 reserved */ 199 0, /* 52 reserved */ 200 0, /* 53 reserved */ 201 0, /* 54 reserved */ 202 0, /* 55 reserved */ 203 0, /* 56 cisptr_lsw */ 204 0, /* 57 cisprt_msw */ 205 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 206 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 207 0, /* 60 reserved */ 208 0, /* 61 reserved */ 209 0, /* 62 reserved */ 210 0 /* 63 reserved */ 211 }; 212 213 static ADW_EEP_38C1600_CONFIG 214 Default_38C1600_EEPROM_Config = { 215 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 216 0x0000, /* 01 cfg_msw */ 217 0xFFFF, /* 02 disc_enable */ 218 0xFFFF, /* 03 wdtr_able */ 219 0x5555, /* 04 sdtr_speed1 */ 220 0xFFFF, /* 05 start_motor */ 221 0xFFFF, /* 06 tagqng_able */ 222 0xFFFF, /* 07 bios_scan */ 223 0, /* 08 scam_tolerant */ 224 7, /* 09 adapter_scsi_id */ 225 0, /* bios_boot_delay */ 226 3, /* 10 scsi_reset_delay */ 227 0, /* bios_id_lun */ 228 0, /* 11 termination_se */ 229 0, /* termination_lvd */ 230 0xFFE7, /* 12 bios_ctrl */ 231 0x5555, /* 13 sdtr_speed2 */ 232 0x5555, /* 14 sdtr_speed3 */ 233 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 234 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 235 0, /* 16 dvc_cntl */ 236 0x5555, /* 17 sdtr_speed4 */ 237 0, /* 18 serial_number_word1 */ 238 0, /* 19 serial_number_word2 */ 239 0, /* 20 serial_number_word3 */ 240 0, /* 21 check_sum */ 241 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 242 0, /* 30 dvc_err_code */ 243 0, /* 31 adv_err_code */ 244 0, /* 32 adv_err_addr */ 245 0, /* 33 saved_dvc_err_code */ 246 0, /* 34 saved_adv_err_code */ 247 0, /* 35 saved_adv_err_addr */ 248 0, /* 36 reserved */ 249 0, /* 37 reserved */ 250 0, /* 38 reserved */ 251 0, /* 39 reserved */ 252 0, /* 40 reserved */ 253 0, /* 41 reserved */ 254 0, /* 42 reserved */ 255 0, /* 43 reserved */ 256 0, /* 44 reserved */ 257 0, /* 45 reserved */ 258 0, /* 46 reserved */ 259 0, /* 47 reserved */ 260 0, /* 48 reserved */ 261 0, /* 49 reserved */ 262 0, /* 50 reserved */ 263 0, /* 51 reserved */ 264 0, /* 52 reserved */ 265 0, /* 53 reserved */ 266 0, /* 54 reserved */ 267 0, /* 55 reserved */ 268 0, /* 56 cisptr_lsw */ 269 0, /* 57 cisprt_msw */ 270 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 271 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 272 0, /* 60 reserved */ 273 0, /* 61 reserved */ 274 0, /* 62 reserved */ 275 0 /* 63 reserved */ 276 }; 277 278 /* 279 * Initialize the ASC3550. 280 * 281 * On failure set the ADW_SOFTC field 'err_code' and return ADW_ERROR. 282 * 283 * For a non-fatal error return a warning code. If there are no warnings 284 * then 0 is returned. 285 */ 286 int 287 AdvInitAsc3550Driver(sc) 288 ADW_SOFTC *sc; 289 { 290 bus_space_tag_t iot = sc->sc_iot; 291 bus_space_handle_t ioh = sc->sc_ioh; 292 u_int16_t warn_code; 293 u_int32_t sum; 294 int begin_addr; 295 int end_addr; 296 u_int16_t code_sum; 297 int word; 298 int i, j; 299 int adv_asc3550_expanded_size; 300 u_int16_t scsi_cfg1; 301 u_int8_t tid; 302 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 303 0x40-0x8F. */ 304 u_int16_t wdtr_able = 0, sdtr_able, tagqng_able; 305 u_int8_t max_cmd[ADW_MAX_TID + 1]; 306 307 308 warn_code = 0; 309 310 /* 311 * Save the RISC memory BIOS region before writing the microcode. 312 * The BIOS may already be loaded and using its RISC LRAM region 313 * so its region must be saved and restored. 314 * 315 * Note: This code makes the assumption, which is currently true, 316 * that a chip reset does not clear RISC LRAM. 317 */ 318 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 319 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM+(2*i), bios_mem[i]); 320 } 321 322 /* 323 * Save current per TID negotiated values. 324 */ 325 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA) { 326 327 u_int16_t bios_version, major, minor; 328 329 bios_version = bios_mem[(ASC_MC_BIOS_VERSION-ASC_MC_BIOSMEM)/2]; 330 major = (bios_version >> 12) & 0xF; 331 minor = (bios_version >> 8) & 0xF; 332 if (major < 3 || (major == 3 && minor == 1)) { 333 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 334 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 335 } else { 336 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 337 } 338 } 339 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 340 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 341 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 342 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 343 max_cmd[tid]); 344 } 345 346 /* 347 * Load the Microcode 348 * 349 * Write the microcode image to RISC memory starting at address 0. 350 */ 351 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 352 353 /* Assume the following compressed format of the microcode buffer: 354 * 355 * 254 word (508 byte) table indexed by byte code followed 356 * by the following byte codes: 357 * 358 * 1-Byte Code: 359 * 00: Emit word 0 in table. 360 * 01: Emit word 1 in table. 361 * . 362 * FD: Emit word 253 in table. 363 * 364 * Multi-Byte Code: 365 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 366 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 367 */ 368 word = 0; 369 for (i = 253 * 2; i < adv_asc3550_mcode_size; i++) { 370 if (adv_asc3550_mcode[i] == 0xff) { 371 for (j = 0; j < adv_asc3550_mcode[i + 1]; j++) { 372 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 373 (((u_int16_t)adv_asc3550_mcode[i + 3] << 8) | 374 adv_asc3550_mcode[i + 2])); 375 word++; 376 } 377 i += 3; 378 } else if (adv_asc3550_mcode[i] == 0xfe) { 379 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 380 (((u_int16_t)adv_asc3550_mcode[i + 2] << 8) | 381 adv_asc3550_mcode[i + 1])); 382 i += 2; 383 word++; 384 } else { 385 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 386 adv_asc3550_mcode[(adv_asc3550_mcode[i] * 2) + 1] <<8)| 387 adv_asc3550_mcode[adv_asc3550_mcode[i] * 2])); 388 word++; 389 } 390 } 391 392 /* 393 * Set 'word' for later use to clear the rest of memory and save 394 * the expanded mcode size. 395 */ 396 word *= 2; 397 adv_asc3550_expanded_size = word; 398 399 /* 400 * Clear the rest of ASC-3550 Internal RAM (8KB). 401 */ 402 for (; word < ADV_3550_MEMSIZE; word += 2) { 403 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 404 } 405 406 /* 407 * Verify the microcode checksum. 408 */ 409 sum = 0; 410 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 411 412 for (word = 0; word < adv_asc3550_expanded_size; word += 2) { 413 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 414 } 415 416 if (sum != adv_asc3550_mcode_chksum) { 417 return ASC_IERR_MCODE_CHKSUM; 418 } 419 420 /* 421 * Restore the RISC memory BIOS region. 422 */ 423 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 424 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 425 bios_mem[i]); 426 } 427 428 /* 429 * Calculate and write the microcode code checksum to the microcode 430 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 431 */ 432 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 433 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 434 code_sum = 0; 435 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 436 for (word = begin_addr; word < end_addr; word += 2) { 437 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 438 } 439 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 440 441 /* 442 * Read and save microcode version and date. 443 */ 444 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 445 sc->cfg.mcode_date); 446 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 447 sc->cfg.mcode_version); 448 449 /* 450 * Set the chip type to indicate the ASC3550. 451 */ 452 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 453 454 /* 455 * If the PCI Configuration Command Register "Parity Error Response 456 * Control" Bit was clear (0), then set the microcode variable 457 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 458 * to ignore DMA parity errors. 459 */ 460 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 461 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 462 word |= CONTROL_FLAG_IGNORE_PERR; 463 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 464 } 465 466 /* 467 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 468 * threshold of 128 bytes. This register is only accessible to the host. 469 */ 470 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 471 START_CTL_EMFU | READ_CMD_MRM); 472 473 /* 474 * Microcode operating variables for WDTR, SDTR, and command tag 475 * queuing will be set in AdvInquiryHandling() based on what a 476 * device reports it is capable of in Inquiry byte 7. 477 * 478 * If SCSI Bus Resets haev been disabled, then directly set 479 * SDTR and WDTR from the EEPROM configuration. This will allow 480 * the BIOS and warm boot to work without a SCSI bus hang on 481 * the Inquiry caused by host and target mismatched DTR values. 482 * Without the SCSI Bus Reset, before an Inquiry a device can't 483 * be assumed to be in Asynchronous, Narrow mode. 484 */ 485 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 486 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 487 sc->wdtr_able); 488 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 489 sc->sdtr_able); 490 } 491 492 /* 493 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 494 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 495 * bitmask. These values determine the maximum SDTR speed negotiated 496 * with a device. 497 * 498 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 499 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 500 * without determining here whether the device supports SDTR. 501 * 502 * 4-bit speed SDTR speed name 503 * =========== =============== 504 * 0000b (0x0) SDTR disabled 505 * 0001b (0x1) 5 Mhz 506 * 0010b (0x2) 10 Mhz 507 * 0011b (0x3) 20 Mhz (Ultra) 508 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 509 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 510 * 0110b (0x6) Undefined 511 * . 512 * 1111b (0xF) Undefined 513 */ 514 word = 0; 515 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 516 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 517 /* Set Ultra speed for TID 'tid'. */ 518 word |= (0x3 << (4 * (tid % 4))); 519 } else { 520 /* Set Fast speed for TID 'tid'. */ 521 word |= (0x2 << (4 * (tid % 4))); 522 } 523 /* Check if done with sdtr_speed1. */ 524 if (tid == 3) { 525 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, word); 526 word = 0; 527 /* Check if done with sdtr_speed2. */ 528 } else if (tid == 7) { 529 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, word); 530 word = 0; 531 /* Check if done with sdtr_speed3. */ 532 } else if (tid == 11) { 533 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, word); 534 word = 0; 535 /* Check if done with sdtr_speed4. */ 536 } else if (tid == 15) { 537 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, word); 538 /* End of loop. */ 539 } 540 } 541 542 /* 543 * Set microcode operating variable for the disconnect per TID bitmask. 544 */ 545 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 546 547 548 /* 549 * Set SCSI_CFG0 Microcode Default Value. 550 * 551 * The microcode will set the SCSI_CFG0 register using this value 552 * after it is started below. 553 */ 554 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 555 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 556 ADW_OUR_ID_EN | sc->chip_scsi_id); 557 558 /* 559 * Determine SCSI_CFG1 Microcode Default Value. 560 * 561 * The microcode will set the SCSI_CFG1 register using this value 562 * after it is started below. 563 */ 564 565 /* Read current SCSI_CFG1 Register value. */ 566 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 567 568 /* 569 * If all three connectors are in use, return an error. 570 */ 571 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 572 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 573 return ASC_IERR_ILLEGAL_CONNECTION; 574 } 575 576 /* 577 * If the internal narrow cable is reversed all of the SCSI_CTRL 578 * register signals will be set. Check for and return an error if 579 * this condition is found. 580 */ 581 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 582 0x3F07) { 583 return ASC_IERR_REVERSED_CABLE; 584 } 585 586 /* 587 * If this is a differential board and a single-ended device 588 * is attached to one of the connectors, return an error. 589 */ 590 if ((scsi_cfg1 & ADW_DIFF_MODE) && (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 591 return ASC_IERR_SINGLE_END_DEVICE; 592 } 593 594 /* 595 * If automatic termination control is enabled, then set the 596 * termination value based on a table listed in a_condor.h. 597 * 598 * If manual termination was specified with an EEPROM setting 599 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 600 * is ready to be 'ored' into SCSI_CFG1. 601 */ 602 if (sc->cfg.termination == 0) { 603 /* 604 * The software always controls termination by setting 605 * TERM_CTL_SEL. 606 * If TERM_CTL_SEL were set to 0, the hardware would set 607 * termination. 608 */ 609 sc->cfg.termination |= ADW_TERM_CTL_SEL; 610 611 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 612 /* TERM_CTL_H: on, TERM_CTL_L: on */ 613 case 0x3: case 0x7: case 0xB: 614 case 0xD: case 0xE: case 0xF: 615 sc->cfg.termination |= 616 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 617 break; 618 619 /* TERM_CTL_H: on, TERM_CTL_L: off */ 620 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC: 621 sc->cfg.termination |= ADW_TERM_CTL_H; 622 break; 623 624 /* TERM_CTL_H: off, TERM_CTL_L: off */ 625 case 0x2: case 0x6: 626 break; 627 } 628 } 629 630 /* 631 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 632 */ 633 scsi_cfg1 &= ~ADW_TERM_CTL; 634 635 /* 636 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 637 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 638 * referenced, because the hardware internally inverts 639 * the Termination High and Low bits if TERM_POL is set. 640 */ 641 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~sc->cfg.termination & ADW_TERM_CTL)); 642 643 /* 644 * Set SCSI_CFG1 Microcode Default Value 645 * 646 * Set filter value and possibly modified termination control 647 * bits in the Microcode SCSI_CFG1 Register Value. 648 * 649 * The microcode will set the SCSI_CFG1 register using this value 650 * after it is started below. 651 */ 652 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, 653 ADW_FLTR_DISABLE | scsi_cfg1); 654 655 /* 656 * Set MEM_CFG Microcode Default Value 657 * 658 * The microcode will set the MEM_CFG register using this value 659 * after it is started below. 660 * 661 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 662 * are defined. 663 * 664 * ASC-3550 has 8KB internal memory. 665 */ 666 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 667 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 668 669 /* 670 * Set SEL_MASK Microcode Default Value 671 * 672 * The microcode will set the SEL_MASK register using this value 673 * after it is started below. 674 */ 675 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 676 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 677 678 679 /* 680 * Set-up the Host->RISC Initiator Command Queue (ICQ). 681 */ 682 683 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 684 return ASC_IERR_NO_CARRIER; 685 } 686 sc->carr_freelist = adw_carrier_phys_kv(sc, 687 ASC_GET_CARRP(sc->icq_sp->next_vpa)); 688 689 /* 690 * The first command issued will be placed in the stopper carrier. 691 */ 692 sc->icq_sp->next_vpa = ASC_CQ_STOPPER; 693 694 /* 695 * Set RISC ICQ physical address start value. 696 */ 697 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); 698 699 /* 700 * Set-up the RISC->Host Initiator Response Queue (IRQ). 701 */ 702 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 703 return ASC_IERR_NO_CARRIER; 704 } 705 sc->carr_freelist = adw_carrier_phys_kv(sc, 706 ASC_GET_CARRP(sc->irq_sp->next_vpa)); 707 708 /* 709 * The first command completed by the RISC will be placed in 710 * the stopper. 711 * 712 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 713 * completed the RISC will set the ASC_RQ_STOPPER bit. 714 */ 715 sc->irq_sp->next_vpa = ASC_CQ_STOPPER; 716 717 /* 718 * Set RISC IRQ physical address start value. 719 */ 720 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); 721 sc->carr_pending_cnt = 0; 722 723 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 724 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 725 726 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 727 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 728 729 /* finally, finally, gentlemen, start your engine */ 730 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 731 732 /* 733 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 734 * Resets should be performed. The RISC has to be running 735 * to issue a SCSI Bus Reset. 736 */ 737 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 738 { 739 /* 740 * If the BIOS Signature is present in memory, restore the 741 * BIOS Handshake Configuration Table and do not perform 742 * a SCSI Bus Reset. 743 */ 744 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 745 0x55AA) { 746 /* 747 * Restore per TID negotiated values. 748 */ 749 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 750 wdtr_able); 751 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 752 sdtr_able); 753 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 754 tagqng_able); 755 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 756 ADW_WRITE_BYTE_LRAM(iot, ioh, 757 ASC_MC_NUMBER_OF_MAX_CMD + tid, 758 max_cmd[tid]); 759 } 760 } else { 761 if (AdvResetCCB(sc) != ADW_TRUE) { 762 warn_code = ASC_WARN_BUSRESET_ERROR; 763 } 764 } 765 } 766 767 return warn_code; 768 } 769 770 /* 771 * Initialize the ASC-38C0800. 772 * 773 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 774 * 775 * For a non-fatal error return a warning code. If there are no warnings 776 * then 0 is returned. 777 */ 778 int 779 AdvInitAsc38C0800Driver(sc) 780 ADW_SOFTC *sc; 781 { 782 bus_space_tag_t iot = sc->sc_iot; 783 bus_space_handle_t ioh = sc->sc_ioh; 784 u_int16_t warn_code; 785 u_int32_t sum; 786 int begin_addr; 787 int end_addr; 788 u_int16_t code_sum; 789 int word; 790 int i, j; 791 int adv_asc38C0800_expanded_size; 792 u_int16_t scsi_cfg1; 793 u_int8_t byte; 794 u_int8_t tid; 795 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 796 0x40-0x8F. */ 797 u_int16_t wdtr_able, sdtr_able, tagqng_able; 798 u_int8_t max_cmd[ADW_MAX_TID + 1]; 799 800 801 warn_code = 0; 802 803 /* 804 * Save the RISC memory BIOS region before writing the microcode. 805 * The BIOS may already be loaded and using its RISC LRAM region 806 * so its region must be saved and restored. 807 * 808 * Note: This code makes the assumption, which is currently true, 809 * that a chip reset does not clear RISC LRAM. 810 */ 811 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 812 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]); 813 } 814 815 /* 816 * Save current per TID negotiated values. 817 */ 818 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 819 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 820 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 821 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 822 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 823 max_cmd[tid]); 824 } 825 826 /* 827 * RAM BIST (RAM Built-In Self Test) 828 * 829 * Address : I/O base + offset 0x38h register (byte). 830 * Function: Bit 7-6(RW) : RAM mode 831 * Normal Mode : 0x00 832 * Pre-test Mode : 0x40 833 * RAM Test Mode : 0x80 834 * Bit 5 : unused 835 * Bit 4(RO) : Done bit 836 * Bit 3-0(RO) : Status 837 * Host Error : 0x08 838 * Int_RAM Error : 0x04 839 * RISC Error : 0x02 840 * SCSI Error : 0x01 841 * No Error : 0x00 842 * 843 * Note: RAM BIST code should be put right here, before loading the 844 * microcode and after saving the RISC memory BIOS region. 845 */ 846 847 /* 848 * LRAM Pre-test 849 * 850 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 851 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 852 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 853 * to NORMAL_MODE, return an error too. 854 */ 855 for (i = 0; i < 2; i++) { 856 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 857 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 858 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 859 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 860 PRE_TEST_VALUE) { 861 return ASC_IERR_BIST_PRE_TEST; 862 } 863 864 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 865 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 866 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 867 != NORMAL_VALUE) { 868 return ASC_IERR_BIST_PRE_TEST; 869 } 870 } 871 872 /* 873 * LRAM Test - It takes about 1.5 ms to run through the test. 874 * 875 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 876 * If Done bit not set or Status not 0, save register byte, set the 877 * err_code, and return an error. 878 */ 879 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 880 AdvSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 881 882 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 883 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 884 /* Get here if Done bit not set or Status not 0. */ 885 return ASC_IERR_BIST_RAM_TEST; 886 } 887 888 /* We need to reset back to normal mode after LRAM test passes. */ 889 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 890 891 /* 892 * Load the Microcode 893 * 894 * Write the microcode image to RISC memory starting at address 0. 895 * 896 */ 897 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 898 899 /* Assume the following compressed format of the microcode buffer: 900 * 901 * 254 word (508 byte) table indexed by byte code followed 902 * by the following byte codes: 903 * 904 * 1-Byte Code: 905 * 00: Emit word 0 in table. 906 * 01: Emit word 1 in table. 907 * . 908 * FD: Emit word 253 in table. 909 * 910 * Multi-Byte Code: 911 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 912 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 913 */ 914 word = 0; 915 for (i = 253 * 2; i < adv_asc38C0800_mcode_size; i++) { 916 if (adv_asc38C0800_mcode[i] == 0xff) { 917 for (j = 0; j < adv_asc38C0800_mcode[i + 1]; j++) { 918 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 919 (((u_int16_t) 920 adv_asc38C0800_mcode[i + 3] << 8) | 921 adv_asc38C0800_mcode[i + 2])); 922 word++; 923 } 924 i += 3; 925 } else if (adv_asc38C0800_mcode[i] == 0xfe) { 926 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 927 adv_asc38C0800_mcode[i + 2] << 8) | 928 adv_asc38C0800_mcode[i + 1])); 929 i += 2; 930 word++; 931 } else { 932 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 933 adv_asc38C0800_mcode[(adv_asc38C0800_mcode[i] * 2) + 1] << 8) | 934 adv_asc38C0800_mcode[adv_asc38C0800_mcode[i] * 2])); 935 word++; 936 } 937 } 938 939 /* 940 * Set 'word' for later use to clear the rest of memory and save 941 * the expanded mcode size. 942 */ 943 word *= 2; 944 adv_asc38C0800_expanded_size = word; 945 946 /* 947 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 948 */ 949 for (; word < ADV_38C0800_MEMSIZE; word += 2) { 950 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 951 } 952 953 /* 954 * Verify the microcode checksum. 955 */ 956 sum = 0; 957 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 958 959 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2) { 960 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 961 } 962 963 if (sum != adv_asc38C0800_mcode_chksum) { 964 return ASC_IERR_MCODE_CHKSUM; 965 } 966 967 /* 968 * Restore the RISC memory BIOS region. 969 */ 970 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 971 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 972 bios_mem[i]); 973 } 974 975 /* 976 * Calculate and write the microcode code checksum to the microcode 977 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 978 */ 979 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 980 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 981 code_sum = 0; 982 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 983 for (word = begin_addr; word < end_addr; word += 2) { 984 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 985 } 986 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 987 988 /* 989 * Read microcode version and date. 990 */ 991 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 992 sc->cfg.mcode_date); 993 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 994 sc->cfg.mcode_version); 995 996 /* 997 * Set the chip type to indicate the ASC38C0800. 998 */ 999 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 1000 1001 /* 1002 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 1003 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 1004 * cable detection and then we are able to read C_DET[3:0]. 1005 * 1006 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 1007 * Microcode Default Value' section below. 1008 */ 1009 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1010 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 1011 scsi_cfg1 | ADW_DIS_TERM_DRV); 1012 1013 /* 1014 * If the PCI Configuration Command Register "Parity Error Response 1015 * Control" Bit was clear (0), then set the microcode variable 1016 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 1017 * to ignore DMA parity errors. 1018 */ 1019 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 1020 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1021 word |= CONTROL_FLAG_IGNORE_PERR; 1022 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1023 } 1024 1025 /* 1026 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 1027 * START_CTL_TH [3:2] bits for the default FIFO threshold. 1028 * 1029 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 1030 * 1031 * For DMA Errata #4 set the BC_THRESH_ENB bit. 1032 */ 1033 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 1034 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 1035 1036 /* 1037 * Microcode operating variables for WDTR, SDTR, and command tag 1038 * queuing will be set in AdvInquiryHandling() based on what a 1039 * device reports it is capable of in Inquiry byte 7. 1040 * 1041 * If SCSI Bus Resets have been disabled, then directly set 1042 * SDTR and WDTR from the EEPROM configuration. This will allow 1043 * the BIOS and warm boot to work without a SCSI bus hang on 1044 * the Inquiry caused by host and target mismatched DTR values. 1045 * Without the SCSI Bus Reset, before an Inquiry a device can't 1046 * be assumed to be in Asynchronous, Narrow mode. 1047 */ 1048 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 1049 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, sc->wdtr_able); 1050 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sc->sdtr_able); 1051 } 1052 1053 /* 1054 * Set microcode operating variables for DISC and SDTR_SPEED1, 1055 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 1056 * configuration values. 1057 * 1058 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1059 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1060 * without determining here whether the device supports SDTR. 1061 */ 1062 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 1063 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, sc->sdtr_speed1); 1064 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, sc->sdtr_speed2); 1065 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, sc->sdtr_speed3); 1066 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, sc->sdtr_speed4); 1067 1068 /* 1069 * Set SCSI_CFG0 Microcode Default Value. 1070 * 1071 * The microcode will set the SCSI_CFG0 register using this value 1072 * after it is started below. 1073 */ 1074 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 1075 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 1076 ADW_OUR_ID_EN | sc->chip_scsi_id); 1077 1078 /* 1079 * Determine SCSI_CFG1 Microcode Default Value. 1080 * 1081 * The microcode will set the SCSI_CFG1 register using this value 1082 * after it is started below. 1083 */ 1084 1085 /* Read current SCSI_CFG1 Register value. */ 1086 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1087 1088 /* 1089 * If the internal narrow cable is reversed all of the SCSI_CTRL 1090 * register signals will be set. Check for and return an error if 1091 * this condition is found. 1092 */ 1093 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1094 0x3F07) { 1095 return ASC_IERR_REVERSED_CABLE; 1096 } 1097 1098 /* 1099 * All kind of combinations of devices attached to one of four connectors 1100 * are acceptable except HVD device attached. For example, LVD device can 1101 * be attached to SE connector while SE device attached to LVD connector. 1102 * If LVD device attached to SE connector, it only runs up to Ultra speed. 1103 * 1104 * If an HVD device is attached to one of LVD connectors, return an error. 1105 * However, there is no way to detect HVD device attached to SE connectors. 1106 */ 1107 if (scsi_cfg1 & ADW_HVD) { 1108 return ASC_IERR_HVD_DEVICE; 1109 } 1110 1111 /* 1112 * If either SE or LVD automatic termination control is enabled, then 1113 * set the termination value based on a table listed in a_condor.h. 1114 * 1115 * If manual termination was specified with an EEPROM setting then 1116 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to 1117 * be 'ored' into SCSI_CFG1. 1118 */ 1119 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1120 /* SE automatic termination control is enabled. */ 1121 switch(scsi_cfg1 & ADW_C_DET_SE) { 1122 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1123 case 0x1: case 0x2: case 0x3: 1124 sc->cfg.termination |= ADW_TERM_SE; 1125 break; 1126 1127 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1128 case 0x0: 1129 sc->cfg.termination |= ADW_TERM_SE_HI; 1130 break; 1131 } 1132 } 1133 1134 if ((sc->cfg.termination & ADW_TERM_LVD) == 0) { 1135 /* LVD automatic termination control is enabled. */ 1136 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1137 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1138 case 0x4: case 0x8: case 0xC: 1139 sc->cfg.termination |= ADW_TERM_LVD; 1140 break; 1141 1142 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1143 case 0x0: 1144 break; 1145 } 1146 } 1147 1148 /* 1149 * Clear any set TERM_SE and TERM_LVD bits. 1150 */ 1151 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1152 1153 /* 1154 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1155 */ 1156 scsi_cfg1 |= (~sc->cfg.termination & 0xF0); 1157 1158 /* 1159 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits 1160 * and set possibly modified termination control bits in the Microcode 1161 * SCSI_CFG1 Register Value. 1162 */ 1163 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1164 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1165 1166 /* 1167 * Set SCSI_CFG1 Microcode Default Value 1168 * 1169 * Set possibly modified termination control and reset DIS_TERM_DRV 1170 * bits in the Microcode SCSI_CFG1 Register Value. 1171 * 1172 * The microcode will set the SCSI_CFG1 register using this value 1173 * after it is started below. 1174 */ 1175 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1176 1177 /* 1178 * Set MEM_CFG Microcode Default Value 1179 * 1180 * The microcode will set the MEM_CFG register using this value 1181 * after it is started below. 1182 * 1183 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1184 * are defined. 1185 * 1186 * ASC-38C0800 has 16KB internal memory. 1187 */ 1188 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 1189 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1190 1191 /* 1192 * Set SEL_MASK Microcode Default Value 1193 * 1194 * The microcode will set the SEL_MASK register using this value 1195 * after it is started below. 1196 */ 1197 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 1198 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1199 1200 1201 /* 1202 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1203 */ 1204 1205 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1206 return ASC_IERR_NO_CARRIER; 1207 } 1208 sc->carr_freelist = adw_carrier_phys_kv(sc, 1209 ASC_GET_CARRP(sc->icq_sp->next_vpa)); 1210 1211 1212 /* 1213 * The first command issued will be placed in the stopper carrier. 1214 */ 1215 sc->icq_sp->next_vpa = ASC_CQ_STOPPER; 1216 1217 /* 1218 * Set RISC ICQ physical address start value. 1219 */ 1220 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); 1221 1222 /* 1223 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1224 */ 1225 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1226 return ASC_IERR_NO_CARRIER; 1227 } 1228 sc->carr_freelist = adw_carrier_phys_kv(sc, 1229 ASC_GET_CARRP(sc->irq_sp->next_vpa)); 1230 1231 /* 1232 * The first command completed by the RISC will be placed in 1233 * the stopper. 1234 * 1235 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 1236 * completed the RISC will set the ASC_RQ_STOPPER bit. 1237 */ 1238 sc->irq_sp->next_vpa = ASC_CQ_STOPPER; 1239 1240 /* 1241 * Set RISC IRQ physical address start value. 1242 */ 1243 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); 1244 sc->carr_pending_cnt = 0; 1245 1246 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1247 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1248 /* 1249 * Note: Don't remove the use of a temporary variable in 1250 * the following code, otherwise some C compiler 1251 * might turn the following lines into a no-op. 1252 */ 1253 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 1254 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1255 1256 /* finally, finally, gentlemen, start your engine */ 1257 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1258 1259 /* 1260 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1261 * Resets should be performed. The RISC has to be running 1262 * to issue a SCSI Bus Reset. 1263 */ 1264 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1265 /* 1266 * If the BIOS Signature is present in memory, restore the 1267 * BIOS Handshake Configuration Table and do not perform 1268 * a SCSI Bus Reset. 1269 */ 1270 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 1271 0x55AA) { 1272 /* 1273 * Restore per TID negotiated values. 1274 */ 1275 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 1276 wdtr_able); 1277 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 1278 sdtr_able); 1279 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1280 tagqng_able); 1281 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1282 ADW_WRITE_BYTE_LRAM(iot, ioh, 1283 ASC_MC_NUMBER_OF_MAX_CMD + tid, 1284 max_cmd[tid]); 1285 } 1286 } else { 1287 if (AdvResetCCB(sc) != ADW_TRUE) { 1288 warn_code = ASC_WARN_BUSRESET_ERROR; 1289 } 1290 } 1291 } 1292 1293 return warn_code; 1294 } 1295 1296 1297 /* 1298 * Initialize the ASC-38C1600. 1299 * 1300 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 1301 * 1302 * For a non-fatal error return a warning code. If there are no warnings 1303 * then 0 is returned. 1304 */ 1305 int 1306 AdvInitAsc38C1600Driver(sc) 1307 ADW_SOFTC *sc; 1308 { 1309 bus_space_tag_t iot = sc->sc_iot; 1310 bus_space_handle_t ioh = sc->sc_ioh; 1311 u_int16_t warn_code; 1312 u_int32_t sum; 1313 int begin_addr; 1314 int end_addr; 1315 u_int16_t code_sum; 1316 int word; 1317 int i, j; 1318 int adv_asc38C1600_expanded_size; 1319 u_int16_t scsi_cfg1; 1320 u_int8_t byte; 1321 u_int8_t tid; 1322 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 1323 0x40-0x8F. */ 1324 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1325 u_int8_t max_cmd[ADW_MAX_TID + 1]; 1326 1327 1328 warn_code = 0; 1329 1330 1331 /* 1332 * Save the RISC memory BIOS region before writing the microcode. 1333 * The BIOS may already be loaded and using its RISC LRAM region 1334 * so its region must be saved and restored. 1335 * 1336 * Note: This code makes the assumption, which is currently true, 1337 * that a chip reset does not clear RISC LRAM. 1338 */ 1339 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 1340 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]); 1341 } 1342 1343 /* 1344 * Save current per TID negotiated values. 1345 */ 1346 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 1347 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 1348 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, ppr_able); 1349 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 1350 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1351 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 1352 max_cmd[tid]); 1353 } 1354 1355 /* 1356 * RAM BIST (RAM Built-In Self Test) 1357 * 1358 * Address : I/O base + offset 0x38h register (byte). 1359 * Function: Bit 7-6(RW) : RAM mode 1360 * Normal Mode : 0x00 1361 * Pre-test Mode : 0x40 1362 * RAM Test Mode : 0x80 1363 * Bit 5 : unused 1364 * Bit 4(RO) : Done bit 1365 * Bit 3-0(RO) : Status 1366 * Host Error : 0x08 1367 * Int_RAM Error : 0x04 1368 * RISC Error : 0x02 1369 * SCSI Error : 0x01 1370 * No Error : 0x00 1371 * 1372 * Note: RAM BIST code should be put right here, before loading the 1373 * microcode and after saving the RISC memory BIOS region. 1374 */ 1375 1376 /* 1377 * LRAM Pre-test 1378 * 1379 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 1380 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 1381 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 1382 * to NORMAL_MODE, return an error too. 1383 */ 1384 for (i = 0; i < 2; i++) { 1385 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 1386 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 1387 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1388 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 1389 PRE_TEST_VALUE) { 1390 return ASC_IERR_BIST_PRE_TEST; 1391 } 1392 1393 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1394 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 1395 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1396 != NORMAL_VALUE) { 1397 return ASC_IERR_BIST_PRE_TEST; 1398 } 1399 } 1400 1401 /* 1402 * LRAM Test - It takes about 1.5 ms to run through the test. 1403 * 1404 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 1405 * If Done bit not set or Status not 0, save register byte, set the 1406 * err_code, and return an error. 1407 */ 1408 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1409 AdvSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 1410 1411 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1412 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 1413 /* Get here if Done bit not set or Status not 0. */ 1414 return ASC_IERR_BIST_RAM_TEST; 1415 } 1416 1417 /* We need to reset back to normal mode after LRAM test passes. */ 1418 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1419 1420 1421 /* 1422 * Load the Microcode 1423 * 1424 * Write the microcode image to RISC memory starting at address 0. 1425 * 1426 */ 1427 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1428 1429 /* Assume the following compressed format of the microcode buffer: 1430 * 1431 * 254 word (508 byte) table indexed by byte code followed 1432 * by the following byte codes: 1433 * 1434 * 1-Byte Code: 1435 * 00: Emit word 0 in table. 1436 * 01: Emit word 1 in table. 1437 * . 1438 * FD: Emit word 253 in table. 1439 * 1440 * Multi-Byte Code: 1441 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1442 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1443 */ 1444 word = 0; 1445 for (i = 253 * 2; i < adv_asc38C1600_mcode_size; i++) { 1446 if (adv_asc38C1600_mcode[i] == 0xff) { 1447 for (j = 0; j < adv_asc38C1600_mcode[i + 1]; j++) { 1448 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1449 (((u_int16_t) 1450 adv_asc38C1600_mcode[i + 3] << 8) | 1451 adv_asc38C1600_mcode[i + 2])); 1452 word++; 1453 } 1454 i += 3; 1455 } else if (adv_asc38C1600_mcode[i] == 0xfe) { 1456 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1457 adv_asc38C1600_mcode[i + 2] << 8) | 1458 adv_asc38C1600_mcode[i + 1])); 1459 i += 2; 1460 word++; 1461 } else { 1462 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1463 adv_asc38C1600_mcode[(adv_asc38C1600_mcode[i] * 2) + 1] << 8) | 1464 adv_asc38C1600_mcode[adv_asc38C1600_mcode[i] * 2])); 1465 word++; 1466 } 1467 } 1468 1469 /* 1470 * Set 'word' for later use to clear the rest of memory and save 1471 * the expanded mcode size. 1472 */ 1473 word *= 2; 1474 adv_asc38C1600_expanded_size = word; 1475 1476 /* 1477 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 1478 */ 1479 for (; word < ADV_38C1600_MEMSIZE; word += 2) { 1480 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1481 } 1482 1483 /* 1484 * Verify the microcode checksum. 1485 */ 1486 sum = 0; 1487 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1488 1489 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2) { 1490 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1491 } 1492 1493 if (sum != adv_asc38C1600_mcode_chksum) { 1494 return ASC_IERR_MCODE_CHKSUM; 1495 } 1496 1497 /* 1498 * Restore the RISC memory BIOS region. 1499 */ 1500 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 1501 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 1502 bios_mem[i]); 1503 } 1504 1505 /* 1506 * Calculate and write the microcode code checksum to the microcode 1507 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 1508 */ 1509 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 1510 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 1511 code_sum = 0; 1512 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1513 for (word = begin_addr; word < end_addr; word += 2) { 1514 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1515 } 1516 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 1517 1518 /* 1519 * Read microcode version and date. 1520 */ 1521 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 1522 sc->cfg.mcode_date); 1523 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 1524 sc->cfg.mcode_version); 1525 1526 /* 1527 * Set the chip type to indicate the ASC38C1600. 1528 */ 1529 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); 1530 1531 /* 1532 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 1533 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 1534 * cable detection and then we are able to read C_DET[3:0]. 1535 * 1536 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 1537 * Microcode Default Value' section below. 1538 */ 1539 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1540 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 1541 scsi_cfg1 | ADW_DIS_TERM_DRV); 1542 1543 /* 1544 * If the PCI Configuration Command Register "Parity Error Response 1545 * Control" Bit was clear (0), then set the microcode variable 1546 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 1547 * to ignore DMA parity errors. 1548 */ 1549 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 1550 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1551 word |= CONTROL_FLAG_IGNORE_PERR; 1552 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1553 } 1554 1555 /* 1556 * If the BIOS control flag AIPP (Asynchronous Information 1557 * Phase Protection) disable bit is not set, then set the firmware 1558 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 1559 * AIPP checking and encoding. 1560 */ 1561 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 1562 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1563 word |= CONTROL_FLAG_ENABLE_AIPP; 1564 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1565 } 1566 1567 /* 1568 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 1569 * and START_CTL_TH [3:2]. 1570 */ 1571 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 1572 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 1573 1574 /* 1575 * Microcode operating variables for WDTR, SDTR, and command tag 1576 * queuing will be set in AdvInquiryHandling() based on what a 1577 * device reports it is capable of in Inquiry byte 7. 1578 * 1579 * If SCSI Bus Resets have been disabled, then directly set 1580 * SDTR and WDTR from the EEPROM configuration. This will allow 1581 * the BIOS and warm boot to work without a SCSI bus hang on 1582 * the Inquiry caused by host and target mismatched DTR values. 1583 * Without the SCSI Bus Reset, before an Inquiry a device can't 1584 * be assumed to be in Asynchronous, Narrow mode. 1585 */ 1586 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 1587 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, sc->wdtr_able); 1588 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sc->sdtr_able); 1589 } 1590 1591 /* 1592 * Set microcode operating variables for DISC and SDTR_SPEED1, 1593 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 1594 * configuration values. 1595 * 1596 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1597 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1598 * without determining here whether the device supports SDTR. 1599 */ 1600 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 1601 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, sc->sdtr_speed1); 1602 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, sc->sdtr_speed2); 1603 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, sc->sdtr_speed3); 1604 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, sc->sdtr_speed4); 1605 1606 /* 1607 * Set SCSI_CFG0 Microcode Default Value. 1608 * 1609 * The microcode will set the SCSI_CFG0 register using this value 1610 * after it is started below. 1611 */ 1612 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 1613 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 1614 ADW_OUR_ID_EN | sc->chip_scsi_id); 1615 1616 /* 1617 * Calculate SCSI_CFG1 Microcode Default Value. 1618 * 1619 * The microcode will set the SCSI_CFG1 register using this value 1620 * after it is started below. 1621 * 1622 * Each ASC-38C1600 function has only two cable detect bits. 1623 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1624 */ 1625 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1626 1627 /* 1628 * If the cable is reversed all of the SCSI_CTRL register signals 1629 * will be set. Check for and return an error if this condition is 1630 * found. 1631 */ 1632 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1633 0x3F07) { 1634 return ASC_IERR_REVERSED_CABLE; 1635 } 1636 1637 /* 1638 * Each ASC-38C1600 function has two connectors. Only an HVD device 1639 * can not be connected to either connector. An LVD device or SE device 1640 * may be connected to either connecor. If an SE device is connected, 1641 * then at most Ultra speed (20 Mhz) can be used on both connectors. 1642 * 1643 * If an HVD device is attached, return an error. 1644 */ 1645 if (scsi_cfg1 & ADW_HVD) { 1646 return ASC_IERR_HVD_DEVICE; 1647 } 1648 1649 /* 1650 * Each function in the ASC-38C1600 uses only the SE cable detect and 1651 * termination because there are two connectors for each function. Each 1652 * function may use either LVD or SE mode. Corresponding the SE automatic 1653 * termination control EEPROM bits are used for each function. Each 1654 * function has its own EEPROM. If SE automatic control is enabled for 1655 * the function, then set the termination value based on a table listed 1656 * in a_condor.h. 1657 * 1658 * If manual termination is specified in the EEPROM for the function, 1659 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 1660 * ready to be 'ored' into SCSI_CFG1. 1661 */ 1662 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1663 /* SE automatic termination control is enabled. */ 1664 switch(scsi_cfg1 & ADW_C_DET_SE) { 1665 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1666 case 0x1: case 0x2: case 0x3: 1667 sc->cfg.termination |= ADW_TERM_SE; 1668 break; 1669 1670 case 0x0: 1671 /* !!!!TODO!!!! */ 1672 // if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0) { 1673 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1674 // } 1675 // else 1676 // { 1677 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1678 sc->cfg.termination |= ADW_TERM_SE_HI; 1679 // } 1680 break; 1681 } 1682 } 1683 1684 /* 1685 * Clear any set TERM_SE bits. 1686 */ 1687 scsi_cfg1 &= ~ADW_TERM_SE; 1688 1689 /* 1690 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1691 */ 1692 scsi_cfg1 |= (~sc->cfg.termination & ADW_TERM_SE); 1693 1694 /* 1695 * Clear Big Endian and Terminator Polarity bits and set possibly 1696 * modified termination control bits in the Microcode SCSI_CFG1 1697 * Register Value. 1698 */ 1699 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1700 1701 /* 1702 * Set SCSI_CFG1 Microcode Default Value 1703 * 1704 * Set possibly modified termination control bits in the Microcode 1705 * SCSI_CFG1 Register Value. 1706 * 1707 * The microcode will set the SCSI_CFG1 register using this value 1708 * after it is started below. 1709 */ 1710 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1711 1712 /* 1713 * Set MEM_CFG Microcode Default Value 1714 * 1715 * The microcode will set the MEM_CFG register using this value 1716 * after it is started below. 1717 * 1718 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1719 * are defined. 1720 * 1721 * ASC-38C1600 has 32KB internal memory. 1722 */ 1723 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 1724 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1725 1726 /* 1727 * Set SEL_MASK Microcode Default Value 1728 * 1729 * The microcode will set the SEL_MASK register using this value 1730 * after it is started below. 1731 */ 1732 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 1733 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1734 1735 /* 1736 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1737 */ 1738 1739 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1740 return ASC_IERR_NO_CARRIER; 1741 } 1742 sc->carr_freelist = adw_carrier_phys_kv(sc, 1743 ASC_GET_CARRP(sc->icq_sp->next_vpa)); 1744 1745 /* 1746 * The first command issued will be placed in the stopper carrier. 1747 */ 1748 sc->icq_sp->next_vpa = ASC_CQ_STOPPER; 1749 1750 /* 1751 * Set RISC ICQ physical address start value. Initialize the 1752 * COMMA register to the same value otherwise the RISC will 1753 * prematurely detect a command is available. 1754 */ 1755 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); 1756 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, sc->icq_sp->carr_pa); 1757 1758 /* 1759 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1760 */ 1761 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1762 return ASC_IERR_NO_CARRIER; 1763 } 1764 sc->carr_freelist = adw_carrier_phys_kv(sc, 1765 ASC_GET_CARRP(sc->irq_sp->next_vpa)); 1766 1767 /* 1768 * The first command completed by the RISC will be placed in 1769 * the stopper. 1770 * 1771 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 1772 * completed the RISC will set the ASC_RQ_STOPPER bit. 1773 */ 1774 sc->irq_sp->next_vpa = ASC_CQ_STOPPER; 1775 1776 /* 1777 * Set RISC IRQ physical address start value. 1778 */ 1779 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); 1780 sc->carr_pending_cnt = 0; 1781 1782 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1783 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1784 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 1785 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1786 1787 /* finally, finally, gentlemen, start your engine */ 1788 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1789 1790 /* 1791 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1792 * Resets should be performed. The RISC has to be running 1793 * to issue a SCSI Bus Reset. 1794 */ 1795 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1796 /* 1797 * If the BIOS Signature is present in memory, restore the 1798 * per TID microcode operating variables. 1799 */ 1800 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 1801 0x55AA) { 1802 /* 1803 * Restore per TID negotiated values. 1804 */ 1805 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 1806 wdtr_able); 1807 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 1808 sdtr_able); 1809 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, 1810 ppr_able); 1811 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1812 tagqng_able); 1813 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1814 ADW_WRITE_BYTE_LRAM(iot, ioh, 1815 ASC_MC_NUMBER_OF_MAX_CMD + tid, 1816 max_cmd[tid]); 1817 } 1818 } else { 1819 if (AdvResetCCB(sc) != ADW_TRUE) { 1820 warn_code = ASC_WARN_BUSRESET_ERROR; 1821 } 1822 } 1823 } 1824 1825 return warn_code; 1826 } 1827 1828 1829 /* 1830 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1831 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1832 * all of this is done. 1833 * 1834 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1835 * 1836 * For a non-fatal error return a warning code. If there are no warnings 1837 * then 0 is returned. 1838 * 1839 * Note: Chip is stopped on entry. 1840 */ 1841 int 1842 AdvInitFrom3550EEP(sc) 1843 ADW_SOFTC *sc; 1844 { 1845 bus_space_tag_t iot = sc->sc_iot; 1846 bus_space_handle_t ioh = sc->sc_ioh; 1847 u_int16_t warn_code; 1848 ADW_EEP_3550_CONFIG eep_config; 1849 int i; 1850 1851 1852 warn_code = 0; 1853 1854 /* 1855 * Read the board's EEPROM configuration. 1856 * 1857 * Set default values if a bad checksum is found. 1858 * 1859 * XXX - Don't handle big-endian access to EEPROM yet. 1860 */ 1861 if (AdvGet3550EEPConfig(iot, ioh, &eep_config) != eep_config.check_sum){ 1862 warn_code |= ASC_WARN_EEPROM_CHKSUM; 1863 1864 /* 1865 * Set EEPROM default values. 1866 */ 1867 for (i = 0; i < sizeof(ADW_EEP_3550_CONFIG); i++) { 1868 *((u_int8_t *) &eep_config + i) = 1869 *((u_int8_t *) &Default_3550_EEPROM_Config + i); 1870 } 1871 1872 /* 1873 * Assume the 6 byte board serial number that was read 1874 * from EEPROM is correct even if the EEPROM checksum 1875 * failed. 1876 */ 1877 eep_config.serial_number_word3 = 1878 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 1879 1880 eep_config.serial_number_word2 = 1881 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 1882 1883 eep_config.serial_number_word1 = 1884 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 1885 1886 AdvSet3550EEPConfig(iot, ioh, &eep_config); 1887 } 1888 /* 1889 * Set sc and sc->cfg variables from the EEPROM configuration 1890 * that was read. 1891 * 1892 * This is the mapping of EEPROM fields to Adv Library fields. 1893 */ 1894 sc->wdtr_able = eep_config.wdtr_able; 1895 sc->sdtr_able = eep_config.sdtr_able; 1896 sc->ultra_able = eep_config.ultra_able; 1897 sc->tagqng_able = eep_config.tagqng_able; 1898 sc->cfg.disc_enable = eep_config.disc_enable; 1899 sc->max_host_qng = eep_config.max_host_qng; 1900 sc->max_dvc_qng = eep_config.max_dvc_qng; 1901 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 1902 sc->start_motor = eep_config.start_motor; 1903 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 1904 sc->bios_ctrl = eep_config.bios_ctrl; 1905 sc->no_scam = eep_config.scam_tolerant; 1906 sc->cfg.serial1 = eep_config.serial_number_word1; 1907 sc->cfg.serial2 = eep_config.serial_number_word2; 1908 sc->cfg.serial3 = eep_config.serial_number_word3; 1909 1910 /* 1911 * Set the host maximum queuing (max. 253, min. 16) and the per device 1912 * maximum queuing (max. 63, min. 4). 1913 */ 1914 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 1915 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1916 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) 1917 { 1918 /* If the value is zero, assume it is uninitialized. */ 1919 if (eep_config.max_host_qng == 0) { 1920 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1921 } else { 1922 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 1923 } 1924 } 1925 1926 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 1927 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1928 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 1929 /* If the value is zero, assume it is uninitialized. */ 1930 if (eep_config.max_dvc_qng == 0) { 1931 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1932 } else { 1933 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 1934 } 1935 } 1936 1937 /* 1938 * If 'max_dvc_qng' is greater than 'max_host_qng', then 1939 * set 'max_dvc_qng' to 'max_host_qng'. 1940 */ 1941 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 1942 eep_config.max_dvc_qng = eep_config.max_host_qng; 1943 } 1944 1945 /* 1946 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 1947 * values based on possibly adjusted EEPROM values. 1948 */ 1949 sc->max_host_qng = eep_config.max_host_qng; 1950 sc->max_dvc_qng = eep_config.max_dvc_qng; 1951 1952 1953 /* 1954 * If the EEPROM 'termination' field is set to automatic (0), then set 1955 * the ADV_DVC_CFG 'termination' field to automatic also. 1956 * 1957 * If the termination is specified with a non-zero 'termination' 1958 * value check that a legal value is set and set the ADV_DVC_CFG 1959 * 'termination' field appropriately. 1960 */ 1961 1962 sc->cfg.termination = 0; /* auto termination */ 1963 switch(eep_config.termination) { 1964 case 3: 1965 /* Enable manual control with low on / high on. */ 1966 sc->cfg.termination |= ADW_TERM_CTL_L; 1967 case 2: 1968 /* Enable manual control with low off / high on. */ 1969 sc->cfg.termination |= ADW_TERM_CTL_H; 1970 case 1: 1971 /* Enable manual control with low off / high off. */ 1972 sc->cfg.termination |= ADW_TERM_CTL_SEL; 1973 case 0: 1974 break; 1975 default: 1976 warn_code |= ASC_WARN_EEPROM_TERMINATION; 1977 } 1978 1979 return warn_code; 1980 } 1981 1982 1983 /* 1984 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1985 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1986 * all of this is done. 1987 * 1988 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1989 * 1990 * For a non-fatal error return a warning code. If there are no warnings 1991 * then 0 is returned. 1992 * 1993 * Note: Chip is stopped on entry. 1994 */ 1995 int 1996 AdvInitFrom38C0800EEP(sc) 1997 ADW_SOFTC *sc; 1998 { 1999 bus_space_tag_t iot = sc->sc_iot; 2000 bus_space_handle_t ioh = sc->sc_ioh; 2001 u_int16_t warn_code; 2002 ADW_EEP_38C0800_CONFIG eep_config; 2003 int i; 2004 u_int8_t tid, termination; 2005 u_int16_t sdtr_speed = 0; 2006 2007 2008 warn_code = 0; 2009 2010 /* 2011 * Read the board's EEPROM configuration. 2012 * 2013 * Set default values if a bad checksum is found. 2014 */ 2015 if (AdvGet38C0800EEPConfig(iot, ioh, &eep_config) != 2016 eep_config.check_sum) { 2017 warn_code |= ASC_WARN_EEPROM_CHKSUM; 2018 2019 /* 2020 * Set EEPROM default values. 2021 */ 2022 for (i = 0; i < sizeof(ADW_EEP_38C0800_CONFIG); i++) { 2023 *((u_int8_t *) &eep_config + i) = 2024 *((u_int8_t *)&Default_38C0800_EEPROM_Config+i); 2025 } 2026 2027 /* 2028 * Assume the 6 byte board serial number that was read 2029 * from EEPROM is correct even if the EEPROM checksum 2030 * failed. 2031 */ 2032 eep_config.serial_number_word3 = 2033 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 2034 2035 eep_config.serial_number_word2 = 2036 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 2037 2038 eep_config.serial_number_word1 = 2039 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 2040 2041 AdvSet38C0800EEPConfig(iot, ioh, &eep_config); 2042 } 2043 /* 2044 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 2045 * EEPROM configuration that was read. 2046 * 2047 * This is the mapping of EEPROM fields to Adv Library fields. 2048 */ 2049 sc->wdtr_able = eep_config.wdtr_able; 2050 sc->sdtr_speed1 = eep_config.sdtr_speed1; 2051 sc->sdtr_speed2 = eep_config.sdtr_speed2; 2052 sc->sdtr_speed3 = eep_config.sdtr_speed3; 2053 sc->sdtr_speed4 = eep_config.sdtr_speed4; 2054 sc->tagqng_able = eep_config.tagqng_able; 2055 sc->cfg.disc_enable = eep_config.disc_enable; 2056 sc->max_host_qng = eep_config.max_host_qng; 2057 sc->max_dvc_qng = eep_config.max_dvc_qng; 2058 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 2059 sc->start_motor = eep_config.start_motor; 2060 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 2061 sc->bios_ctrl = eep_config.bios_ctrl; 2062 sc->no_scam = eep_config.scam_tolerant; 2063 sc->cfg.serial1 = eep_config.serial_number_word1; 2064 sc->cfg.serial2 = eep_config.serial_number_word2; 2065 sc->cfg.serial3 = eep_config.serial_number_word3; 2066 2067 /* 2068 * For every Target ID if any of its 'sdtr_speed[1234]' bits 2069 * are set, then set an 'sdtr_able' bit for it. 2070 */ 2071 sc->sdtr_able = 0; 2072 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2073 if (tid == 0) { 2074 sdtr_speed = sc->sdtr_speed1; 2075 } else if (tid == 4) { 2076 sdtr_speed = sc->sdtr_speed2; 2077 } else if (tid == 8) { 2078 sdtr_speed = sc->sdtr_speed3; 2079 } else if (tid == 12) { 2080 sdtr_speed = sc->sdtr_speed4; 2081 } 2082 if (sdtr_speed & ADW_MAX_TID) { 2083 sc->sdtr_able |= (1 << tid); 2084 } 2085 sdtr_speed >>= 4; 2086 } 2087 2088 /* 2089 * Set the host maximum queuing (max. 253, min. 16) and the per device 2090 * maximum queuing (max. 63, min. 4). 2091 */ 2092 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 2093 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2094 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 2095 /* If the value is zero, assume it is uninitialized. */ 2096 if (eep_config.max_host_qng == 0) { 2097 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2098 } else { 2099 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 2100 } 2101 } 2102 2103 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 2104 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2105 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 2106 /* If the value is zero, assume it is uninitialized. */ 2107 if (eep_config.max_dvc_qng == 0) { 2108 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2109 } else { 2110 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 2111 } 2112 } 2113 2114 /* 2115 * If 'max_dvc_qng' is greater than 'max_host_qng', then 2116 * set 'max_dvc_qng' to 'max_host_qng'. 2117 */ 2118 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 2119 eep_config.max_dvc_qng = eep_config.max_host_qng; 2120 } 2121 2122 /* 2123 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 2124 * values based on possibly adjusted EEPROM values. 2125 */ 2126 sc->max_host_qng = eep_config.max_host_qng; 2127 sc->max_dvc_qng = eep_config.max_dvc_qng; 2128 2129 /* 2130 * If the EEPROM 'termination' field is set to automatic (0), then set 2131 * the ADV_DVC_CFG 'termination' field to automatic also. 2132 * 2133 * If the termination is specified with a non-zero 'termination' 2134 * value check that a legal value is set and set the ADV_DVC_CFG 2135 * 'termination' field appropriately. 2136 */ 2137 2138 switch(eep_config.termination_se) { 2139 case 0: 2140 /* auto termination for SE */ 2141 termination = 0; 2142 break; 2143 case 1: 2144 /* Enable manual control with low off / high off. */ 2145 termination = 0; 2146 break; 2147 case 2: 2148 /* Enable manual control with low off / high on. */ 2149 termination = ADW_TERM_SE_HI; 2150 break; 2151 case 3: 2152 /* Enable manual control with low on / high on. */ 2153 termination = ADW_TERM_SE; 2154 break; 2155 default: 2156 /* 2157 * The EEPROM 'termination_se' field contains a bad value. 2158 * Use automatic termination instead. 2159 */ 2160 termination = 0; 2161 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2162 } 2163 2164 switch(eep_config.termination_lvd) { 2165 case 0: 2166 /* auto termination for LVD */ 2167 sc->cfg.termination = termination; 2168 break; 2169 case 1: 2170 /* Enable manual control with low off / high off. */ 2171 sc->cfg.termination = termination; 2172 break; 2173 case 2: 2174 /* Enable manual control with low off / high on. */ 2175 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 2176 break; 2177 case 3: 2178 /* Enable manual control with low on / high on. */ 2179 sc->cfg.termination = termination | ADW_TERM_LVD; 2180 break; 2181 default: 2182 /* 2183 * The EEPROM 'termination_lvd' field contains a bad value. 2184 * Use automatic termination instead. 2185 */ 2186 sc->cfg.termination = termination; 2187 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2188 } 2189 2190 return warn_code; 2191 } 2192 2193 2194 /* 2195 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 2196 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 2197 * all of this is done. 2198 * 2199 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 2200 * 2201 * For a non-fatal error return a warning code. If there are no warnings 2202 * then 0 is returned. 2203 * 2204 * Note: Chip is stopped on entry. 2205 */ 2206 int 2207 AdvInitFrom38C1600EEP(sc) 2208 ADW_SOFTC *sc; 2209 { 2210 bus_space_tag_t iot = sc->sc_iot; 2211 bus_space_handle_t ioh = sc->sc_ioh; 2212 u_int16_t warn_code; 2213 ADW_EEP_38C1600_CONFIG eep_config; 2214 int i; 2215 u_int8_t tid, termination; 2216 u_int16_t sdtr_speed = 0; 2217 2218 2219 warn_code = 0; 2220 2221 /* 2222 * Read the board's EEPROM configuration. 2223 * 2224 * Set default values if a bad checksum is found. 2225 */ 2226 if (AdvGet38C1600EEPConfig(iot, ioh, &eep_config) != 2227 eep_config.check_sum) { 2228 warn_code |= ASC_WARN_EEPROM_CHKSUM; 2229 2230 /* 2231 * Set EEPROM default values. 2232 */ 2233 for (i = 0; i < sizeof(ADW_EEP_38C1600_CONFIG); i++) { 2234 /* !!!!TODO!!!! */ 2235 // if (i == 1 && ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 2236 if (i == 1 ) { 2237 /* 2238 * Set Function 1 EEPROM Word 0 MSB 2239 * 2240 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11) 2241 * EEPROM bits. 2242 * 2243 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and 2244 * old Mac system booting problem. The Expansion ROM must 2245 * be disabled in Function 1 for these systems. 2246 * 2247 */ 2248 *((u_int8_t *) &eep_config + i) = 2249 ((*((u_int8_t *) &Default_38C1600_EEPROM_Config + i)) & 2250 (~(((ADW_EEPROM_BIOS_ENABLE | ADW_EEPROM_INTAB) >> 8) & 2251 0xFF))); 2252 2253 /* 2254 * Set the INTAB (bit 11) if the GPIO 0 input 2255 * indicates the Function 1 interrupt line is 2256 * wired to INTA. 2257 * 2258 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 2259 * 1 - Function 1 interrupt line wired to INT A. 2260 * 0 - Function 1 interrupt line wired to INT B. 2261 * 2262 * Note: Adapter boards always have Function 0 2263 * wired to INTA. 2264 * Put all 5 GPIO bits in input mode and then 2265 * read their input values. 2266 */ 2267 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2268 IOPB_GPIO_CNTL, 0); 2269 if (ADW_READ_BYTE_REGISTER(iot, ioh, 2270 IOPB_GPIO_DATA) & 0x01) { 2271 /* Function 1 interrupt wired to INTA; 2272 Set EEPROM bit. */ 2273 *((u_int8_t *) &eep_config + i) |= 2274 ((ADW_EEPROM_INTAB >> 8) &0xFF); 2275 } 2276 } else { 2277 *((u_int8_t *)&eep_config + i) = 2278 *((u_int8_t *)&Default_38C1600_EEPROM_Config+i); 2279 } 2280 } 2281 2282 /* 2283 * Assume the 6 byte board serial number that was read 2284 * from EEPROM is correct even if the EEPROM checksum 2285 * failed. 2286 */ 2287 eep_config.serial_number_word3 = 2288 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 2289 2290 eep_config.serial_number_word2 = 2291 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 2292 2293 eep_config.serial_number_word1 = 2294 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 2295 2296 AdvSet38C1600EEPConfig(iot, ioh, &eep_config); 2297 } 2298 2299 /* 2300 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 2301 * EEPROM configuration that was read. 2302 * 2303 * This is the mapping of EEPROM fields to Adv Library fields. 2304 */ 2305 sc->wdtr_able = eep_config.wdtr_able; 2306 sc->sdtr_speed1 = eep_config.sdtr_speed1; 2307 sc->sdtr_speed2 = eep_config.sdtr_speed2; 2308 sc->sdtr_speed3 = eep_config.sdtr_speed3; 2309 sc->sdtr_speed4 = eep_config.sdtr_speed4; 2310 sc->ppr_able = 0; 2311 sc->tagqng_able = eep_config.tagqng_able; 2312 sc->cfg.disc_enable = eep_config.disc_enable; 2313 sc->max_host_qng = eep_config.max_host_qng; 2314 sc->max_dvc_qng = eep_config.max_dvc_qng; 2315 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 2316 sc->start_motor = eep_config.start_motor; 2317 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 2318 sc->bios_ctrl = eep_config.bios_ctrl; 2319 sc->no_scam = eep_config.scam_tolerant; 2320 2321 /* 2322 * For every Target ID if any of its 'sdtr_speed[1234]' bits 2323 * are set, then set an 'sdtr_able' bit for it. 2324 */ 2325 sc->sdtr_able = 0; 2326 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2327 if (tid == 0) { 2328 sdtr_speed = sc->sdtr_speed1; 2329 } else if (tid == 4) { 2330 sdtr_speed = sc->sdtr_speed2; 2331 } else if (tid == 8) { 2332 sdtr_speed = sc->sdtr_speed3; 2333 } else if (tid == 12) { 2334 sdtr_speed = sc->sdtr_speed4; 2335 } 2336 if (sdtr_speed & ADW_MAX_TID) { 2337 sc->sdtr_able |= (1 << tid); 2338 } 2339 sdtr_speed >>= 4; 2340 } 2341 2342 /* 2343 * Set the host maximum queuing (max. 253, min. 16) and the per device 2344 * maximum queuing (max. 63, min. 4). 2345 */ 2346 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 2347 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2348 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 2349 /* If the value is zero, assume it is uninitialized. */ 2350 if (eep_config.max_host_qng == 0) { 2351 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2352 } else { 2353 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 2354 } 2355 } 2356 2357 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 2358 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2359 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 2360 /* If the value is zero, assume it is uninitialized. */ 2361 if (eep_config.max_dvc_qng == 0) { 2362 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2363 } else { 2364 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 2365 } 2366 } 2367 2368 /* 2369 * If 'max_dvc_qng' is greater than 'max_host_qng', then 2370 * set 'max_dvc_qng' to 'max_host_qng'. 2371 */ 2372 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 2373 eep_config.max_dvc_qng = eep_config.max_host_qng; 2374 } 2375 2376 /* 2377 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 2378 * values based on possibly adjusted EEPROM values. 2379 */ 2380 sc->max_host_qng = eep_config.max_host_qng; 2381 sc->max_dvc_qng = eep_config.max_dvc_qng; 2382 2383 /* 2384 * If the EEPROM 'termination' field is set to automatic (0), then set 2385 * the ASC_DVC_CFG 'termination' field to automatic also. 2386 * 2387 * If the termination is specified with a non-zero 'termination' 2388 * value check that a legal value is set and set the ASC_DVC_CFG 2389 * 'termination' field appropriately. 2390 */ 2391 2392 switch(eep_config.termination_se) { 2393 case 0: /* auto termination for SE */ 2394 termination = 0; 2395 break; 2396 case 1: /* Enable manual control with low off / high off. */ 2397 termination = 0; 2398 break; 2399 case 2: /* Enable manual control with low off / high on. */ 2400 termination = ADW_TERM_SE_HI; 2401 break; 2402 case 3: /* Enable manual control with low on / high on. */ 2403 termination = ADW_TERM_SE; 2404 break; 2405 default: 2406 /* 2407 * The EEPROM 'termination_se' field contains a bad value. 2408 * Use automatic termination instead. 2409 */ 2410 termination = 0; 2411 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2412 } 2413 2414 switch(eep_config.termination_lvd) { 2415 case 0: /* auto termination for LVD */ 2416 sc->cfg.termination = termination; 2417 break; 2418 case 1: /* Enable manual control with low off / high off. */ 2419 sc->cfg.termination = termination; 2420 break; 2421 case 2: /* Enable manual control with low off / high on. */ 2422 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 2423 break; 2424 case 3: /* Enable manual control with low on / high on. */ 2425 sc->cfg.termination = termination | ADW_TERM_LVD; 2426 break; 2427 default: 2428 /* 2429 * The EEPROM 'termination_lvd' field contains a bad value. 2430 * Use automatic termination instead. 2431 */ 2432 sc->cfg.termination = termination; 2433 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2434 } 2435 2436 return warn_code; 2437 } 2438 2439 2440 /* 2441 * Read EEPROM configuration into the specified buffer. 2442 * 2443 * Return a checksum based on the EEPROM configuration read. 2444 */ 2445 static u_int16_t 2446 AdvGet3550EEPConfig(iot, ioh, cfg_buf) 2447 bus_space_tag_t iot; 2448 bus_space_handle_t ioh; 2449 ADW_EEP_3550_CONFIG *cfg_buf; 2450 { 2451 u_int16_t wval, chksum; 2452 u_int16_t *wbuf; 2453 int eep_addr; 2454 2455 2456 wbuf = (u_int16_t *) cfg_buf; 2457 chksum = 0; 2458 2459 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2460 eep_addr < ASC_EEP_DVC_CFG_END; 2461 eep_addr++, wbuf++) { 2462 wval = AdvReadEEPWord(iot, ioh, eep_addr); 2463 chksum += wval; 2464 *wbuf = wval; 2465 } 2466 2467 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2468 wbuf++; 2469 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2470 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2471 eep_addr++, wbuf++) { 2472 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2473 } 2474 2475 return chksum; 2476 } 2477 2478 2479 /* 2480 * Read EEPROM configuration into the specified buffer. 2481 * 2482 * Return a checksum based on the EEPROM configuration read. 2483 */ 2484 static u_int16_t 2485 AdvGet38C0800EEPConfig(iot, ioh, cfg_buf) 2486 bus_space_tag_t iot; 2487 bus_space_handle_t ioh; 2488 ADW_EEP_38C0800_CONFIG *cfg_buf; 2489 { 2490 u_int16_t wval, chksum; 2491 u_int16_t *wbuf; 2492 int eep_addr; 2493 2494 2495 wbuf = (u_int16_t *) cfg_buf; 2496 chksum = 0; 2497 2498 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2499 eep_addr < ASC_EEP_DVC_CFG_END; 2500 eep_addr++, wbuf++) { 2501 wval = AdvReadEEPWord(iot, ioh, eep_addr); 2502 chksum += wval; 2503 *wbuf = wval; 2504 } 2505 2506 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2507 wbuf++; 2508 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2509 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2510 eep_addr++, wbuf++) { 2511 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2512 } 2513 2514 return chksum; 2515 } 2516 2517 2518 /* 2519 * Read EEPROM configuration into the specified buffer. 2520 * 2521 * Return a checksum based on the EEPROM configuration read. 2522 */ 2523 static u_int16_t 2524 AdvGet38C1600EEPConfig(iot, ioh, cfg_buf) 2525 bus_space_tag_t iot; 2526 bus_space_handle_t ioh; 2527 ADW_EEP_38C1600_CONFIG *cfg_buf; 2528 { 2529 u_int16_t wval, chksum; 2530 u_int16_t *wbuf; 2531 int eep_addr; 2532 2533 2534 wbuf = (u_int16_t *) cfg_buf; 2535 chksum = 0; 2536 2537 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2538 eep_addr < ASC_EEP_DVC_CFG_END; 2539 eep_addr++, wbuf++) { 2540 wval = AdvReadEEPWord(iot, ioh, eep_addr); 2541 chksum += wval; 2542 *wbuf = wval; 2543 } 2544 2545 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2546 wbuf++; 2547 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2548 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2549 eep_addr++, wbuf++) { 2550 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2551 } 2552 2553 return chksum; 2554 } 2555 2556 2557 /* 2558 * Read the EEPROM from specified location 2559 */ 2560 static u_int16_t 2561 AdvReadEEPWord(iot, ioh, eep_word_addr) 2562 bus_space_tag_t iot; 2563 bus_space_handle_t ioh; 2564 int eep_word_addr; 2565 { 2566 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2567 ASC_EEP_CMD_READ | eep_word_addr); 2568 AdvWaitEEPCmd(iot, ioh); 2569 2570 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 2571 } 2572 2573 2574 /* 2575 * Wait for EEPROM command to complete 2576 */ 2577 static void 2578 AdvWaitEEPCmd(iot, ioh) 2579 bus_space_tag_t iot; 2580 bus_space_handle_t ioh; 2581 { 2582 int eep_delay_ms; 2583 2584 2585 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 2586 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 2587 ASC_EEP_CMD_DONE) { 2588 break; 2589 } 2590 AdvSleepMilliSecond(1); 2591 } 2592 2593 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 2594 } 2595 2596 2597 /* 2598 * Write the EEPROM from 'cfg_buf'. 2599 */ 2600 static void 2601 AdvSet3550EEPConfig(iot, ioh, cfg_buf) 2602 bus_space_tag_t iot; 2603 bus_space_handle_t ioh; 2604 ADW_EEP_3550_CONFIG *cfg_buf; 2605 { 2606 u_int16_t *wbuf; 2607 u_int16_t addr, chksum; 2608 2609 2610 wbuf = (u_int16_t *) cfg_buf; 2611 chksum = 0; 2612 2613 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2614 AdvWaitEEPCmd(iot, ioh); 2615 2616 /* 2617 * Write EEPROM from word 0 to word 20 2618 */ 2619 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2620 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2621 chksum += *wbuf; 2622 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2623 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2624 ASC_EEP_CMD_WRITE | addr); 2625 AdvWaitEEPCmd(iot, ioh); 2626 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 2627 } 2628 2629 /* 2630 * Write EEPROM checksum at word 21 2631 */ 2632 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2633 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2634 ASC_EEP_CMD_WRITE | addr); 2635 AdvWaitEEPCmd(iot, ioh); 2636 wbuf++; /* skip over check_sum */ 2637 2638 /* 2639 * Write EEPROM OEM name at words 22 to 29 2640 */ 2641 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2642 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2643 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2644 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2645 ASC_EEP_CMD_WRITE | addr); 2646 AdvWaitEEPCmd(iot, ioh); 2647 } 2648 2649 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2650 ASC_EEP_CMD_WRITE_DISABLE); 2651 AdvWaitEEPCmd(iot, ioh); 2652 2653 return; 2654 } 2655 2656 2657 /* 2658 * Write the EEPROM from 'cfg_buf'. 2659 */ 2660 static void 2661 AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) 2662 bus_space_tag_t iot; 2663 bus_space_handle_t ioh; 2664 ADW_EEP_38C0800_CONFIG *cfg_buf; 2665 { 2666 u_int16_t *wbuf; 2667 u_int16_t addr, chksum; 2668 2669 2670 wbuf = (u_int16_t *) cfg_buf; 2671 chksum = 0; 2672 2673 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2674 AdvWaitEEPCmd(iot, ioh); 2675 2676 /* 2677 * Write EEPROM from word 0 to word 20 2678 */ 2679 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2680 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2681 chksum += *wbuf; 2682 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2683 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2684 ASC_EEP_CMD_WRITE | addr); 2685 AdvWaitEEPCmd(iot, ioh); 2686 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 2687 } 2688 2689 /* 2690 * Write EEPROM checksum at word 21 2691 */ 2692 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2693 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2694 ASC_EEP_CMD_WRITE | addr); 2695 AdvWaitEEPCmd(iot, ioh); 2696 wbuf++; /* skip over check_sum */ 2697 2698 /* 2699 * Write EEPROM OEM name at words 22 to 29 2700 */ 2701 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2702 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2703 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2704 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2705 ASC_EEP_CMD_WRITE | addr); 2706 AdvWaitEEPCmd(iot, ioh); 2707 } 2708 2709 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2710 ASC_EEP_CMD_WRITE_DISABLE); 2711 AdvWaitEEPCmd(iot, ioh); 2712 2713 return; 2714 } 2715 2716 2717 /* 2718 * Write the EEPROM from 'cfg_buf'. 2719 */ 2720 static void 2721 AdvSet38C1600EEPConfig(iot, ioh, cfg_buf) 2722 bus_space_tag_t iot; 2723 bus_space_handle_t ioh; 2724 ADW_EEP_38C1600_CONFIG *cfg_buf; 2725 { 2726 u_int16_t *wbuf; 2727 u_int16_t addr, chksum; 2728 2729 2730 wbuf = (u_int16_t *) cfg_buf; 2731 chksum = 0; 2732 2733 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2734 AdvWaitEEPCmd(iot, ioh); 2735 2736 /* 2737 * Write EEPROM from word 0 to word 20 2738 */ 2739 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2740 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2741 chksum += *wbuf; 2742 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2743 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2744 ASC_EEP_CMD_WRITE | addr); 2745 AdvWaitEEPCmd(iot, ioh); 2746 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 2747 } 2748 2749 /* 2750 * Write EEPROM checksum at word 21 2751 */ 2752 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2753 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2754 ASC_EEP_CMD_WRITE | addr); 2755 AdvWaitEEPCmd(iot, ioh); 2756 wbuf++; /* skip over check_sum */ 2757 2758 /* 2759 * Write EEPROM OEM name at words 22 to 29 2760 */ 2761 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2762 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2763 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2764 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2765 ASC_EEP_CMD_WRITE | addr); 2766 AdvWaitEEPCmd(iot, ioh); 2767 } 2768 2769 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2770 ASC_EEP_CMD_WRITE_DISABLE); 2771 AdvWaitEEPCmd(iot, ioh); 2772 2773 return; 2774 } 2775 2776 2777 /* 2778 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 2779 * 2780 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 2781 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 2782 * RISC to notify it a new command is ready to be executed. 2783 * 2784 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 2785 * set to SCSI_MAX_RETRY. 2786 * 2787 * Return: 2788 * ADW_SUCCESS(1) - The request was successfully queued. 2789 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 2790 * request completes. 2791 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 2792 * host IC error. 2793 */ 2794 int 2795 AdvExeScsiQueue(sc, scsiq) 2796 ADW_SOFTC *sc; 2797 ADW_SCSI_REQ_Q *scsiq; 2798 { 2799 bus_space_tag_t iot = sc->sc_iot; 2800 bus_space_handle_t ioh = sc->sc_ioh; 2801 ADW_CCB *ccb; 2802 long req_size; 2803 u_int32_t req_paddr; 2804 ADW_CARRIER *new_carrp; 2805 2806 /* 2807 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 2808 */ 2809 if (scsiq->target_id > ADW_MAX_TID) { 2810 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 2811 scsiq->done_status = QD_WITH_ERROR; 2812 return ADW_ERROR; 2813 } 2814 2815 /* 2816 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 2817 */ 2818 2819 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 2820 2821 /* 2822 * Allocate a carrier ensuring at least one carrier always 2823 * remains on the freelist and initialize fields. 2824 */ 2825 if ((new_carrp = sc->carr_freelist) == NULL) { 2826 return ADW_BUSY; 2827 } 2828 sc->carr_freelist = adw_carrier_phys_kv(sc, 2829 ASC_GET_CARRP(new_carrp->next_vpa)); 2830 sc->carr_pending_cnt++; 2831 2832 /* 2833 * Set the carrier to be a stopper by setting 'next_vpa' 2834 * to the stopper value. The current stopper will be changed 2835 * below to point to the new stopper. 2836 */ 2837 new_carrp->next_vpa = ASC_CQ_STOPPER; 2838 2839 req_size = sizeof(ADW_SCSI_REQ_Q); 2840 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 2841 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 2842 2843 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 2844 scsiq->scsiq_rptr = req_paddr; 2845 2846 /* 2847 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian 2848 * order during initialization. 2849 */ 2850 scsiq->carr_pa = sc->icq_sp->carr_pa; 2851 scsiq->carr_va = sc->icq_sp->carr_pa; 2852 2853 /* 2854 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 2855 * the microcode. The newly allocated stopper will become the new 2856 * stopper. 2857 */ 2858 sc->icq_sp->areq_vpa = req_paddr; 2859 2860 /* 2861 * Set the 'next_vpa' pointer for the old stopper to be the 2862 * physical address of the new stopper. The RISC can only 2863 * follow physical addresses. 2864 */ 2865 sc->icq_sp->next_vpa = new_carrp->carr_pa; 2866 2867 /* 2868 * Set the host adapter stopper pointer to point to the new carrier. 2869 */ 2870 sc->icq_sp = new_carrp; 2871 2872 if (sc->chip_type == ADV_CHIP_ASC3550 || 2873 sc->chip_type == ADV_CHIP_ASC38C0800) { 2874 /* 2875 * Tickle the RISC to tell it to read its Command Queue Head 2876 * pointer. 2877 */ 2878 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); 2879 if (sc->chip_type == ADV_CHIP_ASC3550) { 2880 /* 2881 * Clear the tickle value. In the ASC-3550 the RISC flag 2882 * command 'clr_tickle_a' does not work unless the host 2883 * value is cleared. 2884 */ 2885 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 2886 ADV_TICKLE_NOP); 2887 } 2888 } else if (sc->chip_type == ADV_CHIP_ASC38C1600) { 2889 /* 2890 * Notify the RISC a carrier is ready by writing the physical 2891 * address of the new carrier stopper to the COMMA register. 2892 */ 2893 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 2894 new_carrp->carr_pa); 2895 } 2896 2897 /* 2898 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 2899 */ 2900 2901 return ADW_SUCCESS; 2902 } 2903 2904 2905 void 2906 AdvResetChip(iot, ioh) 2907 bus_space_tag_t iot; 2908 bus_space_handle_t ioh; 2909 { 2910 2911 /* 2912 * Reset Chip. 2913 */ 2914 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2915 ADW_CTRL_REG_CMD_RESET); 2916 AdvSleepMilliSecond(100); 2917 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2918 ADW_CTRL_REG_CMD_WR_IO_REG); 2919 } 2920 2921 2922 /* 2923 * Reset SCSI Bus and purge all outstanding requests. 2924 * 2925 * Return Value: 2926 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 2927 * ADW_FALSE(0) - Microcode command failed. 2928 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 2929 * may be hung which requires driver recovery. 2930 */ 2931 int 2932 AdvResetCCB(sc) 2933 ADW_SOFTC *sc; 2934 { 2935 int status; 2936 2937 /* 2938 * Send the SCSI Bus Reset idle start idle command which asserts 2939 * the SCSI Bus Reset signal. 2940 */ 2941 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 2942 if (status != ADW_TRUE) { 2943 return status; 2944 } 2945 2946 /* 2947 * Delay for the specified SCSI Bus Reset hold time. 2948 * 2949 * The hold time delay is done on the host because the RISC has no 2950 * microsecond accurate timer. 2951 */ 2952 AdvDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 2953 2954 /* 2955 * Send the SCSI Bus Reset end idle command which de-asserts 2956 * the SCSI Bus Reset signal and purges any pending requests. 2957 */ 2958 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 2959 if (status != ADW_TRUE) { 2960 return status; 2961 } 2962 2963 AdvSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 2964 2965 return status; 2966 } 2967 2968 2969 /* 2970 * Reset chip and SCSI Bus. 2971 * 2972 * Return Value: 2973 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 2974 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 2975 */ 2976 int 2977 AdvResetSCSIBus(sc) 2978 ADW_SOFTC *sc; 2979 { 2980 bus_space_tag_t iot = sc->sc_iot; 2981 bus_space_handle_t ioh = sc->sc_ioh; 2982 int status; 2983 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 2984 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 2985 u_int16_t bios_sig; 2986 2987 2988 /* 2989 * Save current per TID negotiated values. 2990 */ 2991 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 2992 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 2993 if (sc->chip_type == ADV_CHIP_ASC38C1600) { 2994 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, ppr_able); 2995 } 2996 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 2997 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2998 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 2999 max_cmd[tid]); 3000 } 3001 3002 /* 3003 * Force the AdvInitAsc3550/38C0800Driver() function to 3004 * perform a SCSI Bus Reset by clearing the BIOS signature word. 3005 * The initialization functions assumes a SCSI Bus Reset is not 3006 * needed if the BIOS signature word is present. 3007 */ 3008 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); 3009 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, 0); 3010 3011 /* 3012 * Stop chip and reset it. 3013 */ 3014 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 3015 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 3016 ADW_CTRL_REG_CMD_RESET); 3017 AdvSleepMilliSecond(100); 3018 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 3019 ADW_CTRL_REG_CMD_WR_IO_REG); 3020 3021 /* 3022 * Reset Adv Library error code, if any, and try 3023 * re-initializing the chip. 3024 */ 3025 if (sc->chip_type == ADV_CHIP_ASC38C1600) { 3026 status = AdvInitAsc38C1600Driver(sc); 3027 } else if (sc->chip_type == ADV_CHIP_ASC38C0800) { 3028 status = AdvInitAsc38C0800Driver(sc); 3029 } else { 3030 status = AdvInitAsc3550Driver(sc); 3031 } 3032 3033 /* Translate initialization return value to status value. */ 3034 if (status == 0) { 3035 status = ADW_TRUE; 3036 } else { 3037 status = ADW_FALSE; 3038 } 3039 3040 /* 3041 * Restore the BIOS signature word. 3042 */ 3043 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); 3044 3045 /* 3046 * Restore per TID negotiated values. 3047 */ 3048 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 3049 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 3050 if (sc->chip_type == ADV_CHIP_ASC38C1600) { 3051 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, ppr_able); 3052 } 3053 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 3054 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 3055 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 3056 max_cmd[tid]); 3057 } 3058 3059 return status; 3060 } 3061 3062 3063 /* 3064 * Adv Library Interrupt Service Routine 3065 * 3066 * This function is called by a driver's interrupt service routine. 3067 * The function disables and re-enables interrupts. 3068 * 3069 * When a microcode idle command is completed, the ADV_DVC_VAR 3070 * 'idle_cmd_done' field is set to ADW_TRUE. 3071 * 3072 * Note: AdvISR() can be called when interrupts are disabled or even 3073 * when there is no hardware interrupt condition present. It will 3074 * always check for completed idle commands and microcode requests. 3075 * This is an important feature that shouldn't be changed because it 3076 * allows commands to be completed from polling mode loops. 3077 * 3078 * Return: 3079 * ADW_TRUE(1) - interrupt was pending 3080 * ADW_FALSE(0) - no interrupt was pending 3081 */ 3082 int 3083 AdvISR(sc) 3084 ADW_SOFTC *sc; 3085 { 3086 bus_space_tag_t iot = sc->sc_iot; 3087 bus_space_handle_t ioh = sc->sc_ioh; 3088 u_int8_t int_stat; 3089 u_int16_t target_bit; 3090 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 3091 u_int32_t irq_next_pa; 3092 ADW_SCSI_REQ_Q *scsiq; 3093 ADW_CCB *ccb; 3094 int s; 3095 3096 3097 s = splbio(); 3098 3099 /* Reading the register clears the interrupt. */ 3100 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 3101 3102 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 3103 ADW_INTR_STATUS_INTRC)) == 0) { 3104 splx(s); 3105 return ADW_FALSE; 3106 } 3107 3108 /* 3109 * Notify the driver of an asynchronous microcode condition by 3110 * calling the ADV_DVC_VAR.async_callback function. The function 3111 * is passed the microcode ASC_MC_INTRB_CODE byte value. 3112 */ 3113 if (int_stat & ADW_INTR_STATUS_INTRB) { 3114 u_int8_t intrb_code; 3115 3116 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_INTRB_CODE, intrb_code); 3117 3118 if (sc->chip_type == ADV_CHIP_ASC3550 || 3119 sc->chip_type == ADV_CHIP_ASC38C0800) { 3120 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 3121 sc->carr_pending_cnt != 0) { 3122 ADW_WRITE_BYTE_REGISTER(iot, ioh, 3123 IOPB_TICKLE, ADV_TICKLE_A); 3124 if (sc->chip_type == ADV_CHIP_ASC3550) { 3125 ADW_WRITE_BYTE_REGISTER(iot, ioh, 3126 IOPB_TICKLE, ADV_TICKLE_NOP); 3127 } 3128 } 3129 } 3130 3131 if (sc->async_callback != 0) { 3132 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 3133 } 3134 } 3135 3136 /* 3137 * Check if the IRQ stopper carrier contains a completed request. 3138 */ 3139 while (((irq_next_pa = sc->irq_sp->next_vpa) & ASC_RQ_DONE) != 0) 3140 { 3141 /* 3142 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 3143 * structure. 3144 * The RISC will have set 'areq_vpa' to a virtual address. 3145 * 3146 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 3147 * field to the carrier ADV_CARR_T.areq_vpa field. 3148 * The conversion below complements the conversion of 3149 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdvExeScsiQueue(). 3150 */ 3151 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_vpa); 3152 scsiq = &ccb->scsiq; 3153 scsiq->ccb_ptr = sc->irq_sp->areq_vpa; 3154 3155 /* 3156 * Request finished with good status and the queue was not 3157 * DMAed to host memory by the firmware. Set all status fields 3158 * to indicate good status. 3159 */ 3160 if ((irq_next_pa & ASC_RQ_GOOD) != 0) { 3161 scsiq->done_status = QD_NO_ERROR; 3162 scsiq->host_status = scsiq->scsi_status = 0; 3163 scsiq->data_cnt = 0L; 3164 } 3165 3166 /* 3167 * Advance the stopper pointer to the next carrier 3168 * ignoring the lower four bits. Free the previous 3169 * stopper carrier. 3170 */ 3171 free_carrp = sc->irq_sp; 3172 sc->irq_sp = adw_carrier_phys_kv(sc, ASC_GET_CARRP(irq_next_pa)); 3173 3174 free_carrp->next_vpa = sc->carr_freelist->carr_pa; 3175 sc->carr_freelist = free_carrp; 3176 sc->carr_pending_cnt--; 3177 3178 3179 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 3180 3181 /* 3182 * Clear request microcode control flag. 3183 */ 3184 scsiq->cntl = 0; 3185 3186 /* 3187 * Check Condition handling 3188 */ 3189 /* 3190 * If the command that completed was a SCSI INQUIRY and 3191 * LUN 0 was sent the command, then process the INQUIRY 3192 * command information for the device. 3193 */ 3194 if (scsiq->done_status == QD_NO_ERROR && 3195 scsiq->cdb[0] == INQUIRY && 3196 scsiq->target_lun == 0) { 3197 AdvInquiryHandling(sc, scsiq); 3198 } 3199 3200 /* 3201 * Notify the driver of the completed request by passing 3202 * the ADW_SCSI_REQ_Q pointer to its callback function. 3203 */ 3204 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 3205 /* 3206 * Note: After the driver callback function is called, 'scsiq' 3207 * can no longer be referenced. 3208 * 3209 * Fall through and continue processing other completed 3210 * requests... 3211 */ 3212 } 3213 3214 splx(s); 3215 3216 return ADW_TRUE; 3217 } 3218 3219 3220 /* 3221 * Send an idle command to the chip and wait for completion. 3222 * 3223 * Command completion is polled for once per microsecond. 3224 * 3225 * The function can be called from anywhere including an interrupt handler. 3226 * But the function is not re-entrant, so it uses the splbio/splx() 3227 * functions to prevent reentrancy. 3228 * 3229 * Return Values: 3230 * ADW_TRUE - command completed successfully 3231 * ADW_FALSE - command failed 3232 * ADW_ERROR - command timed out 3233 */ 3234 int 3235 AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 3236 ADW_SOFTC *sc; 3237 u_int16_t idle_cmd; 3238 u_int32_t idle_cmd_parameter; 3239 { 3240 bus_space_tag_t iot = sc->sc_iot; 3241 bus_space_handle_t ioh = sc->sc_ioh; 3242 int result; 3243 u_int32_t i, j, s; 3244 3245 s = splbio(); 3246 3247 /* 3248 * Clear the idle command status which is set by the microcode 3249 * to a non-zero value to indicate when the command is completed. 3250 * The non-zero result is one of the IDLE_CMD_STATUS_* values 3251 * defined in a_advlib.h. 3252 */ 3253 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 3254 3255 /* 3256 * Write the idle command value after the idle command parameter 3257 * has been written to avoid a race condition. If the order is not 3258 * followed, the microcode may process the idle command before the 3259 * parameters have been written to LRAM. 3260 */ 3261 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_PARAMETER, 3262 idle_cmd_parameter); 3263 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD, idle_cmd); 3264 3265 /* 3266 * Tickle the RISC to tell it to process the idle command. 3267 */ 3268 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_B); 3269 if (sc->chip_type == ADV_CHIP_ASC3550) { 3270 /* 3271 * Clear the tickle value. In the ASC-3550 the RISC flag 3272 * command 'clr_tickle_b' does not work unless the host 3273 * value is cleared. 3274 */ 3275 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 3276 } 3277 3278 /* Wait for up to 100 millisecond for the idle command to timeout. */ 3279 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 3280 /* Poll once each microsecond for command completion. */ 3281 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 3282 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, result); 3283 if (result != 0) { 3284 splx(s); 3285 return result; 3286 } 3287 AdvDelayMicroSecond(1); 3288 } 3289 } 3290 3291 splx(s); 3292 return ADW_ERROR; 3293 } 3294 3295 3296 /* 3297 * Inquiry Information Byte 7 Handling 3298 * 3299 * Handle SCSI Inquiry Command information for a device by setting 3300 * microcode operating variables that affect WDTR, SDTR, and Tag 3301 * Queuing. 3302 */ 3303 static void 3304 AdvInquiryHandling(sc, scsiq) 3305 ADW_SOFTC *sc; 3306 ADW_SCSI_REQ_Q *scsiq; 3307 { 3308 #ifndef FAILSAFE 3309 bus_space_tag_t iot = sc->sc_iot; 3310 bus_space_handle_t ioh = sc->sc_ioh; 3311 u_int8_t tid; 3312 ADW_SCSI_INQUIRY *inq; 3313 u_int16_t tidmask; 3314 u_int16_t cfg_word; 3315 3316 3317 /* 3318 * AdvInquiryHandling() requires up to INQUIRY information Byte 7 3319 * to be available. 3320 * 3321 * If less than 8 bytes of INQUIRY information were requested or less 3322 * than 8 bytes were transferred, then return. cdb[4] is the request 3323 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 3324 * microcode to the transfer residual count. 3325 */ 3326 3327 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 3328 return; 3329 } 3330 3331 tid = scsiq->target_id; 3332 3333 inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; 3334 3335 /* 3336 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 3337 */ 3338 if (inq->rsp_data_fmt < 2 && inq->ansi_apr_ver < 2) { 3339 return; 3340 } else { 3341 /* 3342 * INQUIRY Byte 7 Handling 3343 * 3344 * Use a device's INQUIRY byte 7 to determine whether it 3345 * supports WDTR, SDTR, and Tag Queuing. If the feature 3346 * is enabled in the EEPROM and the device supports the 3347 * feature, then enable it in the microcode. 3348 */ 3349 3350 tidmask = ADW_TID_TO_TIDMASK(tid); 3351 3352 /* 3353 * Wide Transfers 3354 * 3355 * If the EEPROM enabled WDTR for the device and the device 3356 * supports wide bus (16 bit) transfers, then turn on the 3357 * device's 'wdtr_able' bit and write the new value to the 3358 * microcode. 3359 */ 3360 #ifdef SCSI_ADW_WDTR_DISABLE 3361 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 3362 #endif /* SCSI_ADW_WDTR_DISABLE */ 3363 if ((sc->wdtr_able & tidmask) && inq->WBus16) { 3364 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 3365 cfg_word); 3366 if ((cfg_word & tidmask) == 0) { 3367 cfg_word |= tidmask; 3368 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 3369 cfg_word); 3370 3371 /* 3372 * Clear the microcode "SDTR negotiation" and "WDTR 3373 * negotiation" done indicators for the target to cause 3374 * it to negotiate with the new setting set above. 3375 * WDTR when accepted causes the target to enter 3376 * asynchronous mode, so SDTR must be negotiated. 3377 */ 3378 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3379 cfg_word); 3380 cfg_word &= ~tidmask; 3381 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3382 cfg_word); 3383 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 3384 cfg_word); 3385 cfg_word &= ~tidmask; 3386 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 3387 cfg_word); 3388 } 3389 } 3390 3391 /* 3392 * Synchronous Transfers 3393 * 3394 * If the EEPROM enabled SDTR for the device and the device 3395 * supports synchronous transfers, then turn on the device's 3396 * 'sdtr_able' bit. Write the new value to the microcode. 3397 */ 3398 #ifdef SCSI_ADW_SDTR_DISABLE 3399 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 3400 #endif /* SCSI_ADW_SDTR_DISABLE */ 3401 if ((sc->sdtr_able & tidmask) && inq->Sync) { 3402 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, cfg_word); 3403 if ((cfg_word & tidmask) == 0) { 3404 cfg_word |= tidmask; 3405 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 3406 cfg_word); 3407 3408 /* 3409 * Clear the microcode "SDTR negotiation" done indicator 3410 * for the target to cause it to negotiate with the new 3411 * setting set above. 3412 */ 3413 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3414 cfg_word); 3415 cfg_word &= ~tidmask; 3416 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3417 cfg_word); 3418 } 3419 } 3420 /* 3421 * If the Inquiry data included enough space for the SPI-3 3422 * Clocking field, then check if DT mode is supported. 3423 */ 3424 if (sc->chip_type == ADV_CHIP_ASC38C1600 && 3425 (scsiq->cdb[4] >= 57 || 3426 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 3427 /* 3428 * PPR (Parallel Protocol Request) Capable 3429 * 3430 * If the device supports DT mode, then it must be 3431 * PPR capable. 3432 * The PPR message will be used in place of the SDTR 3433 * and WDTR messages to negotiate synchronous speed 3434 * and offset, transfer width, and protocol options. 3435 */ 3436 if (inq->Clocking & INQ_CLOCKING_DT_ONLY) 3437 { 3438 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, 3439 sc->ppr_able); 3440 sc->ppr_able |= tidmask; 3441 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, 3442 sc->ppr_able); 3443 } 3444 } 3445 3446 /* 3447 * If the EEPROM enabled Tag Queuing for the device and the 3448 * device supports Tag Queueing, then turn on the device's 3449 * 'tagqng_enable' bit in the microcode and set the microcode 3450 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 3451 * value. 3452 * 3453 * Tag Queuing is disabled for the BIOS which runs in polled 3454 * mode and would see no benefit from Tag Queuing. Also by 3455 * disabling Tag Queuing in the BIOS devices with Tag Queuing 3456 * bugs will at least work with the BIOS. 3457 */ 3458 #ifdef SCSI_ADW_TAGQ_DISABLE 3459 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 3460 #endif /* SCSI_ADW_TAGQ_DISABLE */ 3461 if ((sc->tagqng_able & tidmask) && inq->CmdQue) { 3462 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 3463 cfg_word); 3464 cfg_word |= tidmask; 3465 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 3466 cfg_word); 3467 3468 ADW_WRITE_BYTE_LRAM(iot, ioh, 3469 ASC_MC_NUMBER_OF_MAX_CMD + tid, 3470 sc->max_dvc_qng); 3471 } 3472 } 3473 #endif /* FAILSAFE */ 3474 } 3475 3476 3477 static void 3478 AdvSleepMilliSecond(n) 3479 u_int32_t n; 3480 { 3481 3482 DELAY(n * 1000); 3483 } 3484 3485 3486 static void 3487 AdvDelayMicroSecond(n) 3488 u_int32_t n; 3489 { 3490 3491 DELAY(n); 3492 } 3493 3494
Indexes created Tue Sep 23 02:09:52 GMT 2025