adwlib.c revision 1.13
1 /* $NetBSD: adwlib.c,v 1.13 2000/05/14 18:25:49 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_param.h> 73 #include <vm/pmap.h> 74 75 #include <dev/ic/adwlib.h> 76 #include <dev/ic/adw.h> 77 #include <dev/ic/adwmcode.h> 78 79 80 /* Static Functions */ 81 82 static u_int16_t AdvGet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 83 ADW_EEP_3550_CONFIG *)); 84 static u_int16_t AdvGet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_EEP_38C0800_CONFIG *)); 86 static u_int16_t AdvGet38C1600EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 87 ADW_EEP_38C1600_CONFIG *)); 88 static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 89 static void AdvWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 90 static void AdvSet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 91 ADW_EEP_3550_CONFIG *)); 92 static void AdvSet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 93 ADW_EEP_38C0800_CONFIG *)); 94 static void AdvSet38C1600EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 95 ADW_EEP_38C1600_CONFIG *)); 96 static void AdvInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 97 98 static void AdvSleepMilliSecond __P((u_int32_t)); 99 static void AdvDelayMicroSecond __P((u_int32_t)); 100 101 102 /* 103 * EEPROM Configuration. 104 * 105 * All drivers should use this structure to set the default EEPROM 106 * configuration. The BIOS now uses this structure when it is built. 107 * Additional structure information can be found in advlib.h where 108 * the structure is defined. 109 */ 110 static ADW_EEP_3550_CONFIG 111 Default_3550_EEPROM_Config = { 112 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 113 0x0000, /* cfg_msw */ 114 0xFFFF, /* disc_enable */ 115 0xFFFF, /* wdtr_able */ 116 0xFFFF, /* sdtr_able */ 117 0xFFFF, /* start_motor */ 118 0xFFFF, /* tagqng_able */ 119 0xFFFF, /* bios_scan */ 120 0, /* scam_tolerant */ 121 7, /* adapter_scsi_id */ 122 0, /* bios_boot_delay */ 123 3, /* scsi_reset_delay */ 124 0, /* bios_id_lun */ 125 0, /* termination */ 126 0, /* reserved1 */ 127 0xFFE7, /* bios_ctrl */ 128 0xFFFF, /* ultra_able */ 129 0, /* reserved2 */ 130 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 131 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 132 0, /* dvc_cntl */ 133 0, /* bug_fix */ 134 0, /* serial_number_word1 */ 135 0, /* serial_number_word2 */ 136 0, /* serial_number_word3 */ 137 0, /* check_sum */ 138 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */ 139 0, /* dvc_err_code */ 140 0, /* adv_err_code */ 141 0, /* adv_err_addr */ 142 0, /* saved_dvc_err_code */ 143 0, /* saved_adv_err_code */ 144 0, /* saved_adv_err_addr */ 145 0 /* num_of_err */ 146 }; 147 148 static ADW_EEP_38C0800_CONFIG 149 Default_38C0800_EEPROM_Config = { 150 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 151 0x0000, /* 01 cfg_msw */ 152 0xFFFF, /* 02 disc_enable */ 153 0xFFFF, /* 03 wdtr_able */ 154 0x4444, /* 04 sdtr_speed1 */ 155 0xFFFF, /* 05 start_motor */ 156 0xFFFF, /* 06 tagqng_able */ 157 0xFFFF, /* 07 bios_scan */ 158 0, /* 08 scam_tolerant */ 159 7, /* 09 adapter_scsi_id */ 160 0, /* bios_boot_delay */ 161 3, /* 10 scsi_reset_delay */ 162 0, /* bios_id_lun */ 163 0, /* 11 termination_se */ 164 0, /* termination_lvd */ 165 0xFFE7, /* 12 bios_ctrl */ 166 0x4444, /* 13 sdtr_speed2 */ 167 0x4444, /* 14 sdtr_speed3 */ 168 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 169 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 170 0, /* 16 dvc_cntl */ 171 0x4444, /* 17 sdtr_speed4 */ 172 0, /* 18 serial_number_word1 */ 173 0, /* 19 serial_number_word2 */ 174 0, /* 20 serial_number_word3 */ 175 0, /* 21 check_sum */ 176 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 177 0, /* 30 dvc_err_code */ 178 0, /* 31 adv_err_code */ 179 0, /* 32 adv_err_addr */ 180 0, /* 33 saved_dvc_err_code */ 181 0, /* 34 saved_adv_err_code */ 182 0, /* 35 saved_adv_err_addr */ 183 0, /* 36 reserved */ 184 0, /* 37 reserved */ 185 0, /* 38 reserved */ 186 0, /* 39 reserved */ 187 0, /* 40 reserved */ 188 0, /* 41 reserved */ 189 0, /* 42 reserved */ 190 0, /* 43 reserved */ 191 0, /* 44 reserved */ 192 0, /* 45 reserved */ 193 0, /* 46 reserved */ 194 0, /* 47 reserved */ 195 0, /* 48 reserved */ 196 0, /* 49 reserved */ 197 0, /* 50 reserved */ 198 0, /* 51 reserved */ 199 0, /* 52 reserved */ 200 0, /* 53 reserved */ 201 0, /* 54 reserved */ 202 0, /* 55 reserved */ 203 0, /* 56 cisptr_lsw */ 204 0, /* 57 cisprt_msw */ 205 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 206 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 207 0, /* 60 reserved */ 208 0, /* 61 reserved */ 209 0, /* 62 reserved */ 210 0 /* 63 reserved */ 211 }; 212 213 static ADW_EEP_38C1600_CONFIG 214 Default_38C1600_EEPROM_Config = { 215 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 216 0x0000, /* 01 cfg_msw */ 217 0xFFFF, /* 02 disc_enable */ 218 0xFFFF, /* 03 wdtr_able */ 219 0x5555, /* 04 sdtr_speed1 */ 220 0xFFFF, /* 05 start_motor */ 221 0xFFFF, /* 06 tagqng_able */ 222 0xFFFF, /* 07 bios_scan */ 223 0, /* 08 scam_tolerant */ 224 7, /* 09 adapter_scsi_id */ 225 0, /* bios_boot_delay */ 226 3, /* 10 scsi_reset_delay */ 227 0, /* bios_id_lun */ 228 0, /* 11 termination_se */ 229 0, /* termination_lvd */ 230 0xFFE7, /* 12 bios_ctrl */ 231 0x5555, /* 13 sdtr_speed2 */ 232 0x5555, /* 14 sdtr_speed3 */ 233 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 234 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 235 0, /* 16 dvc_cntl */ 236 0x5555, /* 17 sdtr_speed4 */ 237 0, /* 18 serial_number_word1 */ 238 0, /* 19 serial_number_word2 */ 239 0, /* 20 serial_number_word3 */ 240 0, /* 21 check_sum */ 241 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 242 0, /* 30 dvc_err_code */ 243 0, /* 31 adv_err_code */ 244 0, /* 32 adv_err_addr */ 245 0, /* 33 saved_dvc_err_code */ 246 0, /* 34 saved_adv_err_code */ 247 0, /* 35 saved_adv_err_addr */ 248 0, /* 36 reserved */ 249 0, /* 37 reserved */ 250 0, /* 38 reserved */ 251 0, /* 39 reserved */ 252 0, /* 40 reserved */ 253 0, /* 41 reserved */ 254 0, /* 42 reserved */ 255 0, /* 43 reserved */ 256 0, /* 44 reserved */ 257 0, /* 45 reserved */ 258 0, /* 46 reserved */ 259 0, /* 47 reserved */ 260 0, /* 48 reserved */ 261 0, /* 49 reserved */ 262 0, /* 50 reserved */ 263 0, /* 51 reserved */ 264 0, /* 52 reserved */ 265 0, /* 53 reserved */ 266 0, /* 54 reserved */ 267 0, /* 55 reserved */ 268 0, /* 56 cisptr_lsw */ 269 0, /* 57 cisprt_msw */ 270 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 271 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 272 0, /* 60 reserved */ 273 0, /* 61 reserved */ 274 0, /* 62 reserved */ 275 0 /* 63 reserved */ 276 }; 277 278 /* 279 * Initialize the ASC3550. 280 * 281 * On failure set the ADW_SOFTC field 'err_code' and return ADW_ERROR. 282 * 283 * For a non-fatal error return a warning code. If there are no warnings 284 * then 0 is returned. 285 */ 286 int 287 AdvInitAsc3550Driver(sc) 288 ADW_SOFTC *sc; 289 { 290 bus_space_tag_t iot = sc->sc_iot; 291 bus_space_handle_t ioh = sc->sc_ioh; 292 u_int16_t warn_code; 293 u_int32_t sum; 294 int begin_addr; 295 int end_addr; 296 u_int16_t code_sum; 297 int word; 298 int i, j; 299 int adv_asc3550_expanded_size; 300 u_int16_t scsi_cfg1; 301 u_int8_t tid; 302 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 303 0x40-0x8F. */ 304 u_int16_t wdtr_able = 0, sdtr_able, tagqng_able; 305 u_int8_t max_cmd[ADW_MAX_TID + 1]; 306 307 308 warn_code = 0; 309 310 /* 311 * Save the RISC memory BIOS region before writing the microcode. 312 * The BIOS may already be loaded and using its RISC LRAM region 313 * so its region must be saved and restored. 314 * 315 * Note: This code makes the assumption, which is currently true, 316 * that a chip reset does not clear RISC LRAM. 317 */ 318 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 319 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM+(2*i), bios_mem[i]); 320 } 321 322 /* 323 * Save current per TID negotiated values. 324 */ 325 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA) { 326 327 u_int16_t bios_version, major, minor; 328 329 bios_version = bios_mem[(ASC_MC_BIOS_VERSION-ASC_MC_BIOSMEM)/2]; 330 major = (bios_version >> 12) & 0xF; 331 minor = (bios_version >> 8) & 0xF; 332 if (major < 3 || (major == 3 && minor == 1)) { 333 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 334 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 335 } else { 336 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 337 } 338 } 339 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 340 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 341 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 342 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 343 max_cmd[tid]); 344 } 345 346 /* 347 * Load the Microcode 348 * 349 * Write the microcode image to RISC memory starting at address 0. 350 */ 351 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 352 353 /* Assume the following compressed format of the microcode buffer: 354 * 355 * 254 word (508 byte) table indexed by byte code followed 356 * by the following byte codes: 357 * 358 * 1-Byte Code: 359 * 00: Emit word 0 in table. 360 * 01: Emit word 1 in table. 361 * . 362 * FD: Emit word 253 in table. 363 * 364 * Multi-Byte Code: 365 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 366 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 367 */ 368 word = 0; 369 for (i = 253 * 2; i < adv_asc3550_mcode_size; i++) { 370 if (adv_asc3550_mcode[i] == 0xff) { 371 for (j = 0; j < adv_asc3550_mcode[i + 1]; j++) { 372 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 373 (((u_int16_t)adv_asc3550_mcode[i + 3] << 8) | 374 adv_asc3550_mcode[i + 2])); 375 word++; 376 } 377 i += 3; 378 } else if (adv_asc3550_mcode[i] == 0xfe) { 379 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 380 (((u_int16_t)adv_asc3550_mcode[i + 2] << 8) | 381 adv_asc3550_mcode[i + 1])); 382 i += 2; 383 word++; 384 } else { 385 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 386 adv_asc3550_mcode[(adv_asc3550_mcode[i] * 2) + 1] <<8)| 387 adv_asc3550_mcode[adv_asc3550_mcode[i] * 2])); 388 word++; 389 } 390 } 391 392 /* 393 * Set 'word' for later use to clear the rest of memory and save 394 * the expanded mcode size. 395 */ 396 word *= 2; 397 adv_asc3550_expanded_size = word; 398 399 /* 400 * Clear the rest of ASC-3550 Internal RAM (8KB). 401 */ 402 for (; word < ADV_3550_MEMSIZE; word += 2) { 403 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 404 } 405 406 /* 407 * Verify the microcode checksum. 408 */ 409 sum = 0; 410 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 411 412 for (word = 0; word < adv_asc3550_expanded_size; word += 2) { 413 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 414 } 415 416 if (sum != adv_asc3550_mcode_chksum) { 417 return ASC_IERR_MCODE_CHKSUM; 418 } 419 420 /* 421 * Restore the RISC memory BIOS region. 422 */ 423 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 424 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 425 bios_mem[i]); 426 } 427 428 /* 429 * Calculate and write the microcode code checksum to the microcode 430 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 431 */ 432 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 433 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 434 code_sum = 0; 435 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 436 for (word = begin_addr; word < end_addr; word += 2) { 437 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 438 } 439 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 440 441 /* 442 * Read and save microcode version and date. 443 */ 444 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 445 sc->cfg.mcode_date); 446 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 447 sc->cfg.mcode_version); 448 449 /* 450 * Set the chip type to indicate the ASC3550. 451 */ 452 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 453 454 /* 455 * If the PCI Configuration Command Register "Parity Error Response 456 * Control" Bit was clear (0), then set the microcode variable 457 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 458 * to ignore DMA parity errors. 459 */ 460 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 461 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 462 word |= CONTROL_FLAG_IGNORE_PERR; 463 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 464 } 465 466 /* 467 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 468 * threshold of 128 bytes. This register is only accessible to the host. 469 */ 470 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 471 START_CTL_EMFU | READ_CMD_MRM); 472 473 /* 474 * Microcode operating variables for WDTR, SDTR, and command tag 475 * queuing will be set in AdvInquiryHandling() based on what a 476 * device reports it is capable of in Inquiry byte 7. 477 * 478 * If SCSI Bus Resets haev been disabled, then directly set 479 * SDTR and WDTR from the EEPROM configuration. This will allow 480 * the BIOS and warm boot to work without a SCSI bus hang on 481 * the Inquiry caused by host and target mismatched DTR values. 482 * Without the SCSI Bus Reset, before an Inquiry a device can't 483 * be assumed to be in Asynchronous, Narrow mode. 484 */ 485 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 486 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 487 sc->wdtr_able); 488 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 489 sc->sdtr_able); 490 } 491 492 /* 493 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 494 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 495 * bitmask. These values determine the maximum SDTR speed negotiated 496 * with a device. 497 * 498 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 499 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 500 * without determining here whether the device supports SDTR. 501 * 502 * 4-bit speed SDTR speed name 503 * =========== =============== 504 * 0000b (0x0) SDTR disabled 505 * 0001b (0x1) 5 Mhz 506 * 0010b (0x2) 10 Mhz 507 * 0011b (0x3) 20 Mhz (Ultra) 508 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 509 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 510 * 0110b (0x6) Undefined 511 * . 512 * 1111b (0xF) Undefined 513 */ 514 word = 0; 515 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 516 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 517 /* Set Ultra speed for TID 'tid'. */ 518 word |= (0x3 << (4 * (tid % 4))); 519 } else { 520 /* Set Fast speed for TID 'tid'. */ 521 word |= (0x2 << (4 * (tid % 4))); 522 } 523 /* Check if done with sdtr_speed1. */ 524 if (tid == 3) { 525 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, word); 526 word = 0; 527 /* Check if done with sdtr_speed2. */ 528 } else if (tid == 7) { 529 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, word); 530 word = 0; 531 /* Check if done with sdtr_speed3. */ 532 } else if (tid == 11) { 533 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, word); 534 word = 0; 535 /* Check if done with sdtr_speed4. */ 536 } else if (tid == 15) { 537 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, word); 538 /* End of loop. */ 539 } 540 } 541 542 /* 543 * Set microcode operating variable for the disconnect per TID bitmask. 544 */ 545 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 546 547 548 /* 549 * Set SCSI_CFG0 Microcode Default Value. 550 * 551 * The microcode will set the SCSI_CFG0 register using this value 552 * after it is started below. 553 */ 554 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 555 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 556 ADW_OUR_ID_EN | sc->chip_scsi_id); 557 558 /* 559 * Determine SCSI_CFG1 Microcode Default Value. 560 * 561 * The microcode will set the SCSI_CFG1 register using this value 562 * after it is started below. 563 */ 564 565 /* Read current SCSI_CFG1 Register value. */ 566 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 567 568 /* 569 * If all three connectors are in use, return an error. 570 */ 571 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 572 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 573 return ASC_IERR_ILLEGAL_CONNECTION; 574 } 575 576 /* 577 * If the internal narrow cable is reversed all of the SCSI_CTRL 578 * register signals will be set. Check for and return an error if 579 * this condition is found. 580 */ 581 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 582 0x3F07) { 583 return ASC_IERR_REVERSED_CABLE; 584 } 585 586 /* 587 * If this is a differential board and a single-ended device 588 * is attached to one of the connectors, return an error. 589 */ 590 if ((scsi_cfg1 & ADW_DIFF_MODE) && (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 591 return ASC_IERR_SINGLE_END_DEVICE; 592 } 593 594 /* 595 * If automatic termination control is enabled, then set the 596 * termination value based on a table listed in a_condor.h. 597 * 598 * If manual termination was specified with an EEPROM setting 599 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 600 * is ready to be 'ored' into SCSI_CFG1. 601 */ 602 if (sc->cfg.termination == 0) { 603 /* 604 * The software always controls termination by setting 605 * TERM_CTL_SEL. 606 * If TERM_CTL_SEL were set to 0, the hardware would set 607 * termination. 608 */ 609 sc->cfg.termination |= ADW_TERM_CTL_SEL; 610 611 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 612 /* TERM_CTL_H: on, TERM_CTL_L: on */ 613 case 0x3: case 0x7: case 0xB: 614 case 0xD: case 0xE: case 0xF: 615 sc->cfg.termination |= 616 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 617 break; 618 619 /* TERM_CTL_H: on, TERM_CTL_L: off */ 620 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC: 621 sc->cfg.termination |= ADW_TERM_CTL_H; 622 break; 623 624 /* TERM_CTL_H: off, TERM_CTL_L: off */ 625 case 0x2: case 0x6: 626 break; 627 } 628 } 629 630 /* 631 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 632 */ 633 scsi_cfg1 &= ~ADW_TERM_CTL; 634 635 /* 636 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 637 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 638 * referenced, because the hardware internally inverts 639 * the Termination High and Low bits if TERM_POL is set. 640 */ 641 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~sc->cfg.termination & ADW_TERM_CTL)); 642 643 /* 644 * Set SCSI_CFG1 Microcode Default Value 645 * 646 * Set filter value and possibly modified termination control 647 * bits in the Microcode SCSI_CFG1 Register Value. 648 * 649 * The microcode will set the SCSI_CFG1 register using this value 650 * after it is started below. 651 */ 652 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, 653 ADW_FLTR_DISABLE | scsi_cfg1); 654 655 /* 656 * Set MEM_CFG Microcode Default Value 657 * 658 * The microcode will set the MEM_CFG register using this value 659 * after it is started below. 660 * 661 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 662 * are defined. 663 * 664 * ASC-3550 has 8KB internal memory. 665 */ 666 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 667 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 668 669 /* 670 * Set SEL_MASK Microcode Default Value 671 * 672 * The microcode will set the SEL_MASK register using this value 673 * after it is started below. 674 */ 675 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 676 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 677 678 679 /* 680 * Set-up the Host->RISC Initiator Command Queue (ICQ). 681 */ 682 683 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 684 return ASC_IERR_NO_CARRIER; 685 } 686 sc->carr_freelist = adw_carrier_phys_kv(sc, 687 ASC_GET_CARRP(sc->icq_sp->next_ba)); 688 689 /* 690 * The first command issued will be placed in the stopper carrier. 691 */ 692 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 693 694 /* 695 * Set RISC ICQ physical address start value. 696 */ 697 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_ba); 698 699 /* 700 * Set-up the RISC->Host Initiator Response Queue (IRQ). 701 */ 702 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 703 return ASC_IERR_NO_CARRIER; 704 } 705 sc->carr_freelist = adw_carrier_phys_kv(sc, 706 ASC_GET_CARRP(sc->irq_sp->next_ba)); 707 708 /* 709 * The first command completed by the RISC will be placed in 710 * the stopper. 711 * 712 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 713 * completed the RISC will set the ASC_RQ_STOPPER bit. 714 */ 715 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 716 717 /* 718 * Set RISC IRQ physical address start value. 719 */ 720 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_ba); 721 sc->carr_pending_cnt = 0; 722 723 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 724 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 725 726 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 727 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 728 729 /* finally, finally, gentlemen, start your engine */ 730 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 731 732 /* 733 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 734 * Resets should be performed. The RISC has to be running 735 * to issue a SCSI Bus Reset. 736 */ 737 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 738 { 739 /* 740 * If the BIOS Signature is present in memory, restore the 741 * BIOS Handshake Configuration Table and do not perform 742 * a SCSI Bus Reset. 743 */ 744 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 745 0x55AA) { 746 /* 747 * Restore per TID negotiated values. 748 */ 749 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 750 wdtr_able); 751 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 752 sdtr_able); 753 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 754 tagqng_able); 755 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 756 ADW_WRITE_BYTE_LRAM(iot, ioh, 757 ASC_MC_NUMBER_OF_MAX_CMD + tid, 758 max_cmd[tid]); 759 } 760 } else { 761 if (AdvResetCCB(sc) != ADW_TRUE) { 762 warn_code = ASC_WARN_BUSRESET_ERROR; 763 } 764 } 765 } 766 767 return warn_code; 768 } 769 770 /* 771 * Initialize the ASC-38C0800. 772 * 773 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 774 * 775 * For a non-fatal error return a warning code. If there are no warnings 776 * then 0 is returned. 777 */ 778 int 779 AdvInitAsc38C0800Driver(sc) 780 ADW_SOFTC *sc; 781 { 782 bus_space_tag_t iot = sc->sc_iot; 783 bus_space_handle_t ioh = sc->sc_ioh; 784 u_int16_t warn_code; 785 u_int32_t sum; 786 int begin_addr; 787 int end_addr; 788 u_int16_t code_sum; 789 int word; 790 int i, j; 791 int adv_asc38C0800_expanded_size; 792 u_int16_t scsi_cfg1; 793 u_int8_t byte; 794 u_int8_t tid; 795 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 796 0x40-0x8F. */ 797 u_int16_t wdtr_able, sdtr_able, tagqng_able; 798 u_int8_t max_cmd[ADW_MAX_TID + 1]; 799 800 801 warn_code = 0; 802 803 /* 804 * Save the RISC memory BIOS region before writing the microcode. 805 * The BIOS may already be loaded and using its RISC LRAM region 806 * so its region must be saved and restored. 807 * 808 * Note: This code makes the assumption, which is currently true, 809 * that a chip reset does not clear RISC LRAM. 810 */ 811 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 812 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]); 813 } 814 815 /* 816 * Save current per TID negotiated values. 817 */ 818 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 819 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 820 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 821 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 822 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 823 max_cmd[tid]); 824 } 825 826 /* 827 * RAM BIST (RAM Built-In Self Test) 828 * 829 * Address : I/O base + offset 0x38h register (byte). 830 * Function: Bit 7-6(RW) : RAM mode 831 * Normal Mode : 0x00 832 * Pre-test Mode : 0x40 833 * RAM Test Mode : 0x80 834 * Bit 5 : unused 835 * Bit 4(RO) : Done bit 836 * Bit 3-0(RO) : Status 837 * Host Error : 0x08 838 * Int_RAM Error : 0x04 839 * RISC Error : 0x02 840 * SCSI Error : 0x01 841 * No Error : 0x00 842 * 843 * Note: RAM BIST code should be put right here, before loading the 844 * microcode and after saving the RISC memory BIOS region. 845 */ 846 847 /* 848 * LRAM Pre-test 849 * 850 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 851 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 852 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 853 * to NORMAL_MODE, return an error too. 854 */ 855 for (i = 0; i < 2; i++) { 856 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 857 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 858 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 859 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 860 PRE_TEST_VALUE) { 861 return ASC_IERR_BIST_PRE_TEST; 862 } 863 864 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 865 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 866 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 867 != NORMAL_VALUE) { 868 return ASC_IERR_BIST_PRE_TEST; 869 } 870 } 871 872 /* 873 * LRAM Test - It takes about 1.5 ms to run through the test. 874 * 875 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 876 * If Done bit not set or Status not 0, save register byte, set the 877 * err_code, and return an error. 878 */ 879 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 880 AdvSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 881 882 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 883 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 884 /* Get here if Done bit not set or Status not 0. */ 885 return ASC_IERR_BIST_RAM_TEST; 886 } 887 888 /* We need to reset back to normal mode after LRAM test passes. */ 889 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 890 891 /* 892 * Load the Microcode 893 * 894 * Write the microcode image to RISC memory starting at address 0. 895 * 896 */ 897 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 898 899 /* Assume the following compressed format of the microcode buffer: 900 * 901 * 254 word (508 byte) table indexed by byte code followed 902 * by the following byte codes: 903 * 904 * 1-Byte Code: 905 * 00: Emit word 0 in table. 906 * 01: Emit word 1 in table. 907 * . 908 * FD: Emit word 253 in table. 909 * 910 * Multi-Byte Code: 911 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 912 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 913 */ 914 word = 0; 915 for (i = 253 * 2; i < adv_asc38C0800_mcode_size; i++) { 916 if (adv_asc38C0800_mcode[i] == 0xff) { 917 for (j = 0; j < adv_asc38C0800_mcode[i + 1]; j++) { 918 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 919 (((u_int16_t) 920 adv_asc38C0800_mcode[i + 3] << 8) | 921 adv_asc38C0800_mcode[i + 2])); 922 word++; 923 } 924 i += 3; 925 } else if (adv_asc38C0800_mcode[i] == 0xfe) { 926 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 927 adv_asc38C0800_mcode[i + 2] << 8) | 928 adv_asc38C0800_mcode[i + 1])); 929 i += 2; 930 word++; 931 } else { 932 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 933 adv_asc38C0800_mcode[(adv_asc38C0800_mcode[i] * 2) + 1] << 8) | 934 adv_asc38C0800_mcode[adv_asc38C0800_mcode[i] * 2])); 935 word++; 936 } 937 } 938 939 /* 940 * Set 'word' for later use to clear the rest of memory and save 941 * the expanded mcode size. 942 */ 943 word *= 2; 944 adv_asc38C0800_expanded_size = word; 945 946 /* 947 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 948 */ 949 for (; word < ADV_38C0800_MEMSIZE; word += 2) { 950 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 951 } 952 953 /* 954 * Verify the microcode checksum. 955 */ 956 sum = 0; 957 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 958 959 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2) { 960 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 961 } 962 963 if (sum != adv_asc38C0800_mcode_chksum) { 964 return ASC_IERR_MCODE_CHKSUM; 965 } 966 967 /* 968 * Restore the RISC memory BIOS region. 969 */ 970 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 971 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 972 bios_mem[i]); 973 } 974 975 /* 976 * Calculate and write the microcode code checksum to the microcode 977 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 978 */ 979 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 980 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 981 code_sum = 0; 982 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 983 for (word = begin_addr; word < end_addr; word += 2) { 984 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 985 } 986 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 987 988 /* 989 * Read microcode version and date. 990 */ 991 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 992 sc->cfg.mcode_date); 993 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 994 sc->cfg.mcode_version); 995 996 /* 997 * Set the chip type to indicate the ASC38C0800. 998 */ 999 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 1000 1001 /* 1002 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 1003 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 1004 * cable detection and then we are able to read C_DET[3:0]. 1005 * 1006 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 1007 * Microcode Default Value' section below. 1008 */ 1009 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1010 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 1011 scsi_cfg1 | ADW_DIS_TERM_DRV); 1012 1013 /* 1014 * If the PCI Configuration Command Register "Parity Error Response 1015 * Control" Bit was clear (0), then set the microcode variable 1016 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 1017 * to ignore DMA parity errors. 1018 */ 1019 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 1020 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1021 word |= CONTROL_FLAG_IGNORE_PERR; 1022 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1023 } 1024 1025 /* 1026 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 1027 * START_CTL_TH [3:2] bits for the default FIFO threshold. 1028 * 1029 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 1030 * 1031 * For DMA Errata #4 set the BC_THRESH_ENB bit. 1032 */ 1033 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 1034 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 1035 1036 /* 1037 * Microcode operating variables for WDTR, SDTR, and command tag 1038 * queuing will be set in AdvInquiryHandling() based on what a 1039 * device reports it is capable of in Inquiry byte 7. 1040 * 1041 * If SCSI Bus Resets have been disabled, then directly set 1042 * SDTR and WDTR from the EEPROM configuration. This will allow 1043 * the BIOS and warm boot to work without a SCSI bus hang on 1044 * the Inquiry caused by host and target mismatched DTR values. 1045 * Without the SCSI Bus Reset, before an Inquiry a device can't 1046 * be assumed to be in Asynchronous, Narrow mode. 1047 */ 1048 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 1049 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, sc->wdtr_able); 1050 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sc->sdtr_able); 1051 } 1052 1053 /* 1054 * Set microcode operating variables for DISC and SDTR_SPEED1, 1055 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 1056 * configuration values. 1057 * 1058 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1059 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1060 * without determining here whether the device supports SDTR. 1061 */ 1062 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 1063 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, sc->sdtr_speed1); 1064 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, sc->sdtr_speed2); 1065 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, sc->sdtr_speed3); 1066 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, sc->sdtr_speed4); 1067 1068 /* 1069 * Set SCSI_CFG0 Microcode Default Value. 1070 * 1071 * The microcode will set the SCSI_CFG0 register using this value 1072 * after it is started below. 1073 */ 1074 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 1075 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 1076 ADW_OUR_ID_EN | sc->chip_scsi_id); 1077 1078 /* 1079 * Determine SCSI_CFG1 Microcode Default Value. 1080 * 1081 * The microcode will set the SCSI_CFG1 register using this value 1082 * after it is started below. 1083 */ 1084 1085 /* Read current SCSI_CFG1 Register value. */ 1086 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1087 1088 /* 1089 * If the internal narrow cable is reversed all of the SCSI_CTRL 1090 * register signals will be set. Check for and return an error if 1091 * this condition is found. 1092 */ 1093 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1094 0x3F07) { 1095 return ASC_IERR_REVERSED_CABLE; 1096 } 1097 1098 /* 1099 * All kind of combinations of devices attached to one of four connectors 1100 * are acceptable except HVD device attached. For example, LVD device can 1101 * be attached to SE connector while SE device attached to LVD connector. 1102 * If LVD device attached to SE connector, it only runs up to Ultra speed. 1103 * 1104 * If an HVD device is attached to one of LVD connectors, return an error. 1105 * However, there is no way to detect HVD device attached to SE connectors. 1106 */ 1107 if (scsi_cfg1 & ADW_HVD) { 1108 return ASC_IERR_HVD_DEVICE; 1109 } 1110 1111 /* 1112 * If either SE or LVD automatic termination control is enabled, then 1113 * set the termination value based on a table listed in a_condor.h. 1114 * 1115 * If manual termination was specified with an EEPROM setting then 1116 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to 1117 * be 'ored' into SCSI_CFG1. 1118 */ 1119 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1120 /* SE automatic termination control is enabled. */ 1121 switch(scsi_cfg1 & ADW_C_DET_SE) { 1122 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1123 case 0x1: case 0x2: case 0x3: 1124 sc->cfg.termination |= ADW_TERM_SE; 1125 break; 1126 1127 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1128 case 0x0: 1129 sc->cfg.termination |= ADW_TERM_SE_HI; 1130 break; 1131 } 1132 } 1133 1134 if ((sc->cfg.termination & ADW_TERM_LVD) == 0) { 1135 /* LVD automatic termination control is enabled. */ 1136 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1137 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1138 case 0x4: case 0x8: case 0xC: 1139 sc->cfg.termination |= ADW_TERM_LVD; 1140 break; 1141 1142 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1143 case 0x0: 1144 break; 1145 } 1146 } 1147 1148 /* 1149 * Clear any set TERM_SE and TERM_LVD bits. 1150 */ 1151 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1152 1153 /* 1154 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1155 */ 1156 scsi_cfg1 |= (~sc->cfg.termination & 0xF0); 1157 1158 /* 1159 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits 1160 * and set possibly modified termination control bits in the Microcode 1161 * SCSI_CFG1 Register Value. 1162 */ 1163 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1164 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1165 1166 /* 1167 * Set SCSI_CFG1 Microcode Default Value 1168 * 1169 * Set possibly modified termination control and reset DIS_TERM_DRV 1170 * bits in the Microcode SCSI_CFG1 Register Value. 1171 * 1172 * The microcode will set the SCSI_CFG1 register using this value 1173 * after it is started below. 1174 */ 1175 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1176 1177 /* 1178 * Set MEM_CFG Microcode Default Value 1179 * 1180 * The microcode will set the MEM_CFG register using this value 1181 * after it is started below. 1182 * 1183 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1184 * are defined. 1185 * 1186 * ASC-38C0800 has 16KB internal memory. 1187 */ 1188 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 1189 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1190 1191 /* 1192 * Set SEL_MASK Microcode Default Value 1193 * 1194 * The microcode will set the SEL_MASK register using this value 1195 * after it is started below. 1196 */ 1197 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 1198 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1199 1200 1201 /* 1202 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1203 */ 1204 1205 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1206 return ASC_IERR_NO_CARRIER; 1207 } 1208 sc->carr_freelist = adw_carrier_phys_kv(sc, 1209 ASC_GET_CARRP(sc->icq_sp->next_ba)); 1210 1211 /* 1212 * The first command issued will be placed in the stopper carrier. 1213 */ 1214 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 1215 1216 /* 1217 * Set RISC ICQ physical address start value. 1218 */ 1219 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_ba); 1220 1221 /* 1222 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1223 */ 1224 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1225 return ASC_IERR_NO_CARRIER; 1226 } 1227 sc->carr_freelist = adw_carrier_phys_kv(sc, 1228 ASC_GET_CARRP(sc->irq_sp->next_ba)); 1229 1230 /* 1231 * The first command completed by the RISC will be placed in 1232 * the stopper. 1233 * 1234 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 1235 * completed the RISC will set the ASC_RQ_STOPPER bit. 1236 */ 1237 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 1238 1239 /* 1240 * Set RISC IRQ physical address start value. 1241 */ 1242 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_ba); 1243 sc->carr_pending_cnt = 0; 1244 1245 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1246 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1247 1248 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 1249 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1250 1251 /* finally, finally, gentlemen, start your engine */ 1252 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1253 1254 /* 1255 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1256 * Resets should be performed. The RISC has to be running 1257 * to issue a SCSI Bus Reset. 1258 */ 1259 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1260 /* 1261 * If the BIOS Signature is present in memory, restore the 1262 * BIOS Handshake Configuration Table and do not perform 1263 * a SCSI Bus Reset. 1264 */ 1265 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 1266 0x55AA) { 1267 /* 1268 * Restore per TID negotiated values. 1269 */ 1270 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 1271 wdtr_able); 1272 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 1273 sdtr_able); 1274 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1275 tagqng_able); 1276 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1277 ADW_WRITE_BYTE_LRAM(iot, ioh, 1278 ASC_MC_NUMBER_OF_MAX_CMD + tid, 1279 max_cmd[tid]); 1280 } 1281 } else { 1282 if (AdvResetCCB(sc) != ADW_TRUE) { 1283 warn_code = ASC_WARN_BUSRESET_ERROR; 1284 } 1285 } 1286 } 1287 1288 return warn_code; 1289 } 1290 1291 1292 /* 1293 * Initialize the ASC-38C1600. 1294 * 1295 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 1296 * 1297 * For a non-fatal error return a warning code. If there are no warnings 1298 * then 0 is returned. 1299 */ 1300 int 1301 AdvInitAsc38C1600Driver(sc) 1302 ADW_SOFTC *sc; 1303 { 1304 bus_space_tag_t iot = sc->sc_iot; 1305 bus_space_handle_t ioh = sc->sc_ioh; 1306 u_int16_t warn_code; 1307 u_int32_t sum; 1308 int begin_addr; 1309 int end_addr; 1310 u_int16_t code_sum; 1311 int word; 1312 int i, j; 1313 int adv_asc38C1600_expanded_size; 1314 u_int16_t scsi_cfg1; 1315 u_int8_t byte; 1316 u_int8_t tid; 1317 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 1318 0x40-0x8F. */ 1319 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1320 u_int8_t max_cmd[ADW_MAX_TID + 1]; 1321 1322 1323 warn_code = 0; 1324 1325 1326 /* 1327 * Save the RISC memory BIOS region before writing the microcode. 1328 * The BIOS may already be loaded and using its RISC LRAM region 1329 * so its region must be saved and restored. 1330 * 1331 * Note: This code makes the assumption, which is currently true, 1332 * that a chip reset does not clear RISC LRAM. 1333 */ 1334 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 1335 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]); 1336 } 1337 1338 /* 1339 * Save current per TID negotiated values. 1340 */ 1341 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 1342 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 1343 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, ppr_able); 1344 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 1345 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1346 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 1347 max_cmd[tid]); 1348 } 1349 1350 /* 1351 * RAM BIST (RAM Built-In Self Test) 1352 * 1353 * Address : I/O base + offset 0x38h register (byte). 1354 * Function: Bit 7-6(RW) : RAM mode 1355 * Normal Mode : 0x00 1356 * Pre-test Mode : 0x40 1357 * RAM Test Mode : 0x80 1358 * Bit 5 : unused 1359 * Bit 4(RO) : Done bit 1360 * Bit 3-0(RO) : Status 1361 * Host Error : 0x08 1362 * Int_RAM Error : 0x04 1363 * RISC Error : 0x02 1364 * SCSI Error : 0x01 1365 * No Error : 0x00 1366 * 1367 * Note: RAM BIST code should be put right here, before loading the 1368 * microcode and after saving the RISC memory BIOS region. 1369 */ 1370 1371 /* 1372 * LRAM Pre-test 1373 * 1374 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 1375 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 1376 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 1377 * to NORMAL_MODE, return an error too. 1378 */ 1379 for (i = 0; i < 2; i++) { 1380 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 1381 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 1382 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1383 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 1384 PRE_TEST_VALUE) { 1385 return ASC_IERR_BIST_PRE_TEST; 1386 } 1387 1388 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1389 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 1390 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1391 != NORMAL_VALUE) { 1392 return ASC_IERR_BIST_PRE_TEST; 1393 } 1394 } 1395 1396 /* 1397 * LRAM Test - It takes about 1.5 ms to run through the test. 1398 * 1399 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 1400 * If Done bit not set or Status not 0, save register byte, set the 1401 * err_code, and return an error. 1402 */ 1403 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1404 AdvSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 1405 1406 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1407 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 1408 /* Get here if Done bit not set or Status not 0. */ 1409 return ASC_IERR_BIST_RAM_TEST; 1410 } 1411 1412 /* We need to reset back to normal mode after LRAM test passes. */ 1413 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1414 1415 1416 /* 1417 * Load the Microcode 1418 * 1419 * Write the microcode image to RISC memory starting at address 0. 1420 * 1421 */ 1422 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1423 1424 /* Assume the following compressed format of the microcode buffer: 1425 * 1426 * 254 word (508 byte) table indexed by byte code followed 1427 * by the following byte codes: 1428 * 1429 * 1-Byte Code: 1430 * 00: Emit word 0 in table. 1431 * 01: Emit word 1 in table. 1432 * . 1433 * FD: Emit word 253 in table. 1434 * 1435 * Multi-Byte Code: 1436 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1437 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1438 */ 1439 word = 0; 1440 for (i = 253 * 2; i < adv_asc38C1600_mcode_size; i++) { 1441 if (adv_asc38C1600_mcode[i] == 0xff) { 1442 for (j = 0; j < adv_asc38C1600_mcode[i + 1]; j++) { 1443 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1444 (((u_int16_t) 1445 adv_asc38C1600_mcode[i + 3] << 8) | 1446 adv_asc38C1600_mcode[i + 2])); 1447 word++; 1448 } 1449 i += 3; 1450 } else if (adv_asc38C1600_mcode[i] == 0xfe) { 1451 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1452 adv_asc38C1600_mcode[i + 2] << 8) | 1453 adv_asc38C1600_mcode[i + 1])); 1454 i += 2; 1455 word++; 1456 } else { 1457 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1458 adv_asc38C1600_mcode[(adv_asc38C1600_mcode[i] * 2) + 1] << 8) | 1459 adv_asc38C1600_mcode[adv_asc38C1600_mcode[i] * 2])); 1460 word++; 1461 } 1462 } 1463 1464 /* 1465 * Set 'word' for later use to clear the rest of memory and save 1466 * the expanded mcode size. 1467 */ 1468 word *= 2; 1469 adv_asc38C1600_expanded_size = word; 1470 1471 /* 1472 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 1473 */ 1474 for (; word < ADV_38C1600_MEMSIZE; word += 2) { 1475 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1476 } 1477 1478 /* 1479 * Verify the microcode checksum. 1480 */ 1481 sum = 0; 1482 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1483 1484 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2) { 1485 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1486 } 1487 1488 if (sum != adv_asc38C1600_mcode_chksum) { 1489 return ASC_IERR_MCODE_CHKSUM; 1490 } 1491 1492 /* 1493 * Restore the RISC memory BIOS region. 1494 */ 1495 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 1496 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 1497 bios_mem[i]); 1498 } 1499 1500 /* 1501 * Calculate and write the microcode code checksum to the microcode 1502 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 1503 */ 1504 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 1505 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 1506 code_sum = 0; 1507 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1508 for (word = begin_addr; word < end_addr; word += 2) { 1509 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1510 } 1511 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 1512 1513 /* 1514 * Read microcode version and date. 1515 */ 1516 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 1517 sc->cfg.mcode_date); 1518 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 1519 sc->cfg.mcode_version); 1520 1521 /* 1522 * Set the chip type to indicate the ASC38C1600. 1523 */ 1524 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); 1525 1526 /* 1527 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 1528 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 1529 * cable detection and then we are able to read C_DET[3:0]. 1530 * 1531 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 1532 * Microcode Default Value' section below. 1533 */ 1534 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1535 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 1536 scsi_cfg1 | ADW_DIS_TERM_DRV); 1537 1538 /* 1539 * If the PCI Configuration Command Register "Parity Error Response 1540 * Control" Bit was clear (0), then set the microcode variable 1541 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 1542 * to ignore DMA parity errors. 1543 */ 1544 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 1545 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1546 word |= CONTROL_FLAG_IGNORE_PERR; 1547 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1548 } 1549 1550 /* 1551 * If the BIOS control flag AIPP (Asynchronous Information 1552 * Phase Protection) disable bit is not set, then set the firmware 1553 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 1554 * AIPP checking and encoding. 1555 */ 1556 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 1557 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1558 word |= CONTROL_FLAG_ENABLE_AIPP; 1559 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 1560 } 1561 1562 /* 1563 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 1564 * and START_CTL_TH [3:2]. 1565 */ 1566 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 1567 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 1568 1569 /* 1570 * Microcode operating variables for WDTR, SDTR, and command tag 1571 * queuing will be set in AdvInquiryHandling() based on what a 1572 * device reports it is capable of in Inquiry byte 7. 1573 * 1574 * If SCSI Bus Resets have been disabled, then directly set 1575 * SDTR and WDTR from the EEPROM configuration. This will allow 1576 * the BIOS and warm boot to work without a SCSI bus hang on 1577 * the Inquiry caused by host and target mismatched DTR values. 1578 * Without the SCSI Bus Reset, before an Inquiry a device can't 1579 * be assumed to be in Asynchronous, Narrow mode. 1580 */ 1581 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 1582 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, sc->wdtr_able); 1583 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sc->sdtr_able); 1584 } 1585 1586 /* 1587 * Set microcode operating variables for DISC and SDTR_SPEED1, 1588 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 1589 * configuration values. 1590 * 1591 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1592 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1593 * without determining here whether the device supports SDTR. 1594 */ 1595 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 1596 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, sc->sdtr_speed1); 1597 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, sc->sdtr_speed2); 1598 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, sc->sdtr_speed3); 1599 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, sc->sdtr_speed4); 1600 1601 /* 1602 * Set SCSI_CFG0 Microcode Default Value. 1603 * 1604 * The microcode will set the SCSI_CFG0 register using this value 1605 * after it is started below. 1606 */ 1607 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 1608 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 1609 ADW_OUR_ID_EN | sc->chip_scsi_id); 1610 1611 /* 1612 * Calculate SCSI_CFG1 Microcode Default Value. 1613 * 1614 * The microcode will set the SCSI_CFG1 register using this value 1615 * after it is started below. 1616 * 1617 * Each ASC-38C1600 function has only two cable detect bits. 1618 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1619 */ 1620 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1621 1622 /* 1623 * If the cable is reversed all of the SCSI_CTRL register signals 1624 * will be set. Check for and return an error if this condition is 1625 * found. 1626 */ 1627 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1628 0x3F07) { 1629 return ASC_IERR_REVERSED_CABLE; 1630 } 1631 1632 /* 1633 * Each ASC-38C1600 function has two connectors. Only an HVD device 1634 * can not be connected to either connector. An LVD device or SE device 1635 * may be connected to either connecor. If an SE device is connected, 1636 * then at most Ultra speed (20 Mhz) can be used on both connectors. 1637 * 1638 * If an HVD device is attached, return an error. 1639 */ 1640 if (scsi_cfg1 & ADW_HVD) { 1641 return ASC_IERR_HVD_DEVICE; 1642 } 1643 1644 /* 1645 * Each function in the ASC-38C1600 uses only the SE cable detect and 1646 * termination because there are two connectors for each function. Each 1647 * function may use either LVD or SE mode. Corresponding the SE automatic 1648 * termination control EEPROM bits are used for each function. Each 1649 * function has its own EEPROM. If SE automatic control is enabled for 1650 * the function, then set the termination value based on a table listed 1651 * in a_condor.h. 1652 * 1653 * If manual termination is specified in the EEPROM for the function, 1654 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 1655 * ready to be 'ored' into SCSI_CFG1. 1656 */ 1657 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1658 /* SE automatic termination control is enabled. */ 1659 switch(scsi_cfg1 & ADW_C_DET_SE) { 1660 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1661 case 0x1: case 0x2: case 0x3: 1662 sc->cfg.termination |= ADW_TERM_SE; 1663 break; 1664 1665 case 0x0: 1666 /* !!!!TODO!!!! */ 1667 // if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0) { 1668 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1669 // } 1670 // else 1671 // { 1672 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1673 sc->cfg.termination |= ADW_TERM_SE_HI; 1674 // } 1675 break; 1676 } 1677 } 1678 1679 /* 1680 * Clear any set TERM_SE bits. 1681 */ 1682 scsi_cfg1 &= ~ADW_TERM_SE; 1683 1684 /* 1685 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1686 */ 1687 scsi_cfg1 |= (~sc->cfg.termination & ADW_TERM_SE); 1688 1689 /* 1690 * Clear Big Endian and Terminator Polarity bits and set possibly 1691 * modified termination control bits in the Microcode SCSI_CFG1 1692 * Register Value. 1693 */ 1694 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1695 1696 /* 1697 * Set SCSI_CFG1 Microcode Default Value 1698 * 1699 * Set possibly modified termination control bits in the Microcode 1700 * SCSI_CFG1 Register Value. 1701 * 1702 * The microcode will set the SCSI_CFG1 register using this value 1703 * after it is started below. 1704 */ 1705 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1706 1707 /* 1708 * Set MEM_CFG Microcode Default Value 1709 * 1710 * The microcode will set the MEM_CFG register using this value 1711 * after it is started below. 1712 * 1713 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1714 * are defined. 1715 * 1716 * ASC-38C1600 has 32KB internal memory. 1717 */ 1718 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 1719 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1720 1721 /* 1722 * Set SEL_MASK Microcode Default Value 1723 * 1724 * The microcode will set the SEL_MASK register using this value 1725 * after it is started below. 1726 */ 1727 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 1728 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1729 1730 /* 1731 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1732 */ 1733 1734 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1735 return ASC_IERR_NO_CARRIER; 1736 } 1737 sc->carr_freelist = adw_carrier_phys_kv(sc, 1738 ASC_GET_CARRP(sc->icq_sp->next_ba)); 1739 1740 /* 1741 * The first command issued will be placed in the stopper carrier. 1742 */ 1743 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 1744 1745 /* 1746 * Set RISC ICQ physical address start value. Initialize the 1747 * COMMA register to the same value otherwise the RISC will 1748 * prematurely detect a command is available. 1749 */ 1750 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_ba); 1751 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, sc->icq_sp->carr_ba); 1752 1753 /* 1754 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1755 */ 1756 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1757 return ASC_IERR_NO_CARRIER; 1758 } 1759 sc->carr_freelist = adw_carrier_phys_kv(sc, 1760 ASC_GET_CARRP(sc->irq_sp->next_ba)); 1761 1762 /* 1763 * The first command completed by the RISC will be placed in 1764 * the stopper. 1765 * 1766 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 1767 * completed the RISC will set the ASC_RQ_STOPPER bit. 1768 */ 1769 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 1770 1771 /* 1772 * Set RISC IRQ physical address start value. 1773 */ 1774 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_ba); 1775 sc->carr_pending_cnt = 0; 1776 1777 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1778 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1779 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 1780 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1781 1782 /* finally, finally, gentlemen, start your engine */ 1783 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1784 1785 /* 1786 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1787 * Resets should be performed. The RISC has to be running 1788 * to issue a SCSI Bus Reset. 1789 */ 1790 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1791 /* 1792 * If the BIOS Signature is present in memory, restore the 1793 * per TID microcode operating variables. 1794 */ 1795 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 1796 0x55AA) { 1797 /* 1798 * Restore per TID negotiated values. 1799 */ 1800 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 1801 wdtr_able); 1802 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 1803 sdtr_able); 1804 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, 1805 ppr_able); 1806 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1807 tagqng_able); 1808 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1809 ADW_WRITE_BYTE_LRAM(iot, ioh, 1810 ASC_MC_NUMBER_OF_MAX_CMD + tid, 1811 max_cmd[tid]); 1812 } 1813 } else { 1814 if (AdvResetCCB(sc) != ADW_TRUE) { 1815 warn_code = ASC_WARN_BUSRESET_ERROR; 1816 } 1817 } 1818 } 1819 1820 return warn_code; 1821 } 1822 1823 1824 /* 1825 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1826 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1827 * all of this is done. 1828 * 1829 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1830 * 1831 * For a non-fatal error return a warning code. If there are no warnings 1832 * then 0 is returned. 1833 * 1834 * Note: Chip is stopped on entry. 1835 */ 1836 int 1837 AdvInitFrom3550EEP(sc) 1838 ADW_SOFTC *sc; 1839 { 1840 bus_space_tag_t iot = sc->sc_iot; 1841 bus_space_handle_t ioh = sc->sc_ioh; 1842 u_int16_t warn_code; 1843 ADW_EEP_3550_CONFIG eep_config; 1844 int i; 1845 1846 1847 warn_code = 0; 1848 1849 /* 1850 * Read the board's EEPROM configuration. 1851 * 1852 * Set default values if a bad checksum is found. 1853 * 1854 * XXX - Don't handle big-endian access to EEPROM yet. 1855 */ 1856 if (AdvGet3550EEPConfig(iot, ioh, &eep_config) != eep_config.check_sum){ 1857 warn_code |= ASC_WARN_EEPROM_CHKSUM; 1858 1859 /* 1860 * Set EEPROM default values. 1861 */ 1862 for (i = 0; i < sizeof(ADW_EEP_3550_CONFIG); i++) { 1863 *((u_int8_t *) &eep_config + i) = 1864 *((u_int8_t *) &Default_3550_EEPROM_Config + i); 1865 } 1866 1867 /* 1868 * Assume the 6 byte board serial number that was read 1869 * from EEPROM is correct even if the EEPROM checksum 1870 * failed. 1871 */ 1872 eep_config.serial_number_word3 = 1873 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 1874 1875 eep_config.serial_number_word2 = 1876 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 1877 1878 eep_config.serial_number_word1 = 1879 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 1880 1881 AdvSet3550EEPConfig(iot, ioh, &eep_config); 1882 } 1883 /* 1884 * Set sc and sc->cfg variables from the EEPROM configuration 1885 * that was read. 1886 * 1887 * This is the mapping of EEPROM fields to Adv Library fields. 1888 */ 1889 sc->wdtr_able = eep_config.wdtr_able; 1890 sc->sdtr_able = eep_config.sdtr_able; 1891 sc->ultra_able = eep_config.ultra_able; 1892 sc->tagqng_able = eep_config.tagqng_able; 1893 sc->cfg.disc_enable = eep_config.disc_enable; 1894 sc->max_host_qng = eep_config.max_host_qng; 1895 sc->max_dvc_qng = eep_config.max_dvc_qng; 1896 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 1897 sc->start_motor = eep_config.start_motor; 1898 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 1899 sc->bios_ctrl = eep_config.bios_ctrl; 1900 sc->no_scam = eep_config.scam_tolerant; 1901 sc->cfg.serial1 = eep_config.serial_number_word1; 1902 sc->cfg.serial2 = eep_config.serial_number_word2; 1903 sc->cfg.serial3 = eep_config.serial_number_word3; 1904 1905 /* 1906 * Set the host maximum queuing (max. 253, min. 16) and the per device 1907 * maximum queuing (max. 63, min. 4). 1908 */ 1909 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 1910 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1911 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) 1912 { 1913 /* If the value is zero, assume it is uninitialized. */ 1914 if (eep_config.max_host_qng == 0) { 1915 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1916 } else { 1917 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 1918 } 1919 } 1920 1921 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 1922 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1923 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 1924 /* If the value is zero, assume it is uninitialized. */ 1925 if (eep_config.max_dvc_qng == 0) { 1926 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1927 } else { 1928 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 1929 } 1930 } 1931 1932 /* 1933 * If 'max_dvc_qng' is greater than 'max_host_qng', then 1934 * set 'max_dvc_qng' to 'max_host_qng'. 1935 */ 1936 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 1937 eep_config.max_dvc_qng = eep_config.max_host_qng; 1938 } 1939 1940 /* 1941 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 1942 * values based on possibly adjusted EEPROM values. 1943 */ 1944 sc->max_host_qng = eep_config.max_host_qng; 1945 sc->max_dvc_qng = eep_config.max_dvc_qng; 1946 1947 1948 /* 1949 * If the EEPROM 'termination' field is set to automatic (0), then set 1950 * the ADV_DVC_CFG 'termination' field to automatic also. 1951 * 1952 * If the termination is specified with a non-zero 'termination' 1953 * value check that a legal value is set and set the ADV_DVC_CFG 1954 * 'termination' field appropriately. 1955 */ 1956 1957 sc->cfg.termination = 0; /* auto termination */ 1958 switch(eep_config.termination) { 1959 case 3: 1960 /* Enable manual control with low on / high on. */ 1961 sc->cfg.termination |= ADW_TERM_CTL_L; 1962 case 2: 1963 /* Enable manual control with low off / high on. */ 1964 sc->cfg.termination |= ADW_TERM_CTL_H; 1965 case 1: 1966 /* Enable manual control with low off / high off. */ 1967 sc->cfg.termination |= ADW_TERM_CTL_SEL; 1968 case 0: 1969 break; 1970 default: 1971 warn_code |= ASC_WARN_EEPROM_TERMINATION; 1972 } 1973 1974 return warn_code; 1975 } 1976 1977 1978 /* 1979 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1980 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1981 * all of this is done. 1982 * 1983 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1984 * 1985 * For a non-fatal error return a warning code. If there are no warnings 1986 * then 0 is returned. 1987 * 1988 * Note: Chip is stopped on entry. 1989 */ 1990 int 1991 AdvInitFrom38C0800EEP(sc) 1992 ADW_SOFTC *sc; 1993 { 1994 bus_space_tag_t iot = sc->sc_iot; 1995 bus_space_handle_t ioh = sc->sc_ioh; 1996 u_int16_t warn_code; 1997 ADW_EEP_38C0800_CONFIG eep_config; 1998 int i; 1999 u_int8_t tid, termination; 2000 u_int16_t sdtr_speed = 0; 2001 2002 2003 warn_code = 0; 2004 2005 /* 2006 * Read the board's EEPROM configuration. 2007 * 2008 * Set default values if a bad checksum is found. 2009 */ 2010 if (AdvGet38C0800EEPConfig(iot, ioh, &eep_config) != 2011 eep_config.check_sum) { 2012 warn_code |= ASC_WARN_EEPROM_CHKSUM; 2013 2014 /* 2015 * Set EEPROM default values. 2016 */ 2017 for (i = 0; i < sizeof(ADW_EEP_38C0800_CONFIG); i++) { 2018 *((u_int8_t *) &eep_config + i) = 2019 *((u_int8_t *)&Default_38C0800_EEPROM_Config+i); 2020 } 2021 2022 /* 2023 * Assume the 6 byte board serial number that was read 2024 * from EEPROM is correct even if the EEPROM checksum 2025 * failed. 2026 */ 2027 eep_config.serial_number_word3 = 2028 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 2029 2030 eep_config.serial_number_word2 = 2031 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 2032 2033 eep_config.serial_number_word1 = 2034 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 2035 2036 AdvSet38C0800EEPConfig(iot, ioh, &eep_config); 2037 } 2038 /* 2039 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 2040 * EEPROM configuration that was read. 2041 * 2042 * This is the mapping of EEPROM fields to Adv Library fields. 2043 */ 2044 sc->wdtr_able = eep_config.wdtr_able; 2045 sc->sdtr_speed1 = eep_config.sdtr_speed1; 2046 sc->sdtr_speed2 = eep_config.sdtr_speed2; 2047 sc->sdtr_speed3 = eep_config.sdtr_speed3; 2048 sc->sdtr_speed4 = eep_config.sdtr_speed4; 2049 sc->tagqng_able = eep_config.tagqng_able; 2050 sc->cfg.disc_enable = eep_config.disc_enable; 2051 sc->max_host_qng = eep_config.max_host_qng; 2052 sc->max_dvc_qng = eep_config.max_dvc_qng; 2053 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 2054 sc->start_motor = eep_config.start_motor; 2055 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 2056 sc->bios_ctrl = eep_config.bios_ctrl; 2057 sc->no_scam = eep_config.scam_tolerant; 2058 sc->cfg.serial1 = eep_config.serial_number_word1; 2059 sc->cfg.serial2 = eep_config.serial_number_word2; 2060 sc->cfg.serial3 = eep_config.serial_number_word3; 2061 2062 /* 2063 * For every Target ID if any of its 'sdtr_speed[1234]' bits 2064 * are set, then set an 'sdtr_able' bit for it. 2065 */ 2066 sc->sdtr_able = 0; 2067 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2068 if (tid == 0) { 2069 sdtr_speed = sc->sdtr_speed1; 2070 } else if (tid == 4) { 2071 sdtr_speed = sc->sdtr_speed2; 2072 } else if (tid == 8) { 2073 sdtr_speed = sc->sdtr_speed3; 2074 } else if (tid == 12) { 2075 sdtr_speed = sc->sdtr_speed4; 2076 } 2077 if (sdtr_speed & ADW_MAX_TID) { 2078 sc->sdtr_able |= (1 << tid); 2079 } 2080 sdtr_speed >>= 4; 2081 } 2082 2083 /* 2084 * Set the host maximum queuing (max. 253, min. 16) and the per device 2085 * maximum queuing (max. 63, min. 4). 2086 */ 2087 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 2088 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2089 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 2090 /* If the value is zero, assume it is uninitialized. */ 2091 if (eep_config.max_host_qng == 0) { 2092 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2093 } else { 2094 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 2095 } 2096 } 2097 2098 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 2099 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2100 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 2101 /* If the value is zero, assume it is uninitialized. */ 2102 if (eep_config.max_dvc_qng == 0) { 2103 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2104 } else { 2105 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 2106 } 2107 } 2108 2109 /* 2110 * If 'max_dvc_qng' is greater than 'max_host_qng', then 2111 * set 'max_dvc_qng' to 'max_host_qng'. 2112 */ 2113 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 2114 eep_config.max_dvc_qng = eep_config.max_host_qng; 2115 } 2116 2117 /* 2118 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 2119 * values based on possibly adjusted EEPROM values. 2120 */ 2121 sc->max_host_qng = eep_config.max_host_qng; 2122 sc->max_dvc_qng = eep_config.max_dvc_qng; 2123 2124 /* 2125 * If the EEPROM 'termination' field is set to automatic (0), then set 2126 * the ADV_DVC_CFG 'termination' field to automatic also. 2127 * 2128 * If the termination is specified with a non-zero 'termination' 2129 * value check that a legal value is set and set the ADV_DVC_CFG 2130 * 'termination' field appropriately. 2131 */ 2132 2133 switch(eep_config.termination_se) { 2134 case 0: 2135 /* auto termination for SE */ 2136 termination = 0; 2137 break; 2138 case 1: 2139 /* Enable manual control with low off / high off. */ 2140 termination = 0; 2141 break; 2142 case 2: 2143 /* Enable manual control with low off / high on. */ 2144 termination = ADW_TERM_SE_HI; 2145 break; 2146 case 3: 2147 /* Enable manual control with low on / high on. */ 2148 termination = ADW_TERM_SE; 2149 break; 2150 default: 2151 /* 2152 * The EEPROM 'termination_se' field contains a bad value. 2153 * Use automatic termination instead. 2154 */ 2155 termination = 0; 2156 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2157 } 2158 2159 switch(eep_config.termination_lvd) { 2160 case 0: 2161 /* auto termination for LVD */ 2162 sc->cfg.termination = termination; 2163 break; 2164 case 1: 2165 /* Enable manual control with low off / high off. */ 2166 sc->cfg.termination = termination; 2167 break; 2168 case 2: 2169 /* Enable manual control with low off / high on. */ 2170 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 2171 break; 2172 case 3: 2173 /* Enable manual control with low on / high on. */ 2174 sc->cfg.termination = termination | ADW_TERM_LVD; 2175 break; 2176 default: 2177 /* 2178 * The EEPROM 'termination_lvd' field contains a bad value. 2179 * Use automatic termination instead. 2180 */ 2181 sc->cfg.termination = termination; 2182 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2183 } 2184 2185 return warn_code; 2186 } 2187 2188 2189 /* 2190 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 2191 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 2192 * all of this is done. 2193 * 2194 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 2195 * 2196 * For a non-fatal error return a warning code. If there are no warnings 2197 * then 0 is returned. 2198 * 2199 * Note: Chip is stopped on entry. 2200 */ 2201 int 2202 AdvInitFrom38C1600EEP(sc) 2203 ADW_SOFTC *sc; 2204 { 2205 bus_space_tag_t iot = sc->sc_iot; 2206 bus_space_handle_t ioh = sc->sc_ioh; 2207 u_int16_t warn_code; 2208 ADW_EEP_38C1600_CONFIG eep_config; 2209 int i; 2210 u_int8_t tid, termination; 2211 u_int16_t sdtr_speed = 0; 2212 2213 2214 warn_code = 0; 2215 2216 /* 2217 * Read the board's EEPROM configuration. 2218 * 2219 * Set default values if a bad checksum is found. 2220 */ 2221 if (AdvGet38C1600EEPConfig(iot, ioh, &eep_config) != 2222 eep_config.check_sum) { 2223 warn_code |= ASC_WARN_EEPROM_CHKSUM; 2224 2225 /* 2226 * Set EEPROM default values. 2227 */ 2228 for (i = 0; i < sizeof(ADW_EEP_38C1600_CONFIG); i++) { 2229 /* !!!!TODO!!!! */ 2230 // if (i == 1 && ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 2231 if (i == 1 ) { 2232 /* 2233 * Set Function 1 EEPROM Word 0 MSB 2234 * 2235 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11) 2236 * EEPROM bits. 2237 * 2238 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and 2239 * old Mac system booting problem. The Expansion ROM must 2240 * be disabled in Function 1 for these systems. 2241 * 2242 */ 2243 *((u_int8_t *) &eep_config + i) = 2244 ((*((u_int8_t *) &Default_38C1600_EEPROM_Config + i)) & 2245 (~(((ADW_EEPROM_BIOS_ENABLE | ADW_EEPROM_INTAB) >> 8) & 2246 0xFF))); 2247 2248 /* 2249 * Set the INTAB (bit 11) if the GPIO 0 input 2250 * indicates the Function 1 interrupt line is 2251 * wired to INTA. 2252 * 2253 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 2254 * 1 - Function 1 interrupt line wired to INT A. 2255 * 0 - Function 1 interrupt line wired to INT B. 2256 * 2257 * Note: Adapter boards always have Function 0 2258 * wired to INTA. 2259 * Put all 5 GPIO bits in input mode and then 2260 * read their input values. 2261 */ 2262 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2263 IOPB_GPIO_CNTL, 0); 2264 if (ADW_READ_BYTE_REGISTER(iot, ioh, 2265 IOPB_GPIO_DATA) & 0x01) { 2266 /* Function 1 interrupt wired to INTA; 2267 Set EEPROM bit. */ 2268 *((u_int8_t *) &eep_config + i) |= 2269 ((ADW_EEPROM_INTAB >> 8) &0xFF); 2270 } 2271 } else { 2272 *((u_int8_t *)&eep_config + i) = 2273 *((u_int8_t *)&Default_38C1600_EEPROM_Config+i); 2274 } 2275 } 2276 2277 /* 2278 * Assume the 6 byte board serial number that was read 2279 * from EEPROM is correct even if the EEPROM checksum 2280 * failed. 2281 */ 2282 eep_config.serial_number_word3 = 2283 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 2284 2285 eep_config.serial_number_word2 = 2286 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 2287 2288 eep_config.serial_number_word1 = 2289 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 2290 2291 AdvSet38C1600EEPConfig(iot, ioh, &eep_config); 2292 } 2293 2294 /* 2295 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 2296 * EEPROM configuration that was read. 2297 * 2298 * This is the mapping of EEPROM fields to Adv Library fields. 2299 */ 2300 sc->wdtr_able = eep_config.wdtr_able; 2301 sc->sdtr_speed1 = eep_config.sdtr_speed1; 2302 sc->sdtr_speed2 = eep_config.sdtr_speed2; 2303 sc->sdtr_speed3 = eep_config.sdtr_speed3; 2304 sc->sdtr_speed4 = eep_config.sdtr_speed4; 2305 sc->ppr_able = 0; 2306 sc->tagqng_able = eep_config.tagqng_able; 2307 sc->cfg.disc_enable = eep_config.disc_enable; 2308 sc->max_host_qng = eep_config.max_host_qng; 2309 sc->max_dvc_qng = eep_config.max_dvc_qng; 2310 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 2311 sc->start_motor = eep_config.start_motor; 2312 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 2313 sc->bios_ctrl = eep_config.bios_ctrl; 2314 sc->no_scam = eep_config.scam_tolerant; 2315 2316 /* 2317 * For every Target ID if any of its 'sdtr_speed[1234]' bits 2318 * are set, then set an 'sdtr_able' bit for it. 2319 */ 2320 sc->sdtr_able = 0; 2321 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2322 if (tid == 0) { 2323 sdtr_speed = sc->sdtr_speed1; 2324 } else if (tid == 4) { 2325 sdtr_speed = sc->sdtr_speed2; 2326 } else if (tid == 8) { 2327 sdtr_speed = sc->sdtr_speed3; 2328 } else if (tid == 12) { 2329 sdtr_speed = sc->sdtr_speed4; 2330 } 2331 if (sdtr_speed & ADW_MAX_TID) { 2332 sc->sdtr_able |= (1 << tid); 2333 } 2334 sdtr_speed >>= 4; 2335 } 2336 2337 /* 2338 * Set the host maximum queuing (max. 253, min. 16) and the per device 2339 * maximum queuing (max. 63, min. 4). 2340 */ 2341 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 2342 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2343 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 2344 /* If the value is zero, assume it is uninitialized. */ 2345 if (eep_config.max_host_qng == 0) { 2346 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 2347 } else { 2348 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 2349 } 2350 } 2351 2352 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 2353 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2354 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 2355 /* If the value is zero, assume it is uninitialized. */ 2356 if (eep_config.max_dvc_qng == 0) { 2357 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 2358 } else { 2359 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 2360 } 2361 } 2362 2363 /* 2364 * If 'max_dvc_qng' is greater than 'max_host_qng', then 2365 * set 'max_dvc_qng' to 'max_host_qng'. 2366 */ 2367 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 2368 eep_config.max_dvc_qng = eep_config.max_host_qng; 2369 } 2370 2371 /* 2372 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 2373 * values based on possibly adjusted EEPROM values. 2374 */ 2375 sc->max_host_qng = eep_config.max_host_qng; 2376 sc->max_dvc_qng = eep_config.max_dvc_qng; 2377 2378 /* 2379 * If the EEPROM 'termination' field is set to automatic (0), then set 2380 * the ASC_DVC_CFG 'termination' field to automatic also. 2381 * 2382 * If the termination is specified with a non-zero 'termination' 2383 * value check that a legal value is set and set the ASC_DVC_CFG 2384 * 'termination' field appropriately. 2385 */ 2386 2387 switch(eep_config.termination_se) { 2388 case 0: /* auto termination for SE */ 2389 termination = 0; 2390 break; 2391 case 1: /* Enable manual control with low off / high off. */ 2392 termination = 0; 2393 break; 2394 case 2: /* Enable manual control with low off / high on. */ 2395 termination = ADW_TERM_SE_HI; 2396 break; 2397 case 3: /* Enable manual control with low on / high on. */ 2398 termination = ADW_TERM_SE; 2399 break; 2400 default: 2401 /* 2402 * The EEPROM 'termination_se' field contains a bad value. 2403 * Use automatic termination instead. 2404 */ 2405 termination = 0; 2406 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2407 } 2408 2409 switch(eep_config.termination_lvd) { 2410 case 0: /* auto termination for LVD */ 2411 sc->cfg.termination = termination; 2412 break; 2413 case 1: /* Enable manual control with low off / high off. */ 2414 sc->cfg.termination = termination; 2415 break; 2416 case 2: /* Enable manual control with low off / high on. */ 2417 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 2418 break; 2419 case 3: /* Enable manual control with low on / high on. */ 2420 sc->cfg.termination = termination | ADW_TERM_LVD; 2421 break; 2422 default: 2423 /* 2424 * The EEPROM 'termination_lvd' field contains a bad value. 2425 * Use automatic termination instead. 2426 */ 2427 sc->cfg.termination = termination; 2428 warn_code |= ASC_WARN_EEPROM_TERMINATION; 2429 } 2430 2431 return warn_code; 2432 } 2433 2434 2435 /* 2436 * Read EEPROM configuration into the specified buffer. 2437 * 2438 * Return a checksum based on the EEPROM configuration read. 2439 */ 2440 static u_int16_t 2441 AdvGet3550EEPConfig(iot, ioh, cfg_buf) 2442 bus_space_tag_t iot; 2443 bus_space_handle_t ioh; 2444 ADW_EEP_3550_CONFIG *cfg_buf; 2445 { 2446 u_int16_t wval, chksum; 2447 u_int16_t *wbuf; 2448 int eep_addr; 2449 2450 2451 wbuf = (u_int16_t *) cfg_buf; 2452 chksum = 0; 2453 2454 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2455 eep_addr < ASC_EEP_DVC_CFG_END; 2456 eep_addr++, wbuf++) { 2457 wval = AdvReadEEPWord(iot, ioh, eep_addr); 2458 chksum += wval; 2459 *wbuf = wval; 2460 } 2461 2462 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2463 wbuf++; 2464 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2465 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2466 eep_addr++, wbuf++) { 2467 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2468 } 2469 2470 return chksum; 2471 } 2472 2473 2474 /* 2475 * Read EEPROM configuration into the specified buffer. 2476 * 2477 * Return a checksum based on the EEPROM configuration read. 2478 */ 2479 static u_int16_t 2480 AdvGet38C0800EEPConfig(iot, ioh, cfg_buf) 2481 bus_space_tag_t iot; 2482 bus_space_handle_t ioh; 2483 ADW_EEP_38C0800_CONFIG *cfg_buf; 2484 { 2485 u_int16_t wval, chksum; 2486 u_int16_t *wbuf; 2487 int eep_addr; 2488 2489 2490 wbuf = (u_int16_t *) cfg_buf; 2491 chksum = 0; 2492 2493 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2494 eep_addr < ASC_EEP_DVC_CFG_END; 2495 eep_addr++, wbuf++) { 2496 wval = AdvReadEEPWord(iot, ioh, eep_addr); 2497 chksum += wval; 2498 *wbuf = wval; 2499 } 2500 2501 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2502 wbuf++; 2503 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2504 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2505 eep_addr++, wbuf++) { 2506 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2507 } 2508 2509 return chksum; 2510 } 2511 2512 2513 /* 2514 * Read EEPROM configuration into the specified buffer. 2515 * 2516 * Return a checksum based on the EEPROM configuration read. 2517 */ 2518 static u_int16_t 2519 AdvGet38C1600EEPConfig(iot, ioh, cfg_buf) 2520 bus_space_tag_t iot; 2521 bus_space_handle_t ioh; 2522 ADW_EEP_38C1600_CONFIG *cfg_buf; 2523 { 2524 u_int16_t wval, chksum; 2525 u_int16_t *wbuf; 2526 int eep_addr; 2527 2528 2529 wbuf = (u_int16_t *) cfg_buf; 2530 chksum = 0; 2531 2532 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2533 eep_addr < ASC_EEP_DVC_CFG_END; 2534 eep_addr++, wbuf++) { 2535 wval = AdvReadEEPWord(iot, ioh, eep_addr); 2536 chksum += wval; 2537 *wbuf = wval; 2538 } 2539 2540 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2541 wbuf++; 2542 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2543 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2544 eep_addr++, wbuf++) { 2545 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 2546 } 2547 2548 return chksum; 2549 } 2550 2551 2552 /* 2553 * Read the EEPROM from specified location 2554 */ 2555 static u_int16_t 2556 AdvReadEEPWord(iot, ioh, eep_word_addr) 2557 bus_space_tag_t iot; 2558 bus_space_handle_t ioh; 2559 int eep_word_addr; 2560 { 2561 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2562 ASC_EEP_CMD_READ | eep_word_addr); 2563 AdvWaitEEPCmd(iot, ioh); 2564 2565 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 2566 } 2567 2568 2569 /* 2570 * Wait for EEPROM command to complete 2571 */ 2572 static void 2573 AdvWaitEEPCmd(iot, ioh) 2574 bus_space_tag_t iot; 2575 bus_space_handle_t ioh; 2576 { 2577 int eep_delay_ms; 2578 2579 2580 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 2581 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 2582 ASC_EEP_CMD_DONE) { 2583 break; 2584 } 2585 AdvSleepMilliSecond(1); 2586 } 2587 2588 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 2589 } 2590 2591 2592 /* 2593 * Write the EEPROM from 'cfg_buf'. 2594 */ 2595 static void 2596 AdvSet3550EEPConfig(iot, ioh, cfg_buf) 2597 bus_space_tag_t iot; 2598 bus_space_handle_t ioh; 2599 ADW_EEP_3550_CONFIG *cfg_buf; 2600 { 2601 u_int16_t *wbuf; 2602 u_int16_t addr, chksum; 2603 2604 2605 wbuf = (u_int16_t *) cfg_buf; 2606 chksum = 0; 2607 2608 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2609 AdvWaitEEPCmd(iot, ioh); 2610 2611 /* 2612 * Write EEPROM from word 0 to word 20 2613 */ 2614 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2615 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2616 chksum += *wbuf; 2617 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2618 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2619 ASC_EEP_CMD_WRITE | addr); 2620 AdvWaitEEPCmd(iot, ioh); 2621 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 2622 } 2623 2624 /* 2625 * Write EEPROM checksum at word 21 2626 */ 2627 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2628 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2629 ASC_EEP_CMD_WRITE | addr); 2630 AdvWaitEEPCmd(iot, ioh); 2631 wbuf++; /* skip over check_sum */ 2632 2633 /* 2634 * Write EEPROM OEM name at words 22 to 29 2635 */ 2636 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2637 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2638 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2639 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2640 ASC_EEP_CMD_WRITE | addr); 2641 AdvWaitEEPCmd(iot, ioh); 2642 } 2643 2644 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2645 ASC_EEP_CMD_WRITE_DISABLE); 2646 AdvWaitEEPCmd(iot, ioh); 2647 2648 return; 2649 } 2650 2651 2652 /* 2653 * Write the EEPROM from 'cfg_buf'. 2654 */ 2655 static void 2656 AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) 2657 bus_space_tag_t iot; 2658 bus_space_handle_t ioh; 2659 ADW_EEP_38C0800_CONFIG *cfg_buf; 2660 { 2661 u_int16_t *wbuf; 2662 u_int16_t addr, chksum; 2663 2664 2665 wbuf = (u_int16_t *) cfg_buf; 2666 chksum = 0; 2667 2668 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2669 AdvWaitEEPCmd(iot, ioh); 2670 2671 /* 2672 * Write EEPROM from word 0 to word 20 2673 */ 2674 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2675 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2676 chksum += *wbuf; 2677 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2678 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2679 ASC_EEP_CMD_WRITE | addr); 2680 AdvWaitEEPCmd(iot, ioh); 2681 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 2682 } 2683 2684 /* 2685 * Write EEPROM checksum at word 21 2686 */ 2687 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2688 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2689 ASC_EEP_CMD_WRITE | addr); 2690 AdvWaitEEPCmd(iot, ioh); 2691 wbuf++; /* skip over check_sum */ 2692 2693 /* 2694 * Write EEPROM OEM name at words 22 to 29 2695 */ 2696 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2697 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2698 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2699 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2700 ASC_EEP_CMD_WRITE | addr); 2701 AdvWaitEEPCmd(iot, ioh); 2702 } 2703 2704 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2705 ASC_EEP_CMD_WRITE_DISABLE); 2706 AdvWaitEEPCmd(iot, ioh); 2707 2708 return; 2709 } 2710 2711 2712 /* 2713 * Write the EEPROM from 'cfg_buf'. 2714 */ 2715 static void 2716 AdvSet38C1600EEPConfig(iot, ioh, cfg_buf) 2717 bus_space_tag_t iot; 2718 bus_space_handle_t ioh; 2719 ADW_EEP_38C1600_CONFIG *cfg_buf; 2720 { 2721 u_int16_t *wbuf; 2722 u_int16_t addr, chksum; 2723 2724 2725 wbuf = (u_int16_t *) cfg_buf; 2726 chksum = 0; 2727 2728 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2729 AdvWaitEEPCmd(iot, ioh); 2730 2731 /* 2732 * Write EEPROM from word 0 to word 20 2733 */ 2734 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2735 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2736 chksum += *wbuf; 2737 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2738 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2739 ASC_EEP_CMD_WRITE | addr); 2740 AdvWaitEEPCmd(iot, ioh); 2741 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 2742 } 2743 2744 /* 2745 * Write EEPROM checksum at word 21 2746 */ 2747 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2748 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2749 ASC_EEP_CMD_WRITE | addr); 2750 AdvWaitEEPCmd(iot, ioh); 2751 wbuf++; /* skip over check_sum */ 2752 2753 /* 2754 * Write EEPROM OEM name at words 22 to 29 2755 */ 2756 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2757 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2758 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2759 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2760 ASC_EEP_CMD_WRITE | addr); 2761 AdvWaitEEPCmd(iot, ioh); 2762 } 2763 2764 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2765 ASC_EEP_CMD_WRITE_DISABLE); 2766 AdvWaitEEPCmd(iot, ioh); 2767 2768 return; 2769 } 2770 2771 2772 /* 2773 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 2774 * 2775 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 2776 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 2777 * RISC to notify it a new command is ready to be executed. 2778 * 2779 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 2780 * set to SCSI_MAX_RETRY. 2781 * 2782 * Return: 2783 * ADW_SUCCESS(1) - The request was successfully queued. 2784 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 2785 * request completes. 2786 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 2787 * host IC error. 2788 */ 2789 int 2790 AdvExeScsiQueue(sc, scsiq) 2791 ADW_SOFTC *sc; 2792 ADW_SCSI_REQ_Q *scsiq; 2793 { 2794 bus_space_tag_t iot = sc->sc_iot; 2795 bus_space_handle_t ioh = sc->sc_ioh; 2796 ADW_CCB *ccb; 2797 long req_size; 2798 u_int32_t req_paddr; 2799 ADW_CARRIER *new_carrp; 2800 2801 /* 2802 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 2803 */ 2804 if (scsiq->target_id > ADW_MAX_TID) { 2805 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 2806 scsiq->done_status = QD_WITH_ERROR; 2807 return ADW_ERROR; 2808 } 2809 2810 /* 2811 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 2812 */ 2813 2814 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 2815 2816 /* 2817 * Allocate a carrier ensuring at least one carrier always 2818 * remains on the freelist and initialize fields. 2819 */ 2820 if ((new_carrp = sc->carr_freelist) == NULL) { 2821 return ADW_BUSY; 2822 } 2823 sc->carr_freelist = adw_carrier_phys_kv(sc, 2824 ASC_GET_CARRP(new_carrp->next_ba)); 2825 sc->carr_pending_cnt++; 2826 2827 /* 2828 * Set the carrier to be a stopper by setting 'next_ba' 2829 * to the stopper value. The current stopper will be changed 2830 * below to point to the new stopper. 2831 */ 2832 new_carrp->next_ba = ASC_CQ_STOPPER; 2833 2834 req_size = sizeof(ADW_SCSI_REQ_Q); 2835 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 2836 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 2837 2838 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 2839 scsiq->scsiq_rptr = req_paddr; 2840 2841 /* 2842 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 2843 * order during initialization. 2844 */ 2845 scsiq->carr_ba = sc->icq_sp->carr_ba; 2846 scsiq->carr_va = sc->icq_sp->carr_ba; 2847 2848 /* 2849 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 2850 * the microcode. The newly allocated stopper will become the new 2851 * stopper. 2852 */ 2853 sc->icq_sp->areq_ba = req_paddr; 2854 2855 /* 2856 * Set the 'next_ba' pointer for the old stopper to be the 2857 * physical address of the new stopper. The RISC can only 2858 * follow physical addresses. 2859 */ 2860 sc->icq_sp->next_ba = new_carrp->carr_ba; 2861 2862 #if ADW_DEBUG 2863 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 2864 sc->icq_sp->carr_id, 2865 sc->icq_sp->carr_ba, 2866 sc->icq_sp->areq_ba, 2867 sc->icq_sp->next_ba); 2868 #endif 2869 /* 2870 * Set the host adapter stopper pointer to point to the new carrier. 2871 */ 2872 sc->icq_sp = new_carrp; 2873 2874 if (sc->chip_type == ADV_CHIP_ASC3550 || 2875 sc->chip_type == ADV_CHIP_ASC38C0800) { 2876 /* 2877 * Tickle the RISC to tell it to read its Command Queue Head 2878 * pointer. 2879 */ 2880 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); 2881 if (sc->chip_type == ADV_CHIP_ASC3550) { 2882 /* 2883 * Clear the tickle value. In the ASC-3550 the RISC flag 2884 * command 'clr_tickle_a' does not work unless the host 2885 * value is cleared. 2886 */ 2887 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 2888 ADV_TICKLE_NOP); 2889 } 2890 } else if (sc->chip_type == ADV_CHIP_ASC38C1600) { 2891 /* 2892 * Notify the RISC a carrier is ready by writing the physical 2893 * address of the new carrier stopper to the COMMA register. 2894 */ 2895 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 2896 new_carrp->carr_ba); 2897 } 2898 2899 /* 2900 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 2901 */ 2902 2903 return ADW_SUCCESS; 2904 } 2905 2906 2907 void 2908 AdvResetChip(iot, ioh) 2909 bus_space_tag_t iot; 2910 bus_space_handle_t ioh; 2911 { 2912 2913 /* 2914 * Reset Chip. 2915 */ 2916 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2917 ADW_CTRL_REG_CMD_RESET); 2918 AdvSleepMilliSecond(100); 2919 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2920 ADW_CTRL_REG_CMD_WR_IO_REG); 2921 } 2922 2923 2924 /* 2925 * Reset SCSI Bus and purge all outstanding requests. 2926 * 2927 * Return Value: 2928 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 2929 * ADW_FALSE(0) - Microcode command failed. 2930 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 2931 * may be hung which requires driver recovery. 2932 */ 2933 int 2934 AdvResetCCB(sc) 2935 ADW_SOFTC *sc; 2936 { 2937 int status; 2938 2939 /* 2940 * Send the SCSI Bus Reset idle start idle command which asserts 2941 * the SCSI Bus Reset signal. 2942 */ 2943 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 2944 if (status != ADW_TRUE) { 2945 return status; 2946 } 2947 2948 /* 2949 * Delay for the specified SCSI Bus Reset hold time. 2950 * 2951 * The hold time delay is done on the host because the RISC has no 2952 * microsecond accurate timer. 2953 */ 2954 AdvDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 2955 2956 /* 2957 * Send the SCSI Bus Reset end idle command which de-asserts 2958 * the SCSI Bus Reset signal and purges any pending requests. 2959 */ 2960 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 2961 if (status != ADW_TRUE) { 2962 return status; 2963 } 2964 2965 AdvSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 2966 2967 return status; 2968 } 2969 2970 2971 /* 2972 * Reset chip and SCSI Bus. 2973 * 2974 * Return Value: 2975 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 2976 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 2977 */ 2978 int 2979 AdvResetSCSIBus(sc) 2980 ADW_SOFTC *sc; 2981 { 2982 bus_space_tag_t iot = sc->sc_iot; 2983 bus_space_handle_t ioh = sc->sc_ioh; 2984 int status; 2985 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 2986 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 2987 u_int16_t bios_sig; 2988 2989 2990 /* 2991 * Save current per TID negotiated values. 2992 */ 2993 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 2994 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 2995 if (sc->chip_type == ADV_CHIP_ASC38C1600) { 2996 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, ppr_able); 2997 } 2998 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 2999 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 3000 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 3001 max_cmd[tid]); 3002 } 3003 3004 /* 3005 * Force the AdvInitAsc3550/38C0800Driver() function to 3006 * perform a SCSI Bus Reset by clearing the BIOS signature word. 3007 * The initialization functions assumes a SCSI Bus Reset is not 3008 * needed if the BIOS signature word is present. 3009 */ 3010 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); 3011 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, 0); 3012 3013 /* 3014 * Stop chip and reset it. 3015 */ 3016 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 3017 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 3018 ADW_CTRL_REG_CMD_RESET); 3019 AdvSleepMilliSecond(100); 3020 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 3021 ADW_CTRL_REG_CMD_WR_IO_REG); 3022 3023 /* 3024 * Reset Adv Library error code, if any, and try 3025 * re-initializing the chip. 3026 */ 3027 if (sc->chip_type == ADV_CHIP_ASC38C1600) { 3028 status = AdvInitAsc38C1600Driver(sc); 3029 } else if (sc->chip_type == ADV_CHIP_ASC38C0800) { 3030 status = AdvInitAsc38C0800Driver(sc); 3031 } else { 3032 status = AdvInitAsc3550Driver(sc); 3033 } 3034 3035 /* Translate initialization return value to status value. */ 3036 status = (status == 0)? ADW_TRUE : ADW_FALSE; 3037 3038 /* 3039 * Restore the BIOS signature word. 3040 */ 3041 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); 3042 3043 /* 3044 * Restore per TID negotiated values. 3045 */ 3046 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 3047 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 3048 if (sc->chip_type == ADV_CHIP_ASC38C1600) { 3049 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, ppr_able); 3050 } 3051 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 3052 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 3053 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 3054 max_cmd[tid]); 3055 } 3056 3057 return status; 3058 } 3059 3060 3061 /* 3062 * Adv Library Interrupt Service Routine 3063 * 3064 * This function is called by a driver's interrupt service routine. 3065 * The function disables and re-enables interrupts. 3066 * 3067 * When a microcode idle command is completed, the ADV_DVC_VAR 3068 * 'idle_cmd_done' field is set to ADW_TRUE. 3069 * 3070 * Note: AdvISR() can be called when interrupts are disabled or even 3071 * when there is no hardware interrupt condition present. It will 3072 * always check for completed idle commands and microcode requests. 3073 * This is an important feature that shouldn't be changed because it 3074 * allows commands to be completed from polling mode loops. 3075 * 3076 * Return: 3077 * ADW_TRUE(1) - interrupt was pending 3078 * ADW_FALSE(0) - no interrupt was pending 3079 */ 3080 int 3081 AdvISR(sc) 3082 ADW_SOFTC *sc; 3083 { 3084 bus_space_tag_t iot = sc->sc_iot; 3085 bus_space_handle_t ioh = sc->sc_ioh; 3086 u_int8_t int_stat; 3087 u_int16_t target_bit; 3088 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 3089 u_int32_t irq_next_pa; 3090 ADW_SCSI_REQ_Q *scsiq; 3091 ADW_CCB *ccb; 3092 int s; 3093 3094 3095 s = splbio(); 3096 3097 /* Reading the register clears the interrupt. */ 3098 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 3099 3100 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 3101 ADW_INTR_STATUS_INTRC)) == 0) { 3102 splx(s); 3103 return ADW_FALSE; 3104 } 3105 3106 /* 3107 * Notify the driver of an asynchronous microcode condition by 3108 * calling the ADV_DVC_VAR.async_callback function. The function 3109 * is passed the microcode ASC_MC_INTRB_CODE byte value. 3110 */ 3111 if (int_stat & ADW_INTR_STATUS_INTRB) { 3112 u_int8_t intrb_code; 3113 3114 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_INTRB_CODE, intrb_code); 3115 3116 if (sc->chip_type == ADV_CHIP_ASC3550 || 3117 sc->chip_type == ADV_CHIP_ASC38C0800) { 3118 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 3119 sc->carr_pending_cnt != 0) { 3120 ADW_WRITE_BYTE_REGISTER(iot, ioh, 3121 IOPB_TICKLE, ADV_TICKLE_A); 3122 if (sc->chip_type == ADV_CHIP_ASC3550) { 3123 ADW_WRITE_BYTE_REGISTER(iot, ioh, 3124 IOPB_TICKLE, ADV_TICKLE_NOP); 3125 } 3126 } 3127 } 3128 3129 if (sc->async_callback != 0) { 3130 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 3131 } 3132 } 3133 3134 /* 3135 * Check if the IRQ stopper carrier contains a completed request. 3136 */ 3137 while (((irq_next_pa = sc->irq_sp->next_ba) & ASC_RQ_DONE) != 0) 3138 { 3139 #if ADW_DEBUG 3140 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 3141 sc->irq_sp->carr_id, 3142 sc->irq_sp->carr_ba, 3143 sc->irq_sp->areq_ba, 3144 sc->irq_sp->next_ba); 3145 #endif 3146 /* 3147 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 3148 * structure. 3149 * The RISC will have set 'areq_ba' to a virtual address. 3150 * 3151 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 3152 * field to the carrier ADV_CARR_T.areq_ba field. 3153 * The conversion below complements the conversion of 3154 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdvExeScsiQueue(). 3155 */ 3156 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 3157 scsiq = &ccb->scsiq; 3158 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 3159 3160 /* 3161 * Request finished with good status and the queue was not 3162 * DMAed to host memory by the firmware. Set all status fields 3163 * to indicate good status. 3164 */ 3165 if ((irq_next_pa & ASC_RQ_GOOD) != 0) { 3166 scsiq->done_status = QD_NO_ERROR; 3167 scsiq->host_status = scsiq->scsi_status = 0; 3168 scsiq->data_cnt = 0L; 3169 } 3170 3171 /* 3172 * Advance the stopper pointer to the next carrier 3173 * ignoring the lower four bits. Free the previous 3174 * stopper carrier. 3175 */ 3176 free_carrp = sc->irq_sp; 3177 sc->irq_sp = adw_carrier_phys_kv(sc, ASC_GET_CARRP(irq_next_pa)); 3178 3179 free_carrp->next_ba = sc->carr_freelist->carr_ba; 3180 sc->carr_freelist = free_carrp; 3181 sc->carr_pending_cnt--; 3182 3183 3184 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 3185 3186 /* 3187 * Clear request microcode control flag. 3188 */ 3189 scsiq->cntl = 0; 3190 3191 /* 3192 * Check Condition handling 3193 */ 3194 /* 3195 * If the command that completed was a SCSI INQUIRY and 3196 * LUN 0 was sent the command, then process the INQUIRY 3197 * command information for the device. 3198 */ 3199 if (scsiq->done_status == QD_NO_ERROR && 3200 scsiq->cdb[0] == INQUIRY && 3201 scsiq->target_lun == 0) { 3202 AdvInquiryHandling(sc, scsiq); 3203 } 3204 3205 /* 3206 * Notify the driver of the completed request by passing 3207 * the ADW_SCSI_REQ_Q pointer to its callback function. 3208 */ 3209 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 3210 /* 3211 * Note: After the driver callback function is called, 'scsiq' 3212 * can no longer be referenced. 3213 * 3214 * Fall through and continue processing other completed 3215 * requests... 3216 */ 3217 } 3218 3219 splx(s); 3220 3221 return ADW_TRUE; 3222 } 3223 3224 3225 /* 3226 * Send an idle command to the chip and wait for completion. 3227 * 3228 * Command completion is polled for once per microsecond. 3229 * 3230 * The function can be called from anywhere including an interrupt handler. 3231 * But the function is not re-entrant, so it uses the splbio/splx() 3232 * functions to prevent reentrancy. 3233 * 3234 * Return Values: 3235 * ADW_TRUE - command completed successfully 3236 * ADW_FALSE - command failed 3237 * ADW_ERROR - command timed out 3238 */ 3239 int 3240 AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 3241 ADW_SOFTC *sc; 3242 u_int16_t idle_cmd; 3243 u_int32_t idle_cmd_parameter; 3244 { 3245 bus_space_tag_t iot = sc->sc_iot; 3246 bus_space_handle_t ioh = sc->sc_ioh; 3247 u_int16_t result; 3248 u_int32_t i, j, s; 3249 3250 s = splbio(); 3251 3252 /* 3253 * Clear the idle command status which is set by the microcode 3254 * to a non-zero value to indicate when the command is completed. 3255 */ 3256 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 3257 3258 /* 3259 * Write the idle command value after the idle command parameter 3260 * has been written to avoid a race condition. If the order is not 3261 * followed, the microcode may process the idle command before the 3262 * parameters have been written to LRAM. 3263 */ 3264 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_PARAMETER, 3265 idle_cmd_parameter); 3266 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD, idle_cmd); 3267 3268 /* 3269 * Tickle the RISC to tell it to process the idle command. 3270 */ 3271 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_B); 3272 if (sc->chip_type == ADV_CHIP_ASC3550) { 3273 /* 3274 * Clear the tickle value. In the ASC-3550 the RISC flag 3275 * command 'clr_tickle_b' does not work unless the host 3276 * value is cleared. 3277 */ 3278 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 3279 } 3280 3281 /* Wait for up to 100 millisecond for the idle command to timeout. */ 3282 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 3283 /* Poll once each microsecond for command completion. */ 3284 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 3285 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, result); 3286 if (result != 0) { 3287 splx(s); 3288 return result; 3289 } 3290 AdvDelayMicroSecond(1); 3291 } 3292 } 3293 3294 splx(s); 3295 return ADW_ERROR; 3296 } 3297 3298 3299 /* 3300 * Inquiry Information Byte 7 Handling 3301 * 3302 * Handle SCSI Inquiry Command information for a device by setting 3303 * microcode operating variables that affect WDTR, SDTR, and Tag 3304 * Queuing. 3305 */ 3306 static void 3307 AdvInquiryHandling(sc, scsiq) 3308 ADW_SOFTC *sc; 3309 ADW_SCSI_REQ_Q *scsiq; 3310 { 3311 #ifndef FAILSAFE 3312 bus_space_tag_t iot = sc->sc_iot; 3313 bus_space_handle_t ioh = sc->sc_ioh; 3314 u_int8_t tid; 3315 struct scsipi_inquiry_data *inq; 3316 u_int16_t tidmask; 3317 u_int16_t cfg_word; 3318 3319 3320 /* 3321 * AdvInquiryHandling() requires up to INQUIRY information Byte 7 3322 * to be available. 3323 * 3324 * If less than 8 bytes of INQUIRY information were requested or less 3325 * than 8 bytes were transferred, then return. cdb[4] is the request 3326 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 3327 * microcode to the transfer residual count. 3328 */ 3329 3330 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 3331 return; 3332 } 3333 3334 tid = scsiq->target_id; 3335 3336 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 3337 3338 /* 3339 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 3340 */ 3341 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 3342 ((inq->version & SID_ANSII) < 2)) { 3343 return; 3344 } else { 3345 /* 3346 * INQUIRY Byte 7 Handling 3347 * 3348 * Use a device's INQUIRY byte 7 to determine whether it 3349 * supports WDTR, SDTR, and Tag Queuing. If the feature 3350 * is enabled in the EEPROM and the device supports the 3351 * feature, then enable it in the microcode. 3352 */ 3353 3354 tidmask = ADW_TID_TO_TIDMASK(tid); 3355 3356 /* 3357 * Wide Transfers 3358 * 3359 * If the EEPROM enabled WDTR for the device and the device 3360 * supports wide bus (16 bit) transfers, then turn on the 3361 * device's 'wdtr_able' bit and write the new value to the 3362 * microcode. 3363 */ 3364 #ifdef SCSI_ADW_WDTR_DISABLE 3365 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 3366 #endif /* SCSI_ADW_WDTR_DISABLE */ 3367 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 3368 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 3369 cfg_word); 3370 if ((cfg_word & tidmask) == 0) { 3371 cfg_word |= tidmask; 3372 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 3373 cfg_word); 3374 3375 /* 3376 * Clear the microcode "SDTR negotiation" and "WDTR 3377 * negotiation" done indicators for the target to cause 3378 * it to negotiate with the new setting set above. 3379 * WDTR when accepted causes the target to enter 3380 * asynchronous mode, so SDTR must be negotiated. 3381 */ 3382 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3383 cfg_word); 3384 cfg_word &= ~tidmask; 3385 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3386 cfg_word); 3387 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 3388 cfg_word); 3389 cfg_word &= ~tidmask; 3390 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 3391 cfg_word); 3392 } 3393 } 3394 3395 /* 3396 * Synchronous Transfers 3397 * 3398 * If the EEPROM enabled SDTR for the device and the device 3399 * supports synchronous transfers, then turn on the device's 3400 * 'sdtr_able' bit. Write the new value to the microcode. 3401 */ 3402 #ifdef SCSI_ADW_SDTR_DISABLE 3403 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 3404 #endif /* SCSI_ADW_SDTR_DISABLE */ 3405 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 3406 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, cfg_word); 3407 if ((cfg_word & tidmask) == 0) { 3408 cfg_word |= tidmask; 3409 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 3410 cfg_word); 3411 3412 /* 3413 * Clear the microcode "SDTR negotiation" done indicator 3414 * for the target to cause it to negotiate with the new 3415 * setting set above. 3416 */ 3417 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3418 cfg_word); 3419 cfg_word &= ~tidmask; 3420 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 3421 cfg_word); 3422 } 3423 } 3424 /* 3425 * If the Inquiry data included enough space for the SPI-3 3426 * Clocking field, then check if DT mode is supported. 3427 */ 3428 if (sc->chip_type == ADV_CHIP_ASC38C1600 && 3429 (scsiq->cdb[4] >= 57 || 3430 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 3431 /* 3432 * PPR (Parallel Protocol Request) Capable 3433 * 3434 * If the device supports DT mode, then it must be 3435 * PPR capable. 3436 * The PPR message will be used in place of the SDTR 3437 * and WDTR messages to negotiate synchronous speed 3438 * and offset, transfer width, and protocol options. 3439 */ 3440 if ((inq->flags4 & SID_Cloacking) & 3441 SIDV_CLOCKING_DT_ONLY) 3442 { 3443 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, 3444 sc->ppr_able); 3445 sc->ppr_able |= tidmask; 3446 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_PPR_ABLE, 3447 sc->ppr_able); 3448 } 3449 } 3450 3451 /* 3452 * If the EEPROM enabled Tag Queuing for the device and the 3453 * device supports Tag Queueing, then turn on the device's 3454 * 'tagqng_enable' bit in the microcode and set the microcode 3455 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 3456 * value. 3457 * 3458 * Tag Queuing is disabled for the BIOS which runs in polled 3459 * mode and would see no benefit from Tag Queuing. Also by 3460 * disabling Tag Queuing in the BIOS devices with Tag Queuing 3461 * bugs will at least work with the BIOS. 3462 */ 3463 #ifdef SCSI_ADW_TAGQ_DISABLE 3464 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 3465 #endif /* SCSI_ADW_TAGQ_DISABLE */ 3466 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 3467 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 3468 cfg_word); 3469 cfg_word |= tidmask; 3470 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 3471 cfg_word); 3472 3473 ADW_WRITE_BYTE_LRAM(iot, ioh, 3474 ASC_MC_NUMBER_OF_MAX_CMD + tid, 3475 sc->max_dvc_qng); 3476 } 3477 } 3478 #endif /* FAILSAFE */ 3479 } 3480 3481 3482 static void 3483 AdvSleepMilliSecond(n) 3484 u_int32_t n; 3485 { 3486 3487 DELAY(n * 1000); 3488 } 3489 3490 3491 static void 3492 AdvDelayMicroSecond(n) 3493 u_int32_t n; 3494 { 3495 3496 DELAY(n); 3497 } 3498 3499
Indexes created Mon Sep 22 13:09:51 GMT 2025