adwlib.c revision 1.16
1 /* $NetBSD: adwlib.c,v 1.16 2000/05/26 15:13:43 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_param.h> 73 #include <vm/pmap.h> 74 75 #include <dev/ic/adwlib.h> 76 #include <dev/ic/adwmcode.h> 77 #include <dev/ic/adw.h> 78 79 80 /* Static Functions */ 81 82 static u_int16_t AdwGet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 83 ADW_EEP_3550_CONFIG *)); 84 static u_int16_t AdwGet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_EEP_38C0800_CONFIG *)); 86 static u_int16_t AdwGet38C1600EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 87 ADW_EEP_38C1600_CONFIG *)); 88 static u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 89 static void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 90 static void AdwSet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 91 ADW_EEP_3550_CONFIG *)); 92 static void AdwSet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 93 ADW_EEP_38C0800_CONFIG *)); 94 static void AdwSet38C1600EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 95 ADW_EEP_38C1600_CONFIG *)); 96 static void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 97 98 static void AdwSleepMilliSecond __P((u_int32_t)); 99 static void AdwDelayMicroSecond __P((u_int32_t)); 100 101 102 /* 103 * EEPROM Configuration. 104 * 105 * All drivers should use this structure to set the default EEPROM 106 * configuration. The BIOS now uses this structure when it is built. 107 * Additional structure information can be found in adwlib.h where 108 * the structure is defined. 109 */ 110 static ADW_EEP_3550_CONFIG 111 Default_3550_EEPROM_Config = { 112 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 113 0x0000, /* cfg_msw */ 114 0xFFFF, /* disc_enable */ 115 0xFFFF, /* wdtr_able */ 116 0xFFFF, /* sdtr_able */ 117 0xFFFF, /* start_motor */ 118 0xFFFF, /* tagqng_able */ 119 0xFFFF, /* bios_scan */ 120 0, /* scam_tolerant */ 121 7, /* adapter_scsi_id */ 122 0, /* bios_boot_delay */ 123 3, /* scsi_reset_delay */ 124 0, /* bios_id_lun */ 125 0, /* termination */ 126 0, /* reserved1 */ 127 0xFFE7, /* bios_ctrl */ 128 0xFFFF, /* ultra_able */ 129 0, /* reserved2 */ 130 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */ 131 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 132 0, /* dvc_cntl */ 133 0, /* bug_fix */ 134 0, /* serial_number_word1 */ 135 0, /* serial_number_word2 */ 136 0, /* serial_number_word3 */ 137 0, /* check_sum */ 138 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */ 139 0, /* dvc_err_code */ 140 0, /* adv_err_code */ 141 0, /* adv_err_addr */ 142 0, /* saved_dvc_err_code */ 143 0, /* saved_adv_err_code */ 144 0, /* saved_adv_err_addr */ 145 0 /* num_of_err */ 146 }; 147 148 static ADW_EEP_38C0800_CONFIG 149 Default_38C0800_EEPROM_Config = { 150 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 151 0x0000, /* 01 cfg_msw */ 152 0xFFFF, /* 02 disc_enable */ 153 0xFFFF, /* 03 wdtr_able */ 154 0x4444, /* 04 sdtr_speed1 */ 155 0xFFFF, /* 05 start_motor */ 156 0xFFFF, /* 06 tagqng_able */ 157 0xFFFF, /* 07 bios_scan */ 158 0, /* 08 scam_tolerant */ 159 7, /* 09 adapter_scsi_id */ 160 0, /* bios_boot_delay */ 161 3, /* 10 scsi_reset_delay */ 162 0, /* bios_id_lun */ 163 0, /* 11 termination_se */ 164 0, /* termination_lvd */ 165 0xFFE7, /* 12 bios_ctrl */ 166 0x4444, /* 13 sdtr_speed2 */ 167 0x4444, /* 14 sdtr_speed3 */ 168 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 169 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 170 0, /* 16 dvc_cntl */ 171 0x4444, /* 17 sdtr_speed4 */ 172 0, /* 18 serial_number_word1 */ 173 0, /* 19 serial_number_word2 */ 174 0, /* 20 serial_number_word3 */ 175 0, /* 21 check_sum */ 176 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 177 0, /* 30 dvc_err_code */ 178 0, /* 31 adv_err_code */ 179 0, /* 32 adv_err_addr */ 180 0, /* 33 saved_dvc_err_code */ 181 0, /* 34 saved_adv_err_code */ 182 0, /* 35 saved_adv_err_addr */ 183 0, /* 36 reserved */ 184 0, /* 37 reserved */ 185 0, /* 38 reserved */ 186 0, /* 39 reserved */ 187 0, /* 40 reserved */ 188 0, /* 41 reserved */ 189 0, /* 42 reserved */ 190 0, /* 43 reserved */ 191 0, /* 44 reserved */ 192 0, /* 45 reserved */ 193 0, /* 46 reserved */ 194 0, /* 47 reserved */ 195 0, /* 48 reserved */ 196 0, /* 49 reserved */ 197 0, /* 50 reserved */ 198 0, /* 51 reserved */ 199 0, /* 52 reserved */ 200 0, /* 53 reserved */ 201 0, /* 54 reserved */ 202 0, /* 55 reserved */ 203 0, /* 56 cisptr_lsw */ 204 0, /* 57 cisprt_msw */ 205 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 206 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 207 0, /* 60 reserved */ 208 0, /* 61 reserved */ 209 0, /* 62 reserved */ 210 0 /* 63 reserved */ 211 }; 212 213 static ADW_EEP_38C1600_CONFIG 214 Default_38C1600_EEPROM_Config = { 215 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 216 0x0000, /* 01 cfg_msw */ 217 0xFFFF, /* 02 disc_enable */ 218 0xFFFF, /* 03 wdtr_able */ 219 0x5555, /* 04 sdtr_speed1 */ 220 0xFFFF, /* 05 start_motor */ 221 0xFFFF, /* 06 tagqng_able */ 222 0xFFFF, /* 07 bios_scan */ 223 0, /* 08 scam_tolerant */ 224 7, /* 09 adapter_scsi_id */ 225 0, /* bios_boot_delay */ 226 3, /* 10 scsi_reset_delay */ 227 0, /* bios_id_lun */ 228 0, /* 11 termination_se */ 229 0, /* termination_lvd */ 230 0xFFE7, /* 12 bios_ctrl */ 231 0x5555, /* 13 sdtr_speed2 */ 232 0x5555, /* 14 sdtr_speed3 */ 233 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 234 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 235 0, /* 16 dvc_cntl */ 236 0x5555, /* 17 sdtr_speed4 */ 237 0, /* 18 serial_number_word1 */ 238 0, /* 19 serial_number_word2 */ 239 0, /* 20 serial_number_word3 */ 240 0, /* 21 check_sum */ 241 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 242 0, /* 30 dvc_err_code */ 243 0, /* 31 adv_err_code */ 244 0, /* 32 adv_err_addr */ 245 0, /* 33 saved_dvc_err_code */ 246 0, /* 34 saved_adv_err_code */ 247 0, /* 35 saved_adv_err_addr */ 248 0, /* 36 reserved */ 249 0, /* 37 reserved */ 250 0, /* 38 reserved */ 251 0, /* 39 reserved */ 252 0, /* 40 reserved */ 253 0, /* 41 reserved */ 254 0, /* 42 reserved */ 255 0, /* 43 reserved */ 256 0, /* 44 reserved */ 257 0, /* 45 reserved */ 258 0, /* 46 reserved */ 259 0, /* 47 reserved */ 260 0, /* 48 reserved */ 261 0, /* 49 reserved */ 262 0, /* 50 reserved */ 263 0, /* 51 reserved */ 264 0, /* 52 reserved */ 265 0, /* 53 reserved */ 266 0, /* 54 reserved */ 267 0, /* 55 reserved */ 268 0, /* 56 cisptr_lsw */ 269 0, /* 57 cisprt_msw */ 270 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 271 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 272 0, /* 60 reserved */ 273 0, /* 61 reserved */ 274 0, /* 62 reserved */ 275 0 /* 63 reserved */ 276 }; 277 278 /* 279 * Initialize the ASC3550. 280 * 281 * On failure set the ADW_SOFTC field 'err_code' and return ADW_ERROR. 282 * 283 * For a non-fatal error return a warning code. If there are no warnings 284 * then 0 is returned. 285 */ 286 int 287 AdwInitAsc3550Driver(sc) 288 ADW_SOFTC *sc; 289 { 290 bus_space_tag_t iot = sc->sc_iot; 291 bus_space_handle_t ioh = sc->sc_ioh; 292 u_int16_t warn_code; 293 u_int32_t sum; 294 int begin_addr; 295 int end_addr; 296 u_int16_t code_sum; 297 int word; 298 int i, j; 299 int adv_asc3550_expanded_size; 300 u_int16_t scsi_cfg1; 301 u_int8_t tid; 302 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 303 0x40-0x8F. */ 304 u_int16_t wdtr_able = 0, sdtr_able, tagqng_able; 305 u_int8_t max_cmd[ADW_MAX_TID + 1]; 306 307 308 warn_code = 0; 309 310 /* 311 * Save the RISC memory BIOS region before writing the microcode. 312 * The BIOS may already be loaded and using its RISC LRAM region 313 * so its region must be saved and restored. 314 * 315 * Note: This code makes the assumption, which is currently true, 316 * that a chip reset does not clear RISC LRAM. 317 */ 318 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 319 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 320 } 321 322 /* 323 * Save current per TID negotiated values. 324 */ 325 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 0x55AA) { 326 327 u_int16_t bios_version, major, minor; 328 329 bios_version = bios_mem[(ADW_MC_BIOS_VERSION-ADW_MC_BIOSMEM)/2]; 330 major = (bios_version >> 12) & 0xF; 331 minor = (bios_version >> 8) & 0xF; 332 if (major < 3 || (major == 3 && minor == 1)) { 333 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 334 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 335 } else { 336 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 337 } 338 } 339 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 340 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 341 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 342 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 343 max_cmd[tid]); 344 } 345 346 /* 347 * Load the Microcode 348 * 349 * Write the microcode image to RISC memory starting at address 0. 350 */ 351 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 352 353 /* Assume the following compressed format of the microcode buffer: 354 * 355 * 254 word (508 byte) table indexed by byte code followed 356 * by the following byte codes: 357 * 358 * 1-Byte Code: 359 * 00: Emit word 0 in table. 360 * 01: Emit word 1 in table. 361 * . 362 * FD: Emit word 253 in table. 363 * 364 * Multi-Byte Code: 365 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 366 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 367 */ 368 word = 0; 369 for (i = 253 * 2; i < adw_asc3550_mcode_data.mcode_size; i++) { 370 if (adw_asc3550_mcode_data.mcode_data[i] == 0xff) { 371 for (j = 0; j < adw_asc3550_mcode_data.mcode_data[i + 1]; j++) { 372 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 373 (((u_int16_t)adw_asc3550_mcode_data.mcode_data[i + 3] << 8) | 374 adw_asc3550_mcode_data.mcode_data[i + 2])); 375 word++; 376 } 377 i += 3; 378 } else if (adw_asc3550_mcode_data.mcode_data[i] == 0xfe) { 379 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 380 (((u_int16_t)adw_asc3550_mcode_data.mcode_data[i + 2] << 8) | 381 adw_asc3550_mcode_data.mcode_data[i + 1])); 382 i += 2; 383 word++; 384 } else { 385 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 386 adw_asc3550_mcode_data.mcode_data[(adw_asc3550_mcode_data.mcode_data[i] * 2) + 1] <<8)| 387 adw_asc3550_mcode_data.mcode_data[adw_asc3550_mcode_data.mcode_data[i] * 2])); 388 word++; 389 } 390 } 391 392 /* 393 * Set 'word' for later use to clear the rest of memory and save 394 * the expanded mcode size. 395 */ 396 word *= 2; 397 adv_asc3550_expanded_size = word; 398 399 /* 400 * Clear the rest of ASC-3550 Internal RAM (8KB). 401 */ 402 for (; word < ADW_3550_MEMSIZE; word += 2) { 403 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 404 } 405 406 /* 407 * Verify the microcode checksum. 408 */ 409 sum = 0; 410 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 411 412 for (word = 0; word < adv_asc3550_expanded_size; word += 2) { 413 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 414 } 415 416 if (sum != adw_asc3550_mcode_data.mcode_chksum) { 417 return ADW_IERR_MCODE_CHKSUM; 418 } 419 420 /* 421 * Restore the RISC memory BIOS region. 422 */ 423 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 424 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 425 bios_mem[i]); 426 } 427 428 /* 429 * Calculate and write the microcode code checksum to the microcode 430 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 431 */ 432 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 433 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 434 code_sum = 0; 435 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 436 for (word = begin_addr; word < end_addr; word += 2) { 437 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 438 } 439 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 440 441 /* 442 * Read and save microcode version and date. 443 */ 444 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, 445 sc->cfg.mcode_date); 446 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, 447 sc->cfg.mcode_version); 448 449 /* 450 * Set the chip type to indicate the ASC3550. 451 */ 452 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, ADW_CHIP_ASC3550); 453 454 /* 455 * If the PCI Configuration Command Register "Parity Error Response 456 * Control" Bit was clear (0), then set the microcode variable 457 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 458 * to ignore DMA parity errors. 459 */ 460 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 461 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 462 word |= CONTROL_FLAG_IGNORE_PERR; 463 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 464 } 465 466 /* 467 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 468 * threshold of 128 bytes. This register is only accessible to the host. 469 */ 470 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 471 START_CTL_EMFU | READ_CMD_MRM); 472 473 /* 474 * Microcode operating variables for WDTR, SDTR, and command tag 475 * queuing will be set in AdwInquiryHandling() based on what a 476 * device reports it is capable of in Inquiry byte 7. 477 * 478 * If SCSI Bus Resets have been disabled, then directly set 479 * SDTR and WDTR from the EEPROM configuration. This will allow 480 * the BIOS and warm boot to work without a SCSI bus hang on 481 * the Inquiry caused by host and target mismatched DTR values. 482 * Without the SCSI Bus Reset, before an Inquiry a device can't 483 * be assumed to be in Asynchronous, Narrow mode. 484 */ 485 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 486 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 487 sc->wdtr_able); 488 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 489 sc->sdtr_able); 490 } 491 492 /* 493 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 494 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 495 * bitmask. These values determine the maximum SDTR speed negotiated 496 * with a device. 497 * 498 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 499 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 500 * without determining here whether the device supports SDTR. 501 * 502 * 4-bit speed SDTR speed name 503 * =========== =============== 504 * 0000b (0x0) SDTR disabled 505 * 0001b (0x1) 5 Mhz 506 * 0010b (0x2) 10 Mhz 507 * 0011b (0x3) 20 Mhz (Ultra) 508 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 509 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 510 * 0110b (0x6) Undefined 511 * . 512 * 1111b (0xF) Undefined 513 */ 514 word = 0; 515 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 516 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 517 /* Set Ultra speed for TID 'tid'. */ 518 word |= (0x3 << (4 * (tid % 4))); 519 } else { 520 /* Set Fast speed for TID 'tid'. */ 521 word |= (0x2 << (4 * (tid % 4))); 522 } 523 /* Check if done with sdtr_speed1. */ 524 if (tid == 3) { 525 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, word); 526 word = 0; 527 /* Check if done with sdtr_speed2. */ 528 } else if (tid == 7) { 529 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, word); 530 word = 0; 531 /* Check if done with sdtr_speed3. */ 532 } else if (tid == 11) { 533 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, word); 534 word = 0; 535 /* Check if done with sdtr_speed4. */ 536 } else if (tid == 15) { 537 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, word); 538 /* End of loop. */ 539 } 540 } 541 542 /* 543 * Set microcode operating variable for the disconnect per TID bitmask. 544 */ 545 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, sc->cfg.disc_enable); 546 547 548 /* 549 * Set SCSI_CFG0 Microcode Default Value. 550 * 551 * The microcode will set the SCSI_CFG0 register using this value 552 * after it is started below. 553 */ 554 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 555 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 556 ADW_OUR_ID_EN | sc->chip_scsi_id); 557 558 /* 559 * Determine SCSI_CFG1 Microcode Default Value. 560 * 561 * The microcode will set the SCSI_CFG1 register using this value 562 * after it is started below. 563 */ 564 565 /* Read current SCSI_CFG1 Register value. */ 566 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 567 568 /* 569 * If all three connectors are in use, return an error. 570 */ 571 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 572 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 573 return ADW_IERR_ILLEGAL_CONNECTION; 574 } 575 576 /* 577 * If the internal narrow cable is reversed all of the SCSI_CTRL 578 * register signals will be set. Check for and return an error if 579 * this condition is found. 580 */ 581 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 582 0x3F07) { 583 return ADW_IERR_REVERSED_CABLE; 584 } 585 586 /* 587 * If this is a differential board and a single-ended device 588 * is attached to one of the connectors, return an error. 589 */ 590 if ((scsi_cfg1 & ADW_DIFF_MODE) && (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 591 return ADW_IERR_SINGLE_END_DEVICE; 592 } 593 594 /* 595 * If automatic termination control is enabled, then set the 596 * termination value based on a table listed in a_condor.h. 597 * 598 * If manual termination was specified with an EEPROM setting 599 * then 'termination' was set-up in AdwInitFrom3550EEPROM() and 600 * is ready to be 'ored' into SCSI_CFG1. 601 */ 602 if (sc->cfg.termination == 0) { 603 /* 604 * The software always controls termination by setting 605 * TERM_CTL_SEL. 606 * If TERM_CTL_SEL were set to 0, the hardware would set 607 * termination. 608 */ 609 sc->cfg.termination |= ADW_TERM_CTL_SEL; 610 611 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 612 /* TERM_CTL_H: on, TERM_CTL_L: on */ 613 case 0x3: case 0x7: case 0xB: 614 case 0xD: case 0xE: case 0xF: 615 sc->cfg.termination |= 616 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 617 break; 618 619 /* TERM_CTL_H: on, TERM_CTL_L: off */ 620 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC: 621 sc->cfg.termination |= ADW_TERM_CTL_H; 622 break; 623 624 /* TERM_CTL_H: off, TERM_CTL_L: off */ 625 case 0x2: case 0x6: 626 break; 627 } 628 } 629 630 /* 631 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 632 */ 633 scsi_cfg1 &= ~ADW_TERM_CTL; 634 635 /* 636 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 637 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 638 * referenced, because the hardware internally inverts 639 * the Termination High and Low bits if TERM_POL is set. 640 */ 641 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~sc->cfg.termination & ADW_TERM_CTL)); 642 643 /* 644 * Set SCSI_CFG1 Microcode Default Value 645 * 646 * Set filter value and possibly modified termination control 647 * bits in the Microcode SCSI_CFG1 Register Value. 648 * 649 * The microcode will set the SCSI_CFG1 register using this value 650 * after it is started below. 651 */ 652 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 653 ADW_FLTR_DISABLE | scsi_cfg1); 654 655 /* 656 * Set MEM_CFG Microcode Default Value 657 * 658 * The microcode will set the MEM_CFG register using this value 659 * after it is started below. 660 * 661 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 662 * are defined. 663 * 664 * ASC-3550 has 8KB internal memory. 665 */ 666 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 667 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 668 669 /* 670 * Set SEL_MASK Microcode Default Value 671 * 672 * The microcode will set the SEL_MASK register using this value 673 * after it is started below. 674 */ 675 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 676 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 677 678 679 i = AdwInitCarriers(sc->sc_dmamap_carrier, 680 sc->sc_control->carriers, &sc->carr_freelist); 681 if (i == 0) { 682 return ADW_IERR_NO_CARRIER; /* (ENOMEM) */ ; 683 } else if (i != ADW_MAX_CARRIER) { 684 printf("%s: WARNING: only %d of %d Carriers created\n", 685 sc->sc_dev.dv_xname, i, ADW_MAX_CARRIER); 686 } 687 688 /* 689 * Set-up the Host->RISC Initiator Command Queue (ICQ). 690 */ 691 692 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 693 return ADW_IERR_NO_CARRIER; 694 } 695 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 696 ASC_GET_CARRP(sc->icq_sp->next_ba)); 697 698 /* 699 * The first command issued will be placed in the stopper carrier. 700 */ 701 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 702 703 /* 704 * Set RISC ICQ physical address start value. 705 */ 706 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 707 708 /* 709 * Set-up the RISC->Host Initiator Response Queue (IRQ). 710 */ 711 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 712 return ADW_IERR_NO_CARRIER; 713 } 714 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 715 ASC_GET_CARRP(sc->irq_sp->next_ba)); 716 717 /* 718 * The first command completed by the RISC will be placed in 719 * the stopper. 720 * 721 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 722 * completed the RISC will set the ASC_RQ_DONE bit. 723 */ 724 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 725 726 /* 727 * Set RISC IRQ physical address start value. 728 */ 729 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 730 sc->carr_pending_cnt = 0; 731 732 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 733 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 734 735 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 736 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 737 738 /* finally, finally, gentlemen, start your engine */ 739 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 740 741 /* 742 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 743 * Resets should be performed. The RISC has to be running 744 * to issue a SCSI Bus Reset. 745 */ 746 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 747 { 748 /* 749 * If the BIOS Signature is present in memory, restore the 750 * BIOS Handshake Configuration Table and do not perform 751 * a SCSI Bus Reset. 752 */ 753 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 754 0x55AA) { 755 /* 756 * Restore per TID negotiated values. 757 */ 758 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 759 wdtr_able); 760 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 761 sdtr_able); 762 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 763 tagqng_able); 764 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 765 ADW_WRITE_BYTE_LRAM(iot, ioh, 766 ADW_MC_NUMBER_OF_MAX_CMD + tid, 767 max_cmd[tid]); 768 } 769 } else { 770 if (AdwResetCCB(sc) != ADW_TRUE) { 771 warn_code = ADW_WARN_BUSRESET_ERROR; 772 } 773 } 774 } 775 776 return warn_code; 777 } 778 779 /* 780 * Initialize the ASC-38C0800. 781 * 782 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 783 * 784 * For a non-fatal error return a warning code. If there are no warnings 785 * then 0 is returned. 786 */ 787 int 788 AdwInitAsc38C0800Driver(sc) 789 ADW_SOFTC *sc; 790 { 791 bus_space_tag_t iot = sc->sc_iot; 792 bus_space_handle_t ioh = sc->sc_ioh; 793 u_int16_t warn_code; 794 u_int32_t sum; 795 int begin_addr; 796 int end_addr; 797 u_int16_t code_sum; 798 int word; 799 int i, j; 800 int adv_asc38C0800_expanded_size; 801 u_int16_t scsi_cfg1; 802 u_int8_t byte; 803 u_int8_t tid; 804 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 805 0x40-0x8F. */ 806 u_int16_t wdtr_able, sdtr_able, tagqng_able; 807 u_int8_t max_cmd[ADW_MAX_TID + 1]; 808 809 810 warn_code = 0; 811 812 /* 813 * Save the RISC memory BIOS region before writing the microcode. 814 * The BIOS may already be loaded and using its RISC LRAM region 815 * so its region must be saved and restored. 816 * 817 * Note: This code makes the assumption, which is currently true, 818 * that a chip reset does not clear RISC LRAM. 819 */ 820 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 821 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), bios_mem[i]); 822 } 823 824 /* 825 * Save current per TID negotiated values. 826 */ 827 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 828 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 829 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 830 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 831 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 832 max_cmd[tid]); 833 } 834 835 /* 836 * RAM BIST (RAM Built-In Self Test) 837 * 838 * Address : I/O base + offset 0x38h register (byte). 839 * Function: Bit 7-6(RW) : RAM mode 840 * Normal Mode : 0x00 841 * Pre-test Mode : 0x40 842 * RAM Test Mode : 0x80 843 * Bit 5 : unused 844 * Bit 4(RO) : Done bit 845 * Bit 3-0(RO) : Status 846 * Host Error : 0x08 847 * Int_RAM Error : 0x04 848 * RISC Error : 0x02 849 * SCSI Error : 0x01 850 * No Error : 0x00 851 * 852 * Note: RAM BIST code should be put right here, before loading the 853 * microcode and after saving the RISC memory BIOS region. 854 */ 855 856 /* 857 * LRAM Pre-test 858 * 859 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 860 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 861 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 862 * to NORMAL_MODE, return an error too. 863 */ 864 for (i = 0; i < 2; i++) { 865 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 866 AdwSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 867 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 868 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 869 PRE_TEST_VALUE) { 870 return ADW_IERR_BIST_PRE_TEST; 871 } 872 873 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 874 AdwSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 875 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 876 != NORMAL_VALUE) { 877 return ADW_IERR_BIST_PRE_TEST; 878 } 879 } 880 881 /* 882 * LRAM Test - It takes about 1.5 ms to run through the test. 883 * 884 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 885 * If Done bit not set or Status not 0, save register byte, set the 886 * err_code, and return an error. 887 */ 888 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 889 AdwSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 890 891 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 892 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 893 /* Get here if Done bit not set or Status not 0. */ 894 return ADW_IERR_BIST_RAM_TEST; 895 } 896 897 /* We need to reset back to normal mode after LRAM test passes. */ 898 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 899 900 /* 901 * Load the Microcode 902 * 903 * Write the microcode image to RISC memory starting at address 0. 904 * 905 */ 906 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 907 908 /* Assume the following compressed format of the microcode buffer: 909 * 910 * 254 word (508 byte) table indexed by byte code followed 911 * by the following byte codes: 912 * 913 * 1-Byte Code: 914 * 00: Emit word 0 in table. 915 * 01: Emit word 1 in table. 916 * . 917 * FD: Emit word 253 in table. 918 * 919 * Multi-Byte Code: 920 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 921 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 922 */ 923 word = 0; 924 for (i = 253 * 2; i < adw_asc38C0800_mcode_data.mcode_size; i++) { 925 if (adw_asc38C0800_mcode_data.mcode_data[i] == 0xff) { 926 for (j = 0; j < adw_asc38C0800_mcode_data.mcode_data[i + 1]; j++) { 927 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 928 (((u_int16_t) 929 adw_asc38C0800_mcode_data.mcode_data[i + 3] << 8) | 930 adw_asc38C0800_mcode_data.mcode_data[i + 2])); 931 word++; 932 } 933 i += 3; 934 } else if (adw_asc38C0800_mcode_data.mcode_data[i] == 0xfe) { 935 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 936 adw_asc38C0800_mcode_data.mcode_data[i + 2] << 8) | 937 adw_asc38C0800_mcode_data.mcode_data[i + 1])); 938 i += 2; 939 word++; 940 } else { 941 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 942 adw_asc38C0800_mcode_data.mcode_data[(adw_asc38C0800_mcode_data.mcode_data[i] * 2) + 1] << 8) | 943 adw_asc38C0800_mcode_data.mcode_data[adw_asc38C0800_mcode_data.mcode_data[i] * 2])); 944 word++; 945 } 946 } 947 948 /* 949 * Set 'word' for later use to clear the rest of memory and save 950 * the expanded mcode size. 951 */ 952 word *= 2; 953 adv_asc38C0800_expanded_size = word; 954 955 /* 956 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 957 */ 958 for (; word < ADW_38C0800_MEMSIZE; word += 2) { 959 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 960 } 961 962 /* 963 * Verify the microcode checksum. 964 */ 965 sum = 0; 966 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 967 968 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2) { 969 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 970 } 971 972 if (sum != adw_asc38C0800_mcode_data.mcode_chksum) { 973 return ADW_IERR_MCODE_CHKSUM; 974 } 975 976 /* 977 * Restore the RISC memory BIOS region. 978 */ 979 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 980 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 981 bios_mem[i]); 982 } 983 984 /* 985 * Calculate and write the microcode code checksum to the microcode 986 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 987 */ 988 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 989 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 990 code_sum = 0; 991 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 992 for (word = begin_addr; word < end_addr; word += 2) { 993 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 994 } 995 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 996 997 /* 998 * Read microcode version and date. 999 */ 1000 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, 1001 sc->cfg.mcode_date); 1002 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, 1003 sc->cfg.mcode_version); 1004 1005 /* 1006 * Set the chip type to indicate the ASC38C0800. 1007 */ 1008 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, ADW_CHIP_ASC38C0800); 1009 1010 /* 1011 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 1012 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 1013 * cable detection and then we are able to read C_DET[3:0]. 1014 * 1015 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 1016 * Microcode Default Value' section below. 1017 */ 1018 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1019 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 1020 scsi_cfg1 | ADW_DIS_TERM_DRV); 1021 1022 /* 1023 * If the PCI Configuration Command Register "Parity Error Response 1024 * Control" Bit was clear (0), then set the microcode variable 1025 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 1026 * to ignore DMA parity errors. 1027 */ 1028 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 1029 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 1030 word |= CONTROL_FLAG_IGNORE_PERR; 1031 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 1032 } 1033 1034 /* 1035 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 1036 * START_CTL_TH [3:2] bits for the default FIFO threshold. 1037 * 1038 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 1039 * 1040 * For DMA Errata #4 set the BC_THRESH_ENB bit. 1041 */ 1042 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 1043 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 1044 1045 /* 1046 * Microcode operating variables for WDTR, SDTR, and command tag 1047 * queuing will be set in AdwInquiryHandling() based on what a 1048 * device reports it is capable of in Inquiry byte 7. 1049 * 1050 * If SCSI Bus Resets have been disabled, then directly set 1051 * SDTR and WDTR from the EEPROM configuration. This will allow 1052 * the BIOS and warm boot to work without a SCSI bus hang on 1053 * the Inquiry caused by host and target mismatched DTR values. 1054 * Without the SCSI Bus Reset, before an Inquiry a device can't 1055 * be assumed to be in Asynchronous, Narrow mode. 1056 */ 1057 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 1058 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 1059 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 1060 } 1061 1062 /* 1063 * Set microcode operating variables for DISC and SDTR_SPEED1, 1064 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 1065 * configuration values. 1066 * 1067 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1068 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1069 * without determining here whether the device supports SDTR. 1070 */ 1071 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, sc->cfg.disc_enable); 1072 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, sc->sdtr_speed1); 1073 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, sc->sdtr_speed2); 1074 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, sc->sdtr_speed3); 1075 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, sc->sdtr_speed4); 1076 1077 /* 1078 * Set SCSI_CFG0 Microcode Default Value. 1079 * 1080 * The microcode will set the SCSI_CFG0 register using this value 1081 * after it is started below. 1082 */ 1083 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 1084 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 1085 ADW_OUR_ID_EN | sc->chip_scsi_id); 1086 1087 /* 1088 * Determine SCSI_CFG1 Microcode Default Value. 1089 * 1090 * The microcode will set the SCSI_CFG1 register using this value 1091 * after it is started below. 1092 */ 1093 1094 /* Read current SCSI_CFG1 Register value. */ 1095 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1096 1097 /* 1098 * If the internal narrow cable is reversed all of the SCSI_CTRL 1099 * register signals will be set. Check for and return an error if 1100 * this condition is found. 1101 */ 1102 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1103 0x3F07) { 1104 return ADW_IERR_REVERSED_CABLE; 1105 } 1106 1107 /* 1108 * All kind of combinations of devices attached to one of four connectors 1109 * are acceptable except HVD device attached. For example, LVD device can 1110 * be attached to SE connector while SE device attached to LVD connector. 1111 * If LVD device attached to SE connector, it only runs up to Ultra speed. 1112 * 1113 * If an HVD device is attached to one of LVD connectors, return an error. 1114 * However, there is no way to detect HVD device attached to SE connectors. 1115 */ 1116 if (scsi_cfg1 & ADW_HVD) { 1117 return ADW_IERR_HVD_DEVICE; 1118 } 1119 1120 /* 1121 * If either SE or LVD automatic termination control is enabled, then 1122 * set the termination value based on a table listed in a_condor.h. 1123 * 1124 * If manual termination was specified with an EEPROM setting then 1125 * 'termination' was set-up in AdwInitFrom38C0800EEPROM() and is ready to 1126 * be 'ored' into SCSI_CFG1. 1127 */ 1128 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1129 /* SE automatic termination control is enabled. */ 1130 switch(scsi_cfg1 & ADW_C_DET_SE) { 1131 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1132 case 0x1: case 0x2: case 0x3: 1133 sc->cfg.termination |= ADW_TERM_SE; 1134 break; 1135 1136 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1137 case 0x0: 1138 sc->cfg.termination |= ADW_TERM_SE_HI; 1139 break; 1140 } 1141 } 1142 1143 if ((sc->cfg.termination & ADW_TERM_LVD) == 0) { 1144 /* LVD automatic termination control is enabled. */ 1145 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1146 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1147 case 0x4: case 0x8: case 0xC: 1148 sc->cfg.termination |= ADW_TERM_LVD; 1149 break; 1150 1151 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1152 case 0x0: 1153 break; 1154 } 1155 } 1156 1157 /* 1158 * Clear any set TERM_SE and TERM_LVD bits. 1159 */ 1160 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1161 1162 /* 1163 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1164 */ 1165 scsi_cfg1 |= (~sc->cfg.termination & 0xF0); 1166 1167 /* 1168 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits 1169 * and set possibly modified termination control bits in the Microcode 1170 * SCSI_CFG1 Register Value. 1171 */ 1172 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1173 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1174 1175 /* 1176 * Set SCSI_CFG1 Microcode Default Value 1177 * 1178 * Set possibly modified termination control and reset DIS_TERM_DRV 1179 * bits in the Microcode SCSI_CFG1 Register Value. 1180 * 1181 * The microcode will set the SCSI_CFG1 register using this value 1182 * after it is started below. 1183 */ 1184 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1185 1186 /* 1187 * Set MEM_CFG Microcode Default Value 1188 * 1189 * The microcode will set the MEM_CFG register using this value 1190 * after it is started below. 1191 * 1192 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1193 * are defined. 1194 * 1195 * ASC-38C0800 has 16KB internal memory. 1196 */ 1197 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1198 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1199 1200 /* 1201 * Set SEL_MASK Microcode Default Value 1202 * 1203 * The microcode will set the SEL_MASK register using this value 1204 * after it is started below. 1205 */ 1206 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 1207 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1208 1209 1210 i = AdwInitCarriers(sc->sc_dmamap_carrier, 1211 sc->sc_control->carriers, &sc->carr_freelist); 1212 if (i == 0) { 1213 return ADW_IERR_NO_CARRIER; /* (ENOMEM) */ ; 1214 } else if (i != ADW_MAX_CARRIER) { 1215 printf("%s: WARNING: only %d of %d Carriers created\n", 1216 sc->sc_dev.dv_xname, i, ADW_MAX_CARRIER); 1217 } 1218 1219 /* 1220 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1221 */ 1222 1223 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1224 return ADW_IERR_NO_CARRIER; 1225 } 1226 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1227 ASC_GET_CARRP(sc->icq_sp->next_ba)); 1228 1229 /* 1230 * The first command issued will be placed in the stopper carrier. 1231 */ 1232 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 1233 1234 /* 1235 * Set RISC ICQ physical address start value. 1236 */ 1237 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 1238 1239 /* 1240 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1241 */ 1242 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1243 return ADW_IERR_NO_CARRIER; 1244 } 1245 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1246 ASC_GET_CARRP(sc->irq_sp->next_ba)); 1247 1248 /* 1249 * The first command completed by the RISC will be placed in 1250 * the stopper. 1251 * 1252 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 1253 * completed the RISC will set the ASC_RQ_DONE bit. 1254 */ 1255 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 1256 1257 /* 1258 * Set RISC IRQ physical address start value. 1259 */ 1260 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 1261 sc->carr_pending_cnt = 0; 1262 1263 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1264 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1265 1266 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 1267 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1268 1269 /* finally, finally, gentlemen, start your engine */ 1270 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1271 1272 /* 1273 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1274 * Resets should be performed. The RISC has to be running 1275 * to issue a SCSI Bus Reset. 1276 */ 1277 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1278 /* 1279 * If the BIOS Signature is present in memory, restore the 1280 * BIOS Handshake Configuration Table and do not perform 1281 * a SCSI Bus Reset. 1282 */ 1283 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 1284 0x55AA) { 1285 /* 1286 * Restore per TID negotiated values. 1287 */ 1288 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 1289 wdtr_able); 1290 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 1291 sdtr_able); 1292 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 1293 tagqng_able); 1294 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1295 ADW_WRITE_BYTE_LRAM(iot, ioh, 1296 ADW_MC_NUMBER_OF_MAX_CMD + tid, 1297 max_cmd[tid]); 1298 } 1299 } else { 1300 if (AdwResetCCB(sc) != ADW_TRUE) { 1301 warn_code = ADW_WARN_BUSRESET_ERROR; 1302 } 1303 } 1304 } 1305 1306 return warn_code; 1307 } 1308 1309 1310 /* 1311 * Initialize the ASC-38C1600. 1312 * 1313 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 1314 * 1315 * For a non-fatal error return a warning code. If there are no warnings 1316 * then 0 is returned. 1317 */ 1318 int 1319 AdwInitAsc38C1600Driver(sc) 1320 ADW_SOFTC *sc; 1321 { 1322 bus_space_tag_t iot = sc->sc_iot; 1323 bus_space_handle_t ioh = sc->sc_ioh; 1324 u_int16_t warn_code; 1325 u_int32_t sum; 1326 int begin_addr; 1327 int end_addr; 1328 u_int16_t code_sum; 1329 int word; 1330 int i, j; 1331 int adv_asc38C1600_expanded_size; 1332 u_int16_t scsi_cfg1; 1333 u_int8_t byte; 1334 u_int8_t tid; 1335 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 1336 0x40-0x8F. */ 1337 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1338 u_int8_t max_cmd[ADW_MAX_TID + 1]; 1339 1340 1341 warn_code = 0; 1342 1343 1344 /* 1345 * Save the RISC memory BIOS region before writing the microcode. 1346 * The BIOS may already be loaded and using its RISC LRAM region 1347 * so its region must be saved and restored. 1348 * 1349 * Note: This code makes the assumption, which is currently true, 1350 * that a chip reset does not clear RISC LRAM. 1351 */ 1352 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1353 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), bios_mem[i]); 1354 } 1355 1356 /* 1357 * Save current per TID negotiated values. 1358 */ 1359 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1360 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1361 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1362 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1363 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1364 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1365 max_cmd[tid]); 1366 } 1367 1368 /* 1369 * RAM BIST (RAM Built-In Self Test) 1370 * 1371 * Address : I/O base + offset 0x38h register (byte). 1372 * Function: Bit 7-6(RW) : RAM mode 1373 * Normal Mode : 0x00 1374 * Pre-test Mode : 0x40 1375 * RAM Test Mode : 0x80 1376 * Bit 5 : unused 1377 * Bit 4(RO) : Done bit 1378 * Bit 3-0(RO) : Status 1379 * Host Error : 0x08 1380 * Int_RAM Error : 0x04 1381 * RISC Error : 0x02 1382 * SCSI Error : 0x01 1383 * No Error : 0x00 1384 * 1385 * Note: RAM BIST code should be put right here, before loading the 1386 * microcode and after saving the RISC memory BIOS region. 1387 */ 1388 1389 /* 1390 * LRAM Pre-test 1391 * 1392 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 1393 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 1394 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 1395 * to NORMAL_MODE, return an error too. 1396 */ 1397 for (i = 0; i < 2; i++) { 1398 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 1399 AdwSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 1400 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1401 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 1402 PRE_TEST_VALUE) { 1403 return ADW_IERR_BIST_PRE_TEST; 1404 } 1405 1406 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1407 AdwSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 1408 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1409 != NORMAL_VALUE) { 1410 return ADW_IERR_BIST_PRE_TEST; 1411 } 1412 } 1413 1414 /* 1415 * LRAM Test - It takes about 1.5 ms to run through the test. 1416 * 1417 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 1418 * If Done bit not set or Status not 0, save register byte, set the 1419 * err_code, and return an error. 1420 */ 1421 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1422 AdwSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 1423 1424 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1425 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 1426 /* Get here if Done bit not set or Status not 0. */ 1427 return ADW_IERR_BIST_RAM_TEST; 1428 } 1429 1430 /* We need to reset back to normal mode after LRAM test passes. */ 1431 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1432 1433 1434 /* 1435 * Load the Microcode 1436 * 1437 * Write the microcode image to RISC memory starting at address 0. 1438 * 1439 */ 1440 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1441 1442 /* Assume the following compressed format of the microcode buffer: 1443 * 1444 * 254 word (508 byte) table indexed by byte code followed 1445 * by the following byte codes: 1446 * 1447 * 1-Byte Code: 1448 * 00: Emit word 0 in table. 1449 * 01: Emit word 1 in table. 1450 * . 1451 * FD: Emit word 253 in table. 1452 * 1453 * Multi-Byte Code: 1454 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1455 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1456 */ 1457 word = 0; 1458 for (i = 253 * 2; i < adw_asc38C1600_mcode_data.mcode_size; i++) { 1459 if (adw_asc38C1600_mcode_data.mcode_data[i] == 0xff) { 1460 for (j = 0; j < adw_asc38C1600_mcode_data.mcode_data[i + 1]; j++) { 1461 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1462 (((u_int16_t) 1463 adw_asc38C1600_mcode_data.mcode_data[i + 3] << 8) | 1464 adw_asc38C1600_mcode_data.mcode_data[i + 2])); 1465 word++; 1466 } 1467 i += 3; 1468 } else if (adw_asc38C1600_mcode_data.mcode_data[i] == 0xfe) { 1469 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1470 adw_asc38C1600_mcode_data.mcode_data[i + 2] << 8) | 1471 adw_asc38C1600_mcode_data.mcode_data[i + 1])); 1472 i += 2; 1473 word++; 1474 } else { 1475 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1476 adw_asc38C1600_mcode_data.mcode_data[(adw_asc38C1600_mcode_data.mcode_data[i] * 2) + 1] << 8) | 1477 adw_asc38C1600_mcode_data.mcode_data[adw_asc38C1600_mcode_data.mcode_data[i] * 2])); 1478 word++; 1479 } 1480 } 1481 1482 /* 1483 * Set 'word' for later use to clear the rest of memory and save 1484 * the expanded mcode size. 1485 */ 1486 word *= 2; 1487 adv_asc38C1600_expanded_size = word; 1488 1489 /* 1490 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 1491 */ 1492 for (; word < ADW_38C1600_MEMSIZE; word += 2) { 1493 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1494 } 1495 1496 /* 1497 * Verify the microcode checksum. 1498 */ 1499 sum = 0; 1500 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1501 1502 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2) { 1503 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1504 } 1505 1506 if (sum != adw_asc38C1600_mcode_data.mcode_chksum) { 1507 return ADW_IERR_MCODE_CHKSUM; 1508 } 1509 1510 /* 1511 * Restore the RISC memory BIOS region. 1512 */ 1513 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1514 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1515 bios_mem[i]); 1516 } 1517 1518 /* 1519 * Calculate and write the microcode code checksum to the microcode 1520 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1521 */ 1522 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1523 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1524 code_sum = 0; 1525 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1526 for (word = begin_addr; word < end_addr; word += 2) { 1527 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1528 } 1529 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1530 1531 /* 1532 * Read microcode version and date. 1533 */ 1534 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, 1535 sc->cfg.mcode_date); 1536 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, 1537 sc->cfg.mcode_version); 1538 1539 /* 1540 * Set the chip type to indicate the ASC38C1600. 1541 */ 1542 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, ADW_CHIP_ASC38C1600); 1543 1544 /* 1545 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 1546 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 1547 * cable detection and then we are able to read C_DET[3:0]. 1548 * 1549 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 1550 * Microcode Default Value' section below. 1551 */ 1552 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1553 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 1554 scsi_cfg1 | ADW_DIS_TERM_DRV); 1555 1556 /* 1557 * If the PCI Configuration Command Register "Parity Error Response 1558 * Control" Bit was clear (0), then set the microcode variable 1559 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 1560 * to ignore DMA parity errors. 1561 */ 1562 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 1563 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 1564 word |= CONTROL_FLAG_IGNORE_PERR; 1565 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 1566 } 1567 1568 /* 1569 * If the BIOS control flag AIPP (Asynchronous Information 1570 * Phase Protection) disable bit is not set, then set the firmware 1571 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 1572 * AIPP checking and encoding. 1573 */ 1574 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 1575 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 1576 word |= CONTROL_FLAG_ENABLE_AIPP; 1577 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 1578 } 1579 1580 /* 1581 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 1582 * and START_CTL_TH [3:2]. 1583 */ 1584 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 1585 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 1586 1587 /* 1588 * Microcode operating variables for WDTR, SDTR, and command tag 1589 * queuing will be set in AdwInquiryHandling() based on what a 1590 * device reports it is capable of in Inquiry byte 7. 1591 * 1592 * If SCSI Bus Resets have been disabled, then directly set 1593 * SDTR and WDTR from the EEPROM configuration. This will allow 1594 * the BIOS and warm boot to work without a SCSI bus hang on 1595 * the Inquiry caused by host and target mismatched DTR values. 1596 * Without the SCSI Bus Reset, before an Inquiry a device can't 1597 * be assumed to be in Asynchronous, Narrow mode. 1598 */ 1599 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 1600 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 1601 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 1602 } 1603 1604 /* 1605 * Set microcode operating variables for DISC and SDTR_SPEED1, 1606 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 1607 * configuration values. 1608 * 1609 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1610 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1611 * without determining here whether the device supports SDTR. 1612 */ 1613 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, sc->cfg.disc_enable); 1614 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, sc->sdtr_speed1); 1615 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, sc->sdtr_speed2); 1616 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, sc->sdtr_speed3); 1617 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, sc->sdtr_speed4); 1618 1619 /* 1620 * Set SCSI_CFG0 Microcode Default Value. 1621 * 1622 * The microcode will set the SCSI_CFG0 register using this value 1623 * after it is started below. 1624 */ 1625 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 1626 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 1627 ADW_OUR_ID_EN | sc->chip_scsi_id); 1628 1629 /* 1630 * Calculate SCSI_CFG1 Microcode Default Value. 1631 * 1632 * The microcode will set the SCSI_CFG1 register using this value 1633 * after it is started below. 1634 * 1635 * Each ASC-38C1600 function has only two cable detect bits. 1636 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1637 */ 1638 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1639 1640 /* 1641 * If the cable is reversed all of the SCSI_CTRL register signals 1642 * will be set. Check for and return an error if this condition is 1643 * found. 1644 */ 1645 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1646 0x3F07) { 1647 return ADW_IERR_REVERSED_CABLE; 1648 } 1649 1650 /* 1651 * Each ASC-38C1600 function has two connectors. Only an HVD device 1652 * can not be connected to either connector. An LVD device or SE device 1653 * may be connected to either connecor. If an SE device is connected, 1654 * then at most Ultra speed (20 Mhz) can be used on both connectors. 1655 * 1656 * If an HVD device is attached, return an error. 1657 */ 1658 if (scsi_cfg1 & ADW_HVD) { 1659 return ADW_IERR_HVD_DEVICE; 1660 } 1661 1662 /* 1663 * Each function in the ASC-38C1600 uses only the SE cable detect and 1664 * termination because there are two connectors for each function. Each 1665 * function may use either LVD or SE mode. Corresponding the SE automatic 1666 * termination control EEPROM bits are used for each function. Each 1667 * function has its own EEPROM. If SE automatic control is enabled for 1668 * the function, then set the termination value based on a table listed 1669 * in a_condor.h. 1670 * 1671 * If manual termination is specified in the EEPROM for the function, 1672 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 1673 * ready to be 'ored' into SCSI_CFG1. 1674 */ 1675 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1676 /* SE automatic termination control is enabled. */ 1677 switch(scsi_cfg1 & ADW_C_DET_SE) { 1678 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1679 case 0x1: case 0x2: case 0x3: 1680 sc->cfg.termination |= ADW_TERM_SE; 1681 break; 1682 1683 case 0x0: 1684 /* !!!!TODO!!!! */ 1685 // if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0) { 1686 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1687 // } 1688 // else 1689 // { 1690 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1691 sc->cfg.termination |= ADW_TERM_SE_HI; 1692 // } 1693 break; 1694 } 1695 } 1696 1697 /* 1698 * Clear any set TERM_SE bits. 1699 */ 1700 scsi_cfg1 &= ~ADW_TERM_SE; 1701 1702 /* 1703 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1704 */ 1705 scsi_cfg1 |= (~sc->cfg.termination & ADW_TERM_SE); 1706 1707 /* 1708 * Clear Big Endian and Terminator Polarity bits and set possibly 1709 * modified termination control bits in the Microcode SCSI_CFG1 1710 * Register Value. 1711 */ 1712 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1713 1714 /* 1715 * Set SCSI_CFG1 Microcode Default Value 1716 * 1717 * Set possibly modified termination control bits in the Microcode 1718 * SCSI_CFG1 Register Value. 1719 * 1720 * The microcode will set the SCSI_CFG1 register using this value 1721 * after it is started below. 1722 */ 1723 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1724 1725 /* 1726 * Set MEM_CFG Microcode Default Value 1727 * 1728 * The microcode will set the MEM_CFG register using this value 1729 * after it is started below. 1730 * 1731 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1732 * are defined. 1733 * 1734 * ASC-38C1600 has 32KB internal memory. 1735 */ 1736 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1737 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1738 1739 /* 1740 * Set SEL_MASK Microcode Default Value 1741 * 1742 * The microcode will set the SEL_MASK register using this value 1743 * after it is started below. 1744 */ 1745 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 1746 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1747 1748 1749 i = AdwInitCarriers(sc->sc_dmamap_carrier, 1750 sc->sc_control->carriers, &sc->carr_freelist); 1751 if (i == 0) { 1752 return ADW_IERR_NO_CARRIER; /* (ENOMEM) */ ; 1753 } else if (i != ADW_MAX_CARRIER) { 1754 printf("%s: WARNING: only %d of %d Carriers created\n", 1755 sc->sc_dev.dv_xname, i, ADW_MAX_CARRIER); 1756 } 1757 1758 /* 1759 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1760 */ 1761 1762 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1763 return ADW_IERR_NO_CARRIER; 1764 } 1765 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1766 ASC_GET_CARRP(sc->icq_sp->next_ba)); 1767 1768 /* 1769 * The first command issued will be placed in the stopper carrier. 1770 */ 1771 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 1772 1773 /* 1774 * Set RISC ICQ physical address start value. Initialize the 1775 * COMMA register to the same value otherwise the RISC will 1776 * prematurely detect a command is available. 1777 */ 1778 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 1779 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, sc->icq_sp->carr_ba); 1780 1781 /* 1782 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1783 */ 1784 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1785 return ADW_IERR_NO_CARRIER; 1786 } 1787 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1788 ASC_GET_CARRP(sc->irq_sp->next_ba)); 1789 1790 /* 1791 * The first command completed by the RISC will be placed in 1792 * the stopper. 1793 * 1794 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 1795 * completed the RISC will set the ASC_RQ_DONE bit. 1796 */ 1797 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 1798 1799 /* 1800 * Set RISC IRQ physical address start value. 1801 */ 1802 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 1803 sc->carr_pending_cnt = 0; 1804 1805 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1806 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1807 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 1808 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1809 1810 /* finally, finally, gentlemen, start your engine */ 1811 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1812 1813 /* 1814 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1815 * Resets should be performed. The RISC has to be running 1816 * to issue a SCSI Bus Reset. 1817 */ 1818 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1819 /* 1820 * If the BIOS Signature is present in memory, restore the 1821 * per TID microcode operating variables. 1822 */ 1823 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 1824 0x55AA) { 1825 /* 1826 * Restore per TID negotiated values. 1827 */ 1828 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 1829 wdtr_able); 1830 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 1831 sdtr_able); 1832 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 1833 ppr_able); 1834 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 1835 tagqng_able); 1836 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1837 ADW_WRITE_BYTE_LRAM(iot, ioh, 1838 ADW_MC_NUMBER_OF_MAX_CMD + tid, 1839 max_cmd[tid]); 1840 } 1841 } else { 1842 if (AdwResetCCB(sc) != ADW_TRUE) { 1843 warn_code = ADW_WARN_BUSRESET_ERROR; 1844 } 1845 } 1846 } 1847 1848 return warn_code; 1849 } 1850 1851 1852 /* 1853 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1854 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1855 * all of this is done. 1856 * 1857 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1858 * 1859 * For a non-fatal error return a warning code. If there are no warnings 1860 * then 0 is returned. 1861 * 1862 * Note: Chip is stopped on entry. 1863 */ 1864 int 1865 AdwInitFrom3550EEP(sc) 1866 ADW_SOFTC *sc; 1867 { 1868 bus_space_tag_t iot = sc->sc_iot; 1869 bus_space_handle_t ioh = sc->sc_ioh; 1870 u_int16_t warn_code; 1871 ADW_EEP_3550_CONFIG eep_config; 1872 int i; 1873 1874 1875 warn_code = 0; 1876 1877 /* 1878 * Read the board's EEPROM configuration. 1879 * 1880 * Set default values if a bad checksum is found. 1881 * 1882 * XXX - Don't handle big-endian access to EEPROM yet. 1883 */ 1884 if (AdwGet3550EEPConfig(iot, ioh, &eep_config) != eep_config.check_sum){ 1885 warn_code |= ADW_WARN_EEPROM_CHKSUM; 1886 1887 /* 1888 * Set EEPROM default values. 1889 */ 1890 for (i = 0; i < sizeof(ADW_EEP_3550_CONFIG); i++) { 1891 *((u_int8_t *) &eep_config + i) = 1892 *((u_int8_t *) &Default_3550_EEPROM_Config + i); 1893 } 1894 1895 /* 1896 * Assume the 6 byte board serial number that was read 1897 * from EEPROM is correct even if the EEPROM checksum 1898 * failed. 1899 */ 1900 eep_config.serial_number_word3 = 1901 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 1902 1903 eep_config.serial_number_word2 = 1904 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 1905 1906 eep_config.serial_number_word1 = 1907 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 1908 1909 AdwSet3550EEPConfig(iot, ioh, &eep_config); 1910 } 1911 /* 1912 * Set sc and sc->cfg variables from the EEPROM configuration 1913 * that was read. 1914 * 1915 * This is the mapping of EEPROM fields to Adw Library fields. 1916 */ 1917 sc->wdtr_able = eep_config.wdtr_able; 1918 sc->sdtr_able = eep_config.sdtr_able; 1919 sc->ultra_able = eep_config.ultra_able; 1920 sc->tagqng_able = eep_config.tagqng_able; 1921 sc->cfg.disc_enable = eep_config.disc_enable; 1922 sc->max_host_qng = eep_config.max_host_qng; 1923 sc->max_dvc_qng = eep_config.max_dvc_qng; 1924 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 1925 sc->start_motor = eep_config.start_motor; 1926 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 1927 sc->bios_ctrl = eep_config.bios_ctrl; 1928 sc->no_scam = eep_config.scam_tolerant; 1929 sc->cfg.serial1 = eep_config.serial_number_word1; 1930 sc->cfg.serial2 = eep_config.serial_number_word2; 1931 sc->cfg.serial3 = eep_config.serial_number_word3; 1932 1933 /* 1934 * Set the host maximum queuing (max. 253, min. 16) and the per device 1935 * maximum queuing (max. 63, min. 4). 1936 */ 1937 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 1938 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 1939 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 1940 { 1941 /* If the value is zero, assume it is uninitialized. */ 1942 if (eep_config.max_host_qng == 0) { 1943 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 1944 } else { 1945 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 1946 } 1947 } 1948 1949 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 1950 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 1951 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 1952 /* If the value is zero, assume it is uninitialized. */ 1953 if (eep_config.max_dvc_qng == 0) { 1954 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 1955 } else { 1956 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 1957 } 1958 } 1959 1960 /* 1961 * If 'max_dvc_qng' is greater than 'max_host_qng', then 1962 * set 'max_dvc_qng' to 'max_host_qng'. 1963 */ 1964 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 1965 eep_config.max_dvc_qng = eep_config.max_host_qng; 1966 } 1967 1968 /* 1969 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 1970 * values based on possibly adjusted EEPROM values. 1971 */ 1972 sc->max_host_qng = eep_config.max_host_qng; 1973 sc->max_dvc_qng = eep_config.max_dvc_qng; 1974 1975 1976 /* 1977 * If the EEPROM 'termination' field is set to automatic (0), then set 1978 * the ADV_DVC_CFG 'termination' field to automatic also. 1979 * 1980 * If the termination is specified with a non-zero 'termination' 1981 * value check that a legal value is set and set the ADV_DVC_CFG 1982 * 'termination' field appropriately. 1983 */ 1984 1985 sc->cfg.termination = 0; /* auto termination */ 1986 switch(eep_config.termination) { 1987 case 3: 1988 /* Enable manual control with low on / high on. */ 1989 sc->cfg.termination |= ADW_TERM_CTL_L; 1990 case 2: 1991 /* Enable manual control with low off / high on. */ 1992 sc->cfg.termination |= ADW_TERM_CTL_H; 1993 case 1: 1994 /* Enable manual control with low off / high off. */ 1995 sc->cfg.termination |= ADW_TERM_CTL_SEL; 1996 case 0: 1997 break; 1998 default: 1999 warn_code |= ADW_WARN_EEPROM_TERMINATION; 2000 } 2001 2002 return warn_code; 2003 } 2004 2005 2006 /* 2007 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 2008 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 2009 * all of this is done. 2010 * 2011 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 2012 * 2013 * For a non-fatal error return a warning code. If there are no warnings 2014 * then 0 is returned. 2015 * 2016 * Note: Chip is stopped on entry. 2017 */ 2018 int 2019 AdwInitFrom38C0800EEP(sc) 2020 ADW_SOFTC *sc; 2021 { 2022 bus_space_tag_t iot = sc->sc_iot; 2023 bus_space_handle_t ioh = sc->sc_ioh; 2024 u_int16_t warn_code; 2025 ADW_EEP_38C0800_CONFIG eep_config; 2026 int i; 2027 u_int8_t tid, termination; 2028 u_int16_t sdtr_speed = 0; 2029 2030 2031 warn_code = 0; 2032 2033 /* 2034 * Read the board's EEPROM configuration. 2035 * 2036 * Set default values if a bad checksum is found. 2037 */ 2038 if (AdwGet38C0800EEPConfig(iot, ioh, &eep_config) != 2039 eep_config.check_sum) { 2040 warn_code |= ADW_WARN_EEPROM_CHKSUM; 2041 2042 /* 2043 * Set EEPROM default values. 2044 */ 2045 for (i = 0; i < sizeof(ADW_EEP_38C0800_CONFIG); i++) { 2046 *((u_int8_t *) &eep_config + i) = 2047 *((u_int8_t *)&Default_38C0800_EEPROM_Config+i); 2048 } 2049 2050 /* 2051 * Assume the 6 byte board serial number that was read 2052 * from EEPROM is correct even if the EEPROM checksum 2053 * failed. 2054 */ 2055 eep_config.serial_number_word3 = 2056 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 2057 2058 eep_config.serial_number_word2 = 2059 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 2060 2061 eep_config.serial_number_word1 = 2062 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 2063 2064 AdwSet38C0800EEPConfig(iot, ioh, &eep_config); 2065 } 2066 /* 2067 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 2068 * EEPROM configuration that was read. 2069 * 2070 * This is the mapping of EEPROM fields to Adw Library fields. 2071 */ 2072 sc->wdtr_able = eep_config.wdtr_able; 2073 sc->sdtr_speed1 = eep_config.sdtr_speed1; 2074 sc->sdtr_speed2 = eep_config.sdtr_speed2; 2075 sc->sdtr_speed3 = eep_config.sdtr_speed3; 2076 sc->sdtr_speed4 = eep_config.sdtr_speed4; 2077 sc->tagqng_able = eep_config.tagqng_able; 2078 sc->cfg.disc_enable = eep_config.disc_enable; 2079 sc->max_host_qng = eep_config.max_host_qng; 2080 sc->max_dvc_qng = eep_config.max_dvc_qng; 2081 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 2082 sc->start_motor = eep_config.start_motor; 2083 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 2084 sc->bios_ctrl = eep_config.bios_ctrl; 2085 sc->no_scam = eep_config.scam_tolerant; 2086 sc->cfg.serial1 = eep_config.serial_number_word1; 2087 sc->cfg.serial2 = eep_config.serial_number_word2; 2088 sc->cfg.serial3 = eep_config.serial_number_word3; 2089 2090 /* 2091 * For every Target ID if any of its 'sdtr_speed[1234]' bits 2092 * are set, then set an 'sdtr_able' bit for it. 2093 */ 2094 sc->sdtr_able = 0; 2095 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2096 if (tid == 0) { 2097 sdtr_speed = sc->sdtr_speed1; 2098 } else if (tid == 4) { 2099 sdtr_speed = sc->sdtr_speed2; 2100 } else if (tid == 8) { 2101 sdtr_speed = sc->sdtr_speed3; 2102 } else if (tid == 12) { 2103 sdtr_speed = sc->sdtr_speed4; 2104 } 2105 if (sdtr_speed & ADW_MAX_TID) { 2106 sc->sdtr_able |= (1 << tid); 2107 } 2108 sdtr_speed >>= 4; 2109 } 2110 2111 /* 2112 * Set the host maximum queuing (max. 253, min. 16) and the per device 2113 * maximum queuing (max. 63, min. 4). 2114 */ 2115 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 2116 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 2117 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) { 2118 /* If the value is zero, assume it is uninitialized. */ 2119 if (eep_config.max_host_qng == 0) { 2120 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 2121 } else { 2122 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 2123 } 2124 } 2125 2126 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 2127 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 2128 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 2129 /* If the value is zero, assume it is uninitialized. */ 2130 if (eep_config.max_dvc_qng == 0) { 2131 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 2132 } else { 2133 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 2134 } 2135 } 2136 2137 /* 2138 * If 'max_dvc_qng' is greater than 'max_host_qng', then 2139 * set 'max_dvc_qng' to 'max_host_qng'. 2140 */ 2141 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 2142 eep_config.max_dvc_qng = eep_config.max_host_qng; 2143 } 2144 2145 /* 2146 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 2147 * values based on possibly adjusted EEPROM values. 2148 */ 2149 sc->max_host_qng = eep_config.max_host_qng; 2150 sc->max_dvc_qng = eep_config.max_dvc_qng; 2151 2152 /* 2153 * If the EEPROM 'termination' field is set to automatic (0), then set 2154 * the ADV_DVC_CFG 'termination' field to automatic also. 2155 * 2156 * If the termination is specified with a non-zero 'termination' 2157 * value check that a legal value is set and set the ADV_DVC_CFG 2158 * 'termination' field appropriately. 2159 */ 2160 2161 switch(eep_config.termination_se) { 2162 case 0: 2163 /* auto termination for SE */ 2164 termination = 0; 2165 break; 2166 case 1: 2167 /* Enable manual control with low off / high off. */ 2168 termination = 0; 2169 break; 2170 case 2: 2171 /* Enable manual control with low off / high on. */ 2172 termination = ADW_TERM_SE_HI; 2173 break; 2174 case 3: 2175 /* Enable manual control with low on / high on. */ 2176 termination = ADW_TERM_SE; 2177 break; 2178 default: 2179 /* 2180 * The EEPROM 'termination_se' field contains a bad value. 2181 * Use automatic termination instead. 2182 */ 2183 termination = 0; 2184 warn_code |= ADW_WARN_EEPROM_TERMINATION; 2185 } 2186 2187 switch(eep_config.termination_lvd) { 2188 case 0: 2189 /* auto termination for LVD */ 2190 sc->cfg.termination = termination; 2191 break; 2192 case 1: 2193 /* Enable manual control with low off / high off. */ 2194 sc->cfg.termination = termination; 2195 break; 2196 case 2: 2197 /* Enable manual control with low off / high on. */ 2198 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 2199 break; 2200 case 3: 2201 /* Enable manual control with low on / high on. */ 2202 sc->cfg.termination = termination | ADW_TERM_LVD; 2203 break; 2204 default: 2205 /* 2206 * The EEPROM 'termination_lvd' field contains a bad value. 2207 * Use automatic termination instead. 2208 */ 2209 sc->cfg.termination = termination; 2210 warn_code |= ADW_WARN_EEPROM_TERMINATION; 2211 } 2212 2213 return warn_code; 2214 } 2215 2216 2217 /* 2218 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 2219 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 2220 * all of this is done. 2221 * 2222 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 2223 * 2224 * For a non-fatal error return a warning code. If there are no warnings 2225 * then 0 is returned. 2226 * 2227 * Note: Chip is stopped on entry. 2228 */ 2229 int 2230 AdwInitFrom38C1600EEP(sc) 2231 ADW_SOFTC *sc; 2232 { 2233 bus_space_tag_t iot = sc->sc_iot; 2234 bus_space_handle_t ioh = sc->sc_ioh; 2235 u_int16_t warn_code; 2236 ADW_EEP_38C1600_CONFIG eep_config; 2237 int i; 2238 u_int8_t tid, termination; 2239 u_int16_t sdtr_speed = 0; 2240 2241 2242 warn_code = 0; 2243 2244 /* 2245 * Read the board's EEPROM configuration. 2246 * 2247 * Set default values if a bad checksum is found. 2248 */ 2249 if (AdwGet38C1600EEPConfig(iot, ioh, &eep_config) != 2250 eep_config.check_sum) { 2251 warn_code |= ADW_WARN_EEPROM_CHKSUM; 2252 2253 /* 2254 * Set EEPROM default values. 2255 */ 2256 for (i = 0; i < sizeof(ADW_EEP_38C1600_CONFIG); i++) { 2257 /* !!!!TODO!!!! */ 2258 // if (i == 1 && ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 2259 if (i == 1 ) { 2260 /* 2261 * Set Function 1 EEPROM Word 0 MSB 2262 * 2263 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11) 2264 * EEPROM bits. 2265 * 2266 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and 2267 * old Mac system booting problem. The Expansion ROM must 2268 * be disabled in Function 1 for these systems. 2269 * 2270 */ 2271 *((u_int8_t *) &eep_config + i) = 2272 ((*((u_int8_t *) &Default_38C1600_EEPROM_Config + i)) & 2273 (~(((ADW_EEPROM_BIOS_ENABLE | ADW_EEPROM_INTAB) >> 8) & 2274 0xFF))); 2275 2276 /* 2277 * Set the INTAB (bit 11) if the GPIO 0 input 2278 * indicates the Function 1 interrupt line is 2279 * wired to INTA. 2280 * 2281 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 2282 * 1 - Function 1 interrupt line wired to INT A. 2283 * 0 - Function 1 interrupt line wired to INT B. 2284 * 2285 * Note: Adapter boards always have Function 0 2286 * wired to INTA. 2287 * Put all 5 GPIO bits in input mode and then 2288 * read their input values. 2289 */ 2290 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2291 IOPB_GPIO_CNTL, 0); 2292 if (ADW_READ_BYTE_REGISTER(iot, ioh, 2293 IOPB_GPIO_DATA) & 0x01) { 2294 /* Function 1 interrupt wired to INTA; 2295 Set EEPROM bit. */ 2296 *((u_int8_t *) &eep_config + i) |= 2297 ((ADW_EEPROM_INTAB >> 8) &0xFF); 2298 } 2299 } else { 2300 *((u_int8_t *)&eep_config + i) = 2301 *((u_int8_t *)&Default_38C1600_EEPROM_Config+i); 2302 } 2303 } 2304 2305 /* 2306 * Assume the 6 byte board serial number that was read 2307 * from EEPROM is correct even if the EEPROM checksum 2308 * failed. 2309 */ 2310 eep_config.serial_number_word3 = 2311 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 2312 2313 eep_config.serial_number_word2 = 2314 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 2315 2316 eep_config.serial_number_word1 = 2317 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 2318 2319 AdwSet38C1600EEPConfig(iot, ioh, &eep_config); 2320 } 2321 2322 /* 2323 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 2324 * EEPROM configuration that was read. 2325 * 2326 * This is the mapping of EEPROM fields to Adw Library fields. 2327 */ 2328 sc->wdtr_able = eep_config.wdtr_able; 2329 sc->sdtr_speed1 = eep_config.sdtr_speed1; 2330 sc->sdtr_speed2 = eep_config.sdtr_speed2; 2331 sc->sdtr_speed3 = eep_config.sdtr_speed3; 2332 sc->sdtr_speed4 = eep_config.sdtr_speed4; 2333 sc->ppr_able = 0; 2334 sc->tagqng_able = eep_config.tagqng_able; 2335 sc->cfg.disc_enable = eep_config.disc_enable; 2336 sc->max_host_qng = eep_config.max_host_qng; 2337 sc->max_dvc_qng = eep_config.max_dvc_qng; 2338 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 2339 sc->start_motor = eep_config.start_motor; 2340 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 2341 sc->bios_ctrl = eep_config.bios_ctrl; 2342 sc->no_scam = eep_config.scam_tolerant; 2343 2344 /* 2345 * For every Target ID if any of its 'sdtr_speed[1234]' bits 2346 * are set, then set an 'sdtr_able' bit for it. 2347 */ 2348 sc->sdtr_able = 0; 2349 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2350 if (tid == 0) { 2351 sdtr_speed = sc->sdtr_speed1; 2352 } else if (tid == 4) { 2353 sdtr_speed = sc->sdtr_speed2; 2354 } else if (tid == 8) { 2355 sdtr_speed = sc->sdtr_speed3; 2356 } else if (tid == 12) { 2357 sdtr_speed = sc->sdtr_speed4; 2358 } 2359 if (sdtr_speed & ADW_MAX_TID) { 2360 sc->sdtr_able |= (1 << tid); 2361 } 2362 sdtr_speed >>= 4; 2363 } 2364 2365 /* 2366 * Set the host maximum queuing (max. 253, min. 16) and the per device 2367 * maximum queuing (max. 63, min. 4). 2368 */ 2369 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 2370 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 2371 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) { 2372 /* If the value is zero, assume it is uninitialized. */ 2373 if (eep_config.max_host_qng == 0) { 2374 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 2375 } else { 2376 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 2377 } 2378 } 2379 2380 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 2381 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 2382 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 2383 /* If the value is zero, assume it is uninitialized. */ 2384 if (eep_config.max_dvc_qng == 0) { 2385 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 2386 } else { 2387 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 2388 } 2389 } 2390 2391 /* 2392 * If 'max_dvc_qng' is greater than 'max_host_qng', then 2393 * set 'max_dvc_qng' to 'max_host_qng'. 2394 */ 2395 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 2396 eep_config.max_dvc_qng = eep_config.max_host_qng; 2397 } 2398 2399 /* 2400 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 2401 * values based on possibly adjusted EEPROM values. 2402 */ 2403 sc->max_host_qng = eep_config.max_host_qng; 2404 sc->max_dvc_qng = eep_config.max_dvc_qng; 2405 2406 /* 2407 * If the EEPROM 'termination' field is set to automatic (0), then set 2408 * the ASC_DVC_CFG 'termination' field to automatic also. 2409 * 2410 * If the termination is specified with a non-zero 'termination' 2411 * value check that a legal value is set and set the ASC_DVC_CFG 2412 * 'termination' field appropriately. 2413 */ 2414 2415 switch(eep_config.termination_se) { 2416 case 0: /* auto termination for SE */ 2417 termination = 0; 2418 break; 2419 case 1: /* Enable manual control with low off / high off. */ 2420 termination = 0; 2421 break; 2422 case 2: /* Enable manual control with low off / high on. */ 2423 termination = ADW_TERM_SE_HI; 2424 break; 2425 case 3: /* Enable manual control with low on / high on. */ 2426 termination = ADW_TERM_SE; 2427 break; 2428 default: 2429 /* 2430 * The EEPROM 'termination_se' field contains a bad value. 2431 * Use automatic termination instead. 2432 */ 2433 termination = 0; 2434 warn_code |= ADW_WARN_EEPROM_TERMINATION; 2435 } 2436 2437 switch(eep_config.termination_lvd) { 2438 case 0: /* auto termination for LVD */ 2439 sc->cfg.termination = termination; 2440 break; 2441 case 1: /* Enable manual control with low off / high off. */ 2442 sc->cfg.termination = termination; 2443 break; 2444 case 2: /* Enable manual control with low off / high on. */ 2445 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 2446 break; 2447 case 3: /* Enable manual control with low on / high on. */ 2448 sc->cfg.termination = termination | ADW_TERM_LVD; 2449 break; 2450 default: 2451 /* 2452 * The EEPROM 'termination_lvd' field contains a bad value. 2453 * Use automatic termination instead. 2454 */ 2455 sc->cfg.termination = termination; 2456 warn_code |= ADW_WARN_EEPROM_TERMINATION; 2457 } 2458 2459 return warn_code; 2460 } 2461 2462 2463 /* 2464 * Read EEPROM configuration into the specified buffer. 2465 * 2466 * Return a checksum based on the EEPROM configuration read. 2467 */ 2468 static u_int16_t 2469 AdwGet3550EEPConfig(iot, ioh, cfg_buf) 2470 bus_space_tag_t iot; 2471 bus_space_handle_t ioh; 2472 ADW_EEP_3550_CONFIG *cfg_buf; 2473 { 2474 u_int16_t wval, chksum; 2475 u_int16_t *wbuf; 2476 int eep_addr; 2477 2478 2479 wbuf = (u_int16_t *) cfg_buf; 2480 chksum = 0; 2481 2482 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2483 eep_addr < ASC_EEP_DVC_CFG_END; 2484 eep_addr++, wbuf++) { 2485 wval = AdwReadEEPWord(iot, ioh, eep_addr); 2486 chksum += wval; 2487 *wbuf = wval; 2488 } 2489 2490 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 2491 wbuf++; 2492 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2493 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2494 eep_addr++, wbuf++) { 2495 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 2496 } 2497 2498 return chksum; 2499 } 2500 2501 2502 /* 2503 * Read EEPROM configuration into the specified buffer. 2504 * 2505 * Return a checksum based on the EEPROM configuration read. 2506 */ 2507 static u_int16_t 2508 AdwGet38C0800EEPConfig(iot, ioh, cfg_buf) 2509 bus_space_tag_t iot; 2510 bus_space_handle_t ioh; 2511 ADW_EEP_38C0800_CONFIG *cfg_buf; 2512 { 2513 u_int16_t wval, chksum; 2514 u_int16_t *wbuf; 2515 int eep_addr; 2516 2517 2518 wbuf = (u_int16_t *) cfg_buf; 2519 chksum = 0; 2520 2521 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2522 eep_addr < ASC_EEP_DVC_CFG_END; 2523 eep_addr++, wbuf++) { 2524 wval = AdwReadEEPWord(iot, ioh, eep_addr); 2525 chksum += wval; 2526 *wbuf = wval; 2527 } 2528 2529 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 2530 wbuf++; 2531 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2532 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2533 eep_addr++, wbuf++) { 2534 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 2535 } 2536 2537 return chksum; 2538 } 2539 2540 2541 /* 2542 * Read EEPROM configuration into the specified buffer. 2543 * 2544 * Return a checksum based on the EEPROM configuration read. 2545 */ 2546 static u_int16_t 2547 AdwGet38C1600EEPConfig(iot, ioh, cfg_buf) 2548 bus_space_tag_t iot; 2549 bus_space_handle_t ioh; 2550 ADW_EEP_38C1600_CONFIG *cfg_buf; 2551 { 2552 u_int16_t wval, chksum; 2553 u_int16_t *wbuf; 2554 int eep_addr; 2555 2556 2557 wbuf = (u_int16_t *) cfg_buf; 2558 chksum = 0; 2559 2560 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 2561 eep_addr < ASC_EEP_DVC_CFG_END; 2562 eep_addr++, wbuf++) { 2563 wval = AdwReadEEPWord(iot, ioh, eep_addr); 2564 chksum += wval; 2565 *wbuf = wval; 2566 } 2567 2568 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 2569 wbuf++; 2570 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 2571 eep_addr < ASC_EEP_MAX_WORD_ADDR; 2572 eep_addr++, wbuf++) { 2573 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 2574 } 2575 2576 return chksum; 2577 } 2578 2579 2580 /* 2581 * Read the EEPROM from specified location 2582 */ 2583 static u_int16_t 2584 AdwReadEEPWord(iot, ioh, eep_word_addr) 2585 bus_space_tag_t iot; 2586 bus_space_handle_t ioh; 2587 int eep_word_addr; 2588 { 2589 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2590 ASC_EEP_CMD_READ | eep_word_addr); 2591 AdwWaitEEPCmd(iot, ioh); 2592 2593 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 2594 } 2595 2596 2597 /* 2598 * Wait for EEPROM command to complete 2599 */ 2600 static void 2601 AdwWaitEEPCmd(iot, ioh) 2602 bus_space_tag_t iot; 2603 bus_space_handle_t ioh; 2604 { 2605 int eep_delay_ms; 2606 2607 2608 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 2609 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 2610 ASC_EEP_CMD_DONE) { 2611 break; 2612 } 2613 AdwSleepMilliSecond(1); 2614 } 2615 2616 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 2617 } 2618 2619 2620 /* 2621 * Write the EEPROM from 'cfg_buf'. 2622 */ 2623 static void 2624 AdwSet3550EEPConfig(iot, ioh, cfg_buf) 2625 bus_space_tag_t iot; 2626 bus_space_handle_t ioh; 2627 ADW_EEP_3550_CONFIG *cfg_buf; 2628 { 2629 u_int16_t *wbuf; 2630 u_int16_t addr, chksum; 2631 2632 2633 wbuf = (u_int16_t *) cfg_buf; 2634 chksum = 0; 2635 2636 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2637 AdwWaitEEPCmd(iot, ioh); 2638 2639 /* 2640 * Write EEPROM from word 0 to word 20 2641 */ 2642 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2643 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2644 chksum += *wbuf; 2645 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2646 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2647 ASC_EEP_CMD_WRITE | addr); 2648 AdwWaitEEPCmd(iot, ioh); 2649 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 2650 } 2651 2652 /* 2653 * Write EEPROM checksum at word 21 2654 */ 2655 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2656 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2657 ASC_EEP_CMD_WRITE | addr); 2658 AdwWaitEEPCmd(iot, ioh); 2659 wbuf++; /* skip over check_sum */ 2660 2661 /* 2662 * Write EEPROM OEM name at words 22 to 29 2663 */ 2664 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2665 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2666 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2667 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2668 ASC_EEP_CMD_WRITE | addr); 2669 AdwWaitEEPCmd(iot, ioh); 2670 } 2671 2672 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2673 ASC_EEP_CMD_WRITE_DISABLE); 2674 AdwWaitEEPCmd(iot, ioh); 2675 2676 return; 2677 } 2678 2679 2680 /* 2681 * Write the EEPROM from 'cfg_buf'. 2682 */ 2683 static void 2684 AdwSet38C0800EEPConfig(iot, ioh, cfg_buf) 2685 bus_space_tag_t iot; 2686 bus_space_handle_t ioh; 2687 ADW_EEP_38C0800_CONFIG *cfg_buf; 2688 { 2689 u_int16_t *wbuf; 2690 u_int16_t addr, chksum; 2691 2692 2693 wbuf = (u_int16_t *) cfg_buf; 2694 chksum = 0; 2695 2696 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2697 AdwWaitEEPCmd(iot, ioh); 2698 2699 /* 2700 * Write EEPROM from word 0 to word 20 2701 */ 2702 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2703 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2704 chksum += *wbuf; 2705 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2706 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2707 ASC_EEP_CMD_WRITE | addr); 2708 AdwWaitEEPCmd(iot, ioh); 2709 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 2710 } 2711 2712 /* 2713 * Write EEPROM checksum at word 21 2714 */ 2715 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2716 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2717 ASC_EEP_CMD_WRITE | addr); 2718 AdwWaitEEPCmd(iot, ioh); 2719 wbuf++; /* skip over check_sum */ 2720 2721 /* 2722 * Write EEPROM OEM name at words 22 to 29 2723 */ 2724 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2725 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2726 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2727 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2728 ASC_EEP_CMD_WRITE | addr); 2729 AdwWaitEEPCmd(iot, ioh); 2730 } 2731 2732 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2733 ASC_EEP_CMD_WRITE_DISABLE); 2734 AdwWaitEEPCmd(iot, ioh); 2735 2736 return; 2737 } 2738 2739 2740 /* 2741 * Write the EEPROM from 'cfg_buf'. 2742 */ 2743 static void 2744 AdwSet38C1600EEPConfig(iot, ioh, cfg_buf) 2745 bus_space_tag_t iot; 2746 bus_space_handle_t ioh; 2747 ADW_EEP_38C1600_CONFIG *cfg_buf; 2748 { 2749 u_int16_t *wbuf; 2750 u_int16_t addr, chksum; 2751 2752 2753 wbuf = (u_int16_t *) cfg_buf; 2754 chksum = 0; 2755 2756 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 2757 AdwWaitEEPCmd(iot, ioh); 2758 2759 /* 2760 * Write EEPROM from word 0 to word 20 2761 */ 2762 for (addr = ASC_EEP_DVC_CFG_BEGIN; 2763 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 2764 chksum += *wbuf; 2765 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2766 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2767 ASC_EEP_CMD_WRITE | addr); 2768 AdwWaitEEPCmd(iot, ioh); 2769 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 2770 } 2771 2772 /* 2773 * Write EEPROM checksum at word 21 2774 */ 2775 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 2776 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2777 ASC_EEP_CMD_WRITE | addr); 2778 AdwWaitEEPCmd(iot, ioh); 2779 wbuf++; /* skip over check_sum */ 2780 2781 /* 2782 * Write EEPROM OEM name at words 22 to 29 2783 */ 2784 for (addr = ASC_EEP_DVC_CTL_BEGIN; 2785 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 2786 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 2787 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2788 ASC_EEP_CMD_WRITE | addr); 2789 AdwWaitEEPCmd(iot, ioh); 2790 } 2791 2792 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 2793 ASC_EEP_CMD_WRITE_DISABLE); 2794 AdwWaitEEPCmd(iot, ioh); 2795 2796 return; 2797 } 2798 2799 2800 /* 2801 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 2802 * 2803 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 2804 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 2805 * RISC to notify it a new command is ready to be executed. 2806 * 2807 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 2808 * set to SCSI_MAX_RETRY. 2809 * 2810 * Return: 2811 * ADW_SUCCESS(1) - The request was successfully queued. 2812 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 2813 * request completes. 2814 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 2815 * host IC error. 2816 */ 2817 int 2818 AdwExeScsiQueue(sc, scsiq) 2819 ADW_SOFTC *sc; 2820 ADW_SCSI_REQ_Q *scsiq; 2821 { 2822 bus_space_tag_t iot = sc->sc_iot; 2823 bus_space_handle_t ioh = sc->sc_ioh; 2824 ADW_CCB *ccb; 2825 long req_size; 2826 u_int32_t req_paddr; 2827 ADW_CARRIER *new_carrp; 2828 2829 /* 2830 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 2831 */ 2832 if (scsiq->target_id > ADW_MAX_TID) { 2833 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 2834 scsiq->done_status = QD_WITH_ERROR; 2835 return ADW_ERROR; 2836 } 2837 2838 /* 2839 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 2840 */ 2841 2842 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 2843 2844 /* 2845 * Allocate a carrier and initialize fields. 2846 */ 2847 if ((new_carrp = sc->carr_freelist) == NULL) { 2848 return ADW_BUSY; 2849 } 2850 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 2851 ASC_GET_CARRP(new_carrp->next_ba)); 2852 sc->carr_pending_cnt++; 2853 2854 /* 2855 * Set the carrier to be a stopper by setting 'next_ba' 2856 * to the stopper value. The current stopper will be changed 2857 * below to point to the new stopper. 2858 */ 2859 new_carrp->next_ba = ASC_CQ_STOPPER; 2860 2861 req_size = sizeof(ADW_SCSI_REQ_Q); 2862 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 2863 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 2864 2865 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 2866 scsiq->scsiq_rptr = req_paddr; 2867 2868 /* 2869 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 2870 * order during initialization. 2871 */ 2872 scsiq->carr_ba = sc->icq_sp->carr_ba; 2873 scsiq->carr_va = sc->icq_sp->carr_ba; 2874 2875 /* 2876 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 2877 * the microcode. The newly allocated stopper will become the new 2878 * stopper. 2879 */ 2880 sc->icq_sp->areq_ba = req_paddr; 2881 2882 /* 2883 * Set the 'next_ba' pointer for the old stopper to be the 2884 * physical address of the new stopper. The RISC can only 2885 * follow physical addresses. 2886 */ 2887 sc->icq_sp->next_ba = new_carrp->carr_ba; 2888 2889 #if ADW_DEBUG 2890 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 2891 sc->icq_sp->carr_id, 2892 sc->icq_sp->carr_ba, 2893 sc->icq_sp->areq_ba, 2894 sc->icq_sp->next_ba); 2895 #endif 2896 /* 2897 * Set the host adapter stopper pointer to point to the new carrier. 2898 */ 2899 sc->icq_sp = new_carrp; 2900 2901 if (sc->chip_type == ADW_CHIP_ASC3550 || 2902 sc->chip_type == ADW_CHIP_ASC38C0800) { 2903 /* 2904 * Tickle the RISC to tell it to read its Command Queue Head 2905 * pointer. 2906 */ 2907 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); 2908 if (sc->chip_type == ADW_CHIP_ASC3550) { 2909 /* 2910 * Clear the tickle value. In the ASC-3550 the RISC flag 2911 * command 'clr_tickle_a' does not work unless the host 2912 * value is cleared. 2913 */ 2914 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 2915 ADV_TICKLE_NOP); 2916 } 2917 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 2918 /* 2919 * Notify the RISC a carrier is ready by writing the physical 2920 * address of the new carrier stopper to the COMMA register. 2921 */ 2922 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 2923 new_carrp->carr_ba); 2924 } 2925 2926 /* 2927 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 2928 */ 2929 2930 return ADW_SUCCESS; 2931 } 2932 2933 2934 void 2935 AdwResetChip(iot, ioh) 2936 bus_space_tag_t iot; 2937 bus_space_handle_t ioh; 2938 { 2939 2940 /* 2941 * Reset Chip. 2942 */ 2943 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2944 ADW_CTRL_REG_CMD_RESET); 2945 AdwSleepMilliSecond(100); 2946 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2947 ADW_CTRL_REG_CMD_WR_IO_REG); 2948 } 2949 2950 2951 /* 2952 * Reset SCSI Bus and purge all outstanding requests. 2953 * 2954 * Return Value: 2955 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 2956 * ADW_FALSE(0) - Microcode command failed. 2957 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 2958 * may be hung which requires driver recovery. 2959 */ 2960 int 2961 AdwResetCCB(sc) 2962 ADW_SOFTC *sc; 2963 { 2964 int status; 2965 2966 /* 2967 * Send the SCSI Bus Reset idle start idle command which asserts 2968 * the SCSI Bus Reset signal. 2969 */ 2970 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 2971 if (status != ADW_TRUE) { 2972 return status; 2973 } 2974 2975 /* 2976 * Delay for the specified SCSI Bus Reset hold time. 2977 * 2978 * The hold time delay is done on the host because the RISC has no 2979 * microsecond accurate timer. 2980 */ 2981 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 2982 2983 /* 2984 * Send the SCSI Bus Reset end idle command which de-asserts 2985 * the SCSI Bus Reset signal and purges any pending requests. 2986 */ 2987 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 2988 if (status != ADW_TRUE) { 2989 return status; 2990 } 2991 2992 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 2993 2994 return status; 2995 } 2996 2997 2998 /* 2999 * Reset chip and SCSI Bus. 3000 * 3001 * Return Value: 3002 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 3003 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 3004 */ 3005 int 3006 AdwResetSCSIBus(sc) 3007 ADW_SOFTC *sc; 3008 { 3009 bus_space_tag_t iot = sc->sc_iot; 3010 bus_space_handle_t ioh = sc->sc_ioh; 3011 int status; 3012 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 3013 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 3014 u_int16_t bios_sig; 3015 3016 3017 /* 3018 * Save current per TID negotiated values. 3019 */ 3020 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 3021 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 3022 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 3023 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 3024 } 3025 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 3026 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 3027 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 3028 max_cmd[tid]); 3029 } 3030 3031 /* 3032 * Force the AdwInitAsc3550/38C0800Driver() function to 3033 * perform a SCSI Bus Reset by clearing the BIOS signature word. 3034 * The initialization functions assumes a SCSI Bus Reset is not 3035 * needed if the BIOS signature word is present. 3036 */ 3037 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 3038 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 3039 3040 /* 3041 * Stop chip and reset it. 3042 */ 3043 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 3044 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 3045 ADW_CTRL_REG_CMD_RESET); 3046 AdwSleepMilliSecond(100); 3047 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 3048 ADW_CTRL_REG_CMD_WR_IO_REG); 3049 3050 /* 3051 * Reset Adv Library error code, if any, and try 3052 * re-initializing the chip. 3053 */ 3054 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 3055 status = AdwInitAsc38C1600Driver(sc); 3056 } else if (sc->chip_type == ADW_CHIP_ASC38C0800) { 3057 status = AdwInitAsc38C0800Driver(sc); 3058 } else { 3059 status = AdwInitAsc3550Driver(sc); 3060 } 3061 3062 /* Translate initialization return value to status value. */ 3063 status = (status == 0)? ADW_TRUE : ADW_FALSE; 3064 3065 /* 3066 * Restore the BIOS signature word. 3067 */ 3068 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 3069 3070 /* 3071 * Restore per TID negotiated values. 3072 */ 3073 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 3074 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 3075 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 3076 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 3077 } 3078 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 3079 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 3080 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 3081 max_cmd[tid]); 3082 } 3083 3084 return status; 3085 } 3086 3087 3088 /* 3089 * Adv Library Interrupt Service Routine 3090 * 3091 * This function is called by a driver's interrupt service routine. 3092 * The function disables and re-enables interrupts. 3093 * 3094 * When a microcode idle command is completed, the ADV_DVC_VAR 3095 * 'idle_cmd_done' field is set to ADW_TRUE. 3096 * 3097 * Note: AdwISR() can be called when interrupts are disabled or even 3098 * when there is no hardware interrupt condition present. It will 3099 * always check for completed idle commands and microcode requests. 3100 * This is an important feature that shouldn't be changed because it 3101 * allows commands to be completed from polling mode loops. 3102 * 3103 * Return: 3104 * ADW_TRUE(1) - interrupt was pending 3105 * ADW_FALSE(0) - no interrupt was pending 3106 */ 3107 int 3108 AdwISR(sc) 3109 ADW_SOFTC *sc; 3110 { 3111 bus_space_tag_t iot = sc->sc_iot; 3112 bus_space_handle_t ioh = sc->sc_ioh; 3113 u_int8_t int_stat; 3114 u_int16_t target_bit; 3115 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 3116 u_int32_t irq_next_pa; 3117 ADW_SCSI_REQ_Q *scsiq; 3118 ADW_CCB *ccb; 3119 int s; 3120 3121 3122 s = splbio(); 3123 3124 /* Reading the register clears the interrupt. */ 3125 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 3126 3127 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 3128 ADW_INTR_STATUS_INTRC)) == 0) { 3129 splx(s); 3130 return ADW_FALSE; 3131 } 3132 3133 /* 3134 * Notify the driver of an asynchronous microcode condition by 3135 * calling the ADV_DVC_VAR.async_callback function. The function 3136 * is passed the microcode ADW_MC_INTRB_CODE byte value. 3137 */ 3138 if (int_stat & ADW_INTR_STATUS_INTRB) { 3139 u_int8_t intrb_code; 3140 3141 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 3142 3143 if (sc->chip_type == ADW_CHIP_ASC3550 || 3144 sc->chip_type == ADW_CHIP_ASC38C0800) { 3145 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 3146 sc->carr_pending_cnt != 0) { 3147 ADW_WRITE_BYTE_REGISTER(iot, ioh, 3148 IOPB_TICKLE, ADV_TICKLE_A); 3149 if (sc->chip_type == ADW_CHIP_ASC3550) { 3150 ADW_WRITE_BYTE_REGISTER(iot, ioh, 3151 IOPB_TICKLE, ADV_TICKLE_NOP); 3152 } 3153 } 3154 } 3155 3156 if (sc->async_callback != 0) { 3157 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 3158 } 3159 } 3160 3161 /* 3162 * Check if the IRQ stopper carrier contains a completed request. 3163 */ 3164 while (((irq_next_pa = sc->irq_sp->next_ba) & ASC_RQ_DONE) != 0) 3165 { 3166 #if ADW_DEBUG 3167 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 3168 sc->irq_sp->carr_id, 3169 sc->irq_sp->carr_ba, 3170 sc->irq_sp->areq_ba, 3171 sc->irq_sp->next_ba); 3172 #endif 3173 /* 3174 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 3175 * structure. 3176 * The RISC will have set 'areq_ba' to a virtual address. 3177 * 3178 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 3179 * field to the carrier ADV_CARR_T.areq_ba field. 3180 * The conversion below complements the conversion of 3181 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 3182 */ 3183 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 3184 scsiq = &ccb->scsiq; 3185 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 3186 3187 /* 3188 * Request finished with good status and the queue was not 3189 * DMAed to host memory by the firmware. Set all status fields 3190 * to indicate good status. 3191 */ 3192 if ((irq_next_pa & ASC_RQ_GOOD) != 0) { 3193 scsiq->done_status = QD_NO_ERROR; 3194 scsiq->host_status = scsiq->scsi_status = 0; 3195 scsiq->data_cnt = 0L; 3196 } 3197 3198 /* 3199 * Advance the stopper pointer to the next carrier 3200 * ignoring the lower four bits. Free the previous 3201 * stopper carrier. 3202 */ 3203 free_carrp = sc->irq_sp; 3204 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 3205 3206 free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL 3207 : sc->carr_freelist->carr_ba; 3208 sc->carr_freelist = free_carrp; 3209 sc->carr_pending_cnt--; 3210 3211 3212 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 3213 3214 /* 3215 * Clear request microcode control flag. 3216 */ 3217 scsiq->cntl = 0; 3218 3219 /* 3220 * Check Condition handling 3221 */ 3222 /* 3223 * If the command that completed was a SCSI INQUIRY and 3224 * LUN 0 was sent the command, then process the INQUIRY 3225 * command information for the device. 3226 */ 3227 if (scsiq->done_status == QD_NO_ERROR && 3228 scsiq->cdb[0] == INQUIRY && 3229 scsiq->target_lun == 0) { 3230 AdwInquiryHandling(sc, scsiq); 3231 } 3232 3233 /* 3234 * Notify the driver of the completed request by passing 3235 * the ADW_SCSI_REQ_Q pointer to its callback function. 3236 */ 3237 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 3238 /* 3239 * Note: After the driver callback function is called, 'scsiq' 3240 * can no longer be referenced. 3241 * 3242 * Fall through and continue processing other completed 3243 * requests... 3244 */ 3245 } 3246 3247 splx(s); 3248 3249 return ADW_TRUE; 3250 } 3251 3252 3253 /* 3254 * Send an idle command to the chip and wait for completion. 3255 * 3256 * Command completion is polled for once per microsecond. 3257 * 3258 * The function can be called from anywhere including an interrupt handler. 3259 * But the function is not re-entrant, so it uses the splbio/splx() 3260 * functions to prevent reentrancy. 3261 * 3262 * Return Values: 3263 * ADW_TRUE - command completed successfully 3264 * ADW_FALSE - command failed 3265 * ADW_ERROR - command timed out 3266 */ 3267 int 3268 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 3269 ADW_SOFTC *sc; 3270 u_int16_t idle_cmd; 3271 u_int32_t idle_cmd_parameter; 3272 { 3273 bus_space_tag_t iot = sc->sc_iot; 3274 bus_space_handle_t ioh = sc->sc_ioh; 3275 u_int16_t result; 3276 u_int32_t i, j, s; 3277 3278 s = splbio(); 3279 3280 /* 3281 * Clear the idle command status which is set by the microcode 3282 * to a non-zero value to indicate when the command is completed. 3283 */ 3284 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 3285 3286 /* 3287 * Write the idle command value after the idle command parameter 3288 * has been written to avoid a race condition. If the order is not 3289 * followed, the microcode may process the idle command before the 3290 * parameters have been written to LRAM. 3291 */ 3292 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 3293 idle_cmd_parameter); 3294 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 3295 3296 /* 3297 * Tickle the RISC to tell it to process the idle command. 3298 */ 3299 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_B); 3300 if (sc->chip_type == ADW_CHIP_ASC3550) { 3301 /* 3302 * Clear the tickle value. In the ASC-3550 the RISC flag 3303 * command 'clr_tickle_b' does not work unless the host 3304 * value is cleared. 3305 */ 3306 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 3307 } 3308 3309 /* Wait for up to 100 millisecond for the idle command to timeout. */ 3310 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 3311 /* Poll once each microsecond for command completion. */ 3312 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 3313 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, result); 3314 if (result != 0) { 3315 splx(s); 3316 return result; 3317 } 3318 AdwDelayMicroSecond(1); 3319 } 3320 } 3321 3322 splx(s); 3323 return ADW_ERROR; 3324 } 3325 3326 3327 /* 3328 * Inquiry Information Byte 7 Handling 3329 * 3330 * Handle SCSI Inquiry Command information for a device by setting 3331 * microcode operating variables that affect WDTR, SDTR, and Tag 3332 * Queuing. 3333 */ 3334 static void 3335 AdwInquiryHandling(sc, scsiq) 3336 ADW_SOFTC *sc; 3337 ADW_SCSI_REQ_Q *scsiq; 3338 { 3339 #ifndef FAILSAFE 3340 bus_space_tag_t iot = sc->sc_iot; 3341 bus_space_handle_t ioh = sc->sc_ioh; 3342 u_int8_t tid; 3343 struct scsipi_inquiry_data *inq; 3344 u_int16_t tidmask; 3345 u_int16_t cfg_word; 3346 3347 3348 /* 3349 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 3350 * to be available. 3351 * 3352 * If less than 8 bytes of INQUIRY information were requested or less 3353 * than 8 bytes were transferred, then return. cdb[4] is the request 3354 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 3355 * microcode to the transfer residual count. 3356 */ 3357 3358 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 3359 return; 3360 } 3361 3362 tid = scsiq->target_id; 3363 3364 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 3365 3366 /* 3367 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 3368 */ 3369 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 3370 ((inq->version & SID_ANSII) < 2)) { 3371 return; 3372 } else { 3373 /* 3374 * INQUIRY Byte 7 Handling 3375 * 3376 * Use a device's INQUIRY byte 7 to determine whether it 3377 * supports WDTR, SDTR, and Tag Queuing. If the feature 3378 * is enabled in the EEPROM and the device supports the 3379 * feature, then enable it in the microcode. 3380 */ 3381 3382 tidmask = ADW_TID_TO_TIDMASK(tid); 3383 3384 /* 3385 * Wide Transfers 3386 * 3387 * If the EEPROM enabled WDTR for the device and the device 3388 * supports wide bus (16 bit) transfers, then turn on the 3389 * device's 'wdtr_able' bit and write the new value to the 3390 * microcode. 3391 */ 3392 #ifdef SCSI_ADW_WDTR_DISABLE 3393 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 3394 #endif /* SCSI_ADW_WDTR_DISABLE */ 3395 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 3396 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 3397 cfg_word); 3398 if ((cfg_word & tidmask) == 0) { 3399 cfg_word |= tidmask; 3400 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 3401 cfg_word); 3402 3403 /* 3404 * Clear the microcode "SDTR negotiation" and 3405 * "WDTR negotiation" done indicators for the 3406 * target to cause it to negotiate with the new 3407 * setting set above. 3408 * WDTR when accepted causes the target to enter 3409 * asynchronous mode, so SDTR must be negotiated 3410 */ 3411 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 3412 cfg_word); 3413 cfg_word &= ~tidmask; 3414 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 3415 cfg_word); 3416 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 3417 cfg_word); 3418 cfg_word &= ~tidmask; 3419 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 3420 cfg_word); 3421 } 3422 } 3423 3424 /* 3425 * Synchronous Transfers 3426 * 3427 * If the EEPROM enabled SDTR for the device and the device 3428 * supports synchronous transfers, then turn on the device's 3429 * 'sdtr_able' bit. Write the new value to the microcode. 3430 */ 3431 #ifdef SCSI_ADW_SDTR_DISABLE 3432 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 3433 #endif /* SCSI_ADW_SDTR_DISABLE */ 3434 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 3435 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, cfg_word); 3436 if ((cfg_word & tidmask) == 0) { 3437 cfg_word |= tidmask; 3438 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 3439 cfg_word); 3440 3441 /* 3442 * Clear the microcode "SDTR negotiation" 3443 * done indicator for the target to cause it 3444 * to negotiate with the new setting set above. 3445 */ 3446 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 3447 cfg_word); 3448 cfg_word &= ~tidmask; 3449 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 3450 cfg_word); 3451 } 3452 } 3453 /* 3454 * If the Inquiry data included enough space for the SPI-3 3455 * Clocking field, then check if DT mode is supported. 3456 */ 3457 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 3458 (scsiq->cdb[4] >= 57 || 3459 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 3460 /* 3461 * PPR (Parallel Protocol Request) Capable 3462 * 3463 * If the device supports DT mode, then it must be 3464 * PPR capable. 3465 * The PPR message will be used in place of the SDTR 3466 * and WDTR messages to negotiate synchronous speed 3467 * and offset, transfer width, and protocol options. 3468 */ 3469 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 3470 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 3471 sc->ppr_able); 3472 sc->ppr_able |= tidmask; 3473 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 3474 sc->ppr_able); 3475 } 3476 } 3477 3478 /* 3479 * If the EEPROM enabled Tag Queuing for the device and the 3480 * device supports Tag Queueing, then turn on the device's 3481 * 'tagqng_enable' bit in the microcode and set the microcode 3482 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 3483 * value. 3484 * 3485 * Tag Queuing is disabled for the BIOS which runs in polled 3486 * mode and would see no benefit from Tag Queuing. Also by 3487 * disabling Tag Queuing in the BIOS devices with Tag Queuing 3488 * bugs will at least work with the BIOS. 3489 */ 3490 #ifdef SCSI_ADW_TAGQ_DISABLE 3491 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 3492 #endif /* SCSI_ADW_TAGQ_DISABLE */ 3493 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 3494 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 3495 cfg_word); 3496 cfg_word |= tidmask; 3497 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 3498 cfg_word); 3499 3500 ADW_WRITE_BYTE_LRAM(iot, ioh, 3501 ADW_MC_NUMBER_OF_MAX_CMD + tid, 3502 sc->max_dvc_qng); 3503 } 3504 } 3505 #endif /* FAILSAFE */ 3506 } 3507 3508 3509 static void 3510 AdwSleepMilliSecond(n) 3511 u_int32_t n; 3512 { 3513 3514 DELAY(n * 1000); 3515 } 3516 3517 3518 static void 3519 AdwDelayMicroSecond(n) 3520 u_int32_t n; 3521 { 3522 3523 DELAY(n); 3524 } 3525 3526
Indexes created Tue Sep 23 14:10:03 GMT 2025