adwlib.c revision 1.19
1 /* $NetBSD: adwlib.c,v 1.19 2000/06/28 17:12:50 mrg Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <uvm/uvm_extern.h> 72 73 #include <dev/ic/adwlib.h> 74 #include <dev/ic/adwmcode.h> 75 #include <dev/ic/adw.h> 76 77 78 /* Static Functions */ 79 80 int AdwRamSelfTest __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 81 int AdwLoadMCode __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 82 u_int8_t)); 83 int AdwASC3550Cabling __P((bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *)); 84 int AdwASC38C0800Cabling __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_DVC_CFG *)); 86 int AdwASC38C1600Cabling __P((bus_space_tag_t, bus_space_handle_t, 87 ADW_DVC_CFG *)); 88 89 static u_int16_t AdwGetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 90 ADW_EEPROM *)); 91 static void AdwSetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 92 ADW_EEPROM *)); 93 static u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 94 static void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 95 96 static void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 97 98 static void AdwSleepMilliSecond __P((u_int32_t)); 99 static void AdwDelayMicroSecond __P((u_int32_t)); 100 101 102 /* 103 * EEPROM Configuration. 104 * 105 * All drivers should use this structure to set the default EEPROM 106 * configuration. The BIOS now uses this structure when it is built. 107 * Additional structure information can be found in adwlib.h where 108 * the structure is defined. 109 */ 110 const static ADW_EEPROM adw_3550_Default_EEPROM = { 111 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 112 0x0000, /* 01 cfg_msw */ 113 0xFFFF, /* 02 disc_enable */ 114 0xFFFF, /* 03 wdtr_able */ 115 { 0xFFFF }, /* 04 sdtr_able */ 116 0xFFFF, /* 05 start_motor */ 117 0xFFFF, /* 06 tagqng_able */ 118 0xFFFF, /* 07 bios_scan */ 119 0, /* 08 scam_tolerant */ 120 7, /* 09 adapter_scsi_id */ 121 0, /* bios_boot_delay */ 122 3, /* 10 scsi_reset_delay */ 123 0, /* bios_id_lun */ 124 0, /* 11 termination */ 125 0, /* reserved1 */ 126 0xFFE7, /* 12 bios_ctrl */ 127 { 0xFFFF }, /* 13 ultra_able */ 128 { 0 }, /* 14 reserved2 */ 129 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 130 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 131 0, /* 16 dvc_cntl */ 132 { 0 }, /* 17 bug_fix */ 133 { 0,0,0 }, /* 18-20 serial_number[3] */ 134 0, /* 21 check_sum */ 135 { /* 22-29 oem_name[16] */ 136 0,0,0,0,0,0,0,0, 137 0,0,0,0,0,0,0,0 138 }, 139 0, /* 30 dvc_err_code */ 140 0, /* 31 adv_err_code */ 141 0, /* 32 adv_err_addr */ 142 0, /* 33 saved_dvc_err_code */ 143 0, /* 34 saved_adv_err_code */ 144 0 /* 35 saved_adv_err_addr */ 145 }; 146 147 const static ADW_EEPROM adw_38C0800_Default_EEPROM = { 148 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 149 0x0000, /* 01 cfg_msw */ 150 0xFFFF, /* 02 disc_enable */ 151 0xFFFF, /* 03 wdtr_able */ 152 { 0x4444 }, /* 04 sdtr_speed1 */ 153 0xFFFF, /* 05 start_motor */ 154 0xFFFF, /* 06 tagqng_able */ 155 0xFFFF, /* 07 bios_scan */ 156 0, /* 08 scam_tolerant */ 157 7, /* 09 adapter_scsi_id */ 158 0, /* bios_boot_delay */ 159 3, /* 10 scsi_reset_delay */ 160 0, /* bios_id_lun */ 161 0, /* 11 termination_se */ 162 0, /* termination_lvd */ 163 0xFFE7, /* 12 bios_ctrl */ 164 { 0x4444 }, /* 13 sdtr_speed2 */ 165 { 0x4444 }, /* 14 sdtr_speed3 */ 166 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 167 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 168 0, /* 16 dvc_cntl */ 169 { 0x4444 }, /* 17 sdtr_speed4 */ 170 { 0,0,0 }, /* 18-20 serial_number[3] */ 171 0, /* 21 check_sum */ 172 { /* 22-29 oem_name[16] */ 173 0,0,0,0,0,0,0,0, 174 0,0,0,0,0,0,0,0 175 }, 176 0, /* 30 dvc_err_code */ 177 0, /* 31 adv_err_code */ 178 0, /* 32 adv_err_addr */ 179 0, /* 33 saved_dvc_err_code */ 180 0, /* 34 saved_adv_err_code */ 181 0, /* 35 saved_adv_err_addr */ 182 { /* 36-55 reserved1[16] */ 183 0,0,0,0,0,0,0,0,0,0, 184 0,0,0,0,0,0,0,0,0,0 185 }, 186 0, /* 56 cisptr_lsw */ 187 0, /* 57 cisprt_msw */ 188 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 189 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 190 { 0,0,0,0 } /* 60-63 reserved2[4] */ 191 }; 192 193 const static ADW_EEPROM adw_38C1600_Default_EEPROM = { 194 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 195 0x0000, /* 01 cfg_msw */ 196 0xFFFF, /* 02 disc_enable */ 197 0xFFFF, /* 03 wdtr_able */ 198 { 0x5555 }, /* 04 sdtr_speed1 */ 199 0xFFFF, /* 05 start_motor */ 200 0xFFFF, /* 06 tagqng_able */ 201 0xFFFF, /* 07 bios_scan */ 202 0, /* 08 scam_tolerant */ 203 7, /* 09 adapter_scsi_id */ 204 0, /* bios_boot_delay */ 205 3, /* 10 scsi_reset_delay */ 206 0, /* bios_id_lun */ 207 0, /* 11 termination_se */ 208 0, /* termination_lvd */ 209 0xFFE7, /* 12 bios_ctrl */ 210 { 0x5555 }, /* 13 sdtr_speed2 */ 211 { 0x5555 }, /* 14 sdtr_speed3 */ 212 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 213 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 214 0, /* 16 dvc_cntl */ 215 { 0x5555 }, /* 17 sdtr_speed4 */ 216 { 0,0,0 }, /* 18-20 serial_number[3] */ 217 0, /* 21 check_sum */ 218 { /* 22-29 oem_name[16] */ 219 0,0,0,0,0,0,0,0, 220 0,0,0,0,0,0,0,0 221 }, 222 0, /* 30 dvc_err_code */ 223 0, /* 31 adv_err_code */ 224 0, /* 32 adv_err_addr */ 225 0, /* 33 saved_dvc_err_code */ 226 0, /* 34 saved_adv_err_code */ 227 0, /* 35 saved_adv_err_addr */ 228 { /* 36-55 reserved1[16] */ 229 0,0,0,0,0,0,0,0,0,0, 230 0,0,0,0,0,0,0,0,0,0 231 }, 232 0, /* 56 cisptr_lsw */ 233 0, /* 57 cisprt_msw */ 234 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 235 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 236 { 0,0,0,0 } /* 60-63 reserved2[4] */ 237 }; 238 239 240 /* 241 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 242 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 243 * all of this is done. 244 * 245 * For a non-fatal error return a warning code. If there are no warnings 246 * then 0 is returned. 247 * 248 * Note: Chip is stopped on entry. 249 */ 250 int 251 AdwInitFromEEPROM(sc) 252 ADW_SOFTC *sc; 253 { 254 bus_space_tag_t iot = sc->sc_iot; 255 bus_space_handle_t ioh = sc->sc_ioh; 256 ADW_EEPROM eep_config; 257 u_int16_t warn_code; 258 u_int16_t sdtr_speed = 0; 259 u_int8_t tid, termination; 260 int i, j; 261 262 263 warn_code = 0; 264 265 /* 266 * Read the board's EEPROM configuration. 267 * 268 * Set default values if a bad checksum is found. 269 * 270 * XXX - Don't handle big-endian access to EEPROM yet. 271 */ 272 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 273 warn_code |= ADW_WARN_EEPROM_CHKSUM; 274 275 /* 276 * Set EEPROM default values. 277 */ 278 switch(sc->chip_type) { 279 case ADW_CHIP_ASC3550: 280 eep_config = adw_3550_Default_EEPROM; 281 break; 282 case ADW_CHIP_ASC38C0800: 283 eep_config = adw_38C0800_Default_EEPROM; 284 break; 285 case ADW_CHIP_ASC38C1600: 286 eep_config = adw_38C1600_Default_EEPROM; 287 288 // XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 289 if (sc->cfg.pci_slot_info != 0) { 290 u_int8_t lsw_msb; 291 292 lsw_msb = eep_config.cfg_lsw >> 8; 293 /* 294 * Set Function 1 EEPROM Word 0 MSB 295 * 296 * Clear the BIOS_ENABLE (bit 14) and 297 * INTAB (bit 11) EEPROM bits. 298 * 299 * Disable Bit 14 (BIOS_ENABLE) to fix 300 * SPARC Ultra 60 and old Mac system booting 301 * problem. The Expansion ROM must 302 * be disabled in Function 1 for these systems. 303 */ 304 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 305 ADW_EEPROM_INTAB) >> 8) & 0xFF); 306 /* 307 * Set the INTAB (bit 11) if the GPIO 0 input 308 * indicates the Function 1 interrupt line is 309 * wired to INTA. 310 * 311 * Set/Clear Bit 11 (INTAB) from 312 * the GPIO bit 0 input: 313 * 1 - Function 1 intr line wired to INT A. 314 * 0 - Function 1 intr line wired to INT B. 315 * 316 * Note: Adapter boards always have Function 0 317 * wired to INTA. 318 * Put all 5 GPIO bits in input mode and then 319 * read their input values. 320 */ 321 ADW_WRITE_BYTE_REGISTER(iot, ioh, 322 IOPB_GPIO_CNTL, 0); 323 if (ADW_READ_BYTE_REGISTER(iot, ioh, 324 IOPB_GPIO_DATA) & 0x01) { 325 /* 326 * Function 1 interrupt wired to INTA; 327 * Set EEPROM bit. 328 */ 329 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 330 & 0xFF; 331 } 332 eep_config.cfg_lsw &= 0x00FF; 333 eep_config.cfg_lsw |= lsw_msb << 8; 334 } 335 break; 336 } 337 338 /* 339 * Assume the 6 byte board serial number that was read 340 * from EEPROM is correct even if the EEPROM checksum 341 * failed. 342 */ 343 for (i=2, j=1; i>=0; i--, j++) { 344 eep_config.serial_number[i] = 345 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 346 } 347 348 AdwSetEEPROMConfig(iot, ioh, &eep_config); 349 } 350 /* 351 * Set sc and sc->cfg variables from the EEPROM configuration 352 * that was read. 353 * 354 * This is the mapping of EEPROM fields to Adw Library fields. 355 */ 356 sc->wdtr_able = eep_config.wdtr_able; 357 if (sc->chip_type == ADW_CHIP_ASC3550) { 358 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 359 sc->ultra_able = eep_config.sdtr2.ultra_able; 360 } else { 361 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 362 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 363 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 364 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 365 } 366 sc->ppr_able = 0; 367 sc->tagqng_able = eep_config.tagqng_able; 368 sc->cfg.disc_enable = eep_config.disc_enable; 369 sc->max_host_qng = eep_config.max_host_qng; 370 sc->max_dvc_qng = eep_config.max_dvc_qng; 371 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 372 sc->start_motor = eep_config.start_motor; 373 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 374 sc->bios_ctrl = eep_config.bios_ctrl; 375 sc->no_scam = eep_config.scam_tolerant; 376 sc->cfg.serial1 = eep_config.serial_number[0]; 377 sc->cfg.serial2 = eep_config.serial_number[1]; 378 sc->cfg.serial3 = eep_config.serial_number[2]; 379 380 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 381 sc->chip_type == ADW_CHIP_ASC38C1600) { 382 sc->sdtr_able = 0; 383 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 384 if (tid == 0) { 385 sdtr_speed = sc->sdtr_speed1; 386 } else if (tid == 4) { 387 sdtr_speed = sc->sdtr_speed2; 388 } else if (tid == 8) { 389 sdtr_speed = sc->sdtr_speed3; 390 } else if (tid == 12) { 391 sdtr_speed = sc->sdtr_speed4; 392 } 393 if (sdtr_speed & ADW_MAX_TID) { 394 sc->sdtr_able |= (1 << tid); 395 } 396 sdtr_speed >>= 4; 397 } 398 } 399 400 /* 401 * Set the host maximum queuing (max. 253, min. 16) and the per device 402 * maximum queuing (max. 63, min. 4). 403 */ 404 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 405 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 406 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 407 { 408 /* If the value is zero, assume it is uninitialized. */ 409 if (eep_config.max_host_qng == 0) { 410 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 411 } else { 412 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 413 } 414 } 415 416 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 417 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 418 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 419 /* If the value is zero, assume it is uninitialized. */ 420 if (eep_config.max_dvc_qng == 0) { 421 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 422 } else { 423 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 424 } 425 } 426 427 /* 428 * If 'max_dvc_qng' is greater than 'max_host_qng', then 429 * set 'max_dvc_qng' to 'max_host_qng'. 430 */ 431 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 432 eep_config.max_dvc_qng = eep_config.max_host_qng; 433 } 434 435 /* 436 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 437 * values based on possibly adjusted EEPROM values. 438 */ 439 sc->max_host_qng = eep_config.max_host_qng; 440 sc->max_dvc_qng = eep_config.max_dvc_qng; 441 442 443 /* 444 * If the EEPROM 'termination' field is set to automatic (0), then set 445 * the ADV_DVC_CFG 'termination' field to automatic also. 446 * 447 * If the termination is specified with a non-zero 'termination' 448 * value check that a legal value is set and set the ADV_DVC_CFG 449 * 'termination' field appropriately. 450 */ 451 452 switch(sc->chip_type) { 453 case ADW_CHIP_ASC3550: 454 sc->cfg.termination = 0; /* auto termination */ 455 switch(eep_config.termination_se) { 456 case 3: 457 /* Enable manual control with low on / high on. */ 458 sc->cfg.termination |= ADW_TERM_CTL_L; 459 case 2: 460 /* Enable manual control with low off / high on. */ 461 sc->cfg.termination |= ADW_TERM_CTL_H; 462 case 1: 463 /* Enable manual control with low off / high off. */ 464 sc->cfg.termination |= ADW_TERM_CTL_SEL; 465 case 0: 466 break; 467 default: 468 warn_code |= ADW_WARN_EEPROM_TERMINATION; 469 } 470 break; 471 472 case ADW_CHIP_ASC38C0800: 473 case ADW_CHIP_ASC38C1600: 474 switch(eep_config.termination_se) { 475 case 0: 476 /* auto termination for SE */ 477 termination = 0; 478 break; 479 case 1: 480 /* Enable manual control with low off / high off. */ 481 termination = 0; 482 break; 483 case 2: 484 /* Enable manual control with low off / high on. */ 485 termination = ADW_TERM_SE_HI; 486 break; 487 case 3: 488 /* Enable manual control with low on / high on. */ 489 termination = ADW_TERM_SE; 490 break; 491 default: 492 /* 493 * The EEPROM 'termination_se' field contains a 494 * bad value. Use automatic termination instead. 495 */ 496 termination = 0; 497 warn_code |= ADW_WARN_EEPROM_TERMINATION; 498 } 499 500 switch(eep_config.termination_lvd) { 501 case 0: 502 /* auto termination for LVD */ 503 sc->cfg.termination = termination; 504 break; 505 case 1: 506 /* Enable manual control with low off / high off. */ 507 sc->cfg.termination = termination; 508 break; 509 case 2: 510 /* Enable manual control with low off / high on. */ 511 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 512 break; 513 case 3: 514 /* Enable manual control with low on / high on. */ 515 sc->cfg.termination = termination | ADW_TERM_LVD; 516 break; 517 default: 518 /* 519 * The EEPROM 'termination_lvd' field contains a 520 * bad value. Use automatic termination instead. 521 */ 522 sc->cfg.termination = termination; 523 warn_code |= ADW_WARN_EEPROM_TERMINATION; 524 } 525 break; 526 } 527 528 return warn_code; 529 } 530 531 532 /* 533 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 534 * 535 * On failure return the error code. 536 */ 537 int 538 AdwInitDriver(sc) 539 ADW_SOFTC *sc; 540 { 541 bus_space_tag_t iot = sc->sc_iot; 542 bus_space_handle_t ioh = sc->sc_ioh; 543 u_int16_t error_code; 544 int word; 545 int i; 546 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 547 0x40-0x8F. */ 548 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 549 u_int8_t max_cmd[ADW_MAX_TID + 1]; 550 u_int8_t tid; 551 552 553 error_code = 0; 554 555 /* 556 * Save the RISC memory BIOS region before writing the microcode. 557 * The BIOS may already be loaded and using its RISC LRAM region 558 * so its region must be saved and restored. 559 * 560 * Note: This code makes the assumption, which is currently true, 561 * that a chip reset does not clear RISC LRAM. 562 */ 563 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 564 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 565 } 566 567 /* 568 * Save current per TID negotiated values. 569 */ 570 switch (sc->chip_type) { 571 case ADW_CHIP_ASC3550: 572 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 573 574 u_int16_t bios_version, major, minor; 575 576 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 577 ADW_MC_BIOSMEM) / 2]; 578 major = (bios_version >> 12) & 0xF; 579 minor = (bios_version >> 8) & 0xF; 580 if (major < 3 || (major == 3 && minor == 1)) { 581 /* 582 * BIOS 3.1 and earlier location of 583 * 'wdtr_able' variable. 584 */ 585 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 586 } else { 587 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 588 wdtr_able); 589 } 590 } 591 break; 592 593 case ADW_CHIP_ASC38C1600: 594 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 595 /* FALLTHROUGH */ 596 case ADW_CHIP_ASC38C0800: 597 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 598 break; 599 } 600 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 601 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 602 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 603 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 604 max_cmd[tid]); 605 } 606 607 /* 608 * Perform a RAM Built-In Self Test 609 */ 610 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 611 return error_code; 612 } 613 614 /* 615 * Load the Microcode 616 */ 617 ; 618 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 619 return error_code; 620 } 621 622 /* 623 * Read microcode version and date. 624 */ 625 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 626 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 627 628 /* 629 * If the PCI Configuration Command Register "Parity Error Response 630 * Control" Bit was clear (0), then set the microcode variable 631 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 632 * to ignore DMA parity errors. 633 */ 634 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 635 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 636 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 637 word | CONTROL_FLAG_IGNORE_PERR); 638 } 639 640 switch (sc->chip_type) { 641 case ADW_CHIP_ASC3550: 642 /* 643 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 644 * FIFO threshold of 128 bytes. 645 * This register is only accessible to the host. 646 */ 647 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 648 START_CTL_EMFU | READ_CMD_MRM); 649 break; 650 651 case ADW_CHIP_ASC38C0800: 652 /* 653 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 654 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 655 * cable detection and then we are able to read C_DET[3:0]. 656 * 657 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 658 * Microcode Default Value' section below. 659 */ 660 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 661 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 662 | ADW_DIS_TERM_DRV); 663 664 /* 665 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 666 * START_CTL_TH [3:2] bits for the default FIFO threshold. 667 * 668 * Note: ASC-38C0800 FIFO threshold has been changed to 669 * 256 bytes. 670 * 671 * For DMA Errata #4 set the BC_THRESH_ENB bit. 672 */ 673 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 674 BC_THRESH_ENB | FIFO_THRESH_80B 675 | START_CTL_TH | READ_CMD_MRM); 676 break; 677 678 case ADW_CHIP_ASC38C1600: 679 /* 680 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 681 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 682 * cable detection and then we are able to read C_DET[3:0]. 683 * 684 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 685 * Microcode Default Value' section below. 686 */ 687 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 688 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 689 | ADW_DIS_TERM_DRV); 690 691 /* 692 * If the BIOS control flag AIPP (Asynchronous Information 693 * Phase Protection) disable bit is not set, then set the 694 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 695 * enable AIPP checking and encoding. 696 */ 697 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 698 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 699 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 700 word | CONTROL_FLAG_ENABLE_AIPP); 701 } 702 703 /* 704 * For ASC-38C1600 use DMA_CFG0 default values: 705 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 706 */ 707 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 708 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 709 break; 710 } 711 712 /* 713 * Microcode operating variables for WDTR, SDTR, and command tag 714 * queuing will be set in AdvInquiryHandling() based on what a 715 * device reports it is capable of in Inquiry byte 7. 716 * 717 * If SCSI Bus Resets have been disabled, then directly set 718 * SDTR and WDTR from the EEPROM configuration. This will allow 719 * the BIOS and warm boot to work without a SCSI bus hang on 720 * the Inquiry caused by host and target mismatched DTR values. 721 * Without the SCSI Bus Reset, before an Inquiry a device can't 722 * be assumed to be in Asynchronous, Narrow mode. 723 */ 724 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 725 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 726 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 727 } 728 729 /* 730 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 731 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 732 * bitmask. These values determine the maximum SDTR speed negotiated 733 * with a device. 734 * 735 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 736 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 737 * without determining here whether the device supports SDTR. 738 */ 739 switch (sc->chip_type) { 740 case ADW_CHIP_ASC3550: 741 word = 0; 742 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 743 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 744 /* Set Ultra speed for TID 'tid'. */ 745 word |= (0x3 << (4 * (tid % 4))); 746 } else { 747 /* Set Fast speed for TID 'tid'. */ 748 word |= (0x2 << (4 * (tid % 4))); 749 } 750 /* Check if done with sdtr_speed1. */ 751 if (tid == 3) { 752 ADW_WRITE_WORD_LRAM(iot, ioh, 753 ADW_MC_SDTR_SPEED1, word); 754 word = 0; 755 /* Check if done with sdtr_speed2. */ 756 } else if (tid == 7) { 757 ADW_WRITE_WORD_LRAM(iot, ioh, 758 ADW_MC_SDTR_SPEED2, word); 759 word = 0; 760 /* Check if done with sdtr_speed3. */ 761 } else if (tid == 11) { 762 ADW_WRITE_WORD_LRAM(iot, ioh, 763 ADW_MC_SDTR_SPEED3, word); 764 word = 0; 765 /* Check if done with sdtr_speed4. */ 766 } else if (tid == 15) { 767 ADW_WRITE_WORD_LRAM(iot, ioh, 768 ADW_MC_SDTR_SPEED4, word); 769 /* End of loop. */ 770 } 771 } 772 773 /* 774 * Set microcode operating variable for the 775 * disconnect per TID bitmask. 776 */ 777 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 778 sc->cfg.disc_enable); 779 break; 780 781 case ADW_CHIP_ASC38C0800: 782 /* FALLTHROUGH */ 783 case ADW_CHIP_ASC38C1600: 784 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 785 sc->cfg.disc_enable); 786 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 787 sc->sdtr_speed1); 788 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 789 sc->sdtr_speed2); 790 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 791 sc->sdtr_speed3); 792 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 793 sc->sdtr_speed4); 794 break; 795 } 796 797 798 /* 799 * Set SCSI_CFG0 Microcode Default Value. 800 * 801 * The microcode will set the SCSI_CFG0 register using this value 802 * after it is started below. 803 */ 804 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 805 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 806 ADW_OUR_ID_EN | sc->chip_scsi_id); 807 808 809 switch(sc->chip_type) { 810 case ADW_CHIP_ASC3550: 811 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 812 break; 813 814 case ADW_CHIP_ASC38C0800: 815 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 816 break; 817 818 case ADW_CHIP_ASC38C1600: 819 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 820 break; 821 } 822 if(error_code) { 823 return error_code; 824 } 825 826 /* 827 * Set SEL_MASK Microcode Default Value 828 * 829 * The microcode will set the SEL_MASK register using this value 830 * after it is started below. 831 */ 832 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 833 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 834 835 /* 836 * Create and Initialize Host->RISC Carrier lists 837 */ 838 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 839 sc->sc_control->carriers); 840 841 /* 842 * Set-up the Host->RISC Initiator Command Queue (ICQ). 843 */ 844 845 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 846 return ADW_IERR_NO_CARRIER; 847 } 848 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 849 ASC_GET_CARRP(sc->icq_sp->next_ba)); 850 851 /* 852 * The first command issued will be placed in the stopper carrier. 853 */ 854 sc->icq_sp->next_ba = ASC_CQ_STOPPER; 855 856 /* 857 * Set RISC ICQ physical address start value. 858 */ 859 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 860 861 /* 862 * Initialize the COMMA register to the same value otherwise 863 * the RISC will prematurely detect a command is available. 864 */ 865 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 866 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 867 sc->icq_sp->carr_ba); 868 } 869 870 /* 871 * Set-up the RISC->Host Initiator Response Queue (IRQ). 872 */ 873 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 874 return ADW_IERR_NO_CARRIER; 875 } 876 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 877 ASC_GET_CARRP(sc->irq_sp->next_ba)); 878 879 /* 880 * The first command completed by the RISC will be placed in 881 * the stopper. 882 * 883 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 884 * completed the RISC will set the ASC_RQ_DONE bit. 885 */ 886 sc->irq_sp->next_ba = ASC_CQ_STOPPER; 887 888 /* 889 * Set RISC IRQ physical address start value. 890 */ 891 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 892 sc->carr_pending_cnt = 0; 893 894 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 895 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 896 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 897 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 898 899 /* finally, finally, gentlemen, start your engine */ 900 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 901 902 /* 903 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 904 * Resets should be performed. The RISC has to be running 905 * to issue a SCSI Bus Reset. 906 */ 907 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 908 { 909 /* 910 * If the BIOS Signature is present in memory, restore the 911 * BIOS Handshake Configuration Table and do not perform 912 * a SCSI Bus Reset. 913 */ 914 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 915 0x55AA) { 916 /* 917 * Restore per TID negotiated values. 918 */ 919 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 920 wdtr_able); 921 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 922 sdtr_able); 923 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 924 tagqng_able); 925 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 926 ADW_WRITE_BYTE_LRAM(iot, ioh, 927 ADW_MC_NUMBER_OF_MAX_CMD + tid, 928 max_cmd[tid]); 929 } 930 } else { 931 if (AdwResetCCB(sc) != ADW_TRUE) { 932 error_code = ADW_WARN_BUSRESET_ERROR; 933 } 934 } 935 } 936 937 return error_code; 938 } 939 940 941 int 942 AdwRamSelfTest(iot, ioh, chip_type) 943 bus_space_tag_t iot; 944 bus_space_handle_t ioh; 945 u_int8_t chip_type; 946 { 947 int i; 948 u_int8_t byte; 949 950 951 if ((chip_type == ADW_CHIP_ASC38C0800) || 952 (chip_type == ADW_CHIP_ASC38C1600)) { 953 /* 954 * RAM BIST (RAM Built-In Self Test) 955 * 956 * Address : I/O base + offset 0x38h register (byte). 957 * Function: Bit 7-6(RW) : RAM mode 958 * Normal Mode : 0x00 959 * Pre-test Mode : 0x40 960 * RAM Test Mode : 0x80 961 * Bit 5 : unused 962 * Bit 4(RO) : Done bit 963 * Bit 3-0(RO) : Status 964 * Host Error : 0x08 965 * Int_RAM Error : 0x04 966 * RISC Error : 0x02 967 * SCSI Error : 0x01 968 * No Error : 0x00 969 * 970 * Note: RAM BIST code should be put right here, before loading 971 * the microcode and after saving the RISC memory BIOS region. 972 */ 973 974 /* 975 * LRAM Pre-test 976 * 977 * Write PRE_TEST_MODE (0x40) to register and wait for 978 * 10 milliseconds. 979 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 980 * return an error. Reset to NORMAL_MODE (0x00) and do again. 981 * If cannot reset to NORMAL_MODE, return an error too. 982 */ 983 for (i = 0; i < 2; i++) { 984 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 985 PRE_TEST_MODE); 986 /* Wait for 10ms before reading back. */ 987 AdwSleepMilliSecond(10); 988 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 989 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 990 PRE_TEST_VALUE) { 991 return ADW_IERR_BIST_PRE_TEST; 992 } 993 994 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 995 NORMAL_MODE); 996 /* Wait for 10ms before reading back. */ 997 AdwSleepMilliSecond(10); 998 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 999 != NORMAL_VALUE) { 1000 return ADW_IERR_BIST_PRE_TEST; 1001 } 1002 } 1003 1004 /* 1005 * LRAM Test - It takes about 1.5 ms to run through the test. 1006 * 1007 * Write RAM_TEST_MODE (0x80) to register and wait for 1008 * 10 milliseconds. 1009 * If Done bit not set or Status not 0, save register byte, 1010 * set the err_code, and return an error. 1011 */ 1012 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1013 /* Wait for 10ms before checking status. */ 1014 AdwSleepMilliSecond(10); 1015 1016 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1017 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1018 /* Get here if Done bit not set or Status not 0. */ 1019 return ADW_IERR_BIST_RAM_TEST; 1020 } 1021 1022 /* We need to reset back to normal mode after LRAM test passes*/ 1023 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1024 } 1025 1026 return 0; 1027 } 1028 1029 1030 int 1031 AdwLoadMCode(iot, ioh, bios_mem, chip_type) 1032 bus_space_tag_t iot; 1033 bus_space_handle_t ioh; 1034 u_int16_t *bios_mem; 1035 u_int8_t chip_type; 1036 { 1037 u_int8_t *mcode_data; 1038 u_int32_t mcode_chksum; 1039 u_int16_t mcode_size; 1040 u_int32_t sum; 1041 u_int16_t code_sum; 1042 int begin_addr; 1043 int end_addr; 1044 int word; 1045 int adw_memsize; 1046 int adw_mcode_expanded_size; 1047 int i, j; 1048 1049 1050 switch(chip_type) { 1051 case ADW_CHIP_ASC3550: 1052 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1053 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1054 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1055 adw_memsize = ADW_3550_MEMSIZE; 1056 break; 1057 1058 case ADW_CHIP_ASC38C0800: 1059 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1060 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1061 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1062 adw_memsize = ADW_38C0800_MEMSIZE; 1063 break; 1064 1065 case ADW_CHIP_ASC38C1600: 1066 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1067 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1068 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1069 adw_memsize = ADW_38C1600_MEMSIZE; 1070 break; 1071 } 1072 1073 /* 1074 * Write the microcode image to RISC memory starting at address 0. 1075 */ 1076 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1077 1078 /* Assume the following compressed format of the microcode buffer: 1079 * 1080 * 254 word (508 byte) table indexed by byte code followed 1081 * by the following byte codes: 1082 * 1083 * 1-Byte Code: 1084 * 00: Emit word 0 in table. 1085 * 01: Emit word 1 in table. 1086 * . 1087 * FD: Emit word 253 in table. 1088 * 1089 * Multi-Byte Code: 1090 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1091 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1092 */ 1093 word = 0; 1094 for (i = 253 * 2; i < mcode_size; i++) { 1095 if (mcode_data[i] == 0xff) { 1096 for (j = 0; j < mcode_data[i + 1]; j++) { 1097 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1098 (((u_int16_t)mcode_data[i + 3] << 8) | 1099 mcode_data[i + 2])); 1100 word++; 1101 } 1102 i += 3; 1103 } else if (mcode_data[i] == 0xfe) { 1104 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1105 (((u_int16_t)mcode_data[i + 2] << 8) | 1106 mcode_data[i + 1])); 1107 i += 2; 1108 word++; 1109 } else { 1110 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1111 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1112 mcode_data[mcode_data[i] * 2])); 1113 word++; 1114 } 1115 } 1116 1117 /* 1118 * Set 'word' for later use to clear the rest of memory and save 1119 * the expanded mcode size. 1120 */ 1121 word *= 2; 1122 adw_mcode_expanded_size = word; 1123 1124 /* 1125 * Clear the rest of the Internal RAM. 1126 */ 1127 for (; word < adw_memsize; word += 2) { 1128 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1129 } 1130 1131 /* 1132 * Verify the microcode checksum. 1133 */ 1134 sum = 0; 1135 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1136 1137 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1138 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1139 } 1140 1141 if (sum != mcode_chksum) { 1142 return ADW_IERR_MCODE_CHKSUM; 1143 } 1144 1145 /* 1146 * Restore the RISC memory BIOS region. 1147 */ 1148 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1149 if(chip_type == ADW_CHIP_ASC3550) { 1150 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1151 bios_mem[i]); 1152 } else { 1153 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1154 bios_mem[i]); 1155 } 1156 } 1157 1158 /* 1159 * Calculate and write the microcode code checksum to the microcode 1160 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1161 */ 1162 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1163 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1164 code_sum = 0; 1165 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1166 for (word = begin_addr; word < end_addr; word += 2) { 1167 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1168 } 1169 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1170 1171 /* 1172 * Set the chip type. 1173 */ 1174 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1175 1176 return 0; 1177 } 1178 1179 1180 int 1181 AdwASC3550Cabling(iot, ioh, cfg) 1182 bus_space_tag_t iot; 1183 bus_space_handle_t ioh; 1184 ADW_DVC_CFG *cfg; 1185 { 1186 u_int16_t scsi_cfg1; 1187 1188 1189 /* 1190 * Determine SCSI_CFG1 Microcode Default Value. 1191 * 1192 * The microcode will set the SCSI_CFG1 register using this value 1193 * after it is started below. 1194 */ 1195 1196 /* Read current SCSI_CFG1 Register value. */ 1197 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1198 1199 /* 1200 * If all three connectors are in use in ASC3550, return an error. 1201 */ 1202 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1203 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1204 return ADW_IERR_ILLEGAL_CONNECTION; 1205 } 1206 1207 /* 1208 * If the cable is reversed all of the SCSI_CTRL register signals 1209 * will be set. Check for and return an error if this condition is 1210 * found. 1211 */ 1212 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1213 return ADW_IERR_REVERSED_CABLE; 1214 } 1215 1216 /* 1217 * If this is a differential board and a single-ended device 1218 * is attached to one of the connectors, return an error. 1219 */ 1220 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1221 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1222 return ADW_IERR_SINGLE_END_DEVICE; 1223 } 1224 1225 /* 1226 * If automatic termination control is enabled, then set the 1227 * termination value based on a table listed in a_condor.h. 1228 * 1229 * If manual termination was specified with an EEPROM setting 1230 * then 'termination' was set-up in AdwInitFromEEPROM() and 1231 * is ready to be 'ored' into SCSI_CFG1. 1232 */ 1233 if (cfg->termination == 0) { 1234 /* 1235 * The software always controls termination by setting 1236 * TERM_CTL_SEL. 1237 * If TERM_CTL_SEL were set to 0, the hardware would set 1238 * termination. 1239 */ 1240 cfg->termination |= ADW_TERM_CTL_SEL; 1241 1242 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1243 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1244 case 0x3: case 0x7: case 0xB: 1245 case 0xD: case 0xE: case 0xF: 1246 cfg->termination |= 1247 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1248 break; 1249 1250 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1251 case 0x1: case 0x5: case 0x9: 1252 case 0xA: case 0xC: 1253 cfg->termination |= ADW_TERM_CTL_H; 1254 break; 1255 1256 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1257 case 0x2: case 0x6: 1258 break; 1259 } 1260 } 1261 1262 /* 1263 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1264 */ 1265 scsi_cfg1 &= ~ADW_TERM_CTL; 1266 1267 /* 1268 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1269 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1270 * referenced, because the hardware internally inverts 1271 * the Termination High and Low bits if TERM_POL is set. 1272 */ 1273 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1274 1275 /* 1276 * Set SCSI_CFG1 Microcode Default Value 1277 * 1278 * Set filter value and possibly modified termination control 1279 * bits in the Microcode SCSI_CFG1 Register Value. 1280 * 1281 * The microcode will set the SCSI_CFG1 register using this value 1282 * after it is started below. 1283 */ 1284 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1285 ADW_FLTR_DISABLE | scsi_cfg1); 1286 1287 /* 1288 * Set MEM_CFG Microcode Default Value 1289 * 1290 * The microcode will set the MEM_CFG register using this value 1291 * after it is started below. 1292 * 1293 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1294 * are defined. 1295 * 1296 * ASC-3550 has 8KB internal memory. 1297 */ 1298 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1299 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1300 1301 return 0; 1302 } 1303 1304 1305 int 1306 AdwASC38C0800Cabling(iot, ioh, cfg) 1307 bus_space_tag_t iot; 1308 bus_space_handle_t ioh; 1309 ADW_DVC_CFG *cfg; 1310 { 1311 u_int16_t scsi_cfg1; 1312 1313 1314 /* 1315 * Determine SCSI_CFG1 Microcode Default Value. 1316 * 1317 * The microcode will set the SCSI_CFG1 register using this value 1318 * after it is started below. 1319 */ 1320 1321 /* Read current SCSI_CFG1 Register value. */ 1322 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1323 1324 /* 1325 * If the cable is reversed all of the SCSI_CTRL register signals 1326 * will be set. Check for and return an error if this condition is 1327 * found. 1328 */ 1329 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1330 return ADW_IERR_REVERSED_CABLE; 1331 } 1332 1333 /* 1334 * All kind of combinations of devices attached to one of four 1335 * connectors are acceptable except HVD device attached. 1336 * For example, LVD device can be attached to SE connector while 1337 * SE device attached to LVD connector. 1338 * If LVD device attached to SE connector, it only runs up to 1339 * Ultra speed. 1340 * 1341 * If an HVD device is attached to one of LVD connectors, return 1342 * an error. 1343 * However, there is no way to detect HVD device attached to 1344 * SE connectors. 1345 */ 1346 if (scsi_cfg1 & ADW_HVD) { 1347 return ADW_IERR_HVD_DEVICE; 1348 } 1349 1350 /* 1351 * If either SE or LVD automatic termination control is enabled, then 1352 * set the termination value based on a table listed in a_condor.h. 1353 * 1354 * If manual termination was specified with an EEPROM setting then 1355 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1356 * to be 'ored' into SCSI_CFG1. 1357 */ 1358 if ((cfg->termination & ADW_TERM_SE) == 0) { 1359 /* SE automatic termination control is enabled. */ 1360 switch(scsi_cfg1 & ADW_C_DET_SE) { 1361 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1362 case 0x1: case 0x2: case 0x3: 1363 cfg->termination |= ADW_TERM_SE; 1364 break; 1365 1366 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1367 case 0x0: 1368 cfg->termination |= ADW_TERM_SE_HI; 1369 break; 1370 } 1371 } 1372 1373 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1374 /* LVD automatic termination control is enabled. */ 1375 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1376 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1377 case 0x4: case 0x8: case 0xC: 1378 cfg->termination |= ADW_TERM_LVD; 1379 break; 1380 1381 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1382 case 0x0: 1383 break; 1384 } 1385 } 1386 1387 /* 1388 * Clear any set TERM_SE and TERM_LVD bits. 1389 */ 1390 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1391 1392 /* 1393 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1394 */ 1395 scsi_cfg1 |= (~cfg->termination & 0xF0); 1396 1397 /* 1398 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1399 * HVD/LVD/SE bits and set possibly modified termination control bits 1400 * in the Microcode SCSI_CFG1 Register Value. 1401 */ 1402 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1403 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1404 1405 /* 1406 * Set SCSI_CFG1 Microcode Default Value 1407 * 1408 * Set possibly modified termination control and reset DIS_TERM_DRV 1409 * bits in the Microcode SCSI_CFG1 Register Value. 1410 * 1411 * The microcode will set the SCSI_CFG1 register using this value 1412 * after it is started below. 1413 */ 1414 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1415 1416 /* 1417 * Set MEM_CFG Microcode Default Value 1418 * 1419 * The microcode will set the MEM_CFG register using this value 1420 * after it is started below. 1421 * 1422 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1423 * are defined. 1424 * 1425 * ASC-38C0800 has 16KB internal memory. 1426 */ 1427 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1428 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1429 1430 return 0; 1431 } 1432 1433 1434 int 1435 AdwASC38C1600Cabling(iot, ioh, cfg) 1436 bus_space_tag_t iot; 1437 bus_space_handle_t ioh; 1438 ADW_DVC_CFG *cfg; 1439 { 1440 u_int16_t scsi_cfg1; 1441 1442 1443 /* 1444 * Determine SCSI_CFG1 Microcode Default Value. 1445 * 1446 * The microcode will set the SCSI_CFG1 register using this value 1447 * after it is started below. 1448 * Each ASC-38C1600 function has only two cable detect bits. 1449 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1450 */ 1451 1452 /* Read current SCSI_CFG1 Register value. */ 1453 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1454 1455 /* 1456 * If the cable is reversed all of the SCSI_CTRL register signals 1457 * will be set. Check for and return an error if this condition is 1458 * found. 1459 */ 1460 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1461 return ADW_IERR_REVERSED_CABLE; 1462 } 1463 1464 /* 1465 * Each ASC-38C1600 function has two connectors. Only an HVD device 1466 * can not be connected to either connector. An LVD device or SE device 1467 * may be connected to either connecor. If an SE device is connected, 1468 * then at most Ultra speed (20 Mhz) can be used on both connectors. 1469 * 1470 * If an HVD device is attached, return an error. 1471 */ 1472 if (scsi_cfg1 & ADW_HVD) { 1473 return ADW_IERR_HVD_DEVICE; 1474 } 1475 1476 /* 1477 * Each function in the ASC-38C1600 uses only the SE cable detect and 1478 * termination because there are two connectors for each function. 1479 * Each function may use either LVD or SE mode. 1480 * Corresponding the SE automatic termination control EEPROM bits are 1481 * used for each function. 1482 * Each function has its own EEPROM. If SE automatic control is enabled 1483 * for the function, then set the termination value based on a table 1484 * listed in adwlib.h. 1485 * 1486 * If manual termination is specified in the EEPROM for the function, 1487 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1488 * ready to be 'ored' into SCSI_CFG1. 1489 */ 1490 if ((cfg->termination & ADW_TERM_SE) == 0) { 1491 /* SE automatic termination control is enabled. */ 1492 switch(scsi_cfg1 & ADW_C_DET_SE) { 1493 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1494 case 0x1: case 0x2: case 0x3: 1495 cfg->termination |= ADW_TERM_SE; 1496 break; 1497 1498 case 0x0: 1499 /* !!!!TODO!!!! */ 1500 // if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1501 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1502 // } 1503 // else 1504 // { 1505 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1506 cfg->termination |= ADW_TERM_SE_HI; 1507 // } 1508 break; 1509 } 1510 } 1511 1512 /* 1513 * Clear any set TERM_SE bits. 1514 */ 1515 scsi_cfg1 &= ~ADW_TERM_SE; 1516 1517 /* 1518 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1519 */ 1520 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1521 1522 /* 1523 * Clear Big Endian and Terminator Polarity bits and set possibly 1524 * modified termination control bits in the Microcode SCSI_CFG1 1525 * Register Value. 1526 */ 1527 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1528 1529 /* 1530 * Set SCSI_CFG1 Microcode Default Value 1531 * 1532 * Set possibly modified termination control bits in the Microcode 1533 * SCSI_CFG1 Register Value. 1534 * 1535 * The microcode will set the SCSI_CFG1 register using this value 1536 * after it is started below. 1537 */ 1538 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1539 1540 /* 1541 * Set MEM_CFG Microcode Default Value 1542 * 1543 * The microcode will set the MEM_CFG register using this value 1544 * after it is started below. 1545 * 1546 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1547 * are defined. 1548 * 1549 * ASC-38C1600 has 32KB internal memory. 1550 */ 1551 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1552 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1553 1554 return 0; 1555 } 1556 1557 1558 /* 1559 * Read EEPROM configuration into the specified buffer. 1560 * 1561 * Return a checksum based on the EEPROM configuration read. 1562 */ 1563 static u_int16_t 1564 AdwGetEEPROMConfig(iot, ioh, cfg_buf) 1565 bus_space_tag_t iot; 1566 bus_space_handle_t ioh; 1567 ADW_EEPROM *cfg_buf; 1568 { 1569 u_int16_t wval, chksum; 1570 u_int16_t *wbuf; 1571 int eep_addr; 1572 1573 1574 wbuf = (u_int16_t *) cfg_buf; 1575 chksum = 0; 1576 1577 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1578 eep_addr < ASC_EEP_DVC_CFG_END; 1579 eep_addr++, wbuf++) { 1580 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1581 chksum += wval; 1582 *wbuf = wval; 1583 } 1584 1585 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1586 wbuf++; 1587 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1588 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1589 eep_addr++, wbuf++) { 1590 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1591 } 1592 1593 return chksum; 1594 } 1595 1596 1597 /* 1598 * Read the EEPROM from specified location 1599 */ 1600 static u_int16_t 1601 AdwReadEEPWord(iot, ioh, eep_word_addr) 1602 bus_space_tag_t iot; 1603 bus_space_handle_t ioh; 1604 int eep_word_addr; 1605 { 1606 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1607 ASC_EEP_CMD_READ | eep_word_addr); 1608 AdwWaitEEPCmd(iot, ioh); 1609 1610 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1611 } 1612 1613 1614 /* 1615 * Wait for EEPROM command to complete 1616 */ 1617 static void 1618 AdwWaitEEPCmd(iot, ioh) 1619 bus_space_tag_t iot; 1620 bus_space_handle_t ioh; 1621 { 1622 int eep_delay_ms; 1623 1624 1625 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1626 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1627 ASC_EEP_CMD_DONE) { 1628 break; 1629 } 1630 AdwSleepMilliSecond(1); 1631 } 1632 1633 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1634 } 1635 1636 1637 /* 1638 * Write the EEPROM from 'cfg_buf'. 1639 */ 1640 static void 1641 AdwSetEEPROMConfig(iot, ioh, cfg_buf) 1642 bus_space_tag_t iot; 1643 bus_space_handle_t ioh; 1644 ADW_EEPROM *cfg_buf; 1645 { 1646 u_int16_t *wbuf; 1647 u_int16_t addr, chksum; 1648 1649 1650 wbuf = (u_int16_t *) cfg_buf; 1651 chksum = 0; 1652 1653 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1654 AdwWaitEEPCmd(iot, ioh); 1655 1656 /* 1657 * Write EEPROM from word 0 to word 20 1658 */ 1659 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1660 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1661 chksum += *wbuf; 1662 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1663 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1664 ASC_EEP_CMD_WRITE | addr); 1665 AdwWaitEEPCmd(iot, ioh); 1666 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1667 } 1668 1669 /* 1670 * Write EEPROM checksum at word 21 1671 */ 1672 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1673 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1674 ASC_EEP_CMD_WRITE | addr); 1675 AdwWaitEEPCmd(iot, ioh); 1676 wbuf++; /* skip over check_sum */ 1677 1678 /* 1679 * Write EEPROM OEM name at words 22 to 29 1680 */ 1681 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1682 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1683 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1684 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1685 ASC_EEP_CMD_WRITE | addr); 1686 AdwWaitEEPCmd(iot, ioh); 1687 } 1688 1689 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1690 ASC_EEP_CMD_WRITE_DISABLE); 1691 AdwWaitEEPCmd(iot, ioh); 1692 1693 return; 1694 } 1695 1696 1697 /* 1698 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1699 * 1700 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1701 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1702 * RISC to notify it a new command is ready to be executed. 1703 * 1704 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1705 * set to SCSI_MAX_RETRY. 1706 * 1707 * Return: 1708 * ADW_SUCCESS(1) - The request was successfully queued. 1709 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1710 * request completes. 1711 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1712 * host IC error. 1713 */ 1714 int 1715 AdwExeScsiQueue(sc, scsiq) 1716 ADW_SOFTC *sc; 1717 ADW_SCSI_REQ_Q *scsiq; 1718 { 1719 bus_space_tag_t iot = sc->sc_iot; 1720 bus_space_handle_t ioh = sc->sc_ioh; 1721 ADW_CCB *ccb; 1722 long req_size; 1723 u_int32_t req_paddr; 1724 ADW_CARRIER *new_carrp; 1725 1726 /* 1727 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1728 */ 1729 if (scsiq->target_id > ADW_MAX_TID) { 1730 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1731 scsiq->done_status = QD_WITH_ERROR; 1732 return ADW_ERROR; 1733 } 1734 1735 /* 1736 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1737 */ 1738 1739 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1740 1741 /* 1742 * Allocate a carrier and initialize fields. 1743 */ 1744 if ((new_carrp = sc->carr_freelist) == NULL) { 1745 return ADW_BUSY; 1746 } 1747 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1748 ASC_GET_CARRP(new_carrp->next_ba)); 1749 sc->carr_pending_cnt++; 1750 1751 /* 1752 * Set the carrier to be a stopper by setting 'next_ba' 1753 * to the stopper value. The current stopper will be changed 1754 * below to point to the new stopper. 1755 */ 1756 new_carrp->next_ba = ASC_CQ_STOPPER; 1757 1758 req_size = sizeof(ADW_SCSI_REQ_Q); 1759 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1760 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1761 1762 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1763 scsiq->scsiq_rptr = req_paddr; 1764 1765 /* 1766 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1767 * order during initialization. 1768 */ 1769 scsiq->carr_ba = sc->icq_sp->carr_ba; 1770 scsiq->carr_va = sc->icq_sp->carr_ba; 1771 1772 /* 1773 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1774 * the microcode. The newly allocated stopper will become the new 1775 * stopper. 1776 */ 1777 sc->icq_sp->areq_ba = req_paddr; 1778 1779 /* 1780 * Set the 'next_ba' pointer for the old stopper to be the 1781 * physical address of the new stopper. The RISC can only 1782 * follow physical addresses. 1783 */ 1784 sc->icq_sp->next_ba = new_carrp->carr_ba; 1785 1786 #if ADW_DEBUG 1787 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1788 sc->icq_sp->carr_id, 1789 sc->icq_sp->carr_ba, 1790 sc->icq_sp->areq_ba, 1791 sc->icq_sp->next_ba); 1792 #endif 1793 /* 1794 * Set the host adapter stopper pointer to point to the new carrier. 1795 */ 1796 sc->icq_sp = new_carrp; 1797 1798 if (sc->chip_type == ADW_CHIP_ASC3550 || 1799 sc->chip_type == ADW_CHIP_ASC38C0800) { 1800 /* 1801 * Tickle the RISC to tell it to read its Command Queue Head 1802 * pointer. 1803 */ 1804 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); 1805 if (sc->chip_type == ADW_CHIP_ASC3550) { 1806 /* 1807 * Clear the tickle value. In the ASC-3550 the RISC flag 1808 * command 'clr_tickle_a' does not work unless the host 1809 * value is cleared. 1810 */ 1811 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1812 ADV_TICKLE_NOP); 1813 } 1814 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1815 /* 1816 * Notify the RISC a carrier is ready by writing the physical 1817 * address of the new carrier stopper to the COMMA register. 1818 */ 1819 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1820 new_carrp->carr_ba); 1821 } 1822 1823 /* 1824 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1825 */ 1826 1827 return ADW_SUCCESS; 1828 } 1829 1830 1831 void 1832 AdwResetChip(iot, ioh) 1833 bus_space_tag_t iot; 1834 bus_space_handle_t ioh; 1835 { 1836 1837 /* 1838 * Reset Chip. 1839 */ 1840 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1841 ADW_CTRL_REG_CMD_RESET); 1842 AdwSleepMilliSecond(100); 1843 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1844 ADW_CTRL_REG_CMD_WR_IO_REG); 1845 } 1846 1847 1848 /* 1849 * Reset SCSI Bus and purge all outstanding requests. 1850 * 1851 * Return Value: 1852 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1853 * ADW_FALSE(0) - Microcode command failed. 1854 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1855 * may be hung which requires driver recovery. 1856 */ 1857 int 1858 AdwResetCCB(sc) 1859 ADW_SOFTC *sc; 1860 { 1861 int status; 1862 1863 /* 1864 * Send the SCSI Bus Reset idle start idle command which asserts 1865 * the SCSI Bus Reset signal. 1866 */ 1867 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1868 if (status != ADW_TRUE) { 1869 return status; 1870 } 1871 1872 /* 1873 * Delay for the specified SCSI Bus Reset hold time. 1874 * 1875 * The hold time delay is done on the host because the RISC has no 1876 * microsecond accurate timer. 1877 */ 1878 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1879 1880 /* 1881 * Send the SCSI Bus Reset end idle command which de-asserts 1882 * the SCSI Bus Reset signal and purges any pending requests. 1883 */ 1884 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1885 if (status != ADW_TRUE) { 1886 return status; 1887 } 1888 1889 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1890 1891 return status; 1892 } 1893 1894 1895 /* 1896 * Reset chip and SCSI Bus. 1897 * 1898 * Return Value: 1899 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1900 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1901 */ 1902 int 1903 AdwResetSCSIBus(sc) 1904 ADW_SOFTC *sc; 1905 { 1906 bus_space_tag_t iot = sc->sc_iot; 1907 bus_space_handle_t ioh = sc->sc_ioh; 1908 int status; 1909 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1910 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1911 u_int16_t bios_sig; 1912 1913 1914 /* 1915 * Save current per TID negotiated values. 1916 */ 1917 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1918 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1919 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1920 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1921 } 1922 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1923 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1924 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1925 max_cmd[tid]); 1926 } 1927 1928 /* 1929 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1930 * by clearing the BIOS signature word. 1931 * The initialization functions assumes a SCSI Bus Reset is not 1932 * needed if the BIOS signature word is present. 1933 */ 1934 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1935 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1936 1937 /* 1938 * Stop chip and reset it. 1939 */ 1940 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1941 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1942 ADW_CTRL_REG_CMD_RESET); 1943 AdwSleepMilliSecond(100); 1944 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1945 ADW_CTRL_REG_CMD_WR_IO_REG); 1946 1947 /* 1948 * Reset Adv Library error code, if any, and try 1949 * re-initializing the chip. 1950 * Then translate initialization return value to status value. 1951 */ 1952 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1953 1954 /* 1955 * Restore the BIOS signature word. 1956 */ 1957 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1958 1959 /* 1960 * Restore per TID negotiated values. 1961 */ 1962 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1963 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1964 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1965 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1966 } 1967 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1968 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1969 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1970 max_cmd[tid]); 1971 } 1972 1973 return status; 1974 } 1975 1976 1977 /* 1978 * Adv Library Interrupt Service Routine 1979 * 1980 * This function is called by a driver's interrupt service routine. 1981 * The function disables and re-enables interrupts. 1982 * 1983 * When a microcode idle command is completed, the ADV_DVC_VAR 1984 * 'idle_cmd_done' field is set to ADW_TRUE. 1985 * 1986 * Note: AdwISR() can be called when interrupts are disabled or even 1987 * when there is no hardware interrupt condition present. It will 1988 * always check for completed idle commands and microcode requests. 1989 * This is an important feature that shouldn't be changed because it 1990 * allows commands to be completed from polling mode loops. 1991 * 1992 * Return: 1993 * ADW_TRUE(1) - interrupt was pending 1994 * ADW_FALSE(0) - no interrupt was pending 1995 */ 1996 int 1997 AdwISR(sc) 1998 ADW_SOFTC *sc; 1999 { 2000 bus_space_tag_t iot = sc->sc_iot; 2001 bus_space_handle_t ioh = sc->sc_ioh; 2002 u_int8_t int_stat; 2003 u_int16_t target_bit; 2004 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 2005 u_int32_t irq_next_pa; 2006 ADW_SCSI_REQ_Q *scsiq; 2007 ADW_CCB *ccb; 2008 int s; 2009 2010 2011 s = splbio(); 2012 2013 /* Reading the register clears the interrupt. */ 2014 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 2015 2016 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 2017 ADW_INTR_STATUS_INTRC)) == 0) { 2018 splx(s); 2019 return ADW_FALSE; 2020 } 2021 2022 /* 2023 * Notify the driver of an asynchronous microcode condition by 2024 * calling the ADV_DVC_VAR.async_callback function. The function 2025 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2026 */ 2027 if (int_stat & ADW_INTR_STATUS_INTRB) { 2028 u_int8_t intrb_code; 2029 2030 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2031 2032 if (sc->chip_type == ADW_CHIP_ASC3550 || 2033 sc->chip_type == ADW_CHIP_ASC38C0800) { 2034 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2035 sc->carr_pending_cnt != 0) { 2036 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2037 IOPB_TICKLE, ADV_TICKLE_A); 2038 if (sc->chip_type == ADW_CHIP_ASC3550) { 2039 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2040 IOPB_TICKLE, ADV_TICKLE_NOP); 2041 } 2042 } 2043 } 2044 2045 if (sc->async_callback != 0) { 2046 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2047 } 2048 } 2049 2050 /* 2051 * Check if the IRQ stopper carrier contains a completed request. 2052 */ 2053 while (((irq_next_pa = sc->irq_sp->next_ba) & ASC_RQ_DONE) != 0) 2054 { 2055 #if ADW_DEBUG 2056 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2057 sc->irq_sp->carr_id, 2058 sc->irq_sp->carr_ba, 2059 sc->irq_sp->areq_ba, 2060 sc->irq_sp->next_ba); 2061 #endif 2062 /* 2063 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2064 * structure. 2065 * The RISC will have set 'areq_ba' to a virtual address. 2066 * 2067 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2068 * field to the carrier ADV_CARR_T.areq_ba field. 2069 * The conversion below complements the conversion of 2070 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2071 */ 2072 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2073 scsiq = &ccb->scsiq; 2074 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2075 2076 /* 2077 * Request finished with good status and the queue was not 2078 * DMAed to host memory by the firmware. Set all status fields 2079 * to indicate good status. 2080 */ 2081 if ((irq_next_pa & ASC_RQ_GOOD) != 0) { 2082 scsiq->done_status = QD_NO_ERROR; 2083 scsiq->host_status = scsiq->scsi_status = 0; 2084 scsiq->data_cnt = 0L; 2085 } 2086 2087 /* 2088 * Advance the stopper pointer to the next carrier 2089 * ignoring the lower four bits. Free the previous 2090 * stopper carrier. 2091 */ 2092 free_carrp = sc->irq_sp; 2093 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2094 2095 free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL 2096 : sc->carr_freelist->carr_ba; 2097 sc->carr_freelist = free_carrp; 2098 sc->carr_pending_cnt--; 2099 2100 2101 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2102 2103 /* 2104 * Clear request microcode control flag. 2105 */ 2106 scsiq->cntl = 0; 2107 2108 /* 2109 * Check Condition handling 2110 */ 2111 /* 2112 * If the command that completed was a SCSI INQUIRY and 2113 * LUN 0 was sent the command, then process the INQUIRY 2114 * command information for the device. 2115 */ 2116 if (scsiq->done_status == QD_NO_ERROR && 2117 scsiq->cdb[0] == INQUIRY && 2118 scsiq->target_lun == 0) { 2119 AdwInquiryHandling(sc, scsiq); 2120 } 2121 2122 /* 2123 * Notify the driver of the completed request by passing 2124 * the ADW_SCSI_REQ_Q pointer to its callback function. 2125 */ 2126 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2127 /* 2128 * Note: After the driver callback function is called, 'scsiq' 2129 * can no longer be referenced. 2130 * 2131 * Fall through and continue processing other completed 2132 * requests... 2133 */ 2134 } 2135 2136 splx(s); 2137 2138 return ADW_TRUE; 2139 } 2140 2141 2142 /* 2143 * Send an idle command to the chip and wait for completion. 2144 * 2145 * Command completion is polled for once per microsecond. 2146 * 2147 * The function can be called from anywhere including an interrupt handler. 2148 * But the function is not re-entrant, so it uses the splbio/splx() 2149 * functions to prevent reentrancy. 2150 * 2151 * Return Values: 2152 * ADW_TRUE - command completed successfully 2153 * ADW_FALSE - command failed 2154 * ADW_ERROR - command timed out 2155 */ 2156 int 2157 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 2158 ADW_SOFTC *sc; 2159 u_int16_t idle_cmd; 2160 u_int32_t idle_cmd_parameter; 2161 { 2162 bus_space_tag_t iot = sc->sc_iot; 2163 bus_space_handle_t ioh = sc->sc_ioh; 2164 u_int16_t result; 2165 u_int32_t i, j, s; 2166 2167 s = splbio(); 2168 2169 /* 2170 * Clear the idle command status which is set by the microcode 2171 * to a non-zero value to indicate when the command is completed. 2172 */ 2173 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2174 2175 /* 2176 * Write the idle command value after the idle command parameter 2177 * has been written to avoid a race condition. If the order is not 2178 * followed, the microcode may process the idle command before the 2179 * parameters have been written to LRAM. 2180 */ 2181 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2182 idle_cmd_parameter); 2183 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2184 2185 /* 2186 * Tickle the RISC to tell it to process the idle command. 2187 */ 2188 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_B); 2189 if (sc->chip_type == ADW_CHIP_ASC3550) { 2190 /* 2191 * Clear the tickle value. In the ASC-3550 the RISC flag 2192 * command 'clr_tickle_b' does not work unless the host 2193 * value is cleared. 2194 */ 2195 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 2196 } 2197 2198 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2199 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2200 /* Poll once each microsecond for command completion. */ 2201 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2202 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2203 result); 2204 if (result != 0) { 2205 splx(s); 2206 return result; 2207 } 2208 AdwDelayMicroSecond(1); 2209 } 2210 } 2211 2212 splx(s); 2213 return ADW_ERROR; 2214 } 2215 2216 2217 /* 2218 * Inquiry Information Byte 7 Handling 2219 * 2220 * Handle SCSI Inquiry Command information for a device by setting 2221 * microcode operating variables that affect WDTR, SDTR, and Tag 2222 * Queuing. 2223 */ 2224 static void 2225 AdwInquiryHandling(sc, scsiq) 2226 ADW_SOFTC *sc; 2227 ADW_SCSI_REQ_Q *scsiq; 2228 { 2229 #ifndef FAILSAFE 2230 bus_space_tag_t iot = sc->sc_iot; 2231 bus_space_handle_t ioh = sc->sc_ioh; 2232 u_int8_t tid; 2233 struct scsipi_inquiry_data *inq; 2234 u_int16_t tidmask; 2235 u_int16_t cfg_word; 2236 2237 2238 /* 2239 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2240 * to be available. 2241 * 2242 * If less than 8 bytes of INQUIRY information were requested or less 2243 * than 8 bytes were transferred, then return. cdb[4] is the request 2244 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2245 * microcode to the transfer residual count. 2246 */ 2247 2248 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2249 return; 2250 } 2251 2252 tid = scsiq->target_id; 2253 2254 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2255 2256 /* 2257 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2258 */ 2259 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2260 ((inq->version & SID_ANSII) < 2)) { 2261 return; 2262 } else { 2263 /* 2264 * INQUIRY Byte 7 Handling 2265 * 2266 * Use a device's INQUIRY byte 7 to determine whether it 2267 * supports WDTR, SDTR, and Tag Queuing. If the feature 2268 * is enabled in the EEPROM and the device supports the 2269 * feature, then enable it in the microcode. 2270 */ 2271 2272 tidmask = ADW_TID_TO_TIDMASK(tid); 2273 2274 /* 2275 * Wide Transfers 2276 * 2277 * If the EEPROM enabled WDTR for the device and the device 2278 * supports wide bus (16 bit) transfers, then turn on the 2279 * device's 'wdtr_able' bit and write the new value to the 2280 * microcode. 2281 */ 2282 #ifdef SCSI_ADW_WDTR_DISABLE 2283 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2284 #endif /* SCSI_ADW_WDTR_DISABLE */ 2285 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2286 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2287 cfg_word); 2288 if ((cfg_word & tidmask) == 0) { 2289 cfg_word |= tidmask; 2290 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2291 cfg_word); 2292 2293 /* 2294 * Clear the microcode "SDTR negotiation" and 2295 * "WDTR negotiation" done indicators for the 2296 * target to cause it to negotiate with the new 2297 * setting set above. 2298 * WDTR when accepted causes the target to enter 2299 * asynchronous mode, so SDTR must be negotiated 2300 */ 2301 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2302 cfg_word); 2303 cfg_word &= ~tidmask; 2304 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2305 cfg_word); 2306 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2307 cfg_word); 2308 cfg_word &= ~tidmask; 2309 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2310 cfg_word); 2311 } 2312 } 2313 2314 /* 2315 * Synchronous Transfers 2316 * 2317 * If the EEPROM enabled SDTR for the device and the device 2318 * supports synchronous transfers, then turn on the device's 2319 * 'sdtr_able' bit. Write the new value to the microcode. 2320 */ 2321 #ifdef SCSI_ADW_SDTR_DISABLE 2322 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2323 #endif /* SCSI_ADW_SDTR_DISABLE */ 2324 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2325 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2326 if ((cfg_word & tidmask) == 0) { 2327 cfg_word |= tidmask; 2328 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2329 cfg_word); 2330 2331 /* 2332 * Clear the microcode "SDTR negotiation" 2333 * done indicator for the target to cause it 2334 * to negotiate with the new setting set above. 2335 */ 2336 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2337 cfg_word); 2338 cfg_word &= ~tidmask; 2339 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2340 cfg_word); 2341 } 2342 } 2343 /* 2344 * If the Inquiry data included enough space for the SPI-3 2345 * Clocking field, then check if DT mode is supported. 2346 */ 2347 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2348 (scsiq->cdb[4] >= 57 || 2349 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2350 /* 2351 * PPR (Parallel Protocol Request) Capable 2352 * 2353 * If the device supports DT mode, then it must be 2354 * PPR capable. 2355 * The PPR message will be used in place of the SDTR 2356 * and WDTR messages to negotiate synchronous speed 2357 * and offset, transfer width, and protocol options. 2358 */ 2359 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2360 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2361 sc->ppr_able); 2362 sc->ppr_able |= tidmask; 2363 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2364 sc->ppr_able); 2365 } 2366 } 2367 2368 /* 2369 * If the EEPROM enabled Tag Queuing for the device and the 2370 * device supports Tag Queueing, then turn on the device's 2371 * 'tagqng_enable' bit in the microcode and set the microcode 2372 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2373 * value. 2374 * 2375 * Tag Queuing is disabled for the BIOS which runs in polled 2376 * mode and would see no benefit from Tag Queuing. Also by 2377 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2378 * bugs will at least work with the BIOS. 2379 */ 2380 #ifdef SCSI_ADW_TAGQ_DISABLE 2381 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2382 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2383 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2384 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2385 cfg_word); 2386 cfg_word |= tidmask; 2387 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2388 cfg_word); 2389 2390 ADW_WRITE_BYTE_LRAM(iot, ioh, 2391 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2392 sc->max_dvc_qng); 2393 } 2394 } 2395 #endif /* FAILSAFE */ 2396 } 2397 2398 2399 static void 2400 AdwSleepMilliSecond(n) 2401 u_int32_t n; 2402 { 2403 2404 DELAY(n * 1000); 2405 } 2406 2407 2408 static void 2409 AdwDelayMicroSecond(n) 2410 u_int32_t n; 2411 { 2412 2413 DELAY(n); 2414 } 2415 2416
Indexes created Mon Sep 22 05:09:51 GMT 2025