adwlib.c revision 1.22
1 /* $NetBSD: adwlib.c,v 1.22 2001/08/29 17:25:03 briggs Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <uvm/uvm_extern.h> 72 73 #include <dev/ic/adwlib.h> 74 #include <dev/ic/adwmcode.h> 75 #include <dev/ic/adw.h> 76 77 78 /* Static Functions */ 79 80 int AdwRamSelfTest __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 81 int AdwLoadMCode __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 82 u_int8_t)); 83 int AdwASC3550Cabling __P((bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *)); 84 int AdwASC38C0800Cabling __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_DVC_CFG *)); 86 int AdwASC38C1600Cabling __P((bus_space_tag_t, bus_space_handle_t, 87 ADW_DVC_CFG *)); 88 89 static u_int16_t AdwGetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 90 ADW_EEPROM *)); 91 static void AdwSetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 92 ADW_EEPROM *)); 93 static u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 94 static void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 95 96 static void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 97 98 static void AdwSleepMilliSecond __P((u_int32_t)); 99 static void AdwDelayMicroSecond __P((u_int32_t)); 100 101 102 /* 103 * EEPROM Configuration. 104 * 105 * All drivers should use this structure to set the default EEPROM 106 * configuration. The BIOS now uses this structure when it is built. 107 * Additional structure information can be found in adwlib.h where 108 * the structure is defined. 109 */ 110 const static ADW_EEPROM adw_3550_Default_EEPROM = { 111 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 112 0x0000, /* 01 cfg_msw */ 113 0xFFFF, /* 02 disc_enable */ 114 0xFFFF, /* 03 wdtr_able */ 115 { 0xFFFF }, /* 04 sdtr_able */ 116 0xFFFF, /* 05 start_motor */ 117 0xFFFF, /* 06 tagqng_able */ 118 0xFFFF, /* 07 bios_scan */ 119 0, /* 08 scam_tolerant */ 120 7, /* 09 adapter_scsi_id */ 121 0, /* bios_boot_delay */ 122 3, /* 10 scsi_reset_delay */ 123 0, /* bios_id_lun */ 124 0, /* 11 termination */ 125 0, /* reserved1 */ 126 0xFFE7, /* 12 bios_ctrl */ 127 { 0xFFFF }, /* 13 ultra_able */ 128 { 0 }, /* 14 reserved2 */ 129 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 130 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 131 0, /* 16 dvc_cntl */ 132 { 0 }, /* 17 bug_fix */ 133 { 0,0,0 }, /* 18-20 serial_number[3] */ 134 0, /* 21 check_sum */ 135 { /* 22-29 oem_name[16] */ 136 0,0,0,0,0,0,0,0, 137 0,0,0,0,0,0,0,0 138 }, 139 0, /* 30 dvc_err_code */ 140 0, /* 31 adv_err_code */ 141 0, /* 32 adv_err_addr */ 142 0, /* 33 saved_dvc_err_code */ 143 0, /* 34 saved_adv_err_code */ 144 0 /* 35 saved_adv_err_addr */ 145 }; 146 147 const static ADW_EEPROM adw_38C0800_Default_EEPROM = { 148 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 149 0x0000, /* 01 cfg_msw */ 150 0xFFFF, /* 02 disc_enable */ 151 0xFFFF, /* 03 wdtr_able */ 152 { 0x4444 }, /* 04 sdtr_speed1 */ 153 0xFFFF, /* 05 start_motor */ 154 0xFFFF, /* 06 tagqng_able */ 155 0xFFFF, /* 07 bios_scan */ 156 0, /* 08 scam_tolerant */ 157 7, /* 09 adapter_scsi_id */ 158 0, /* bios_boot_delay */ 159 3, /* 10 scsi_reset_delay */ 160 0, /* bios_id_lun */ 161 0, /* 11 termination_se */ 162 0, /* termination_lvd */ 163 0xFFE7, /* 12 bios_ctrl */ 164 { 0x4444 }, /* 13 sdtr_speed2 */ 165 { 0x4444 }, /* 14 sdtr_speed3 */ 166 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 167 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 168 0, /* 16 dvc_cntl */ 169 { 0x4444 }, /* 17 sdtr_speed4 */ 170 { 0,0,0 }, /* 18-20 serial_number[3] */ 171 0, /* 21 check_sum */ 172 { /* 22-29 oem_name[16] */ 173 0,0,0,0,0,0,0,0, 174 0,0,0,0,0,0,0,0 175 }, 176 0, /* 30 dvc_err_code */ 177 0, /* 31 adv_err_code */ 178 0, /* 32 adv_err_addr */ 179 0, /* 33 saved_dvc_err_code */ 180 0, /* 34 saved_adv_err_code */ 181 0, /* 35 saved_adv_err_addr */ 182 { /* 36-55 reserved1[16] */ 183 0,0,0,0,0,0,0,0,0,0, 184 0,0,0,0,0,0,0,0,0,0 185 }, 186 0, /* 56 cisptr_lsw */ 187 0, /* 57 cisprt_msw */ 188 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 189 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 190 { 0,0,0,0 } /* 60-63 reserved2[4] */ 191 }; 192 193 const static ADW_EEPROM adw_38C1600_Default_EEPROM = { 194 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 195 0x0000, /* 01 cfg_msw */ 196 0xFFFF, /* 02 disc_enable */ 197 0xFFFF, /* 03 wdtr_able */ 198 { 0x5555 }, /* 04 sdtr_speed1 */ 199 0xFFFF, /* 05 start_motor */ 200 0xFFFF, /* 06 tagqng_able */ 201 0xFFFF, /* 07 bios_scan */ 202 0, /* 08 scam_tolerant */ 203 7, /* 09 adapter_scsi_id */ 204 0, /* bios_boot_delay */ 205 3, /* 10 scsi_reset_delay */ 206 0, /* bios_id_lun */ 207 0, /* 11 termination_se */ 208 0, /* termination_lvd */ 209 0xFFE7, /* 12 bios_ctrl */ 210 { 0x5555 }, /* 13 sdtr_speed2 */ 211 { 0x5555 }, /* 14 sdtr_speed3 */ 212 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 213 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 214 0, /* 16 dvc_cntl */ 215 { 0x5555 }, /* 17 sdtr_speed4 */ 216 { 0,0,0 }, /* 18-20 serial_number[3] */ 217 0, /* 21 check_sum */ 218 { /* 22-29 oem_name[16] */ 219 0,0,0,0,0,0,0,0, 220 0,0,0,0,0,0,0,0 221 }, 222 0, /* 30 dvc_err_code */ 223 0, /* 31 adv_err_code */ 224 0, /* 32 adv_err_addr */ 225 0, /* 33 saved_dvc_err_code */ 226 0, /* 34 saved_adv_err_code */ 227 0, /* 35 saved_adv_err_addr */ 228 { /* 36-55 reserved1[16] */ 229 0,0,0,0,0,0,0,0,0,0, 230 0,0,0,0,0,0,0,0,0,0 231 }, 232 0, /* 56 cisptr_lsw */ 233 0, /* 57 cisprt_msw */ 234 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 235 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 236 { 0,0,0,0 } /* 60-63 reserved2[4] */ 237 }; 238 239 240 /* 241 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 242 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 243 * all of this is done. 244 * 245 * For a non-fatal error return a warning code. If there are no warnings 246 * then 0 is returned. 247 * 248 * Note: Chip is stopped on entry. 249 */ 250 int 251 AdwInitFromEEPROM(sc) 252 ADW_SOFTC *sc; 253 { 254 bus_space_tag_t iot = sc->sc_iot; 255 bus_space_handle_t ioh = sc->sc_ioh; 256 ADW_EEPROM eep_config; 257 u_int16_t warn_code; 258 u_int16_t sdtr_speed = 0; 259 u_int8_t tid, termination; 260 int i, j; 261 262 263 warn_code = 0; 264 265 /* 266 * Read the board's EEPROM configuration. 267 * 268 * Set default values if a bad checksum is found. 269 * 270 * XXX - Don't handle big-endian access to EEPROM yet. 271 */ 272 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 273 warn_code |= ADW_WARN_EEPROM_CHKSUM; 274 275 /* 276 * Set EEPROM default values. 277 */ 278 switch(sc->chip_type) { 279 case ADW_CHIP_ASC3550: 280 eep_config = adw_3550_Default_EEPROM; 281 break; 282 case ADW_CHIP_ASC38C0800: 283 eep_config = adw_38C0800_Default_EEPROM; 284 break; 285 case ADW_CHIP_ASC38C1600: 286 eep_config = adw_38C1600_Default_EEPROM; 287 288 #if 0 289 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 290 #endif 291 if (sc->cfg.pci_slot_info != 0) { 292 u_int8_t lsw_msb; 293 294 lsw_msb = eep_config.cfg_lsw >> 8; 295 /* 296 * Set Function 1 EEPROM Word 0 MSB 297 * 298 * Clear the BIOS_ENABLE (bit 14) and 299 * INTAB (bit 11) EEPROM bits. 300 * 301 * Disable Bit 14 (BIOS_ENABLE) to fix 302 * SPARC Ultra 60 and old Mac system booting 303 * problem. The Expansion ROM must 304 * be disabled in Function 1 for these systems. 305 */ 306 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 307 ADW_EEPROM_INTAB) >> 8) & 0xFF); 308 /* 309 * Set the INTAB (bit 11) if the GPIO 0 input 310 * indicates the Function 1 interrupt line is 311 * wired to INTA. 312 * 313 * Set/Clear Bit 11 (INTAB) from 314 * the GPIO bit 0 input: 315 * 1 - Function 1 intr line wired to INT A. 316 * 0 - Function 1 intr line wired to INT B. 317 * 318 * Note: Adapter boards always have Function 0 319 * wired to INTA. 320 * Put all 5 GPIO bits in input mode and then 321 * read their input values. 322 */ 323 ADW_WRITE_BYTE_REGISTER(iot, ioh, 324 IOPB_GPIO_CNTL, 0); 325 if (ADW_READ_BYTE_REGISTER(iot, ioh, 326 IOPB_GPIO_DATA) & 0x01) { 327 /* 328 * Function 1 interrupt wired to INTA; 329 * Set EEPROM bit. 330 */ 331 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 332 & 0xFF; 333 } 334 eep_config.cfg_lsw &= 0x00FF; 335 eep_config.cfg_lsw |= lsw_msb << 8; 336 } 337 break; 338 } 339 340 /* 341 * Assume the 6 byte board serial number that was read 342 * from EEPROM is correct even if the EEPROM checksum 343 * failed. 344 */ 345 for (i=2, j=1; i>=0; i--, j++) { 346 eep_config.serial_number[i] = 347 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 348 } 349 350 AdwSetEEPROMConfig(iot, ioh, &eep_config); 351 } 352 /* 353 * Set sc and sc->cfg variables from the EEPROM configuration 354 * that was read. 355 * 356 * This is the mapping of EEPROM fields to Adw Library fields. 357 */ 358 sc->wdtr_able = eep_config.wdtr_able; 359 if (sc->chip_type == ADW_CHIP_ASC3550) { 360 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 361 sc->ultra_able = eep_config.sdtr2.ultra_able; 362 } else { 363 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 364 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 365 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 366 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 367 } 368 sc->ppr_able = 0; 369 sc->tagqng_able = eep_config.tagqng_able; 370 sc->cfg.disc_enable = eep_config.disc_enable; 371 sc->max_host_qng = eep_config.max_host_qng; 372 sc->max_dvc_qng = eep_config.max_dvc_qng; 373 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 374 sc->start_motor = eep_config.start_motor; 375 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 376 sc->bios_ctrl = eep_config.bios_ctrl; 377 sc->no_scam = eep_config.scam_tolerant; 378 sc->cfg.serial1 = eep_config.serial_number[0]; 379 sc->cfg.serial2 = eep_config.serial_number[1]; 380 sc->cfg.serial3 = eep_config.serial_number[2]; 381 382 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 383 sc->chip_type == ADW_CHIP_ASC38C1600) { 384 sc->sdtr_able = 0; 385 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 386 if (tid == 0) { 387 sdtr_speed = sc->sdtr_speed1; 388 } else if (tid == 4) { 389 sdtr_speed = sc->sdtr_speed2; 390 } else if (tid == 8) { 391 sdtr_speed = sc->sdtr_speed3; 392 } else if (tid == 12) { 393 sdtr_speed = sc->sdtr_speed4; 394 } 395 if (sdtr_speed & ADW_MAX_TID) { 396 sc->sdtr_able |= (1 << tid); 397 } 398 sdtr_speed >>= 4; 399 } 400 } 401 402 /* 403 * Set the host maximum queuing (max. 253, min. 16) and the per device 404 * maximum queuing (max. 63, min. 4). 405 */ 406 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 407 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 408 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 409 { 410 /* If the value is zero, assume it is uninitialized. */ 411 if (eep_config.max_host_qng == 0) { 412 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 413 } else { 414 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 415 } 416 } 417 418 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 419 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 420 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 421 /* If the value is zero, assume it is uninitialized. */ 422 if (eep_config.max_dvc_qng == 0) { 423 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 424 } else { 425 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 426 } 427 } 428 429 /* 430 * If 'max_dvc_qng' is greater than 'max_host_qng', then 431 * set 'max_dvc_qng' to 'max_host_qng'. 432 */ 433 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 434 eep_config.max_dvc_qng = eep_config.max_host_qng; 435 } 436 437 /* 438 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 439 * values based on possibly adjusted EEPROM values. 440 */ 441 sc->max_host_qng = eep_config.max_host_qng; 442 sc->max_dvc_qng = eep_config.max_dvc_qng; 443 444 445 /* 446 * If the EEPROM 'termination' field is set to automatic (0), then set 447 * the ADV_DVC_CFG 'termination' field to automatic also. 448 * 449 * If the termination is specified with a non-zero 'termination' 450 * value check that a legal value is set and set the ADV_DVC_CFG 451 * 'termination' field appropriately. 452 */ 453 454 switch(sc->chip_type) { 455 case ADW_CHIP_ASC3550: 456 sc->cfg.termination = 0; /* auto termination */ 457 switch(eep_config.termination_se) { 458 case 3: 459 /* Enable manual control with low on / high on. */ 460 sc->cfg.termination |= ADW_TERM_CTL_L; 461 case 2: 462 /* Enable manual control with low off / high on. */ 463 sc->cfg.termination |= ADW_TERM_CTL_H; 464 case 1: 465 /* Enable manual control with low off / high off. */ 466 sc->cfg.termination |= ADW_TERM_CTL_SEL; 467 case 0: 468 break; 469 default: 470 warn_code |= ADW_WARN_EEPROM_TERMINATION; 471 } 472 break; 473 474 case ADW_CHIP_ASC38C0800: 475 case ADW_CHIP_ASC38C1600: 476 switch(eep_config.termination_se) { 477 case 0: 478 /* auto termination for SE */ 479 termination = 0; 480 break; 481 case 1: 482 /* Enable manual control with low off / high off. */ 483 termination = 0; 484 break; 485 case 2: 486 /* Enable manual control with low off / high on. */ 487 termination = ADW_TERM_SE_HI; 488 break; 489 case 3: 490 /* Enable manual control with low on / high on. */ 491 termination = ADW_TERM_SE; 492 break; 493 default: 494 /* 495 * The EEPROM 'termination_se' field contains a 496 * bad value. Use automatic termination instead. 497 */ 498 termination = 0; 499 warn_code |= ADW_WARN_EEPROM_TERMINATION; 500 } 501 502 switch(eep_config.termination_lvd) { 503 case 0: 504 /* auto termination for LVD */ 505 sc->cfg.termination = termination; 506 break; 507 case 1: 508 /* Enable manual control with low off / high off. */ 509 sc->cfg.termination = termination; 510 break; 511 case 2: 512 /* Enable manual control with low off / high on. */ 513 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 514 break; 515 case 3: 516 /* Enable manual control with low on / high on. */ 517 sc->cfg.termination = termination | ADW_TERM_LVD; 518 break; 519 default: 520 /* 521 * The EEPROM 'termination_lvd' field contains a 522 * bad value. Use automatic termination instead. 523 */ 524 sc->cfg.termination = termination; 525 warn_code |= ADW_WARN_EEPROM_TERMINATION; 526 } 527 break; 528 } 529 530 return warn_code; 531 } 532 533 534 /* 535 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 536 * 537 * On failure return the error code. 538 */ 539 int 540 AdwInitDriver(sc) 541 ADW_SOFTC *sc; 542 { 543 bus_space_tag_t iot = sc->sc_iot; 544 bus_space_handle_t ioh = sc->sc_ioh; 545 u_int16_t error_code; 546 int word; 547 int i; 548 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 549 0x40-0x8F. */ 550 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 551 u_int8_t max_cmd[ADW_MAX_TID + 1]; 552 u_int8_t tid; 553 554 555 error_code = 0; 556 557 /* 558 * Save the RISC memory BIOS region before writing the microcode. 559 * The BIOS may already be loaded and using its RISC LRAM region 560 * so its region must be saved and restored. 561 * 562 * Note: This code makes the assumption, which is currently true, 563 * that a chip reset does not clear RISC LRAM. 564 */ 565 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 566 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 567 } 568 569 /* 570 * Save current per TID negotiated values. 571 */ 572 switch (sc->chip_type) { 573 case ADW_CHIP_ASC3550: 574 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 575 576 u_int16_t bios_version, major, minor; 577 578 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 579 ADW_MC_BIOSMEM) / 2]; 580 major = (bios_version >> 12) & 0xF; 581 minor = (bios_version >> 8) & 0xF; 582 if (major < 3 || (major == 3 && minor == 1)) { 583 /* 584 * BIOS 3.1 and earlier location of 585 * 'wdtr_able' variable. 586 */ 587 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 588 } else { 589 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 590 wdtr_able); 591 } 592 } 593 break; 594 595 case ADW_CHIP_ASC38C1600: 596 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 597 /* FALLTHROUGH */ 598 case ADW_CHIP_ASC38C0800: 599 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 600 break; 601 } 602 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 603 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 604 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 605 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 606 max_cmd[tid]); 607 } 608 609 /* 610 * Perform a RAM Built-In Self Test 611 */ 612 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 613 return error_code; 614 } 615 616 /* 617 * Load the Microcode 618 */ 619 ; 620 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 621 return error_code; 622 } 623 624 /* 625 * Read microcode version and date. 626 */ 627 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 628 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 629 630 /* 631 * If the PCI Configuration Command Register "Parity Error Response 632 * Control" Bit was clear (0), then set the microcode variable 633 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 634 * to ignore DMA parity errors. 635 */ 636 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 637 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 638 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 639 word | CONTROL_FLAG_IGNORE_PERR); 640 } 641 642 switch (sc->chip_type) { 643 case ADW_CHIP_ASC3550: 644 /* 645 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 646 * FIFO threshold of 128 bytes. 647 * This register is only accessible to the host. 648 */ 649 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 650 START_CTL_EMFU | READ_CMD_MRM); 651 break; 652 653 case ADW_CHIP_ASC38C0800: 654 /* 655 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 656 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 657 * cable detection and then we are able to read C_DET[3:0]. 658 * 659 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 660 * Microcode Default Value' section below. 661 */ 662 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 663 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 664 | ADW_DIS_TERM_DRV); 665 666 /* 667 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 668 * START_CTL_TH [3:2] bits for the default FIFO threshold. 669 * 670 * Note: ASC-38C0800 FIFO threshold has been changed to 671 * 256 bytes. 672 * 673 * For DMA Errata #4 set the BC_THRESH_ENB bit. 674 */ 675 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 676 BC_THRESH_ENB | FIFO_THRESH_80B 677 | START_CTL_TH | READ_CMD_MRM); 678 break; 679 680 case ADW_CHIP_ASC38C1600: 681 /* 682 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 683 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 684 * cable detection and then we are able to read C_DET[3:0]. 685 * 686 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 687 * Microcode Default Value' section below. 688 */ 689 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 690 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 691 | ADW_DIS_TERM_DRV); 692 693 /* 694 * If the BIOS control flag AIPP (Asynchronous Information 695 * Phase Protection) disable bit is not set, then set the 696 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 697 * enable AIPP checking and encoding. 698 */ 699 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 700 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 701 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 702 word | CONTROL_FLAG_ENABLE_AIPP); 703 } 704 705 /* 706 * For ASC-38C1600 use DMA_CFG0 default values: 707 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 708 */ 709 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 710 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 711 break; 712 } 713 714 /* 715 * Microcode operating variables for WDTR, SDTR, and command tag 716 * queuing will be set in AdvInquiryHandling() based on what a 717 * device reports it is capable of in Inquiry byte 7. 718 * 719 * If SCSI Bus Resets have been disabled, then directly set 720 * SDTR and WDTR from the EEPROM configuration. This will allow 721 * the BIOS and warm boot to work without a SCSI bus hang on 722 * the Inquiry caused by host and target mismatched DTR values. 723 * Without the SCSI Bus Reset, before an Inquiry a device can't 724 * be assumed to be in Asynchronous, Narrow mode. 725 */ 726 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 727 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 728 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 729 } 730 731 /* 732 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 733 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 734 * bitmask. These values determine the maximum SDTR speed negotiated 735 * with a device. 736 * 737 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 738 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 739 * without determining here whether the device supports SDTR. 740 */ 741 switch (sc->chip_type) { 742 case ADW_CHIP_ASC3550: 743 word = 0; 744 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 745 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 746 /* Set Ultra speed for TID 'tid'. */ 747 word |= (0x3 << (4 * (tid % 4))); 748 } else { 749 /* Set Fast speed for TID 'tid'. */ 750 word |= (0x2 << (4 * (tid % 4))); 751 } 752 /* Check if done with sdtr_speed1. */ 753 if (tid == 3) { 754 ADW_WRITE_WORD_LRAM(iot, ioh, 755 ADW_MC_SDTR_SPEED1, word); 756 word = 0; 757 /* Check if done with sdtr_speed2. */ 758 } else if (tid == 7) { 759 ADW_WRITE_WORD_LRAM(iot, ioh, 760 ADW_MC_SDTR_SPEED2, word); 761 word = 0; 762 /* Check if done with sdtr_speed3. */ 763 } else if (tid == 11) { 764 ADW_WRITE_WORD_LRAM(iot, ioh, 765 ADW_MC_SDTR_SPEED3, word); 766 word = 0; 767 /* Check if done with sdtr_speed4. */ 768 } else if (tid == 15) { 769 ADW_WRITE_WORD_LRAM(iot, ioh, 770 ADW_MC_SDTR_SPEED4, word); 771 /* End of loop. */ 772 } 773 } 774 775 /* 776 * Set microcode operating variable for the 777 * disconnect per TID bitmask. 778 */ 779 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 780 sc->cfg.disc_enable); 781 break; 782 783 case ADW_CHIP_ASC38C0800: 784 /* FALLTHROUGH */ 785 case ADW_CHIP_ASC38C1600: 786 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 787 sc->cfg.disc_enable); 788 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 789 sc->sdtr_speed1); 790 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 791 sc->sdtr_speed2); 792 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 793 sc->sdtr_speed3); 794 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 795 sc->sdtr_speed4); 796 break; 797 } 798 799 800 /* 801 * Set SCSI_CFG0 Microcode Default Value. 802 * 803 * The microcode will set the SCSI_CFG0 register using this value 804 * after it is started below. 805 */ 806 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 807 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 808 ADW_OUR_ID_EN | sc->chip_scsi_id); 809 810 811 switch(sc->chip_type) { 812 case ADW_CHIP_ASC3550: 813 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 814 break; 815 816 case ADW_CHIP_ASC38C0800: 817 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 818 break; 819 820 case ADW_CHIP_ASC38C1600: 821 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 822 break; 823 } 824 if(error_code) { 825 return error_code; 826 } 827 828 /* 829 * Set SEL_MASK Microcode Default Value 830 * 831 * The microcode will set the SEL_MASK register using this value 832 * after it is started below. 833 */ 834 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 835 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 836 837 /* 838 * Create and Initialize Host->RISC Carrier lists 839 */ 840 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 841 sc->sc_control->carriers); 842 843 /* 844 * Set-up the Host->RISC Initiator Command Queue (ICQ). 845 */ 846 847 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 848 return ADW_IERR_NO_CARRIER; 849 } 850 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 851 ASC_GET_CARRP(sc->icq_sp->next_ba)); 852 853 /* 854 * The first command issued will be placed in the stopper carrier. 855 */ 856 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER); 857 858 /* 859 * Set RISC ICQ physical address start value. 860 */ 861 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba)); 862 863 /* 864 * Initialize the COMMA register to the same value otherwise 865 * the RISC will prematurely detect a command is available. 866 */ 867 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 868 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 869 le32toh(sc->icq_sp->carr_ba)); 870 } 871 872 /* 873 * Set-up the RISC->Host Initiator Response Queue (IRQ). 874 */ 875 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 876 return ADW_IERR_NO_CARRIER; 877 } 878 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 879 ASC_GET_CARRP(sc->irq_sp->next_ba)); 880 881 /* 882 * The first command completed by the RISC will be placed in 883 * the stopper. 884 * 885 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 886 * completed the RISC will set the ASC_RQ_DONE bit. 887 */ 888 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER); 889 890 /* 891 * Set RISC IRQ physical address start value. 892 */ 893 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba)); 894 sc->carr_pending_cnt = 0; 895 896 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 897 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 898 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 899 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 900 901 /* finally, finally, gentlemen, start your engine */ 902 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 903 904 /* 905 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 906 * Resets should be performed. The RISC has to be running 907 * to issue a SCSI Bus Reset. 908 */ 909 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 910 { 911 /* 912 * If the BIOS Signature is present in memory, restore the 913 * BIOS Handshake Configuration Table and do not perform 914 * a SCSI Bus Reset. 915 */ 916 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 917 0x55AA) { 918 /* 919 * Restore per TID negotiated values. 920 */ 921 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 922 wdtr_able); 923 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 924 sdtr_able); 925 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 926 tagqng_able); 927 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 928 ADW_WRITE_BYTE_LRAM(iot, ioh, 929 ADW_MC_NUMBER_OF_MAX_CMD + tid, 930 max_cmd[tid]); 931 } 932 } else { 933 if (AdwResetCCB(sc) != ADW_TRUE) { 934 error_code = ADW_WARN_BUSRESET_ERROR; 935 } 936 } 937 } 938 939 return error_code; 940 } 941 942 943 int 944 AdwRamSelfTest(iot, ioh, chip_type) 945 bus_space_tag_t iot; 946 bus_space_handle_t ioh; 947 u_int8_t chip_type; 948 { 949 int i; 950 u_int8_t byte; 951 952 953 if ((chip_type == ADW_CHIP_ASC38C0800) || 954 (chip_type == ADW_CHIP_ASC38C1600)) { 955 /* 956 * RAM BIST (RAM Built-In Self Test) 957 * 958 * Address : I/O base + offset 0x38h register (byte). 959 * Function: Bit 7-6(RW) : RAM mode 960 * Normal Mode : 0x00 961 * Pre-test Mode : 0x40 962 * RAM Test Mode : 0x80 963 * Bit 5 : unused 964 * Bit 4(RO) : Done bit 965 * Bit 3-0(RO) : Status 966 * Host Error : 0x08 967 * Int_RAM Error : 0x04 968 * RISC Error : 0x02 969 * SCSI Error : 0x01 970 * No Error : 0x00 971 * 972 * Note: RAM BIST code should be put right here, before loading 973 * the microcode and after saving the RISC memory BIOS region. 974 */ 975 976 /* 977 * LRAM Pre-test 978 * 979 * Write PRE_TEST_MODE (0x40) to register and wait for 980 * 10 milliseconds. 981 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 982 * return an error. Reset to NORMAL_MODE (0x00) and do again. 983 * If cannot reset to NORMAL_MODE, return an error too. 984 */ 985 for (i = 0; i < 2; i++) { 986 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 987 PRE_TEST_MODE); 988 /* Wait for 10ms before reading back. */ 989 AdwSleepMilliSecond(10); 990 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 991 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 992 PRE_TEST_VALUE) { 993 return ADW_IERR_BIST_PRE_TEST; 994 } 995 996 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 997 NORMAL_MODE); 998 /* Wait for 10ms before reading back. */ 999 AdwSleepMilliSecond(10); 1000 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1001 != NORMAL_VALUE) { 1002 return ADW_IERR_BIST_PRE_TEST; 1003 } 1004 } 1005 1006 /* 1007 * LRAM Test - It takes about 1.5 ms to run through the test. 1008 * 1009 * Write RAM_TEST_MODE (0x80) to register and wait for 1010 * 10 milliseconds. 1011 * If Done bit not set or Status not 0, save register byte, 1012 * set the err_code, and return an error. 1013 */ 1014 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1015 /* Wait for 10ms before checking status. */ 1016 AdwSleepMilliSecond(10); 1017 1018 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1019 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1020 /* Get here if Done bit not set or Status not 0. */ 1021 return ADW_IERR_BIST_RAM_TEST; 1022 } 1023 1024 /* We need to reset back to normal mode after LRAM test passes*/ 1025 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1026 } 1027 1028 return 0; 1029 } 1030 1031 1032 int 1033 AdwLoadMCode(iot, ioh, bios_mem, chip_type) 1034 bus_space_tag_t iot; 1035 bus_space_handle_t ioh; 1036 u_int16_t *bios_mem; 1037 u_int8_t chip_type; 1038 { 1039 u_int8_t *mcode_data; 1040 u_int32_t mcode_chksum; 1041 u_int16_t mcode_size; 1042 u_int32_t sum; 1043 u_int16_t code_sum; 1044 int begin_addr; 1045 int end_addr; 1046 int word; 1047 int adw_memsize; 1048 int adw_mcode_expanded_size; 1049 int i, j; 1050 1051 1052 switch(chip_type) { 1053 case ADW_CHIP_ASC3550: 1054 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1055 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1056 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1057 adw_memsize = ADW_3550_MEMSIZE; 1058 break; 1059 1060 case ADW_CHIP_ASC38C0800: 1061 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1062 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1063 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1064 adw_memsize = ADW_38C0800_MEMSIZE; 1065 break; 1066 1067 case ADW_CHIP_ASC38C1600: 1068 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1069 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1070 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1071 adw_memsize = ADW_38C1600_MEMSIZE; 1072 break; 1073 } 1074 1075 /* 1076 * Write the microcode image to RISC memory starting at address 0. 1077 */ 1078 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1079 1080 /* Assume the following compressed format of the microcode buffer: 1081 * 1082 * 254 word (508 byte) table indexed by byte code followed 1083 * by the following byte codes: 1084 * 1085 * 1-Byte Code: 1086 * 00: Emit word 0 in table. 1087 * 01: Emit word 1 in table. 1088 * . 1089 * FD: Emit word 253 in table. 1090 * 1091 * Multi-Byte Code: 1092 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1093 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1094 */ 1095 word = 0; 1096 for (i = 253 * 2; i < mcode_size; i++) { 1097 if (mcode_data[i] == 0xff) { 1098 for (j = 0; j < mcode_data[i + 1]; j++) { 1099 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1100 (((u_int16_t)mcode_data[i + 3] << 8) | 1101 mcode_data[i + 2])); 1102 word++; 1103 } 1104 i += 3; 1105 } else if (mcode_data[i] == 0xfe) { 1106 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1107 (((u_int16_t)mcode_data[i + 2] << 8) | 1108 mcode_data[i + 1])); 1109 i += 2; 1110 word++; 1111 } else { 1112 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1113 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1114 mcode_data[mcode_data[i] * 2])); 1115 word++; 1116 } 1117 } 1118 1119 /* 1120 * Set 'word' for later use to clear the rest of memory and save 1121 * the expanded mcode size. 1122 */ 1123 word *= 2; 1124 adw_mcode_expanded_size = word; 1125 1126 /* 1127 * Clear the rest of the Internal RAM. 1128 */ 1129 for (; word < adw_memsize; word += 2) { 1130 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1131 } 1132 1133 /* 1134 * Verify the microcode checksum. 1135 */ 1136 sum = 0; 1137 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1138 1139 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1140 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1141 } 1142 1143 if (sum != mcode_chksum) { 1144 return ADW_IERR_MCODE_CHKSUM; 1145 } 1146 1147 /* 1148 * Restore the RISC memory BIOS region. 1149 */ 1150 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1151 if(chip_type == ADW_CHIP_ASC3550) { 1152 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1153 bios_mem[i]); 1154 } else { 1155 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1156 bios_mem[i]); 1157 } 1158 } 1159 1160 /* 1161 * Calculate and write the microcode code checksum to the microcode 1162 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1163 */ 1164 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1165 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1166 code_sum = 0; 1167 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1168 for (word = begin_addr; word < end_addr; word += 2) { 1169 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1170 } 1171 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1172 1173 /* 1174 * Set the chip type. 1175 */ 1176 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1177 1178 return 0; 1179 } 1180 1181 1182 int 1183 AdwASC3550Cabling(iot, ioh, cfg) 1184 bus_space_tag_t iot; 1185 bus_space_handle_t ioh; 1186 ADW_DVC_CFG *cfg; 1187 { 1188 u_int16_t scsi_cfg1; 1189 1190 1191 /* 1192 * Determine SCSI_CFG1 Microcode Default Value. 1193 * 1194 * The microcode will set the SCSI_CFG1 register using this value 1195 * after it is started below. 1196 */ 1197 1198 /* Read current SCSI_CFG1 Register value. */ 1199 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1200 1201 /* 1202 * If all three connectors are in use in ASC3550, return an error. 1203 */ 1204 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1205 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1206 return ADW_IERR_ILLEGAL_CONNECTION; 1207 } 1208 1209 /* 1210 * If the cable is reversed all of the SCSI_CTRL register signals 1211 * will be set. Check for and return an error if this condition is 1212 * found. 1213 */ 1214 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1215 return ADW_IERR_REVERSED_CABLE; 1216 } 1217 1218 /* 1219 * If this is a differential board and a single-ended device 1220 * is attached to one of the connectors, return an error. 1221 */ 1222 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1223 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1224 return ADW_IERR_SINGLE_END_DEVICE; 1225 } 1226 1227 /* 1228 * If automatic termination control is enabled, then set the 1229 * termination value based on a table listed in a_condor.h. 1230 * 1231 * If manual termination was specified with an EEPROM setting 1232 * then 'termination' was set-up in AdwInitFromEEPROM() and 1233 * is ready to be 'ored' into SCSI_CFG1. 1234 */ 1235 if (cfg->termination == 0) { 1236 /* 1237 * The software always controls termination by setting 1238 * TERM_CTL_SEL. 1239 * If TERM_CTL_SEL were set to 0, the hardware would set 1240 * termination. 1241 */ 1242 cfg->termination |= ADW_TERM_CTL_SEL; 1243 1244 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1245 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1246 case 0x3: case 0x7: case 0xB: 1247 case 0xD: case 0xE: case 0xF: 1248 cfg->termination |= 1249 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1250 break; 1251 1252 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1253 case 0x1: case 0x5: case 0x9: 1254 case 0xA: case 0xC: 1255 cfg->termination |= ADW_TERM_CTL_H; 1256 break; 1257 1258 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1259 case 0x2: case 0x6: 1260 break; 1261 } 1262 } 1263 1264 /* 1265 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1266 */ 1267 scsi_cfg1 &= ~ADW_TERM_CTL; 1268 1269 /* 1270 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1271 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1272 * referenced, because the hardware internally inverts 1273 * the Termination High and Low bits if TERM_POL is set. 1274 */ 1275 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1276 1277 /* 1278 * Set SCSI_CFG1 Microcode Default Value 1279 * 1280 * Set filter value and possibly modified termination control 1281 * bits in the Microcode SCSI_CFG1 Register Value. 1282 * 1283 * The microcode will set the SCSI_CFG1 register using this value 1284 * after it is started below. 1285 */ 1286 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1287 ADW_FLTR_DISABLE | scsi_cfg1); 1288 1289 /* 1290 * Set MEM_CFG Microcode Default Value 1291 * 1292 * The microcode will set the MEM_CFG register using this value 1293 * after it is started below. 1294 * 1295 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1296 * are defined. 1297 * 1298 * ASC-3550 has 8KB internal memory. 1299 */ 1300 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1301 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1302 1303 return 0; 1304 } 1305 1306 1307 int 1308 AdwASC38C0800Cabling(iot, ioh, cfg) 1309 bus_space_tag_t iot; 1310 bus_space_handle_t ioh; 1311 ADW_DVC_CFG *cfg; 1312 { 1313 u_int16_t scsi_cfg1; 1314 1315 1316 /* 1317 * Determine SCSI_CFG1 Microcode Default Value. 1318 * 1319 * The microcode will set the SCSI_CFG1 register using this value 1320 * after it is started below. 1321 */ 1322 1323 /* Read current SCSI_CFG1 Register value. */ 1324 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1325 1326 /* 1327 * If the cable is reversed all of the SCSI_CTRL register signals 1328 * will be set. Check for and return an error if this condition is 1329 * found. 1330 */ 1331 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1332 return ADW_IERR_REVERSED_CABLE; 1333 } 1334 1335 /* 1336 * All kind of combinations of devices attached to one of four 1337 * connectors are acceptable except HVD device attached. 1338 * For example, LVD device can be attached to SE connector while 1339 * SE device attached to LVD connector. 1340 * If LVD device attached to SE connector, it only runs up to 1341 * Ultra speed. 1342 * 1343 * If an HVD device is attached to one of LVD connectors, return 1344 * an error. 1345 * However, there is no way to detect HVD device attached to 1346 * SE connectors. 1347 */ 1348 if (scsi_cfg1 & ADW_HVD) { 1349 return ADW_IERR_HVD_DEVICE; 1350 } 1351 1352 /* 1353 * If either SE or LVD automatic termination control is enabled, then 1354 * set the termination value based on a table listed in a_condor.h. 1355 * 1356 * If manual termination was specified with an EEPROM setting then 1357 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1358 * to be 'ored' into SCSI_CFG1. 1359 */ 1360 if ((cfg->termination & ADW_TERM_SE) == 0) { 1361 /* SE automatic termination control is enabled. */ 1362 switch(scsi_cfg1 & ADW_C_DET_SE) { 1363 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1364 case 0x1: case 0x2: case 0x3: 1365 cfg->termination |= ADW_TERM_SE; 1366 break; 1367 1368 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1369 case 0x0: 1370 cfg->termination |= ADW_TERM_SE_HI; 1371 break; 1372 } 1373 } 1374 1375 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1376 /* LVD automatic termination control is enabled. */ 1377 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1378 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1379 case 0x4: case 0x8: case 0xC: 1380 cfg->termination |= ADW_TERM_LVD; 1381 break; 1382 1383 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1384 case 0x0: 1385 break; 1386 } 1387 } 1388 1389 /* 1390 * Clear any set TERM_SE and TERM_LVD bits. 1391 */ 1392 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1393 1394 /* 1395 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1396 */ 1397 scsi_cfg1 |= (~cfg->termination & 0xF0); 1398 1399 /* 1400 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1401 * HVD/LVD/SE bits and set possibly modified termination control bits 1402 * in the Microcode SCSI_CFG1 Register Value. 1403 */ 1404 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1405 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1406 1407 /* 1408 * Set SCSI_CFG1 Microcode Default Value 1409 * 1410 * Set possibly modified termination control and reset DIS_TERM_DRV 1411 * bits in the Microcode SCSI_CFG1 Register Value. 1412 * 1413 * The microcode will set the SCSI_CFG1 register using this value 1414 * after it is started below. 1415 */ 1416 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1417 1418 /* 1419 * Set MEM_CFG Microcode Default Value 1420 * 1421 * The microcode will set the MEM_CFG register using this value 1422 * after it is started below. 1423 * 1424 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1425 * are defined. 1426 * 1427 * ASC-38C0800 has 16KB internal memory. 1428 */ 1429 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1430 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1431 1432 return 0; 1433 } 1434 1435 1436 int 1437 AdwASC38C1600Cabling(iot, ioh, cfg) 1438 bus_space_tag_t iot; 1439 bus_space_handle_t ioh; 1440 ADW_DVC_CFG *cfg; 1441 { 1442 u_int16_t scsi_cfg1; 1443 1444 1445 /* 1446 * Determine SCSI_CFG1 Microcode Default Value. 1447 * 1448 * The microcode will set the SCSI_CFG1 register using this value 1449 * after it is started below. 1450 * Each ASC-38C1600 function has only two cable detect bits. 1451 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1452 */ 1453 1454 /* Read current SCSI_CFG1 Register value. */ 1455 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1456 1457 /* 1458 * If the cable is reversed all of the SCSI_CTRL register signals 1459 * will be set. Check for and return an error if this condition is 1460 * found. 1461 */ 1462 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1463 return ADW_IERR_REVERSED_CABLE; 1464 } 1465 1466 /* 1467 * Each ASC-38C1600 function has two connectors. Only an HVD device 1468 * can not be connected to either connector. An LVD device or SE device 1469 * may be connected to either connecor. If an SE device is connected, 1470 * then at most Ultra speed (20 Mhz) can be used on both connectors. 1471 * 1472 * If an HVD device is attached, return an error. 1473 */ 1474 if (scsi_cfg1 & ADW_HVD) { 1475 return ADW_IERR_HVD_DEVICE; 1476 } 1477 1478 /* 1479 * Each function in the ASC-38C1600 uses only the SE cable detect and 1480 * termination because there are two connectors for each function. 1481 * Each function may use either LVD or SE mode. 1482 * Corresponding the SE automatic termination control EEPROM bits are 1483 * used for each function. 1484 * Each function has its own EEPROM. If SE automatic control is enabled 1485 * for the function, then set the termination value based on a table 1486 * listed in adwlib.h. 1487 * 1488 * If manual termination is specified in the EEPROM for the function, 1489 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1490 * ready to be 'ored' into SCSI_CFG1. 1491 */ 1492 if ((cfg->termination & ADW_TERM_SE) == 0) { 1493 /* SE automatic termination control is enabled. */ 1494 switch(scsi_cfg1 & ADW_C_DET_SE) { 1495 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1496 case 0x1: case 0x2: case 0x3: 1497 cfg->termination |= ADW_TERM_SE; 1498 break; 1499 1500 case 0x0: 1501 #if 0 1502 /* !!!!TODO!!!! */ 1503 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1504 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1505 } 1506 else 1507 #endif 1508 { 1509 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1510 cfg->termination |= ADW_TERM_SE_HI; 1511 } 1512 break; 1513 } 1514 } 1515 1516 /* 1517 * Clear any set TERM_SE bits. 1518 */ 1519 scsi_cfg1 &= ~ADW_TERM_SE; 1520 1521 /* 1522 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1523 */ 1524 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1525 1526 /* 1527 * Clear Big Endian and Terminator Polarity bits and set possibly 1528 * modified termination control bits in the Microcode SCSI_CFG1 1529 * Register Value. 1530 */ 1531 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1532 1533 /* 1534 * Set SCSI_CFG1 Microcode Default Value 1535 * 1536 * Set possibly modified termination control bits in the Microcode 1537 * SCSI_CFG1 Register Value. 1538 * 1539 * The microcode will set the SCSI_CFG1 register using this value 1540 * after it is started below. 1541 */ 1542 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1543 1544 /* 1545 * Set MEM_CFG Microcode Default Value 1546 * 1547 * The microcode will set the MEM_CFG register using this value 1548 * after it is started below. 1549 * 1550 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1551 * are defined. 1552 * 1553 * ASC-38C1600 has 32KB internal memory. 1554 */ 1555 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1556 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1557 1558 return 0; 1559 } 1560 1561 1562 /* 1563 * Read EEPROM configuration into the specified buffer. 1564 * 1565 * Return a checksum based on the EEPROM configuration read. 1566 */ 1567 static u_int16_t 1568 AdwGetEEPROMConfig(iot, ioh, cfg_buf) 1569 bus_space_tag_t iot; 1570 bus_space_handle_t ioh; 1571 ADW_EEPROM *cfg_buf; 1572 { 1573 u_int16_t wval, chksum; 1574 u_int16_t *wbuf; 1575 int eep_addr; 1576 1577 1578 wbuf = (u_int16_t *) cfg_buf; 1579 chksum = 0; 1580 1581 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1582 eep_addr < ASC_EEP_DVC_CFG_END; 1583 eep_addr++, wbuf++) { 1584 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1585 chksum += wval; 1586 *wbuf = wval; 1587 } 1588 1589 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1590 wbuf++; 1591 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1592 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1593 eep_addr++, wbuf++) { 1594 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1595 } 1596 1597 return chksum; 1598 } 1599 1600 1601 /* 1602 * Read the EEPROM from specified location 1603 */ 1604 static u_int16_t 1605 AdwReadEEPWord(iot, ioh, eep_word_addr) 1606 bus_space_tag_t iot; 1607 bus_space_handle_t ioh; 1608 int eep_word_addr; 1609 { 1610 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1611 ASC_EEP_CMD_READ | eep_word_addr); 1612 AdwWaitEEPCmd(iot, ioh); 1613 1614 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1615 } 1616 1617 1618 /* 1619 * Wait for EEPROM command to complete 1620 */ 1621 static void 1622 AdwWaitEEPCmd(iot, ioh) 1623 bus_space_tag_t iot; 1624 bus_space_handle_t ioh; 1625 { 1626 int eep_delay_ms; 1627 1628 1629 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1630 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1631 ASC_EEP_CMD_DONE) { 1632 break; 1633 } 1634 AdwSleepMilliSecond(1); 1635 } 1636 1637 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1638 } 1639 1640 1641 /* 1642 * Write the EEPROM from 'cfg_buf'. 1643 */ 1644 static void 1645 AdwSetEEPROMConfig(iot, ioh, cfg_buf) 1646 bus_space_tag_t iot; 1647 bus_space_handle_t ioh; 1648 ADW_EEPROM *cfg_buf; 1649 { 1650 u_int16_t *wbuf; 1651 u_int16_t addr, chksum; 1652 1653 1654 wbuf = (u_int16_t *) cfg_buf; 1655 chksum = 0; 1656 1657 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1658 AdwWaitEEPCmd(iot, ioh); 1659 1660 /* 1661 * Write EEPROM from word 0 to word 20 1662 */ 1663 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1664 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1665 chksum += *wbuf; 1666 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1667 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1668 ASC_EEP_CMD_WRITE | addr); 1669 AdwWaitEEPCmd(iot, ioh); 1670 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1671 } 1672 1673 /* 1674 * Write EEPROM checksum at word 21 1675 */ 1676 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1677 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1678 ASC_EEP_CMD_WRITE | addr); 1679 AdwWaitEEPCmd(iot, ioh); 1680 wbuf++; /* skip over check_sum */ 1681 1682 /* 1683 * Write EEPROM OEM name at words 22 to 29 1684 */ 1685 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1686 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1687 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1688 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1689 ASC_EEP_CMD_WRITE | addr); 1690 AdwWaitEEPCmd(iot, ioh); 1691 } 1692 1693 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1694 ASC_EEP_CMD_WRITE_DISABLE); 1695 AdwWaitEEPCmd(iot, ioh); 1696 1697 return; 1698 } 1699 1700 1701 /* 1702 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1703 * 1704 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1705 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1706 * RISC to notify it a new command is ready to be executed. 1707 * 1708 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1709 * set to SCSI_MAX_RETRY. 1710 * 1711 * Return: 1712 * ADW_SUCCESS(1) - The request was successfully queued. 1713 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1714 * request completes. 1715 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1716 * host IC error. 1717 */ 1718 int 1719 AdwExeScsiQueue(sc, scsiq) 1720 ADW_SOFTC *sc; 1721 ADW_SCSI_REQ_Q *scsiq; 1722 { 1723 bus_space_tag_t iot = sc->sc_iot; 1724 bus_space_handle_t ioh = sc->sc_ioh; 1725 ADW_CCB *ccb; 1726 long req_size; 1727 u_int32_t req_paddr; 1728 ADW_CARRIER *new_carrp; 1729 1730 /* 1731 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1732 */ 1733 if (scsiq->target_id > ADW_MAX_TID) { 1734 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1735 scsiq->done_status = QD_WITH_ERROR; 1736 return ADW_ERROR; 1737 } 1738 1739 /* 1740 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1741 */ 1742 1743 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1744 1745 /* 1746 * Allocate a carrier and initialize fields. 1747 */ 1748 if ((new_carrp = sc->carr_freelist) == NULL) { 1749 return ADW_BUSY; 1750 } 1751 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1752 ASC_GET_CARRP(new_carrp->next_ba)); 1753 sc->carr_pending_cnt++; 1754 1755 /* 1756 * Set the carrier to be a stopper by setting 'next_ba' 1757 * to the stopper value. The current stopper will be changed 1758 * below to point to the new stopper. 1759 */ 1760 new_carrp->next_ba = htole32(ASC_CQ_STOPPER); 1761 1762 req_size = sizeof(ADW_SCSI_REQ_Q); 1763 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1764 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1765 1766 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1767 scsiq->scsiq_rptr = htole32(req_paddr); 1768 1769 /* 1770 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1771 * order during initialization. 1772 */ 1773 scsiq->carr_ba = sc->icq_sp->carr_ba; 1774 scsiq->carr_va = sc->icq_sp->carr_ba; 1775 1776 /* 1777 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1778 * the microcode. The newly allocated stopper will become the new 1779 * stopper. 1780 */ 1781 sc->icq_sp->areq_ba = htole32(req_paddr); 1782 1783 /* 1784 * Set the 'next_ba' pointer for the old stopper to be the 1785 * physical address of the new stopper. The RISC can only 1786 * follow physical addresses. 1787 */ 1788 sc->icq_sp->next_ba = new_carrp->carr_ba; 1789 1790 #if ADW_DEBUG 1791 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1792 sc->icq_sp->carr_id, 1793 sc->icq_sp->carr_ba, 1794 sc->icq_sp->areq_ba, 1795 sc->icq_sp->next_ba); 1796 #endif 1797 /* 1798 * Set the host adapter stopper pointer to point to the new carrier. 1799 */ 1800 sc->icq_sp = new_carrp; 1801 1802 if (sc->chip_type == ADW_CHIP_ASC3550 || 1803 sc->chip_type == ADW_CHIP_ASC38C0800) { 1804 /* 1805 * Tickle the RISC to tell it to read its Command Queue Head 1806 * pointer. 1807 */ 1808 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1809 if (sc->chip_type == ADW_CHIP_ASC3550) { 1810 /* 1811 * Clear the tickle value. In the ASC-3550 the RISC flag 1812 * command 'clr_tickle_a' does not work unless the host 1813 * value is cleared. 1814 */ 1815 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1816 ADW_TICKLE_NOP); 1817 } 1818 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1819 /* 1820 * Notify the RISC a carrier is ready by writing the physical 1821 * address of the new carrier stopper to the COMMA register. 1822 */ 1823 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1824 le32toh(new_carrp->carr_ba)); 1825 } 1826 1827 /* 1828 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1829 */ 1830 1831 return ADW_SUCCESS; 1832 } 1833 1834 1835 void 1836 AdwResetChip(iot, ioh) 1837 bus_space_tag_t iot; 1838 bus_space_handle_t ioh; 1839 { 1840 1841 /* 1842 * Reset Chip. 1843 */ 1844 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1845 ADW_CTRL_REG_CMD_RESET); 1846 AdwSleepMilliSecond(100); 1847 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1848 ADW_CTRL_REG_CMD_WR_IO_REG); 1849 } 1850 1851 1852 /* 1853 * Reset SCSI Bus and purge all outstanding requests. 1854 * 1855 * Return Value: 1856 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1857 * ADW_FALSE(0) - Microcode command failed. 1858 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1859 * may be hung which requires driver recovery. 1860 */ 1861 int 1862 AdwResetCCB(sc) 1863 ADW_SOFTC *sc; 1864 { 1865 int status; 1866 1867 /* 1868 * Send the SCSI Bus Reset idle start idle command which asserts 1869 * the SCSI Bus Reset signal. 1870 */ 1871 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1872 if (status != ADW_TRUE) { 1873 return status; 1874 } 1875 1876 /* 1877 * Delay for the specified SCSI Bus Reset hold time. 1878 * 1879 * The hold time delay is done on the host because the RISC has no 1880 * microsecond accurate timer. 1881 */ 1882 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1883 1884 /* 1885 * Send the SCSI Bus Reset end idle command which de-asserts 1886 * the SCSI Bus Reset signal and purges any pending requests. 1887 */ 1888 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1889 if (status != ADW_TRUE) { 1890 return status; 1891 } 1892 1893 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1894 1895 return status; 1896 } 1897 1898 1899 /* 1900 * Reset chip and SCSI Bus. 1901 * 1902 * Return Value: 1903 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1904 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1905 */ 1906 int 1907 AdwResetSCSIBus(sc) 1908 ADW_SOFTC *sc; 1909 { 1910 bus_space_tag_t iot = sc->sc_iot; 1911 bus_space_handle_t ioh = sc->sc_ioh; 1912 int status; 1913 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1914 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1915 u_int16_t bios_sig; 1916 1917 1918 /* 1919 * Save current per TID negotiated values. 1920 */ 1921 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1922 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1923 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1924 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1925 } 1926 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1927 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1928 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1929 max_cmd[tid]); 1930 } 1931 1932 /* 1933 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1934 * by clearing the BIOS signature word. 1935 * The initialization functions assumes a SCSI Bus Reset is not 1936 * needed if the BIOS signature word is present. 1937 */ 1938 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1939 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1940 1941 /* 1942 * Stop chip and reset it. 1943 */ 1944 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1945 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1946 ADW_CTRL_REG_CMD_RESET); 1947 AdwSleepMilliSecond(100); 1948 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1949 ADW_CTRL_REG_CMD_WR_IO_REG); 1950 1951 /* 1952 * Reset Adv Library error code, if any, and try 1953 * re-initializing the chip. 1954 * Then translate initialization return value to status value. 1955 */ 1956 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1957 1958 /* 1959 * Restore the BIOS signature word. 1960 */ 1961 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1962 1963 /* 1964 * Restore per TID negotiated values. 1965 */ 1966 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1967 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1968 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1969 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1970 } 1971 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1972 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1973 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1974 max_cmd[tid]); 1975 } 1976 1977 return status; 1978 } 1979 1980 1981 /* 1982 * Adv Library Interrupt Service Routine 1983 * 1984 * This function is called by a driver's interrupt service routine. 1985 * The function disables and re-enables interrupts. 1986 * 1987 * When a microcode idle command is completed, the ADV_DVC_VAR 1988 * 'idle_cmd_done' field is set to ADW_TRUE. 1989 * 1990 * Note: AdwISR() can be called when interrupts are disabled or even 1991 * when there is no hardware interrupt condition present. It will 1992 * always check for completed idle commands and microcode requests. 1993 * This is an important feature that shouldn't be changed because it 1994 * allows commands to be completed from polling mode loops. 1995 * 1996 * Return: 1997 * ADW_TRUE(1) - interrupt was pending 1998 * ADW_FALSE(0) - no interrupt was pending 1999 */ 2000 int 2001 AdwISR(sc) 2002 ADW_SOFTC *sc; 2003 { 2004 bus_space_tag_t iot = sc->sc_iot; 2005 bus_space_handle_t ioh = sc->sc_ioh; 2006 u_int8_t int_stat; 2007 u_int16_t target_bit; 2008 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 2009 u_int32_t irq_next_pa; 2010 ADW_SCSI_REQ_Q *scsiq; 2011 ADW_CCB *ccb; 2012 int s; 2013 2014 2015 s = splbio(); 2016 2017 /* Reading the register clears the interrupt. */ 2018 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 2019 2020 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 2021 ADW_INTR_STATUS_INTRC)) == 0) { 2022 splx(s); 2023 return ADW_FALSE; 2024 } 2025 2026 /* 2027 * Notify the driver of an asynchronous microcode condition by 2028 * calling the ADV_DVC_VAR.async_callback function. The function 2029 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2030 */ 2031 if (int_stat & ADW_INTR_STATUS_INTRB) { 2032 u_int8_t intrb_code; 2033 2034 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2035 2036 if (sc->chip_type == ADW_CHIP_ASC3550 || 2037 sc->chip_type == ADW_CHIP_ASC38C0800) { 2038 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2039 sc->carr_pending_cnt != 0) { 2040 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2041 IOPB_TICKLE, ADW_TICKLE_A); 2042 if (sc->chip_type == ADW_CHIP_ASC3550) { 2043 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2044 IOPB_TICKLE, ADW_TICKLE_NOP); 2045 } 2046 } 2047 } 2048 2049 if (sc->async_callback != 0) { 2050 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2051 } 2052 } 2053 2054 /* 2055 * Check if the IRQ stopper carrier contains a completed request. 2056 */ 2057 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0) 2058 { 2059 #if ADW_DEBUG 2060 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2061 sc->irq_sp->carr_id, 2062 sc->irq_sp->carr_ba, 2063 sc->irq_sp->areq_ba, 2064 sc->irq_sp->next_ba); 2065 #endif 2066 /* 2067 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2068 * structure. 2069 * The RISC will have set 'areq_ba' to a virtual address. 2070 * 2071 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2072 * field to the carrier ADV_CARR_T.areq_ba field. 2073 * The conversion below complements the conversion of 2074 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2075 */ 2076 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2077 scsiq = &ccb->scsiq; 2078 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2079 2080 /* 2081 * Request finished with good status and the queue was not 2082 * DMAed to host memory by the firmware. Set all status fields 2083 * to indicate good status. 2084 */ 2085 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) { 2086 scsiq->done_status = QD_NO_ERROR; 2087 scsiq->host_status = scsiq->scsi_status = 0; 2088 scsiq->data_cnt = 0L; 2089 } 2090 2091 /* 2092 * Advance the stopper pointer to the next carrier 2093 * ignoring the lower four bits. Free the previous 2094 * stopper carrier. 2095 */ 2096 free_carrp = sc->irq_sp; 2097 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2098 2099 free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL 2100 : sc->carr_freelist->carr_ba; 2101 sc->carr_freelist = free_carrp; 2102 sc->carr_pending_cnt--; 2103 2104 2105 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2106 2107 /* 2108 * Clear request microcode control flag. 2109 */ 2110 scsiq->cntl = 0; 2111 2112 /* 2113 * Check Condition handling 2114 */ 2115 /* 2116 * If the command that completed was a SCSI INQUIRY and 2117 * LUN 0 was sent the command, then process the INQUIRY 2118 * command information for the device. 2119 */ 2120 if (scsiq->done_status == QD_NO_ERROR && 2121 scsiq->cdb[0] == INQUIRY && 2122 scsiq->target_lun == 0) { 2123 AdwInquiryHandling(sc, scsiq); 2124 } 2125 2126 /* 2127 * Notify the driver of the completed request by passing 2128 * the ADW_SCSI_REQ_Q pointer to its callback function. 2129 */ 2130 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2131 /* 2132 * Note: After the driver callback function is called, 'scsiq' 2133 * can no longer be referenced. 2134 * 2135 * Fall through and continue processing other completed 2136 * requests... 2137 */ 2138 } 2139 2140 splx(s); 2141 2142 return ADW_TRUE; 2143 } 2144 2145 2146 /* 2147 * Send an idle command to the chip and wait for completion. 2148 * 2149 * Command completion is polled for once per microsecond. 2150 * 2151 * The function can be called from anywhere including an interrupt handler. 2152 * But the function is not re-entrant, so it uses the splbio/splx() 2153 * functions to prevent reentrancy. 2154 * 2155 * Return Values: 2156 * ADW_TRUE - command completed successfully 2157 * ADW_FALSE - command failed 2158 * ADW_ERROR - command timed out 2159 */ 2160 int 2161 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 2162 ADW_SOFTC *sc; 2163 u_int16_t idle_cmd; 2164 u_int32_t idle_cmd_parameter; 2165 { 2166 bus_space_tag_t iot = sc->sc_iot; 2167 bus_space_handle_t ioh = sc->sc_ioh; 2168 u_int16_t result; 2169 u_int32_t i, j, s; 2170 2171 s = splbio(); 2172 2173 /* 2174 * Clear the idle command status which is set by the microcode 2175 * to a non-zero value to indicate when the command is completed. 2176 */ 2177 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2178 2179 /* 2180 * Write the idle command value after the idle command parameter 2181 * has been written to avoid a race condition. If the order is not 2182 * followed, the microcode may process the idle command before the 2183 * parameters have been written to LRAM. 2184 */ 2185 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2186 idle_cmd_parameter); 2187 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2188 2189 /* 2190 * Tickle the RISC to tell it to process the idle command. 2191 */ 2192 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2193 if (sc->chip_type == ADW_CHIP_ASC3550) { 2194 /* 2195 * Clear the tickle value. In the ASC-3550 the RISC flag 2196 * command 'clr_tickle_b' does not work unless the host 2197 * value is cleared. 2198 */ 2199 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2200 } 2201 2202 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2203 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2204 /* Poll once each microsecond for command completion. */ 2205 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2206 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2207 result); 2208 if (result != 0) { 2209 splx(s); 2210 return result; 2211 } 2212 AdwDelayMicroSecond(1); 2213 } 2214 } 2215 2216 splx(s); 2217 return ADW_ERROR; 2218 } 2219 2220 2221 /* 2222 * Inquiry Information Byte 7 Handling 2223 * 2224 * Handle SCSI Inquiry Command information for a device by setting 2225 * microcode operating variables that affect WDTR, SDTR, and Tag 2226 * Queuing. 2227 */ 2228 static void 2229 AdwInquiryHandling(sc, scsiq) 2230 ADW_SOFTC *sc; 2231 ADW_SCSI_REQ_Q *scsiq; 2232 { 2233 #ifndef FAILSAFE 2234 bus_space_tag_t iot = sc->sc_iot; 2235 bus_space_handle_t ioh = sc->sc_ioh; 2236 u_int8_t tid; 2237 struct scsipi_inquiry_data *inq; 2238 u_int16_t tidmask; 2239 u_int16_t cfg_word; 2240 2241 2242 /* 2243 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2244 * to be available. 2245 * 2246 * If less than 8 bytes of INQUIRY information were requested or less 2247 * than 8 bytes were transferred, then return. cdb[4] is the request 2248 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2249 * microcode to the transfer residual count. 2250 */ 2251 2252 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2253 return; 2254 } 2255 2256 tid = scsiq->target_id; 2257 2258 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2259 2260 /* 2261 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2262 */ 2263 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2264 ((inq->version & SID_ANSII) < 2)) { 2265 return; 2266 } else { 2267 /* 2268 * INQUIRY Byte 7 Handling 2269 * 2270 * Use a device's INQUIRY byte 7 to determine whether it 2271 * supports WDTR, SDTR, and Tag Queuing. If the feature 2272 * is enabled in the EEPROM and the device supports the 2273 * feature, then enable it in the microcode. 2274 */ 2275 2276 tidmask = ADW_TID_TO_TIDMASK(tid); 2277 2278 /* 2279 * Wide Transfers 2280 * 2281 * If the EEPROM enabled WDTR for the device and the device 2282 * supports wide bus (16 bit) transfers, then turn on the 2283 * device's 'wdtr_able' bit and write the new value to the 2284 * microcode. 2285 */ 2286 #ifdef SCSI_ADW_WDTR_DISABLE 2287 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2288 #endif /* SCSI_ADW_WDTR_DISABLE */ 2289 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2290 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2291 cfg_word); 2292 if ((cfg_word & tidmask) == 0) { 2293 cfg_word |= tidmask; 2294 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2295 cfg_word); 2296 2297 /* 2298 * Clear the microcode "SDTR negotiation" and 2299 * "WDTR negotiation" done indicators for the 2300 * target to cause it to negotiate with the new 2301 * setting set above. 2302 * WDTR when accepted causes the target to enter 2303 * asynchronous mode, so SDTR must be negotiated 2304 */ 2305 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2306 cfg_word); 2307 cfg_word &= ~tidmask; 2308 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2309 cfg_word); 2310 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2311 cfg_word); 2312 cfg_word &= ~tidmask; 2313 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2314 cfg_word); 2315 } 2316 } 2317 2318 /* 2319 * Synchronous Transfers 2320 * 2321 * If the EEPROM enabled SDTR for the device and the device 2322 * supports synchronous transfers, then turn on the device's 2323 * 'sdtr_able' bit. Write the new value to the microcode. 2324 */ 2325 #ifdef SCSI_ADW_SDTR_DISABLE 2326 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2327 #endif /* SCSI_ADW_SDTR_DISABLE */ 2328 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2329 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2330 if ((cfg_word & tidmask) == 0) { 2331 cfg_word |= tidmask; 2332 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2333 cfg_word); 2334 2335 /* 2336 * Clear the microcode "SDTR negotiation" 2337 * done indicator for the target to cause it 2338 * to negotiate with the new setting set above. 2339 */ 2340 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2341 cfg_word); 2342 cfg_word &= ~tidmask; 2343 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2344 cfg_word); 2345 } 2346 } 2347 /* 2348 * If the Inquiry data included enough space for the SPI-3 2349 * Clocking field, then check if DT mode is supported. 2350 */ 2351 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2352 (scsiq->cdb[4] >= 57 || 2353 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2354 /* 2355 * PPR (Parallel Protocol Request) Capable 2356 * 2357 * If the device supports DT mode, then it must be 2358 * PPR capable. 2359 * The PPR message will be used in place of the SDTR 2360 * and WDTR messages to negotiate synchronous speed 2361 * and offset, transfer width, and protocol options. 2362 */ 2363 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2364 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2365 sc->ppr_able); 2366 sc->ppr_able |= tidmask; 2367 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2368 sc->ppr_able); 2369 } 2370 } 2371 2372 /* 2373 * If the EEPROM enabled Tag Queuing for the device and the 2374 * device supports Tag Queueing, then turn on the device's 2375 * 'tagqng_enable' bit in the microcode and set the microcode 2376 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2377 * value. 2378 * 2379 * Tag Queuing is disabled for the BIOS which runs in polled 2380 * mode and would see no benefit from Tag Queuing. Also by 2381 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2382 * bugs will at least work with the BIOS. 2383 */ 2384 #ifdef SCSI_ADW_TAGQ_DISABLE 2385 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2386 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2387 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2388 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2389 cfg_word); 2390 cfg_word |= tidmask; 2391 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2392 cfg_word); 2393 2394 ADW_WRITE_BYTE_LRAM(iot, ioh, 2395 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2396 sc->max_dvc_qng); 2397 } 2398 } 2399 #endif /* FAILSAFE */ 2400 } 2401 2402 2403 static void 2404 AdwSleepMilliSecond(n) 2405 u_int32_t n; 2406 { 2407 2408 DELAY(n * 1000); 2409 } 2410 2411 2412 static void 2413 AdwDelayMicroSecond(n) 2414 u_int32_t n; 2415 { 2416 2417 DELAY(n); 2418 } 2419 2420
Indexes created Tue Sep 23 14:10:03 GMT 2025