adwlib.c revision 1.23 1 /* $NetBSD: adwlib.c,v 1.23 2001/11/13 13:14:32 lukem Exp $ */
2
3 /*
4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips
5 *
6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * Author: Baldassare Dante Profeta <dante (at) mclink.it>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39 /*
40 * Ported from:
41 */
42 /*
43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
44 *
45 * Copyright (c) 1995-2000 Advanced System Products, Inc.
46 * All Rights Reserved.
47 *
48 * Redistribution and use in source and binary forms, with or without
49 * modification, are permitted provided that redistributions of source
50 * code retain the above copyright notice and this comment without
51 * modification.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.23 2001/11/13 13:14:32 lukem Exp $");
56
57 #include <sys/types.h>
58 #include <sys/param.h>
59 #include <sys/systm.h>
60 #include <sys/malloc.h>
61 #include <sys/kernel.h>
62 #include <sys/queue.h>
63 #include <sys/device.h>
64
65 #include <machine/bus.h>
66 #include <machine/intr.h>
67
68 #include <dev/scsipi/scsi_all.h>
69 #include <dev/scsipi/scsipi_all.h>
70 #include <dev/scsipi/scsiconf.h>
71
72 #include <dev/pci/pcidevs.h>
73
74 #include <uvm/uvm_extern.h>
75
76 #include <dev/ic/adwlib.h>
77 #include <dev/ic/adwmcode.h>
78 #include <dev/ic/adw.h>
79
80
81 /* Static Functions */
82
83 int AdwRamSelfTest __P((bus_space_tag_t, bus_space_handle_t, u_int8_t));
84 int AdwLoadMCode __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *,
85 u_int8_t));
86 int AdwASC3550Cabling __P((bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *));
87 int AdwASC38C0800Cabling __P((bus_space_tag_t, bus_space_handle_t,
88 ADW_DVC_CFG *));
89 int AdwASC38C1600Cabling __P((bus_space_tag_t, bus_space_handle_t,
90 ADW_DVC_CFG *));
91
92 static u_int16_t AdwGetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t,
93 ADW_EEPROM *));
94 static void AdwSetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t,
95 ADW_EEPROM *));
96 static u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int));
97 static void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t));
98
99 static void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *));
100
101 static void AdwSleepMilliSecond __P((u_int32_t));
102 static void AdwDelayMicroSecond __P((u_int32_t));
103
104
105 /*
106 * EEPROM Configuration.
107 *
108 * All drivers should use this structure to set the default EEPROM
109 * configuration. The BIOS now uses this structure when it is built.
110 * Additional structure information can be found in adwlib.h where
111 * the structure is defined.
112 */
113 const static ADW_EEPROM adw_3550_Default_EEPROM = {
114 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
115 0x0000, /* 01 cfg_msw */
116 0xFFFF, /* 02 disc_enable */
117 0xFFFF, /* 03 wdtr_able */
118 { 0xFFFF }, /* 04 sdtr_able */
119 0xFFFF, /* 05 start_motor */
120 0xFFFF, /* 06 tagqng_able */
121 0xFFFF, /* 07 bios_scan */
122 0, /* 08 scam_tolerant */
123 7, /* 09 adapter_scsi_id */
124 0, /* bios_boot_delay */
125 3, /* 10 scsi_reset_delay */
126 0, /* bios_id_lun */
127 0, /* 11 termination */
128 0, /* reserved1 */
129 0xFFE7, /* 12 bios_ctrl */
130 { 0xFFFF }, /* 13 ultra_able */
131 { 0 }, /* 14 reserved2 */
132 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
133 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
134 0, /* 16 dvc_cntl */
135 { 0 }, /* 17 bug_fix */
136 { 0,0,0 }, /* 18-20 serial_number[3] */
137 0, /* 21 check_sum */
138 { /* 22-29 oem_name[16] */
139 0,0,0,0,0,0,0,0,
140 0,0,0,0,0,0,0,0
141 },
142 0, /* 30 dvc_err_code */
143 0, /* 31 adv_err_code */
144 0, /* 32 adv_err_addr */
145 0, /* 33 saved_dvc_err_code */
146 0, /* 34 saved_adv_err_code */
147 0 /* 35 saved_adv_err_addr */
148 };
149
150 const static ADW_EEPROM adw_38C0800_Default_EEPROM = {
151 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
152 0x0000, /* 01 cfg_msw */
153 0xFFFF, /* 02 disc_enable */
154 0xFFFF, /* 03 wdtr_able */
155 { 0x4444 }, /* 04 sdtr_speed1 */
156 0xFFFF, /* 05 start_motor */
157 0xFFFF, /* 06 tagqng_able */
158 0xFFFF, /* 07 bios_scan */
159 0, /* 08 scam_tolerant */
160 7, /* 09 adapter_scsi_id */
161 0, /* bios_boot_delay */
162 3, /* 10 scsi_reset_delay */
163 0, /* bios_id_lun */
164 0, /* 11 termination_se */
165 0, /* termination_lvd */
166 0xFFE7, /* 12 bios_ctrl */
167 { 0x4444 }, /* 13 sdtr_speed2 */
168 { 0x4444 }, /* 14 sdtr_speed3 */
169 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
170 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
171 0, /* 16 dvc_cntl */
172 { 0x4444 }, /* 17 sdtr_speed4 */
173 { 0,0,0 }, /* 18-20 serial_number[3] */
174 0, /* 21 check_sum */
175 { /* 22-29 oem_name[16] */
176 0,0,0,0,0,0,0,0,
177 0,0,0,0,0,0,0,0
178 },
179 0, /* 30 dvc_err_code */
180 0, /* 31 adv_err_code */
181 0, /* 32 adv_err_addr */
182 0, /* 33 saved_dvc_err_code */
183 0, /* 34 saved_adv_err_code */
184 0, /* 35 saved_adv_err_addr */
185 { /* 36-55 reserved1[16] */
186 0,0,0,0,0,0,0,0,0,0,
187 0,0,0,0,0,0,0,0,0,0
188 },
189 0, /* 56 cisptr_lsw */
190 0, /* 57 cisprt_msw */
191 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
192 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */
193 { 0,0,0,0 } /* 60-63 reserved2[4] */
194 };
195
196 const static ADW_EEPROM adw_38C1600_Default_EEPROM = {
197 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
198 0x0000, /* 01 cfg_msw */
199 0xFFFF, /* 02 disc_enable */
200 0xFFFF, /* 03 wdtr_able */
201 { 0x5555 }, /* 04 sdtr_speed1 */
202 0xFFFF, /* 05 start_motor */
203 0xFFFF, /* 06 tagqng_able */
204 0xFFFF, /* 07 bios_scan */
205 0, /* 08 scam_tolerant */
206 7, /* 09 adapter_scsi_id */
207 0, /* bios_boot_delay */
208 3, /* 10 scsi_reset_delay */
209 0, /* bios_id_lun */
210 0, /* 11 termination_se */
211 0, /* termination_lvd */
212 0xFFE7, /* 12 bios_ctrl */
213 { 0x5555 }, /* 13 sdtr_speed2 */
214 { 0x5555 }, /* 14 sdtr_speed3 */
215 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
216 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
217 0, /* 16 dvc_cntl */
218 { 0x5555 }, /* 17 sdtr_speed4 */
219 { 0,0,0 }, /* 18-20 serial_number[3] */
220 0, /* 21 check_sum */
221 { /* 22-29 oem_name[16] */
222 0,0,0,0,0,0,0,0,
223 0,0,0,0,0,0,0,0
224 },
225 0, /* 30 dvc_err_code */
226 0, /* 31 adv_err_code */
227 0, /* 32 adv_err_addr */
228 0, /* 33 saved_dvc_err_code */
229 0, /* 34 saved_adv_err_code */
230 0, /* 35 saved_adv_err_addr */
231 { /* 36-55 reserved1[16] */
232 0,0,0,0,0,0,0,0,0,0,
233 0,0,0,0,0,0,0,0,0,0
234 },
235 0, /* 56 cisptr_lsw */
236 0, /* 57 cisprt_msw */
237 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
238 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */
239 { 0,0,0,0 } /* 60-63 reserved2[4] */
240 };
241
242
243 /*
244 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and
245 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while
246 * all of this is done.
247 *
248 * For a non-fatal error return a warning code. If there are no warnings
249 * then 0 is returned.
250 *
251 * Note: Chip is stopped on entry.
252 */
253 int
254 AdwInitFromEEPROM(sc)
255 ADW_SOFTC *sc;
256 {
257 bus_space_tag_t iot = sc->sc_iot;
258 bus_space_handle_t ioh = sc->sc_ioh;
259 ADW_EEPROM eep_config;
260 u_int16_t warn_code;
261 u_int16_t sdtr_speed = 0;
262 u_int8_t tid, termination;
263 int i, j;
264
265
266 warn_code = 0;
267
268 /*
269 * Read the board's EEPROM configuration.
270 *
271 * Set default values if a bad checksum is found.
272 *
273 * XXX - Don't handle big-endian access to EEPROM yet.
274 */
275 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) {
276 warn_code |= ADW_WARN_EEPROM_CHKSUM;
277
278 /*
279 * Set EEPROM default values.
280 */
281 switch(sc->chip_type) {
282 case ADW_CHIP_ASC3550:
283 eep_config = adw_3550_Default_EEPROM;
284 break;
285 case ADW_CHIP_ASC38C0800:
286 eep_config = adw_38C0800_Default_EEPROM;
287 break;
288 case ADW_CHIP_ASC38C1600:
289 eep_config = adw_38C1600_Default_EEPROM;
290
291 #if 0
292 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) {
293 #endif
294 if (sc->cfg.pci_slot_info != 0) {
295 u_int8_t lsw_msb;
296
297 lsw_msb = eep_config.cfg_lsw >> 8;
298 /*
299 * Set Function 1 EEPROM Word 0 MSB
300 *
301 * Clear the BIOS_ENABLE (bit 14) and
302 * INTAB (bit 11) EEPROM bits.
303 *
304 * Disable Bit 14 (BIOS_ENABLE) to fix
305 * SPARC Ultra 60 and old Mac system booting
306 * problem. The Expansion ROM must
307 * be disabled in Function 1 for these systems.
308 */
309 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE |
310 ADW_EEPROM_INTAB) >> 8) & 0xFF);
311 /*
312 * Set the INTAB (bit 11) if the GPIO 0 input
313 * indicates the Function 1 interrupt line is
314 * wired to INTA.
315 *
316 * Set/Clear Bit 11 (INTAB) from
317 * the GPIO bit 0 input:
318 * 1 - Function 1 intr line wired to INT A.
319 * 0 - Function 1 intr line wired to INT B.
320 *
321 * Note: Adapter boards always have Function 0
322 * wired to INTA.
323 * Put all 5 GPIO bits in input mode and then
324 * read their input values.
325 */
326 ADW_WRITE_BYTE_REGISTER(iot, ioh,
327 IOPB_GPIO_CNTL, 0);
328 if (ADW_READ_BYTE_REGISTER(iot, ioh,
329 IOPB_GPIO_DATA) & 0x01) {
330 /*
331 * Function 1 interrupt wired to INTA;
332 * Set EEPROM bit.
333 */
334 lsw_msb |= (ADW_EEPROM_INTAB >> 8)
335 & 0xFF;
336 }
337 eep_config.cfg_lsw &= 0x00FF;
338 eep_config.cfg_lsw |= lsw_msb << 8;
339 }
340 break;
341 }
342
343 /*
344 * Assume the 6 byte board serial number that was read
345 * from EEPROM is correct even if the EEPROM checksum
346 * failed.
347 */
348 for (i=2, j=1; i>=0; i--, j++) {
349 eep_config.serial_number[i] =
350 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j);
351 }
352
353 AdwSetEEPROMConfig(iot, ioh, &eep_config);
354 }
355 /*
356 * Set sc and sc->cfg variables from the EEPROM configuration
357 * that was read.
358 *
359 * This is the mapping of EEPROM fields to Adw Library fields.
360 */
361 sc->wdtr_able = eep_config.wdtr_able;
362 if (sc->chip_type == ADW_CHIP_ASC3550) {
363 sc->sdtr_able = eep_config.sdtr1.sdtr_able;
364 sc->ultra_able = eep_config.sdtr2.ultra_able;
365 } else {
366 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1;
367 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2;
368 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3;
369 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4;
370 }
371 sc->ppr_able = 0;
372 sc->tagqng_able = eep_config.tagqng_able;
373 sc->cfg.disc_enable = eep_config.disc_enable;
374 sc->max_host_qng = eep_config.max_host_qng;
375 sc->max_dvc_qng = eep_config.max_dvc_qng;
376 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
377 sc->start_motor = eep_config.start_motor;
378 sc->scsi_reset_wait = eep_config.scsi_reset_delay;
379 sc->bios_ctrl = eep_config.bios_ctrl;
380 sc->no_scam = eep_config.scam_tolerant;
381 sc->cfg.serial1 = eep_config.serial_number[0];
382 sc->cfg.serial2 = eep_config.serial_number[1];
383 sc->cfg.serial3 = eep_config.serial_number[2];
384
385 if (sc->chip_type == ADW_CHIP_ASC38C0800 ||
386 sc->chip_type == ADW_CHIP_ASC38C1600) {
387 sc->sdtr_able = 0;
388 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
389 if (tid == 0) {
390 sdtr_speed = sc->sdtr_speed1;
391 } else if (tid == 4) {
392 sdtr_speed = sc->sdtr_speed2;
393 } else if (tid == 8) {
394 sdtr_speed = sc->sdtr_speed3;
395 } else if (tid == 12) {
396 sdtr_speed = sc->sdtr_speed4;
397 }
398 if (sdtr_speed & ADW_MAX_TID) {
399 sc->sdtr_able |= (1 << tid);
400 }
401 sdtr_speed >>= 4;
402 }
403 }
404
405 /*
406 * Set the host maximum queuing (max. 253, min. 16) and the per device
407 * maximum queuing (max. 63, min. 4).
408 */
409 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) {
410 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
411 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG)
412 {
413 /* If the value is zero, assume it is uninitialized. */
414 if (eep_config.max_host_qng == 0) {
415 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
416 } else {
417 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG;
418 }
419 }
420
421 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) {
422 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
423 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) {
424 /* If the value is zero, assume it is uninitialized. */
425 if (eep_config.max_dvc_qng == 0) {
426 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
427 } else {
428 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG;
429 }
430 }
431
432 /*
433 * If 'max_dvc_qng' is greater than 'max_host_qng', then
434 * set 'max_dvc_qng' to 'max_host_qng'.
435 */
436 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
437 eep_config.max_dvc_qng = eep_config.max_host_qng;
438 }
439
440 /*
441 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
442 * values based on possibly adjusted EEPROM values.
443 */
444 sc->max_host_qng = eep_config.max_host_qng;
445 sc->max_dvc_qng = eep_config.max_dvc_qng;
446
447
448 /*
449 * If the EEPROM 'termination' field is set to automatic (0), then set
450 * the ADV_DVC_CFG 'termination' field to automatic also.
451 *
452 * If the termination is specified with a non-zero 'termination'
453 * value check that a legal value is set and set the ADV_DVC_CFG
454 * 'termination' field appropriately.
455 */
456
457 switch(sc->chip_type) {
458 case ADW_CHIP_ASC3550:
459 sc->cfg.termination = 0; /* auto termination */
460 switch(eep_config.termination_se) {
461 case 3:
462 /* Enable manual control with low on / high on. */
463 sc->cfg.termination |= ADW_TERM_CTL_L;
464 case 2:
465 /* Enable manual control with low off / high on. */
466 sc->cfg.termination |= ADW_TERM_CTL_H;
467 case 1:
468 /* Enable manual control with low off / high off. */
469 sc->cfg.termination |= ADW_TERM_CTL_SEL;
470 case 0:
471 break;
472 default:
473 warn_code |= ADW_WARN_EEPROM_TERMINATION;
474 }
475 break;
476
477 case ADW_CHIP_ASC38C0800:
478 case ADW_CHIP_ASC38C1600:
479 switch(eep_config.termination_se) {
480 case 0:
481 /* auto termination for SE */
482 termination = 0;
483 break;
484 case 1:
485 /* Enable manual control with low off / high off. */
486 termination = 0;
487 break;
488 case 2:
489 /* Enable manual control with low off / high on. */
490 termination = ADW_TERM_SE_HI;
491 break;
492 case 3:
493 /* Enable manual control with low on / high on. */
494 termination = ADW_TERM_SE;
495 break;
496 default:
497 /*
498 * The EEPROM 'termination_se' field contains a
499 * bad value. Use automatic termination instead.
500 */
501 termination = 0;
502 warn_code |= ADW_WARN_EEPROM_TERMINATION;
503 }
504
505 switch(eep_config.termination_lvd) {
506 case 0:
507 /* auto termination for LVD */
508 sc->cfg.termination = termination;
509 break;
510 case 1:
511 /* Enable manual control with low off / high off. */
512 sc->cfg.termination = termination;
513 break;
514 case 2:
515 /* Enable manual control with low off / high on. */
516 sc->cfg.termination = termination | ADW_TERM_LVD_HI;
517 break;
518 case 3:
519 /* Enable manual control with low on / high on. */
520 sc->cfg.termination = termination | ADW_TERM_LVD;
521 break;
522 default:
523 /*
524 * The EEPROM 'termination_lvd' field contains a
525 * bad value. Use automatic termination instead.
526 */
527 sc->cfg.termination = termination;
528 warn_code |= ADW_WARN_EEPROM_TERMINATION;
529 }
530 break;
531 }
532
533 return warn_code;
534 }
535
536
537 /*
538 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600.
539 *
540 * On failure return the error code.
541 */
542 int
543 AdwInitDriver(sc)
544 ADW_SOFTC *sc;
545 {
546 bus_space_tag_t iot = sc->sc_iot;
547 bus_space_handle_t ioh = sc->sc_ioh;
548 u_int16_t error_code;
549 int word;
550 int i;
551 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory
552 0x40-0x8F. */
553 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able;
554 u_int8_t max_cmd[ADW_MAX_TID + 1];
555 u_int8_t tid;
556
557
558 error_code = 0;
559
560 /*
561 * Save the RISC memory BIOS region before writing the microcode.
562 * The BIOS may already be loaded and using its RISC LRAM region
563 * so its region must be saved and restored.
564 *
565 * Note: This code makes the assumption, which is currently true,
566 * that a chip reset does not clear RISC LRAM.
567 */
568 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
569 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]);
570 }
571
572 /*
573 * Save current per TID negotiated values.
574 */
575 switch (sc->chip_type) {
576 case ADW_CHIP_ASC3550:
577 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){
578
579 u_int16_t bios_version, major, minor;
580
581 bios_version = bios_mem[(ADW_MC_BIOS_VERSION -
582 ADW_MC_BIOSMEM) / 2];
583 major = (bios_version >> 12) & 0xF;
584 minor = (bios_version >> 8) & 0xF;
585 if (major < 3 || (major == 3 && minor == 1)) {
586 /*
587 * BIOS 3.1 and earlier location of
588 * 'wdtr_able' variable.
589 */
590 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able);
591 } else {
592 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
593 wdtr_able);
594 }
595 }
596 break;
597
598 case ADW_CHIP_ASC38C1600:
599 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
600 /* FALLTHROUGH */
601 case ADW_CHIP_ASC38C0800:
602 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
603 break;
604 }
605 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
606 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
607 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
608 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
609 max_cmd[tid]);
610 }
611
612 /*
613 * Perform a RAM Built-In Self Test
614 */
615 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) {
616 return error_code;
617 }
618
619 /*
620 * Load the Microcode
621 */
622 ;
623 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) {
624 return error_code;
625 }
626
627 /*
628 * Read microcode version and date.
629 */
630 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date);
631 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version);
632
633 /*
634 * If the PCI Configuration Command Register "Parity Error Response
635 * Control" Bit was clear (0), then set the microcode variable
636 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
637 * to ignore DMA parity errors.
638 */
639 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) {
640 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
641 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
642 word | CONTROL_FLAG_IGNORE_PERR);
643 }
644
645 switch (sc->chip_type) {
646 case ADW_CHIP_ASC3550:
647 /*
648 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a
649 * FIFO threshold of 128 bytes.
650 * This register is only accessible to the host.
651 */
652 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
653 START_CTL_EMFU | READ_CMD_MRM);
654 break;
655
656 case ADW_CHIP_ASC38C0800:
657 /*
658 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
659 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
660 * cable detection and then we are able to read C_DET[3:0].
661 *
662 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
663 * Microcode Default Value' section below.
664 */
665 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
666 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
667 | ADW_DIS_TERM_DRV);
668
669 /*
670 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
671 * START_CTL_TH [3:2] bits for the default FIFO threshold.
672 *
673 * Note: ASC-38C0800 FIFO threshold has been changed to
674 * 256 bytes.
675 *
676 * For DMA Errata #4 set the BC_THRESH_ENB bit.
677 */
678 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
679 BC_THRESH_ENB | FIFO_THRESH_80B
680 | START_CTL_TH | READ_CMD_MRM);
681 break;
682
683 case ADW_CHIP_ASC38C1600:
684 /*
685 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
686 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
687 * cable detection and then we are able to read C_DET[3:0].
688 *
689 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
690 * Microcode Default Value' section below.
691 */
692 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
693 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
694 | ADW_DIS_TERM_DRV);
695
696 /*
697 * If the BIOS control flag AIPP (Asynchronous Information
698 * Phase Protection) disable bit is not set, then set the
699 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to
700 * enable AIPP checking and encoding.
701 */
702 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
703 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
704 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
705 word | CONTROL_FLAG_ENABLE_AIPP);
706 }
707
708 /*
709 * For ASC-38C1600 use DMA_CFG0 default values:
710 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2].
711 */
712 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
713 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
714 break;
715 }
716
717 /*
718 * Microcode operating variables for WDTR, SDTR, and command tag
719 * queuing will be set in AdvInquiryHandling() based on what a
720 * device reports it is capable of in Inquiry byte 7.
721 *
722 * If SCSI Bus Resets have been disabled, then directly set
723 * SDTR and WDTR from the EEPROM configuration. This will allow
724 * the BIOS and warm boot to work without a SCSI bus hang on
725 * the Inquiry caused by host and target mismatched DTR values.
726 * Without the SCSI Bus Reset, before an Inquiry a device can't
727 * be assumed to be in Asynchronous, Narrow mode.
728 */
729 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
730 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able);
731 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able);
732 }
733
734 /*
735 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
736 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
737 * bitmask. These values determine the maximum SDTR speed negotiated
738 * with a device.
739 *
740 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
741 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
742 * without determining here whether the device supports SDTR.
743 */
744 switch (sc->chip_type) {
745 case ADW_CHIP_ASC3550:
746 word = 0;
747 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
748 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) {
749 /* Set Ultra speed for TID 'tid'. */
750 word |= (0x3 << (4 * (tid % 4)));
751 } else {
752 /* Set Fast speed for TID 'tid'. */
753 word |= (0x2 << (4 * (tid % 4)));
754 }
755 /* Check if done with sdtr_speed1. */
756 if (tid == 3) {
757 ADW_WRITE_WORD_LRAM(iot, ioh,
758 ADW_MC_SDTR_SPEED1, word);
759 word = 0;
760 /* Check if done with sdtr_speed2. */
761 } else if (tid == 7) {
762 ADW_WRITE_WORD_LRAM(iot, ioh,
763 ADW_MC_SDTR_SPEED2, word);
764 word = 0;
765 /* Check if done with sdtr_speed3. */
766 } else if (tid == 11) {
767 ADW_WRITE_WORD_LRAM(iot, ioh,
768 ADW_MC_SDTR_SPEED3, word);
769 word = 0;
770 /* Check if done with sdtr_speed4. */
771 } else if (tid == 15) {
772 ADW_WRITE_WORD_LRAM(iot, ioh,
773 ADW_MC_SDTR_SPEED4, word);
774 /* End of loop. */
775 }
776 }
777
778 /*
779 * Set microcode operating variable for the
780 * disconnect per TID bitmask.
781 */
782 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
783 sc->cfg.disc_enable);
784 break;
785
786 case ADW_CHIP_ASC38C0800:
787 /* FALLTHROUGH */
788 case ADW_CHIP_ASC38C1600:
789 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
790 sc->cfg.disc_enable);
791 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1,
792 sc->sdtr_speed1);
793 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2,
794 sc->sdtr_speed2);
795 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3,
796 sc->sdtr_speed3);
797 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4,
798 sc->sdtr_speed4);
799 break;
800 }
801
802
803 /*
804 * Set SCSI_CFG0 Microcode Default Value.
805 *
806 * The microcode will set the SCSI_CFG0 register using this value
807 * after it is started below.
808 */
809 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0,
810 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG |
811 ADW_OUR_ID_EN | sc->chip_scsi_id);
812
813
814 switch(sc->chip_type) {
815 case ADW_CHIP_ASC3550:
816 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg);
817 break;
818
819 case ADW_CHIP_ASC38C0800:
820 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg);
821 break;
822
823 case ADW_CHIP_ASC38C1600:
824 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg);
825 break;
826 }
827 if(error_code) {
828 return error_code;
829 }
830
831 /*
832 * Set SEL_MASK Microcode Default Value
833 *
834 * The microcode will set the SEL_MASK register using this value
835 * after it is started below.
836 */
837 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK,
838 ADW_TID_TO_TIDMASK(sc->chip_scsi_id));
839
840 /*
841 * Create and Initialize Host->RISC Carrier lists
842 */
843 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier,
844 sc->sc_control->carriers);
845
846 /*
847 * Set-up the Host->RISC Initiator Command Queue (ICQ).
848 */
849
850 if ((sc->icq_sp = sc->carr_freelist) == NULL) {
851 return ADW_IERR_NO_CARRIER;
852 }
853 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
854 ASC_GET_CARRP(sc->icq_sp->next_ba));
855
856 /*
857 * The first command issued will be placed in the stopper carrier.
858 */
859 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER);
860
861 /*
862 * Set RISC ICQ physical address start value.
863 */
864 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba));
865
866 /*
867 * Initialize the COMMA register to the same value otherwise
868 * the RISC will prematurely detect a command is available.
869 */
870 if(sc->chip_type == ADW_CHIP_ASC38C1600) {
871 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
872 le32toh(sc->icq_sp->carr_ba));
873 }
874
875 /*
876 * Set-up the RISC->Host Initiator Response Queue (IRQ).
877 */
878 if ((sc->irq_sp = sc->carr_freelist) == NULL) {
879 return ADW_IERR_NO_CARRIER;
880 }
881 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
882 ASC_GET_CARRP(sc->irq_sp->next_ba));
883
884 /*
885 * The first command completed by the RISC will be placed in
886 * the stopper.
887 *
888 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is
889 * completed the RISC will set the ASC_RQ_DONE bit.
890 */
891 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER);
892
893 /*
894 * Set RISC IRQ physical address start value.
895 */
896 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba));
897 sc->carr_pending_cnt = 0;
898
899 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES,
900 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR));
901 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word);
902 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word);
903
904 /* finally, finally, gentlemen, start your engine */
905 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN);
906
907 /*
908 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
909 * Resets should be performed. The RISC has to be running
910 * to issue a SCSI Bus Reset.
911 */
912 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
913 {
914 /*
915 * If the BIOS Signature is present in memory, restore the
916 * BIOS Handshake Configuration Table and do not perform
917 * a SCSI Bus Reset.
918 */
919 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] ==
920 0x55AA) {
921 /*
922 * Restore per TID negotiated values.
923 */
924 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
925 wdtr_able);
926 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
927 sdtr_able);
928 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
929 tagqng_able);
930 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
931 ADW_WRITE_BYTE_LRAM(iot, ioh,
932 ADW_MC_NUMBER_OF_MAX_CMD + tid,
933 max_cmd[tid]);
934 }
935 } else {
936 if (AdwResetCCB(sc) != ADW_TRUE) {
937 error_code = ADW_WARN_BUSRESET_ERROR;
938 }
939 }
940 }
941
942 return error_code;
943 }
944
945
946 int
947 AdwRamSelfTest(iot, ioh, chip_type)
948 bus_space_tag_t iot;
949 bus_space_handle_t ioh;
950 u_int8_t chip_type;
951 {
952 int i;
953 u_int8_t byte;
954
955
956 if ((chip_type == ADW_CHIP_ASC38C0800) ||
957 (chip_type == ADW_CHIP_ASC38C1600)) {
958 /*
959 * RAM BIST (RAM Built-In Self Test)
960 *
961 * Address : I/O base + offset 0x38h register (byte).
962 * Function: Bit 7-6(RW) : RAM mode
963 * Normal Mode : 0x00
964 * Pre-test Mode : 0x40
965 * RAM Test Mode : 0x80
966 * Bit 5 : unused
967 * Bit 4(RO) : Done bit
968 * Bit 3-0(RO) : Status
969 * Host Error : 0x08
970 * Int_RAM Error : 0x04
971 * RISC Error : 0x02
972 * SCSI Error : 0x01
973 * No Error : 0x00
974 *
975 * Note: RAM BIST code should be put right here, before loading
976 * the microcode and after saving the RISC memory BIOS region.
977 */
978
979 /*
980 * LRAM Pre-test
981 *
982 * Write PRE_TEST_MODE (0x40) to register and wait for
983 * 10 milliseconds.
984 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05),
985 * return an error. Reset to NORMAL_MODE (0x00) and do again.
986 * If cannot reset to NORMAL_MODE, return an error too.
987 */
988 for (i = 0; i < 2; i++) {
989 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
990 PRE_TEST_MODE);
991 /* Wait for 10ms before reading back. */
992 AdwSleepMilliSecond(10);
993 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
994 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) !=
995 PRE_TEST_VALUE) {
996 return ADW_IERR_BIST_PRE_TEST;
997 }
998
999 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
1000 NORMAL_MODE);
1001 /* Wait for 10ms before reading back. */
1002 AdwSleepMilliSecond(10);
1003 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST)
1004 != NORMAL_VALUE) {
1005 return ADW_IERR_BIST_PRE_TEST;
1006 }
1007 }
1008
1009 /*
1010 * LRAM Test - It takes about 1.5 ms to run through the test.
1011 *
1012 * Write RAM_TEST_MODE (0x80) to register and wait for
1013 * 10 milliseconds.
1014 * If Done bit not set or Status not 0, save register byte,
1015 * set the err_code, and return an error.
1016 */
1017 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE);
1018 /* Wait for 10ms before checking status. */
1019 AdwSleepMilliSecond(10);
1020
1021 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
1022 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) {
1023 /* Get here if Done bit not set or Status not 0. */
1024 return ADW_IERR_BIST_RAM_TEST;
1025 }
1026
1027 /* We need to reset back to normal mode after LRAM test passes*/
1028 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE);
1029 }
1030
1031 return 0;
1032 }
1033
1034
1035 int
1036 AdwLoadMCode(iot, ioh, bios_mem, chip_type)
1037 bus_space_tag_t iot;
1038 bus_space_handle_t ioh;
1039 u_int16_t *bios_mem;
1040 u_int8_t chip_type;
1041 {
1042 u_int8_t *mcode_data;
1043 u_int32_t mcode_chksum;
1044 u_int16_t mcode_size;
1045 u_int32_t sum;
1046 u_int16_t code_sum;
1047 int begin_addr;
1048 int end_addr;
1049 int word;
1050 int adw_memsize;
1051 int adw_mcode_expanded_size;
1052 int i, j;
1053
1054
1055 switch(chip_type) {
1056 case ADW_CHIP_ASC3550:
1057 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data;
1058 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum;
1059 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size;
1060 adw_memsize = ADW_3550_MEMSIZE;
1061 break;
1062
1063 case ADW_CHIP_ASC38C0800:
1064 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data;
1065 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum;
1066 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size;
1067 adw_memsize = ADW_38C0800_MEMSIZE;
1068 break;
1069
1070 case ADW_CHIP_ASC38C1600:
1071 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data;
1072 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum;
1073 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size;
1074 adw_memsize = ADW_38C1600_MEMSIZE;
1075 break;
1076 }
1077
1078 /*
1079 * Write the microcode image to RISC memory starting at address 0.
1080 */
1081 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1082
1083 /* Assume the following compressed format of the microcode buffer:
1084 *
1085 * 254 word (508 byte) table indexed by byte code followed
1086 * by the following byte codes:
1087 *
1088 * 1-Byte Code:
1089 * 00: Emit word 0 in table.
1090 * 01: Emit word 1 in table.
1091 * .
1092 * FD: Emit word 253 in table.
1093 *
1094 * Multi-Byte Code:
1095 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
1096 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
1097 */
1098 word = 0;
1099 for (i = 253 * 2; i < mcode_size; i++) {
1100 if (mcode_data[i] == 0xff) {
1101 for (j = 0; j < mcode_data[i + 1]; j++) {
1102 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1103 (((u_int16_t)mcode_data[i + 3] << 8) |
1104 mcode_data[i + 2]));
1105 word++;
1106 }
1107 i += 3;
1108 } else if (mcode_data[i] == 0xfe) {
1109 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1110 (((u_int16_t)mcode_data[i + 2] << 8) |
1111 mcode_data[i + 1]));
1112 i += 2;
1113 word++;
1114 } else {
1115 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t)
1116 mcode_data[(mcode_data[i] * 2) + 1] <<8) |
1117 mcode_data[mcode_data[i] * 2]));
1118 word++;
1119 }
1120 }
1121
1122 /*
1123 * Set 'word' for later use to clear the rest of memory and save
1124 * the expanded mcode size.
1125 */
1126 word *= 2;
1127 adw_mcode_expanded_size = word;
1128
1129 /*
1130 * Clear the rest of the Internal RAM.
1131 */
1132 for (; word < adw_memsize; word += 2) {
1133 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0);
1134 }
1135
1136 /*
1137 * Verify the microcode checksum.
1138 */
1139 sum = 0;
1140 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1141
1142 for (word = 0; word < adw_mcode_expanded_size; word += 2) {
1143 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1144 }
1145
1146 if (sum != mcode_chksum) {
1147 return ADW_IERR_MCODE_CHKSUM;
1148 }
1149
1150 /*
1151 * Restore the RISC memory BIOS region.
1152 */
1153 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
1154 if(chip_type == ADW_CHIP_ASC3550) {
1155 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1156 bios_mem[i]);
1157 } else {
1158 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1159 bios_mem[i]);
1160 }
1161 }
1162
1163 /*
1164 * Calculate and write the microcode code checksum to the microcode
1165 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C).
1166 */
1167 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr);
1168 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr);
1169 code_sum = 0;
1170 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr);
1171 for (word = begin_addr; word < end_addr; word += 2) {
1172 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1173 }
1174 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum);
1175
1176 /*
1177 * Set the chip type.
1178 */
1179 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type);
1180
1181 return 0;
1182 }
1183
1184
1185 int
1186 AdwASC3550Cabling(iot, ioh, cfg)
1187 bus_space_tag_t iot;
1188 bus_space_handle_t ioh;
1189 ADW_DVC_CFG *cfg;
1190 {
1191 u_int16_t scsi_cfg1;
1192
1193
1194 /*
1195 * Determine SCSI_CFG1 Microcode Default Value.
1196 *
1197 * The microcode will set the SCSI_CFG1 register using this value
1198 * after it is started below.
1199 */
1200
1201 /* Read current SCSI_CFG1 Register value. */
1202 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1203
1204 /*
1205 * If all three connectors are in use in ASC3550, return an error.
1206 */
1207 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
1208 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
1209 return ADW_IERR_ILLEGAL_CONNECTION;
1210 }
1211
1212 /*
1213 * If the cable is reversed all of the SCSI_CTRL register signals
1214 * will be set. Check for and return an error if this condition is
1215 * found.
1216 */
1217 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1218 return ADW_IERR_REVERSED_CABLE;
1219 }
1220
1221 /*
1222 * If this is a differential board and a single-ended device
1223 * is attached to one of the connectors, return an error.
1224 */
1225 if ((scsi_cfg1 & ADW_DIFF_MODE) &&
1226 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) {
1227 return ADW_IERR_SINGLE_END_DEVICE;
1228 }
1229
1230 /*
1231 * If automatic termination control is enabled, then set the
1232 * termination value based on a table listed in a_condor.h.
1233 *
1234 * If manual termination was specified with an EEPROM setting
1235 * then 'termination' was set-up in AdwInitFromEEPROM() and
1236 * is ready to be 'ored' into SCSI_CFG1.
1237 */
1238 if (cfg->termination == 0) {
1239 /*
1240 * The software always controls termination by setting
1241 * TERM_CTL_SEL.
1242 * If TERM_CTL_SEL were set to 0, the hardware would set
1243 * termination.
1244 */
1245 cfg->termination |= ADW_TERM_CTL_SEL;
1246
1247 switch(scsi_cfg1 & ADW_CABLE_DETECT) {
1248 /* TERM_CTL_H: on, TERM_CTL_L: on */
1249 case 0x3: case 0x7: case 0xB:
1250 case 0xD: case 0xE: case 0xF:
1251 cfg->termination |=
1252 (ADW_TERM_CTL_H | ADW_TERM_CTL_L);
1253 break;
1254
1255 /* TERM_CTL_H: on, TERM_CTL_L: off */
1256 case 0x1: case 0x5: case 0x9:
1257 case 0xA: case 0xC:
1258 cfg->termination |= ADW_TERM_CTL_H;
1259 break;
1260
1261 /* TERM_CTL_H: off, TERM_CTL_L: off */
1262 case 0x2: case 0x6:
1263 break;
1264 }
1265 }
1266
1267 /*
1268 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
1269 */
1270 scsi_cfg1 &= ~ADW_TERM_CTL;
1271
1272 /*
1273 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
1274 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
1275 * referenced, because the hardware internally inverts
1276 * the Termination High and Low bits if TERM_POL is set.
1277 */
1278 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL));
1279
1280 /*
1281 * Set SCSI_CFG1 Microcode Default Value
1282 *
1283 * Set filter value and possibly modified termination control
1284 * bits in the Microcode SCSI_CFG1 Register Value.
1285 *
1286 * The microcode will set the SCSI_CFG1 register using this value
1287 * after it is started below.
1288 */
1289 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1,
1290 ADW_FLTR_DISABLE | scsi_cfg1);
1291
1292 /*
1293 * Set MEM_CFG Microcode Default Value
1294 *
1295 * The microcode will set the MEM_CFG register using this value
1296 * after it is started below.
1297 *
1298 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1299 * are defined.
1300 *
1301 * ASC-3550 has 8KB internal memory.
1302 */
1303 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1304 ADW_BIOS_EN | ADW_RAM_SZ_8KB);
1305
1306 return 0;
1307 }
1308
1309
1310 int
1311 AdwASC38C0800Cabling(iot, ioh, cfg)
1312 bus_space_tag_t iot;
1313 bus_space_handle_t ioh;
1314 ADW_DVC_CFG *cfg;
1315 {
1316 u_int16_t scsi_cfg1;
1317
1318
1319 /*
1320 * Determine SCSI_CFG1 Microcode Default Value.
1321 *
1322 * The microcode will set the SCSI_CFG1 register using this value
1323 * after it is started below.
1324 */
1325
1326 /* Read current SCSI_CFG1 Register value. */
1327 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1328
1329 /*
1330 * If the cable is reversed all of the SCSI_CTRL register signals
1331 * will be set. Check for and return an error if this condition is
1332 * found.
1333 */
1334 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1335 return ADW_IERR_REVERSED_CABLE;
1336 }
1337
1338 /*
1339 * All kind of combinations of devices attached to one of four
1340 * connectors are acceptable except HVD device attached.
1341 * For example, LVD device can be attached to SE connector while
1342 * SE device attached to LVD connector.
1343 * If LVD device attached to SE connector, it only runs up to
1344 * Ultra speed.
1345 *
1346 * If an HVD device is attached to one of LVD connectors, return
1347 * an error.
1348 * However, there is no way to detect HVD device attached to
1349 * SE connectors.
1350 */
1351 if (scsi_cfg1 & ADW_HVD) {
1352 return ADW_IERR_HVD_DEVICE;
1353 }
1354
1355 /*
1356 * If either SE or LVD automatic termination control is enabled, then
1357 * set the termination value based on a table listed in a_condor.h.
1358 *
1359 * If manual termination was specified with an EEPROM setting then
1360 * 'termination' was set-up in AdwInitFromEEPROM() and is ready
1361 * to be 'ored' into SCSI_CFG1.
1362 */
1363 if ((cfg->termination & ADW_TERM_SE) == 0) {
1364 /* SE automatic termination control is enabled. */
1365 switch(scsi_cfg1 & ADW_C_DET_SE) {
1366 /* TERM_SE_HI: on, TERM_SE_LO: on */
1367 case 0x1: case 0x2: case 0x3:
1368 cfg->termination |= ADW_TERM_SE;
1369 break;
1370
1371 /* TERM_SE_HI: on, TERM_SE_LO: off */
1372 case 0x0:
1373 cfg->termination |= ADW_TERM_SE_HI;
1374 break;
1375 }
1376 }
1377
1378 if ((cfg->termination & ADW_TERM_LVD) == 0) {
1379 /* LVD automatic termination control is enabled. */
1380 switch(scsi_cfg1 & ADW_C_DET_LVD) {
1381 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
1382 case 0x4: case 0x8: case 0xC:
1383 cfg->termination |= ADW_TERM_LVD;
1384 break;
1385
1386 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
1387 case 0x0:
1388 break;
1389 }
1390 }
1391
1392 /*
1393 * Clear any set TERM_SE and TERM_LVD bits.
1394 */
1395 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD);
1396
1397 /*
1398 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
1399 */
1400 scsi_cfg1 |= (~cfg->termination & 0xF0);
1401
1402 /*
1403 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and
1404 * HVD/LVD/SE bits and set possibly modified termination control bits
1405 * in the Microcode SCSI_CFG1 Register Value.
1406 */
1407 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV &
1408 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE);
1409
1410 /*
1411 * Set SCSI_CFG1 Microcode Default Value
1412 *
1413 * Set possibly modified termination control and reset DIS_TERM_DRV
1414 * bits in the Microcode SCSI_CFG1 Register Value.
1415 *
1416 * The microcode will set the SCSI_CFG1 register using this value
1417 * after it is started below.
1418 */
1419 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1420
1421 /*
1422 * Set MEM_CFG Microcode Default Value
1423 *
1424 * The microcode will set the MEM_CFG register using this value
1425 * after it is started below.
1426 *
1427 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1428 * are defined.
1429 *
1430 * ASC-38C0800 has 16KB internal memory.
1431 */
1432 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1433 ADW_BIOS_EN | ADW_RAM_SZ_16KB);
1434
1435 return 0;
1436 }
1437
1438
1439 int
1440 AdwASC38C1600Cabling(iot, ioh, cfg)
1441 bus_space_tag_t iot;
1442 bus_space_handle_t ioh;
1443 ADW_DVC_CFG *cfg;
1444 {
1445 u_int16_t scsi_cfg1;
1446
1447
1448 /*
1449 * Determine SCSI_CFG1 Microcode Default Value.
1450 *
1451 * The microcode will set the SCSI_CFG1 register using this value
1452 * after it is started below.
1453 * Each ASC-38C1600 function has only two cable detect bits.
1454 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
1455 */
1456
1457 /* Read current SCSI_CFG1 Register value. */
1458 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1459
1460 /*
1461 * If the cable is reversed all of the SCSI_CTRL register signals
1462 * will be set. Check for and return an error if this condition is
1463 * found.
1464 */
1465 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1466 return ADW_IERR_REVERSED_CABLE;
1467 }
1468
1469 /*
1470 * Each ASC-38C1600 function has two connectors. Only an HVD device
1471 * can not be connected to either connector. An LVD device or SE device
1472 * may be connected to either connecor. If an SE device is connected,
1473 * then at most Ultra speed (20 Mhz) can be used on both connectors.
1474 *
1475 * If an HVD device is attached, return an error.
1476 */
1477 if (scsi_cfg1 & ADW_HVD) {
1478 return ADW_IERR_HVD_DEVICE;
1479 }
1480
1481 /*
1482 * Each function in the ASC-38C1600 uses only the SE cable detect and
1483 * termination because there are two connectors for each function.
1484 * Each function may use either LVD or SE mode.
1485 * Corresponding the SE automatic termination control EEPROM bits are
1486 * used for each function.
1487 * Each function has its own EEPROM. If SE automatic control is enabled
1488 * for the function, then set the termination value based on a table
1489 * listed in adwlib.h.
1490 *
1491 * If manual termination is specified in the EEPROM for the function,
1492 * then 'termination' was set-up in AdwInitFromEEPROM() and is
1493 * ready to be 'ored' into SCSI_CFG1.
1494 */
1495 if ((cfg->termination & ADW_TERM_SE) == 0) {
1496 /* SE automatic termination control is enabled. */
1497 switch(scsi_cfg1 & ADW_C_DET_SE) {
1498 /* TERM_SE_HI: on, TERM_SE_LO: on */
1499 case 0x1: case 0x2: case 0x3:
1500 cfg->termination |= ADW_TERM_SE;
1501 break;
1502
1503 case 0x0:
1504 #if 0
1505 /* !!!!TODO!!!! */
1506 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) {
1507 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
1508 }
1509 else
1510 #endif
1511 {
1512 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
1513 cfg->termination |= ADW_TERM_SE_HI;
1514 }
1515 break;
1516 }
1517 }
1518
1519 /*
1520 * Clear any set TERM_SE bits.
1521 */
1522 scsi_cfg1 &= ~ADW_TERM_SE;
1523
1524 /*
1525 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
1526 */
1527 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE);
1528
1529 /*
1530 * Clear Big Endian and Terminator Polarity bits and set possibly
1531 * modified termination control bits in the Microcode SCSI_CFG1
1532 * Register Value.
1533 */
1534 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL);
1535
1536 /*
1537 * Set SCSI_CFG1 Microcode Default Value
1538 *
1539 * Set possibly modified termination control bits in the Microcode
1540 * SCSI_CFG1 Register Value.
1541 *
1542 * The microcode will set the SCSI_CFG1 register using this value
1543 * after it is started below.
1544 */
1545 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1546
1547 /*
1548 * Set MEM_CFG Microcode Default Value
1549 *
1550 * The microcode will set the MEM_CFG register using this value
1551 * after it is started below.
1552 *
1553 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1554 * are defined.
1555 *
1556 * ASC-38C1600 has 32KB internal memory.
1557 */
1558 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1559 ADW_BIOS_EN | ADW_RAM_SZ_32KB);
1560
1561 return 0;
1562 }
1563
1564
1565 /*
1566 * Read EEPROM configuration into the specified buffer.
1567 *
1568 * Return a checksum based on the EEPROM configuration read.
1569 */
1570 static u_int16_t
1571 AdwGetEEPROMConfig(iot, ioh, cfg_buf)
1572 bus_space_tag_t iot;
1573 bus_space_handle_t ioh;
1574 ADW_EEPROM *cfg_buf;
1575 {
1576 u_int16_t wval, chksum;
1577 u_int16_t *wbuf;
1578 int eep_addr;
1579
1580
1581 wbuf = (u_int16_t *) cfg_buf;
1582 chksum = 0;
1583
1584 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN;
1585 eep_addr < ASC_EEP_DVC_CFG_END;
1586 eep_addr++, wbuf++) {
1587 wval = AdwReadEEPWord(iot, ioh, eep_addr);
1588 chksum += wval;
1589 *wbuf = wval;
1590 }
1591
1592 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1593 wbuf++;
1594 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN;
1595 eep_addr < ASC_EEP_MAX_WORD_ADDR;
1596 eep_addr++, wbuf++) {
1597 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1598 }
1599
1600 return chksum;
1601 }
1602
1603
1604 /*
1605 * Read the EEPROM from specified location
1606 */
1607 static u_int16_t
1608 AdwReadEEPWord(iot, ioh, eep_word_addr)
1609 bus_space_tag_t iot;
1610 bus_space_handle_t ioh;
1611 int eep_word_addr;
1612 {
1613 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1614 ASC_EEP_CMD_READ | eep_word_addr);
1615 AdwWaitEEPCmd(iot, ioh);
1616
1617 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA);
1618 }
1619
1620
1621 /*
1622 * Wait for EEPROM command to complete
1623 */
1624 static void
1625 AdwWaitEEPCmd(iot, ioh)
1626 bus_space_tag_t iot;
1627 bus_space_handle_t ioh;
1628 {
1629 int eep_delay_ms;
1630
1631
1632 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){
1633 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) &
1634 ASC_EEP_CMD_DONE) {
1635 break;
1636 }
1637 AdwSleepMilliSecond(1);
1638 }
1639
1640 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD);
1641 }
1642
1643
1644 /*
1645 * Write the EEPROM from 'cfg_buf'.
1646 */
1647 static void
1648 AdwSetEEPROMConfig(iot, ioh, cfg_buf)
1649 bus_space_tag_t iot;
1650 bus_space_handle_t ioh;
1651 ADW_EEPROM *cfg_buf;
1652 {
1653 u_int16_t *wbuf;
1654 u_int16_t addr, chksum;
1655
1656
1657 wbuf = (u_int16_t *) cfg_buf;
1658 chksum = 0;
1659
1660 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
1661 AdwWaitEEPCmd(iot, ioh);
1662
1663 /*
1664 * Write EEPROM from word 0 to word 20
1665 */
1666 for (addr = ASC_EEP_DVC_CFG_BEGIN;
1667 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) {
1668 chksum += *wbuf;
1669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1670 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1671 ASC_EEP_CMD_WRITE | addr);
1672 AdwWaitEEPCmd(iot, ioh);
1673 AdwSleepMilliSecond(ASC_EEP_DELAY_MS);
1674 }
1675
1676 /*
1677 * Write EEPROM checksum at word 21
1678 */
1679 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum);
1680 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1681 ASC_EEP_CMD_WRITE | addr);
1682 AdwWaitEEPCmd(iot, ioh);
1683 wbuf++; /* skip over check_sum */
1684
1685 /*
1686 * Write EEPROM OEM name at words 22 to 29
1687 */
1688 for (addr = ASC_EEP_DVC_CTL_BEGIN;
1689 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
1690 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1691 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1692 ASC_EEP_CMD_WRITE | addr);
1693 AdwWaitEEPCmd(iot, ioh);
1694 }
1695
1696 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1697 ASC_EEP_CMD_WRITE_DISABLE);
1698 AdwWaitEEPCmd(iot, ioh);
1699
1700 return;
1701 }
1702
1703
1704 /*
1705 * AdwExeScsiQueue() - Send a request to the RISC microcode program.
1706 *
1707 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q,
1708 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
1709 * RISC to notify it a new command is ready to be executed.
1710 *
1711 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
1712 * set to SCSI_MAX_RETRY.
1713 *
1714 * Return:
1715 * ADW_SUCCESS(1) - The request was successfully queued.
1716 * ADW_BUSY(0) - Resource unavailable; Retry again after pending
1717 * request completes.
1718 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure
1719 * host IC error.
1720 */
1721 int
1722 AdwExeScsiQueue(sc, scsiq)
1723 ADW_SOFTC *sc;
1724 ADW_SCSI_REQ_Q *scsiq;
1725 {
1726 bus_space_tag_t iot = sc->sc_iot;
1727 bus_space_handle_t ioh = sc->sc_ioh;
1728 ADW_CCB *ccb;
1729 long req_size;
1730 u_int32_t req_paddr;
1731 ADW_CARRIER *new_carrp;
1732
1733 /*
1734 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID.
1735 */
1736 if (scsiq->target_id > ADW_MAX_TID) {
1737 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
1738 scsiq->done_status = QD_WITH_ERROR;
1739 return ADW_ERROR;
1740 }
1741
1742 /*
1743 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair
1744 */
1745
1746 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1747
1748 /*
1749 * Allocate a carrier and initialize fields.
1750 */
1751 if ((new_carrp = sc->carr_freelist) == NULL) {
1752 return ADW_BUSY;
1753 }
1754 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
1755 ASC_GET_CARRP(new_carrp->next_ba));
1756 sc->carr_pending_cnt++;
1757
1758 /*
1759 * Set the carrier to be a stopper by setting 'next_ba'
1760 * to the stopper value. The current stopper will be changed
1761 * below to point to the new stopper.
1762 */
1763 new_carrp->next_ba = htole32(ASC_CQ_STOPPER);
1764
1765 req_size = sizeof(ADW_SCSI_REQ_Q);
1766 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
1767 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq);
1768
1769 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */
1770 scsiq->scsiq_rptr = htole32(req_paddr);
1771
1772 /*
1773 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian
1774 * order during initialization.
1775 */
1776 scsiq->carr_ba = sc->icq_sp->carr_ba;
1777 scsiq->carr_va = sc->icq_sp->carr_ba;
1778
1779 /*
1780 * Use the current stopper to send the ADW_SCSI_REQ_Q command to
1781 * the microcode. The newly allocated stopper will become the new
1782 * stopper.
1783 */
1784 sc->icq_sp->areq_ba = htole32(req_paddr);
1785
1786 /*
1787 * Set the 'next_ba' pointer for the old stopper to be the
1788 * physical address of the new stopper. The RISC can only
1789 * follow physical addresses.
1790 */
1791 sc->icq_sp->next_ba = new_carrp->carr_ba;
1792
1793 #if ADW_DEBUG
1794 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n",
1795 sc->icq_sp->carr_id,
1796 sc->icq_sp->carr_ba,
1797 sc->icq_sp->areq_ba,
1798 sc->icq_sp->next_ba);
1799 #endif
1800 /*
1801 * Set the host adapter stopper pointer to point to the new carrier.
1802 */
1803 sc->icq_sp = new_carrp;
1804
1805 if (sc->chip_type == ADW_CHIP_ASC3550 ||
1806 sc->chip_type == ADW_CHIP_ASC38C0800) {
1807 /*
1808 * Tickle the RISC to tell it to read its Command Queue Head
1809 * pointer.
1810 */
1811 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A);
1812 if (sc->chip_type == ADW_CHIP_ASC3550) {
1813 /*
1814 * Clear the tickle value. In the ASC-3550 the RISC flag
1815 * command 'clr_tickle_a' does not work unless the host
1816 * value is cleared.
1817 */
1818 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE,
1819 ADW_TICKLE_NOP);
1820 }
1821 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1822 /*
1823 * Notify the RISC a carrier is ready by writing the physical
1824 * address of the new carrier stopper to the COMMA register.
1825 */
1826 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
1827 le32toh(new_carrp->carr_ba));
1828 }
1829
1830 /*
1831 * End of CRITICAL SECTION: Must be protected within splbio/splx pair
1832 */
1833
1834 return ADW_SUCCESS;
1835 }
1836
1837
1838 void
1839 AdwResetChip(iot, ioh)
1840 bus_space_tag_t iot;
1841 bus_space_handle_t ioh;
1842 {
1843
1844 /*
1845 * Reset Chip.
1846 */
1847 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1848 ADW_CTRL_REG_CMD_RESET);
1849 AdwSleepMilliSecond(100);
1850 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1851 ADW_CTRL_REG_CMD_WR_IO_REG);
1852 }
1853
1854
1855 /*
1856 * Reset SCSI Bus and purge all outstanding requests.
1857 *
1858 * Return Value:
1859 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset.
1860 * ADW_FALSE(0) - Microcode command failed.
1861 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC
1862 * may be hung which requires driver recovery.
1863 */
1864 int
1865 AdwResetCCB(sc)
1866 ADW_SOFTC *sc;
1867 {
1868 int status;
1869
1870 /*
1871 * Send the SCSI Bus Reset idle start idle command which asserts
1872 * the SCSI Bus Reset signal.
1873 */
1874 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L);
1875 if (status != ADW_TRUE) {
1876 return status;
1877 }
1878
1879 /*
1880 * Delay for the specified SCSI Bus Reset hold time.
1881 *
1882 * The hold time delay is done on the host because the RISC has no
1883 * microsecond accurate timer.
1884 */
1885 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US);
1886
1887 /*
1888 * Send the SCSI Bus Reset end idle command which de-asserts
1889 * the SCSI Bus Reset signal and purges any pending requests.
1890 */
1891 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L);
1892 if (status != ADW_TRUE) {
1893 return status;
1894 }
1895
1896 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000);
1897
1898 return status;
1899 }
1900
1901
1902 /*
1903 * Reset chip and SCSI Bus.
1904 *
1905 * Return Value:
1906 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
1907 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
1908 */
1909 int
1910 AdwResetSCSIBus(sc)
1911 ADW_SOFTC *sc;
1912 {
1913 bus_space_tag_t iot = sc->sc_iot;
1914 bus_space_handle_t ioh = sc->sc_ioh;
1915 int status;
1916 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able;
1917 u_int8_t tid, max_cmd[ADW_MAX_TID + 1];
1918 u_int16_t bios_sig;
1919
1920
1921 /*
1922 * Save current per TID negotiated values.
1923 */
1924 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1925 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1926 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1927 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1928 }
1929 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1930 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1931 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1932 max_cmd[tid]);
1933 }
1934
1935 /*
1936 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset
1937 * by clearing the BIOS signature word.
1938 * The initialization functions assumes a SCSI Bus Reset is not
1939 * needed if the BIOS signature word is present.
1940 */
1941 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1942 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0);
1943
1944 /*
1945 * Stop chip and reset it.
1946 */
1947 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP);
1948 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1949 ADW_CTRL_REG_CMD_RESET);
1950 AdwSleepMilliSecond(100);
1951 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1952 ADW_CTRL_REG_CMD_WR_IO_REG);
1953
1954 /*
1955 * Reset Adv Library error code, if any, and try
1956 * re-initializing the chip.
1957 * Then translate initialization return value to status value.
1958 */
1959 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE;
1960
1961 /*
1962 * Restore the BIOS signature word.
1963 */
1964 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1965
1966 /*
1967 * Restore per TID negotiated values.
1968 */
1969 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1970 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1971 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1972 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1973 }
1974 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1975 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1976 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1977 max_cmd[tid]);
1978 }
1979
1980 return status;
1981 }
1982
1983
1984 /*
1985 * Adv Library Interrupt Service Routine
1986 *
1987 * This function is called by a driver's interrupt service routine.
1988 * The function disables and re-enables interrupts.
1989 *
1990 * When a microcode idle command is completed, the ADV_DVC_VAR
1991 * 'idle_cmd_done' field is set to ADW_TRUE.
1992 *
1993 * Note: AdwISR() can be called when interrupts are disabled or even
1994 * when there is no hardware interrupt condition present. It will
1995 * always check for completed idle commands and microcode requests.
1996 * This is an important feature that shouldn't be changed because it
1997 * allows commands to be completed from polling mode loops.
1998 *
1999 * Return:
2000 * ADW_TRUE(1) - interrupt was pending
2001 * ADW_FALSE(0) - no interrupt was pending
2002 */
2003 int
2004 AdwISR(sc)
2005 ADW_SOFTC *sc;
2006 {
2007 bus_space_tag_t iot = sc->sc_iot;
2008 bus_space_handle_t ioh = sc->sc_ioh;
2009 u_int8_t int_stat;
2010 u_int16_t target_bit;
2011 ADW_CARRIER *free_carrp/*, *ccb_carr*/;
2012 u_int32_t irq_next_pa;
2013 ADW_SCSI_REQ_Q *scsiq;
2014 ADW_CCB *ccb;
2015 int s;
2016
2017
2018 s = splbio();
2019
2020 /* Reading the register clears the interrupt. */
2021 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG);
2022
2023 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB |
2024 ADW_INTR_STATUS_INTRC)) == 0) {
2025 splx(s);
2026 return ADW_FALSE;
2027 }
2028
2029 /*
2030 * Notify the driver of an asynchronous microcode condition by
2031 * calling the ADV_DVC_VAR.async_callback function. The function
2032 * is passed the microcode ADW_MC_INTRB_CODE byte value.
2033 */
2034 if (int_stat & ADW_INTR_STATUS_INTRB) {
2035 u_int8_t intrb_code;
2036
2037 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code);
2038
2039 if (sc->chip_type == ADW_CHIP_ASC3550 ||
2040 sc->chip_type == ADW_CHIP_ASC38C0800) {
2041 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
2042 sc->carr_pending_cnt != 0) {
2043 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2044 IOPB_TICKLE, ADW_TICKLE_A);
2045 if (sc->chip_type == ADW_CHIP_ASC3550) {
2046 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2047 IOPB_TICKLE, ADW_TICKLE_NOP);
2048 }
2049 }
2050 }
2051
2052 if (sc->async_callback != 0) {
2053 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code);
2054 }
2055 }
2056
2057 /*
2058 * Check if the IRQ stopper carrier contains a completed request.
2059 */
2060 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0)
2061 {
2062 #if ADW_DEBUG
2063 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n",
2064 sc->irq_sp->carr_id,
2065 sc->irq_sp->carr_ba,
2066 sc->irq_sp->areq_ba,
2067 sc->irq_sp->next_ba);
2068 #endif
2069 /*
2070 * Get a pointer to the newly completed ADW_SCSI_REQ_Q
2071 * structure.
2072 * The RISC will have set 'areq_ba' to a virtual address.
2073 *
2074 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr
2075 * field to the carrier ADV_CARR_T.areq_ba field.
2076 * The conversion below complements the conversion of
2077 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue().
2078 */
2079 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba);
2080 scsiq = &ccb->scsiq;
2081 scsiq->ccb_ptr = sc->irq_sp->areq_ba;
2082
2083 /*
2084 * Request finished with good status and the queue was not
2085 * DMAed to host memory by the firmware. Set all status fields
2086 * to indicate good status.
2087 */
2088 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) {
2089 scsiq->done_status = QD_NO_ERROR;
2090 scsiq->host_status = scsiq->scsi_status = 0;
2091 scsiq->data_cnt = 0L;
2092 }
2093
2094 /*
2095 * Advance the stopper pointer to the next carrier
2096 * ignoring the lower four bits. Free the previous
2097 * stopper carrier.
2098 */
2099 free_carrp = sc->irq_sp;
2100 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa));
2101
2102 free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL
2103 : sc->carr_freelist->carr_ba;
2104 sc->carr_freelist = free_carrp;
2105 sc->carr_pending_cnt--;
2106
2107
2108 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id);
2109
2110 /*
2111 * Clear request microcode control flag.
2112 */
2113 scsiq->cntl = 0;
2114
2115 /*
2116 * Check Condition handling
2117 */
2118 /*
2119 * If the command that completed was a SCSI INQUIRY and
2120 * LUN 0 was sent the command, then process the INQUIRY
2121 * command information for the device.
2122 */
2123 if (scsiq->done_status == QD_NO_ERROR &&
2124 scsiq->cdb[0] == INQUIRY &&
2125 scsiq->target_lun == 0) {
2126 AdwInquiryHandling(sc, scsiq);
2127 }
2128
2129 /*
2130 * Notify the driver of the completed request by passing
2131 * the ADW_SCSI_REQ_Q pointer to its callback function.
2132 */
2133 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq);
2134 /*
2135 * Note: After the driver callback function is called, 'scsiq'
2136 * can no longer be referenced.
2137 *
2138 * Fall through and continue processing other completed
2139 * requests...
2140 */
2141 }
2142
2143 splx(s);
2144
2145 return ADW_TRUE;
2146 }
2147
2148
2149 /*
2150 * Send an idle command to the chip and wait for completion.
2151 *
2152 * Command completion is polled for once per microsecond.
2153 *
2154 * The function can be called from anywhere including an interrupt handler.
2155 * But the function is not re-entrant, so it uses the splbio/splx()
2156 * functions to prevent reentrancy.
2157 *
2158 * Return Values:
2159 * ADW_TRUE - command completed successfully
2160 * ADW_FALSE - command failed
2161 * ADW_ERROR - command timed out
2162 */
2163 int
2164 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter)
2165 ADW_SOFTC *sc;
2166 u_int16_t idle_cmd;
2167 u_int32_t idle_cmd_parameter;
2168 {
2169 bus_space_tag_t iot = sc->sc_iot;
2170 bus_space_handle_t ioh = sc->sc_ioh;
2171 u_int16_t result;
2172 u_int32_t i, j, s;
2173
2174 s = splbio();
2175
2176 /*
2177 * Clear the idle command status which is set by the microcode
2178 * to a non-zero value to indicate when the command is completed.
2179 */
2180 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0);
2181
2182 /*
2183 * Write the idle command value after the idle command parameter
2184 * has been written to avoid a race condition. If the order is not
2185 * followed, the microcode may process the idle command before the
2186 * parameters have been written to LRAM.
2187 */
2188 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER,
2189 idle_cmd_parameter);
2190 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd);
2191
2192 /*
2193 * Tickle the RISC to tell it to process the idle command.
2194 */
2195 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B);
2196 if (sc->chip_type == ADW_CHIP_ASC3550) {
2197 /*
2198 * Clear the tickle value. In the ASC-3550 the RISC flag
2199 * command 'clr_tickle_b' does not work unless the host
2200 * value is cleared.
2201 */
2202 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP);
2203 }
2204
2205 /* Wait for up to 100 millisecond for the idle command to timeout. */
2206 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
2207 /* Poll once each microsecond for command completion. */
2208 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
2209 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS,
2210 result);
2211 if (result != 0) {
2212 splx(s);
2213 return result;
2214 }
2215 AdwDelayMicroSecond(1);
2216 }
2217 }
2218
2219 splx(s);
2220 return ADW_ERROR;
2221 }
2222
2223
2224 /*
2225 * Inquiry Information Byte 7 Handling
2226 *
2227 * Handle SCSI Inquiry Command information for a device by setting
2228 * microcode operating variables that affect WDTR, SDTR, and Tag
2229 * Queuing.
2230 */
2231 static void
2232 AdwInquiryHandling(sc, scsiq)
2233 ADW_SOFTC *sc;
2234 ADW_SCSI_REQ_Q *scsiq;
2235 {
2236 #ifndef FAILSAFE
2237 bus_space_tag_t iot = sc->sc_iot;
2238 bus_space_handle_t ioh = sc->sc_ioh;
2239 u_int8_t tid;
2240 struct scsipi_inquiry_data *inq;
2241 u_int16_t tidmask;
2242 u_int16_t cfg_word;
2243
2244
2245 /*
2246 * AdwInquiryHandling() requires up to INQUIRY information Byte 7
2247 * to be available.
2248 *
2249 * If less than 8 bytes of INQUIRY information were requested or less
2250 * than 8 bytes were transferred, then return. cdb[4] is the request
2251 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the
2252 * microcode to the transfer residual count.
2253 */
2254
2255 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) {
2256 return;
2257 }
2258
2259 tid = scsiq->target_id;
2260
2261 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr;
2262
2263 /*
2264 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
2265 */
2266 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ &&
2267 ((inq->version & SID_ANSII) < 2)) {
2268 return;
2269 } else {
2270 /*
2271 * INQUIRY Byte 7 Handling
2272 *
2273 * Use a device's INQUIRY byte 7 to determine whether it
2274 * supports WDTR, SDTR, and Tag Queuing. If the feature
2275 * is enabled in the EEPROM and the device supports the
2276 * feature, then enable it in the microcode.
2277 */
2278
2279 tidmask = ADW_TID_TO_TIDMASK(tid);
2280
2281 /*
2282 * Wide Transfers
2283 *
2284 * If the EEPROM enabled WDTR for the device and the device
2285 * supports wide bus (16 bit) transfers, then turn on the
2286 * device's 'wdtr_able' bit and write the new value to the
2287 * microcode.
2288 */
2289 #ifdef SCSI_ADW_WDTR_DISABLE
2290 if(!(tidmask & SCSI_ADW_WDTR_DISABLE))
2291 #endif /* SCSI_ADW_WDTR_DISABLE */
2292 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) {
2293 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2294 cfg_word);
2295 if ((cfg_word & tidmask) == 0) {
2296 cfg_word |= tidmask;
2297 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2298 cfg_word);
2299
2300 /*
2301 * Clear the microcode "SDTR negotiation" and
2302 * "WDTR negotiation" done indicators for the
2303 * target to cause it to negotiate with the new
2304 * setting set above.
2305 * WDTR when accepted causes the target to enter
2306 * asynchronous mode, so SDTR must be negotiated
2307 */
2308 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2309 cfg_word);
2310 cfg_word &= ~tidmask;
2311 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2312 cfg_word);
2313 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2314 cfg_word);
2315 cfg_word &= ~tidmask;
2316 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2317 cfg_word);
2318 }
2319 }
2320
2321 /*
2322 * Synchronous Transfers
2323 *
2324 * If the EEPROM enabled SDTR for the device and the device
2325 * supports synchronous transfers, then turn on the device's
2326 * 'sdtr_able' bit. Write the new value to the microcode.
2327 */
2328 #ifdef SCSI_ADW_SDTR_DISABLE
2329 if(!(tidmask & SCSI_ADW_SDTR_DISABLE))
2330 #endif /* SCSI_ADW_SDTR_DISABLE */
2331 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) {
2332 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word);
2333 if ((cfg_word & tidmask) == 0) {
2334 cfg_word |= tidmask;
2335 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
2336 cfg_word);
2337
2338 /*
2339 * Clear the microcode "SDTR negotiation"
2340 * done indicator for the target to cause it
2341 * to negotiate with the new setting set above.
2342 */
2343 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2344 cfg_word);
2345 cfg_word &= ~tidmask;
2346 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2347 cfg_word);
2348 }
2349 }
2350 /*
2351 * If the Inquiry data included enough space for the SPI-3
2352 * Clocking field, then check if DT mode is supported.
2353 */
2354 if (sc->chip_type == ADW_CHIP_ASC38C1600 &&
2355 (scsiq->cdb[4] >= 57 ||
2356 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) {
2357 /*
2358 * PPR (Parallel Protocol Request) Capable
2359 *
2360 * If the device supports DT mode, then it must be
2361 * PPR capable.
2362 * The PPR message will be used in place of the SDTR
2363 * and WDTR messages to negotiate synchronous speed
2364 * and offset, transfer width, and protocol options.
2365 */
2366 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){
2367 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2368 sc->ppr_able);
2369 sc->ppr_able |= tidmask;
2370 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2371 sc->ppr_able);
2372 }
2373 }
2374
2375 /*
2376 * If the EEPROM enabled Tag Queuing for the device and the
2377 * device supports Tag Queueing, then turn on the device's
2378 * 'tagqng_enable' bit in the microcode and set the microcode
2379 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
2380 * value.
2381 *
2382 * Tag Queuing is disabled for the BIOS which runs in polled
2383 * mode and would see no benefit from Tag Queuing. Also by
2384 * disabling Tag Queuing in the BIOS devices with Tag Queuing
2385 * bugs will at least work with the BIOS.
2386 */
2387 #ifdef SCSI_ADW_TAGQ_DISABLE
2388 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE))
2389 #endif /* SCSI_ADW_TAGQ_DISABLE */
2390 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) {
2391 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2392 cfg_word);
2393 cfg_word |= tidmask;
2394 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2395 cfg_word);
2396
2397 ADW_WRITE_BYTE_LRAM(iot, ioh,
2398 ADW_MC_NUMBER_OF_MAX_CMD + tid,
2399 sc->max_dvc_qng);
2400 }
2401 }
2402 #endif /* FAILSAFE */
2403 }
2404
2405
2406 static void
2407 AdwSleepMilliSecond(n)
2408 u_int32_t n;
2409 {
2410
2411 DELAY(n * 1000);
2412 }
2413
2414
2415 static void
2416 AdwDelayMicroSecond(n)
2417 u_int32_t n;
2418 {
2419
2420 DELAY(n);
2421 }
2422
2423