adwlib.c revision 1.25
1 /* $NetBSD: adwlib.c,v 1.25 2003/02/21 17:14:06 tsutsui Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.25 2003/02/21 17:14:06 tsutsui Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/queue.h> 62 #include <sys/device.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsiconf.h> 70 71 #include <dev/pci/pcidevs.h> 72 73 #include <uvm/uvm_extern.h> 74 75 #include <dev/ic/adwlib.h> 76 #include <dev/ic/adwmcode.h> 77 #include <dev/ic/adw.h> 78 79 80 /* Static Functions */ 81 82 int AdwRamSelfTest __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 83 int AdwLoadMCode __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 84 u_int8_t)); 85 int AdwASC3550Cabling __P((bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *)); 86 int AdwASC38C0800Cabling __P((bus_space_tag_t, bus_space_handle_t, 87 ADW_DVC_CFG *)); 88 int AdwASC38C1600Cabling __P((bus_space_tag_t, bus_space_handle_t, 89 ADW_DVC_CFG *)); 90 91 static u_int16_t AdwGetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 92 ADW_EEPROM *)); 93 static void AdwSetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 94 ADW_EEPROM *)); 95 static u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 96 static void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 97 98 static void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 99 100 static void AdwSleepMilliSecond __P((u_int32_t)); 101 static void AdwDelayMicroSecond __P((u_int32_t)); 102 103 104 /* 105 * EEPROM Configuration. 106 * 107 * All drivers should use this structure to set the default EEPROM 108 * configuration. The BIOS now uses this structure when it is built. 109 * Additional structure information can be found in adwlib.h where 110 * the structure is defined. 111 */ 112 const static ADW_EEPROM adw_3550_Default_EEPROM = { 113 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 114 0x0000, /* 01 cfg_msw */ 115 0xFFFF, /* 02 disc_enable */ 116 0xFFFF, /* 03 wdtr_able */ 117 { 0xFFFF }, /* 04 sdtr_able */ 118 0xFFFF, /* 05 start_motor */ 119 0xFFFF, /* 06 tagqng_able */ 120 0xFFFF, /* 07 bios_scan */ 121 0, /* 08 scam_tolerant */ 122 7, /* 09 adapter_scsi_id */ 123 0, /* bios_boot_delay */ 124 3, /* 10 scsi_reset_delay */ 125 0, /* bios_id_lun */ 126 0, /* 11 termination */ 127 0, /* reserved1 */ 128 0xFFE7, /* 12 bios_ctrl */ 129 { 0xFFFF }, /* 13 ultra_able */ 130 { 0 }, /* 14 reserved2 */ 131 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 132 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 133 0, /* 16 dvc_cntl */ 134 { 0 }, /* 17 bug_fix */ 135 { 0,0,0 }, /* 18-20 serial_number[3] */ 136 0, /* 21 check_sum */ 137 { /* 22-29 oem_name[16] */ 138 0,0,0,0,0,0,0,0, 139 0,0,0,0,0,0,0,0 140 }, 141 0, /* 30 dvc_err_code */ 142 0, /* 31 adv_err_code */ 143 0, /* 32 adv_err_addr */ 144 0, /* 33 saved_dvc_err_code */ 145 0, /* 34 saved_adv_err_code */ 146 0 /* 35 saved_adv_err_addr */ 147 }; 148 149 const static ADW_EEPROM adw_38C0800_Default_EEPROM = { 150 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 151 0x0000, /* 01 cfg_msw */ 152 0xFFFF, /* 02 disc_enable */ 153 0xFFFF, /* 03 wdtr_able */ 154 { 0x4444 }, /* 04 sdtr_speed1 */ 155 0xFFFF, /* 05 start_motor */ 156 0xFFFF, /* 06 tagqng_able */ 157 0xFFFF, /* 07 bios_scan */ 158 0, /* 08 scam_tolerant */ 159 7, /* 09 adapter_scsi_id */ 160 0, /* bios_boot_delay */ 161 3, /* 10 scsi_reset_delay */ 162 0, /* bios_id_lun */ 163 0, /* 11 termination_se */ 164 0, /* termination_lvd */ 165 0xFFE7, /* 12 bios_ctrl */ 166 { 0x4444 }, /* 13 sdtr_speed2 */ 167 { 0x4444 }, /* 14 sdtr_speed3 */ 168 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 169 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 170 0, /* 16 dvc_cntl */ 171 { 0x4444 }, /* 17 sdtr_speed4 */ 172 { 0,0,0 }, /* 18-20 serial_number[3] */ 173 0, /* 21 check_sum */ 174 { /* 22-29 oem_name[16] */ 175 0,0,0,0,0,0,0,0, 176 0,0,0,0,0,0,0,0 177 }, 178 0, /* 30 dvc_err_code */ 179 0, /* 31 adv_err_code */ 180 0, /* 32 adv_err_addr */ 181 0, /* 33 saved_dvc_err_code */ 182 0, /* 34 saved_adv_err_code */ 183 0, /* 35 saved_adv_err_addr */ 184 { /* 36-55 reserved1[16] */ 185 0,0,0,0,0,0,0,0,0,0, 186 0,0,0,0,0,0,0,0,0,0 187 }, 188 0, /* 56 cisptr_lsw */ 189 0, /* 57 cisprt_msw */ 190 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 191 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 192 { 0,0,0,0 } /* 60-63 reserved2[4] */ 193 }; 194 195 const static ADW_EEPROM adw_38C1600_Default_EEPROM = { 196 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 197 0x0000, /* 01 cfg_msw */ 198 0xFFFF, /* 02 disc_enable */ 199 0xFFFF, /* 03 wdtr_able */ 200 { 0x5555 }, /* 04 sdtr_speed1 */ 201 0xFFFF, /* 05 start_motor */ 202 0xFFFF, /* 06 tagqng_able */ 203 0xFFFF, /* 07 bios_scan */ 204 0, /* 08 scam_tolerant */ 205 7, /* 09 adapter_scsi_id */ 206 0, /* bios_boot_delay */ 207 3, /* 10 scsi_reset_delay */ 208 0, /* bios_id_lun */ 209 0, /* 11 termination_se */ 210 0, /* termination_lvd */ 211 0xFFE7, /* 12 bios_ctrl */ 212 { 0x5555 }, /* 13 sdtr_speed2 */ 213 { 0x5555 }, /* 14 sdtr_speed3 */ 214 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 215 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 216 0, /* 16 dvc_cntl */ 217 { 0x5555 }, /* 17 sdtr_speed4 */ 218 { 0,0,0 }, /* 18-20 serial_number[3] */ 219 0, /* 21 check_sum */ 220 { /* 22-29 oem_name[16] */ 221 0,0,0,0,0,0,0,0, 222 0,0,0,0,0,0,0,0 223 }, 224 0, /* 30 dvc_err_code */ 225 0, /* 31 adv_err_code */ 226 0, /* 32 adv_err_addr */ 227 0, /* 33 saved_dvc_err_code */ 228 0, /* 34 saved_adv_err_code */ 229 0, /* 35 saved_adv_err_addr */ 230 { /* 36-55 reserved1[16] */ 231 0,0,0,0,0,0,0,0,0,0, 232 0,0,0,0,0,0,0,0,0,0 233 }, 234 0, /* 56 cisptr_lsw */ 235 0, /* 57 cisprt_msw */ 236 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 237 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 238 { 0,0,0,0 } /* 60-63 reserved2[4] */ 239 }; 240 241 242 /* 243 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 244 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 245 * all of this is done. 246 * 247 * For a non-fatal error return a warning code. If there are no warnings 248 * then 0 is returned. 249 * 250 * Note: Chip is stopped on entry. 251 */ 252 int 253 AdwInitFromEEPROM(sc) 254 ADW_SOFTC *sc; 255 { 256 bus_space_tag_t iot = sc->sc_iot; 257 bus_space_handle_t ioh = sc->sc_ioh; 258 ADW_EEPROM eep_config; 259 u_int16_t warn_code; 260 u_int16_t sdtr_speed = 0; 261 u_int8_t tid, termination; 262 int i, j; 263 264 265 warn_code = 0; 266 267 /* 268 * Read the board's EEPROM configuration. 269 * 270 * Set default values if a bad checksum is found. 271 * 272 * XXX - Don't handle big-endian access to EEPROM yet. 273 */ 274 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 275 warn_code |= ADW_WARN_EEPROM_CHKSUM; 276 277 /* 278 * Set EEPROM default values. 279 */ 280 switch(sc->chip_type) { 281 case ADW_CHIP_ASC3550: 282 eep_config = adw_3550_Default_EEPROM; 283 break; 284 case ADW_CHIP_ASC38C0800: 285 eep_config = adw_38C0800_Default_EEPROM; 286 break; 287 case ADW_CHIP_ASC38C1600: 288 eep_config = adw_38C1600_Default_EEPROM; 289 290 #if 0 291 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 292 #endif 293 if (sc->cfg.pci_slot_info != 0) { 294 u_int8_t lsw_msb; 295 296 lsw_msb = eep_config.cfg_lsw >> 8; 297 /* 298 * Set Function 1 EEPROM Word 0 MSB 299 * 300 * Clear the BIOS_ENABLE (bit 14) and 301 * INTAB (bit 11) EEPROM bits. 302 * 303 * Disable Bit 14 (BIOS_ENABLE) to fix 304 * SPARC Ultra 60 and old Mac system booting 305 * problem. The Expansion ROM must 306 * be disabled in Function 1 for these systems. 307 */ 308 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 309 ADW_EEPROM_INTAB) >> 8) & 0xFF); 310 /* 311 * Set the INTAB (bit 11) if the GPIO 0 input 312 * indicates the Function 1 interrupt line is 313 * wired to INTA. 314 * 315 * Set/Clear Bit 11 (INTAB) from 316 * the GPIO bit 0 input: 317 * 1 - Function 1 intr line wired to INT A. 318 * 0 - Function 1 intr line wired to INT B. 319 * 320 * Note: Adapter boards always have Function 0 321 * wired to INTA. 322 * Put all 5 GPIO bits in input mode and then 323 * read their input values. 324 */ 325 ADW_WRITE_BYTE_REGISTER(iot, ioh, 326 IOPB_GPIO_CNTL, 0); 327 if (ADW_READ_BYTE_REGISTER(iot, ioh, 328 IOPB_GPIO_DATA) & 0x01) { 329 /* 330 * Function 1 interrupt wired to INTA; 331 * Set EEPROM bit. 332 */ 333 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 334 & 0xFF; 335 } 336 eep_config.cfg_lsw &= 0x00FF; 337 eep_config.cfg_lsw |= lsw_msb << 8; 338 } 339 break; 340 } 341 342 /* 343 * Assume the 6 byte board serial number that was read 344 * from EEPROM is correct even if the EEPROM checksum 345 * failed. 346 */ 347 for (i=2, j=1; i>=0; i--, j++) { 348 eep_config.serial_number[i] = 349 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 350 } 351 352 AdwSetEEPROMConfig(iot, ioh, &eep_config); 353 } 354 /* 355 * Set sc and sc->cfg variables from the EEPROM configuration 356 * that was read. 357 * 358 * This is the mapping of EEPROM fields to Adw Library fields. 359 */ 360 sc->wdtr_able = eep_config.wdtr_able; 361 if (sc->chip_type == ADW_CHIP_ASC3550) { 362 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 363 sc->ultra_able = eep_config.sdtr2.ultra_able; 364 } else { 365 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 366 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 367 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 368 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 369 } 370 sc->ppr_able = 0; 371 sc->tagqng_able = eep_config.tagqng_able; 372 sc->cfg.disc_enable = eep_config.disc_enable; 373 sc->max_host_qng = eep_config.max_host_qng; 374 sc->max_dvc_qng = eep_config.max_dvc_qng; 375 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 376 sc->start_motor = eep_config.start_motor; 377 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 378 sc->bios_ctrl = eep_config.bios_ctrl; 379 sc->no_scam = eep_config.scam_tolerant; 380 sc->cfg.serial1 = eep_config.serial_number[0]; 381 sc->cfg.serial2 = eep_config.serial_number[1]; 382 sc->cfg.serial3 = eep_config.serial_number[2]; 383 384 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 385 sc->chip_type == ADW_CHIP_ASC38C1600) { 386 sc->sdtr_able = 0; 387 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 388 if (tid == 0) { 389 sdtr_speed = sc->sdtr_speed1; 390 } else if (tid == 4) { 391 sdtr_speed = sc->sdtr_speed2; 392 } else if (tid == 8) { 393 sdtr_speed = sc->sdtr_speed3; 394 } else if (tid == 12) { 395 sdtr_speed = sc->sdtr_speed4; 396 } 397 if (sdtr_speed & ADW_MAX_TID) { 398 sc->sdtr_able |= (1 << tid); 399 } 400 sdtr_speed >>= 4; 401 } 402 } 403 404 /* 405 * Set the host maximum queuing (max. 253, min. 16) and the per device 406 * maximum queuing (max. 63, min. 4). 407 */ 408 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 409 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 410 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 411 { 412 /* If the value is zero, assume it is uninitialized. */ 413 if (eep_config.max_host_qng == 0) { 414 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 415 } else { 416 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 417 } 418 } 419 420 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 421 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 422 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 423 /* If the value is zero, assume it is uninitialized. */ 424 if (eep_config.max_dvc_qng == 0) { 425 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 426 } else { 427 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 428 } 429 } 430 431 /* 432 * If 'max_dvc_qng' is greater than 'max_host_qng', then 433 * set 'max_dvc_qng' to 'max_host_qng'. 434 */ 435 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 436 eep_config.max_dvc_qng = eep_config.max_host_qng; 437 } 438 439 /* 440 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 441 * values based on possibly adjusted EEPROM values. 442 */ 443 sc->max_host_qng = eep_config.max_host_qng; 444 sc->max_dvc_qng = eep_config.max_dvc_qng; 445 446 447 /* 448 * If the EEPROM 'termination' field is set to automatic (0), then set 449 * the ADV_DVC_CFG 'termination' field to automatic also. 450 * 451 * If the termination is specified with a non-zero 'termination' 452 * value check that a legal value is set and set the ADV_DVC_CFG 453 * 'termination' field appropriately. 454 */ 455 456 switch(sc->chip_type) { 457 case ADW_CHIP_ASC3550: 458 sc->cfg.termination = 0; /* auto termination */ 459 switch(eep_config.termination_se) { 460 case 3: 461 /* Enable manual control with low on / high on. */ 462 sc->cfg.termination |= ADW_TERM_CTL_L; 463 case 2: 464 /* Enable manual control with low off / high on. */ 465 sc->cfg.termination |= ADW_TERM_CTL_H; 466 case 1: 467 /* Enable manual control with low off / high off. */ 468 sc->cfg.termination |= ADW_TERM_CTL_SEL; 469 case 0: 470 break; 471 default: 472 warn_code |= ADW_WARN_EEPROM_TERMINATION; 473 } 474 break; 475 476 case ADW_CHIP_ASC38C0800: 477 case ADW_CHIP_ASC38C1600: 478 switch(eep_config.termination_se) { 479 case 0: 480 /* auto termination for SE */ 481 termination = 0; 482 break; 483 case 1: 484 /* Enable manual control with low off / high off. */ 485 termination = 0; 486 break; 487 case 2: 488 /* Enable manual control with low off / high on. */ 489 termination = ADW_TERM_SE_HI; 490 break; 491 case 3: 492 /* Enable manual control with low on / high on. */ 493 termination = ADW_TERM_SE; 494 break; 495 default: 496 /* 497 * The EEPROM 'termination_se' field contains a 498 * bad value. Use automatic termination instead. 499 */ 500 termination = 0; 501 warn_code |= ADW_WARN_EEPROM_TERMINATION; 502 } 503 504 switch(eep_config.termination_lvd) { 505 case 0: 506 /* auto termination for LVD */ 507 sc->cfg.termination = termination; 508 break; 509 case 1: 510 /* Enable manual control with low off / high off. */ 511 sc->cfg.termination = termination; 512 break; 513 case 2: 514 /* Enable manual control with low off / high on. */ 515 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 516 break; 517 case 3: 518 /* Enable manual control with low on / high on. */ 519 sc->cfg.termination = termination | ADW_TERM_LVD; 520 break; 521 default: 522 /* 523 * The EEPROM 'termination_lvd' field contains a 524 * bad value. Use automatic termination instead. 525 */ 526 sc->cfg.termination = termination; 527 warn_code |= ADW_WARN_EEPROM_TERMINATION; 528 } 529 break; 530 } 531 532 return warn_code; 533 } 534 535 536 /* 537 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 538 * 539 * On failure return the error code. 540 */ 541 int 542 AdwInitDriver(sc) 543 ADW_SOFTC *sc; 544 { 545 bus_space_tag_t iot = sc->sc_iot; 546 bus_space_handle_t ioh = sc->sc_ioh; 547 u_int16_t error_code; 548 int word; 549 int i; 550 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 551 0x40-0x8F. */ 552 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 553 u_int8_t max_cmd[ADW_MAX_TID + 1]; 554 u_int8_t tid; 555 556 557 error_code = 0; 558 559 /* 560 * Save the RISC memory BIOS region before writing the microcode. 561 * The BIOS may already be loaded and using its RISC LRAM region 562 * so its region must be saved and restored. 563 * 564 * Note: This code makes the assumption, which is currently true, 565 * that a chip reset does not clear RISC LRAM. 566 */ 567 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 568 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 569 } 570 571 /* 572 * Save current per TID negotiated values. 573 */ 574 switch (sc->chip_type) { 575 case ADW_CHIP_ASC3550: 576 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 577 578 u_int16_t bios_version, major, minor; 579 580 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 581 ADW_MC_BIOSMEM) / 2]; 582 major = (bios_version >> 12) & 0xF; 583 minor = (bios_version >> 8) & 0xF; 584 if (major < 3 || (major == 3 && minor == 1)) { 585 /* 586 * BIOS 3.1 and earlier location of 587 * 'wdtr_able' variable. 588 */ 589 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 590 } else { 591 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 592 wdtr_able); 593 } 594 } 595 break; 596 597 case ADW_CHIP_ASC38C1600: 598 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 599 /* FALLTHROUGH */ 600 case ADW_CHIP_ASC38C0800: 601 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 602 break; 603 } 604 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 605 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 606 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 607 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 608 max_cmd[tid]); 609 } 610 611 /* 612 * Perform a RAM Built-In Self Test 613 */ 614 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 615 return error_code; 616 } 617 618 /* 619 * Load the Microcode 620 */ 621 ; 622 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 623 return error_code; 624 } 625 626 /* 627 * Read microcode version and date. 628 */ 629 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 630 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 631 632 /* 633 * If the PCI Configuration Command Register "Parity Error Response 634 * Control" Bit was clear (0), then set the microcode variable 635 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 636 * to ignore DMA parity errors. 637 */ 638 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 639 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 640 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 641 word | CONTROL_FLAG_IGNORE_PERR); 642 } 643 644 switch (sc->chip_type) { 645 case ADW_CHIP_ASC3550: 646 /* 647 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 648 * FIFO threshold of 128 bytes. 649 * This register is only accessible to the host. 650 */ 651 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 652 START_CTL_EMFU | READ_CMD_MRM); 653 break; 654 655 case ADW_CHIP_ASC38C0800: 656 /* 657 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 658 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 659 * cable detection and then we are able to read C_DET[3:0]. 660 * 661 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 662 * Microcode Default Value' section below. 663 */ 664 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 665 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 666 | ADW_DIS_TERM_DRV); 667 668 /* 669 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 670 * START_CTL_TH [3:2] bits for the default FIFO threshold. 671 * 672 * Note: ASC-38C0800 FIFO threshold has been changed to 673 * 256 bytes. 674 * 675 * For DMA Errata #4 set the BC_THRESH_ENB bit. 676 */ 677 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 678 BC_THRESH_ENB | FIFO_THRESH_80B 679 | START_CTL_TH | READ_CMD_MRM); 680 break; 681 682 case ADW_CHIP_ASC38C1600: 683 /* 684 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 685 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 686 * cable detection and then we are able to read C_DET[3:0]. 687 * 688 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 689 * Microcode Default Value' section below. 690 */ 691 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 692 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 693 | ADW_DIS_TERM_DRV); 694 695 /* 696 * If the BIOS control flag AIPP (Asynchronous Information 697 * Phase Protection) disable bit is not set, then set the 698 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 699 * enable AIPP checking and encoding. 700 */ 701 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 702 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 703 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 704 word | CONTROL_FLAG_ENABLE_AIPP); 705 } 706 707 /* 708 * For ASC-38C1600 use DMA_CFG0 default values: 709 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 710 */ 711 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 712 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 713 break; 714 } 715 716 /* 717 * Microcode operating variables for WDTR, SDTR, and command tag 718 * queuing will be set in AdvInquiryHandling() based on what a 719 * device reports it is capable of in Inquiry byte 7. 720 * 721 * If SCSI Bus Resets have been disabled, then directly set 722 * SDTR and WDTR from the EEPROM configuration. This will allow 723 * the BIOS and warm boot to work without a SCSI bus hang on 724 * the Inquiry caused by host and target mismatched DTR values. 725 * Without the SCSI Bus Reset, before an Inquiry a device can't 726 * be assumed to be in Asynchronous, Narrow mode. 727 */ 728 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 729 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 730 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 731 } 732 733 /* 734 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 735 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 736 * bitmask. These values determine the maximum SDTR speed negotiated 737 * with a device. 738 * 739 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 740 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 741 * without determining here whether the device supports SDTR. 742 */ 743 switch (sc->chip_type) { 744 case ADW_CHIP_ASC3550: 745 word = 0; 746 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 747 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 748 /* Set Ultra speed for TID 'tid'. */ 749 word |= (0x3 << (4 * (tid % 4))); 750 } else { 751 /* Set Fast speed for TID 'tid'. */ 752 word |= (0x2 << (4 * (tid % 4))); 753 } 754 /* Check if done with sdtr_speed1. */ 755 if (tid == 3) { 756 ADW_WRITE_WORD_LRAM(iot, ioh, 757 ADW_MC_SDTR_SPEED1, word); 758 word = 0; 759 /* Check if done with sdtr_speed2. */ 760 } else if (tid == 7) { 761 ADW_WRITE_WORD_LRAM(iot, ioh, 762 ADW_MC_SDTR_SPEED2, word); 763 word = 0; 764 /* Check if done with sdtr_speed3. */ 765 } else if (tid == 11) { 766 ADW_WRITE_WORD_LRAM(iot, ioh, 767 ADW_MC_SDTR_SPEED3, word); 768 word = 0; 769 /* Check if done with sdtr_speed4. */ 770 } else if (tid == 15) { 771 ADW_WRITE_WORD_LRAM(iot, ioh, 772 ADW_MC_SDTR_SPEED4, word); 773 /* End of loop. */ 774 } 775 } 776 777 /* 778 * Set microcode operating variable for the 779 * disconnect per TID bitmask. 780 */ 781 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 782 sc->cfg.disc_enable); 783 break; 784 785 case ADW_CHIP_ASC38C0800: 786 /* FALLTHROUGH */ 787 case ADW_CHIP_ASC38C1600: 788 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 789 sc->cfg.disc_enable); 790 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 791 sc->sdtr_speed1); 792 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 793 sc->sdtr_speed2); 794 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 795 sc->sdtr_speed3); 796 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 797 sc->sdtr_speed4); 798 break; 799 } 800 801 802 /* 803 * Set SCSI_CFG0 Microcode Default Value. 804 * 805 * The microcode will set the SCSI_CFG0 register using this value 806 * after it is started below. 807 */ 808 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 809 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 810 ADW_OUR_ID_EN | sc->chip_scsi_id); 811 812 813 switch(sc->chip_type) { 814 case ADW_CHIP_ASC3550: 815 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 816 break; 817 818 case ADW_CHIP_ASC38C0800: 819 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 820 break; 821 822 case ADW_CHIP_ASC38C1600: 823 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 824 break; 825 } 826 if(error_code) { 827 return error_code; 828 } 829 830 /* 831 * Set SEL_MASK Microcode Default Value 832 * 833 * The microcode will set the SEL_MASK register using this value 834 * after it is started below. 835 */ 836 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 837 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 838 839 /* 840 * Create and Initialize Host->RISC Carrier lists 841 */ 842 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 843 sc->sc_control->carriers); 844 845 /* 846 * Set-up the Host->RISC Initiator Command Queue (ICQ). 847 */ 848 849 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 850 return ADW_IERR_NO_CARRIER; 851 } 852 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 853 ASC_GET_CARRP(sc->icq_sp->next_ba)); 854 855 /* 856 * The first command issued will be placed in the stopper carrier. 857 */ 858 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER); 859 860 /* 861 * Set RISC ICQ physical address start value. 862 */ 863 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba)); 864 865 /* 866 * Initialize the COMMA register to the same value otherwise 867 * the RISC will prematurely detect a command is available. 868 */ 869 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 870 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 871 le32toh(sc->icq_sp->carr_ba)); 872 } 873 874 /* 875 * Set-up the RISC->Host Initiator Response Queue (IRQ). 876 */ 877 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 878 return ADW_IERR_NO_CARRIER; 879 } 880 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 881 ASC_GET_CARRP(sc->irq_sp->next_ba)); 882 883 /* 884 * The first command completed by the RISC will be placed in 885 * the stopper. 886 * 887 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 888 * completed the RISC will set the ASC_RQ_DONE bit. 889 */ 890 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER); 891 892 /* 893 * Set RISC IRQ physical address start value. 894 */ 895 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba)); 896 sc->carr_pending_cnt = 0; 897 898 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 899 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 900 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 901 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 902 903 /* finally, finally, gentlemen, start your engine */ 904 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 905 906 /* 907 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 908 * Resets should be performed. The RISC has to be running 909 * to issue a SCSI Bus Reset. 910 */ 911 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 912 { 913 /* 914 * If the BIOS Signature is present in memory, restore the 915 * BIOS Handshake Configuration Table and do not perform 916 * a SCSI Bus Reset. 917 */ 918 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 919 0x55AA) { 920 /* 921 * Restore per TID negotiated values. 922 */ 923 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 924 wdtr_able); 925 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 926 sdtr_able); 927 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 928 tagqng_able); 929 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 930 ADW_WRITE_BYTE_LRAM(iot, ioh, 931 ADW_MC_NUMBER_OF_MAX_CMD + tid, 932 max_cmd[tid]); 933 } 934 } else { 935 if (AdwResetCCB(sc) != ADW_TRUE) { 936 error_code = ADW_WARN_BUSRESET_ERROR; 937 } 938 } 939 } 940 941 return error_code; 942 } 943 944 945 int 946 AdwRamSelfTest(iot, ioh, chip_type) 947 bus_space_tag_t iot; 948 bus_space_handle_t ioh; 949 u_int8_t chip_type; 950 { 951 int i; 952 u_int8_t byte; 953 954 955 if ((chip_type == ADW_CHIP_ASC38C0800) || 956 (chip_type == ADW_CHIP_ASC38C1600)) { 957 /* 958 * RAM BIST (RAM Built-In Self Test) 959 * 960 * Address : I/O base + offset 0x38h register (byte). 961 * Function: Bit 7-6(RW) : RAM mode 962 * Normal Mode : 0x00 963 * Pre-test Mode : 0x40 964 * RAM Test Mode : 0x80 965 * Bit 5 : unused 966 * Bit 4(RO) : Done bit 967 * Bit 3-0(RO) : Status 968 * Host Error : 0x08 969 * Int_RAM Error : 0x04 970 * RISC Error : 0x02 971 * SCSI Error : 0x01 972 * No Error : 0x00 973 * 974 * Note: RAM BIST code should be put right here, before loading 975 * the microcode and after saving the RISC memory BIOS region. 976 */ 977 978 /* 979 * LRAM Pre-test 980 * 981 * Write PRE_TEST_MODE (0x40) to register and wait for 982 * 10 milliseconds. 983 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 984 * return an error. Reset to NORMAL_MODE (0x00) and do again. 985 * If cannot reset to NORMAL_MODE, return an error too. 986 */ 987 for (i = 0; i < 2; i++) { 988 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 989 PRE_TEST_MODE); 990 /* Wait for 10ms before reading back. */ 991 AdwSleepMilliSecond(10); 992 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 993 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 994 PRE_TEST_VALUE) { 995 return ADW_IERR_BIST_PRE_TEST; 996 } 997 998 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 999 NORMAL_MODE); 1000 /* Wait for 10ms before reading back. */ 1001 AdwSleepMilliSecond(10); 1002 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1003 != NORMAL_VALUE) { 1004 return ADW_IERR_BIST_PRE_TEST; 1005 } 1006 } 1007 1008 /* 1009 * LRAM Test - It takes about 1.5 ms to run through the test. 1010 * 1011 * Write RAM_TEST_MODE (0x80) to register and wait for 1012 * 10 milliseconds. 1013 * If Done bit not set or Status not 0, save register byte, 1014 * set the err_code, and return an error. 1015 */ 1016 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1017 /* Wait for 10ms before checking status. */ 1018 AdwSleepMilliSecond(10); 1019 1020 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1021 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1022 /* Get here if Done bit not set or Status not 0. */ 1023 return ADW_IERR_BIST_RAM_TEST; 1024 } 1025 1026 /* We need to reset back to normal mode after LRAM test passes*/ 1027 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1028 } 1029 1030 return 0; 1031 } 1032 1033 1034 int 1035 AdwLoadMCode(iot, ioh, bios_mem, chip_type) 1036 bus_space_tag_t iot; 1037 bus_space_handle_t ioh; 1038 u_int16_t *bios_mem; 1039 u_int8_t chip_type; 1040 { 1041 u_int8_t *mcode_data; 1042 u_int32_t mcode_chksum; 1043 u_int16_t mcode_size; 1044 u_int32_t sum; 1045 u_int16_t code_sum; 1046 int begin_addr; 1047 int end_addr; 1048 int word; 1049 int adw_memsize; 1050 int adw_mcode_expanded_size; 1051 int i, j; 1052 1053 1054 switch(chip_type) { 1055 case ADW_CHIP_ASC3550: 1056 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1057 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1058 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1059 adw_memsize = ADW_3550_MEMSIZE; 1060 break; 1061 1062 case ADW_CHIP_ASC38C0800: 1063 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1064 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1065 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1066 adw_memsize = ADW_38C0800_MEMSIZE; 1067 break; 1068 1069 case ADW_CHIP_ASC38C1600: 1070 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1071 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1072 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1073 adw_memsize = ADW_38C1600_MEMSIZE; 1074 break; 1075 } 1076 1077 /* 1078 * Write the microcode image to RISC memory starting at address 0. 1079 */ 1080 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1081 1082 /* Assume the following compressed format of the microcode buffer: 1083 * 1084 * 254 word (508 byte) table indexed by byte code followed 1085 * by the following byte codes: 1086 * 1087 * 1-Byte Code: 1088 * 00: Emit word 0 in table. 1089 * 01: Emit word 1 in table. 1090 * . 1091 * FD: Emit word 253 in table. 1092 * 1093 * Multi-Byte Code: 1094 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1095 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1096 */ 1097 word = 0; 1098 for (i = 253 * 2; i < mcode_size; i++) { 1099 if (mcode_data[i] == 0xff) { 1100 for (j = 0; j < mcode_data[i + 1]; j++) { 1101 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1102 (((u_int16_t)mcode_data[i + 3] << 8) | 1103 mcode_data[i + 2])); 1104 word++; 1105 } 1106 i += 3; 1107 } else if (mcode_data[i] == 0xfe) { 1108 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1109 (((u_int16_t)mcode_data[i + 2] << 8) | 1110 mcode_data[i + 1])); 1111 i += 2; 1112 word++; 1113 } else { 1114 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1115 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1116 mcode_data[mcode_data[i] * 2])); 1117 word++; 1118 } 1119 } 1120 1121 /* 1122 * Set 'word' for later use to clear the rest of memory and save 1123 * the expanded mcode size. 1124 */ 1125 word *= 2; 1126 adw_mcode_expanded_size = word; 1127 1128 /* 1129 * Clear the rest of the Internal RAM. 1130 */ 1131 for (; word < adw_memsize; word += 2) { 1132 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1133 } 1134 1135 /* 1136 * Verify the microcode checksum. 1137 */ 1138 sum = 0; 1139 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1140 1141 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1142 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1143 } 1144 1145 if (sum != mcode_chksum) { 1146 return ADW_IERR_MCODE_CHKSUM; 1147 } 1148 1149 /* 1150 * Restore the RISC memory BIOS region. 1151 */ 1152 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1153 if(chip_type == ADW_CHIP_ASC3550) { 1154 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1155 bios_mem[i]); 1156 } else { 1157 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1158 bios_mem[i]); 1159 } 1160 } 1161 1162 /* 1163 * Calculate and write the microcode code checksum to the microcode 1164 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1165 */ 1166 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1167 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1168 code_sum = 0; 1169 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1170 for (word = begin_addr; word < end_addr; word += 2) { 1171 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1172 } 1173 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1174 1175 /* 1176 * Set the chip type. 1177 */ 1178 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1179 1180 return 0; 1181 } 1182 1183 1184 int 1185 AdwASC3550Cabling(iot, ioh, cfg) 1186 bus_space_tag_t iot; 1187 bus_space_handle_t ioh; 1188 ADW_DVC_CFG *cfg; 1189 { 1190 u_int16_t scsi_cfg1; 1191 1192 1193 /* 1194 * Determine SCSI_CFG1 Microcode Default Value. 1195 * 1196 * The microcode will set the SCSI_CFG1 register using this value 1197 * after it is started below. 1198 */ 1199 1200 /* Read current SCSI_CFG1 Register value. */ 1201 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1202 1203 /* 1204 * If all three connectors are in use in ASC3550, return an error. 1205 */ 1206 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1207 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1208 return ADW_IERR_ILLEGAL_CONNECTION; 1209 } 1210 1211 /* 1212 * If the cable is reversed all of the SCSI_CTRL register signals 1213 * will be set. Check for and return an error if this condition is 1214 * found. 1215 */ 1216 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1217 return ADW_IERR_REVERSED_CABLE; 1218 } 1219 1220 /* 1221 * If this is a differential board and a single-ended device 1222 * is attached to one of the connectors, return an error. 1223 */ 1224 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1225 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1226 return ADW_IERR_SINGLE_END_DEVICE; 1227 } 1228 1229 /* 1230 * If automatic termination control is enabled, then set the 1231 * termination value based on a table listed in a_condor.h. 1232 * 1233 * If manual termination was specified with an EEPROM setting 1234 * then 'termination' was set-up in AdwInitFromEEPROM() and 1235 * is ready to be 'ored' into SCSI_CFG1. 1236 */ 1237 if (cfg->termination == 0) { 1238 /* 1239 * The software always controls termination by setting 1240 * TERM_CTL_SEL. 1241 * If TERM_CTL_SEL were set to 0, the hardware would set 1242 * termination. 1243 */ 1244 cfg->termination |= ADW_TERM_CTL_SEL; 1245 1246 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1247 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1248 case 0x3: case 0x7: case 0xB: 1249 case 0xD: case 0xE: case 0xF: 1250 cfg->termination |= 1251 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1252 break; 1253 1254 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1255 case 0x1: case 0x5: case 0x9: 1256 case 0xA: case 0xC: 1257 cfg->termination |= ADW_TERM_CTL_H; 1258 break; 1259 1260 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1261 case 0x2: case 0x6: 1262 break; 1263 } 1264 } 1265 1266 /* 1267 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1268 */ 1269 scsi_cfg1 &= ~ADW_TERM_CTL; 1270 1271 /* 1272 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1273 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1274 * referenced, because the hardware internally inverts 1275 * the Termination High and Low bits if TERM_POL is set. 1276 */ 1277 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1278 1279 /* 1280 * Set SCSI_CFG1 Microcode Default Value 1281 * 1282 * Set filter value and possibly modified termination control 1283 * bits in the Microcode SCSI_CFG1 Register Value. 1284 * 1285 * The microcode will set the SCSI_CFG1 register using this value 1286 * after it is started below. 1287 */ 1288 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1289 ADW_FLTR_DISABLE | scsi_cfg1); 1290 1291 /* 1292 * Set MEM_CFG Microcode Default Value 1293 * 1294 * The microcode will set the MEM_CFG register using this value 1295 * after it is started below. 1296 * 1297 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1298 * are defined. 1299 * 1300 * ASC-3550 has 8KB internal memory. 1301 */ 1302 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1303 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1304 1305 return 0; 1306 } 1307 1308 1309 int 1310 AdwASC38C0800Cabling(iot, ioh, cfg) 1311 bus_space_tag_t iot; 1312 bus_space_handle_t ioh; 1313 ADW_DVC_CFG *cfg; 1314 { 1315 u_int16_t scsi_cfg1; 1316 1317 1318 /* 1319 * Determine SCSI_CFG1 Microcode Default Value. 1320 * 1321 * The microcode will set the SCSI_CFG1 register using this value 1322 * after it is started below. 1323 */ 1324 1325 /* Read current SCSI_CFG1 Register value. */ 1326 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1327 1328 /* 1329 * If the cable is reversed all of the SCSI_CTRL register signals 1330 * will be set. Check for and return an error if this condition is 1331 * found. 1332 */ 1333 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1334 return ADW_IERR_REVERSED_CABLE; 1335 } 1336 1337 /* 1338 * All kind of combinations of devices attached to one of four 1339 * connectors are acceptable except HVD device attached. 1340 * For example, LVD device can be attached to SE connector while 1341 * SE device attached to LVD connector. 1342 * If LVD device attached to SE connector, it only runs up to 1343 * Ultra speed. 1344 * 1345 * If an HVD device is attached to one of LVD connectors, return 1346 * an error. 1347 * However, there is no way to detect HVD device attached to 1348 * SE connectors. 1349 */ 1350 if (scsi_cfg1 & ADW_HVD) { 1351 return ADW_IERR_HVD_DEVICE; 1352 } 1353 1354 /* 1355 * If either SE or LVD automatic termination control is enabled, then 1356 * set the termination value based on a table listed in a_condor.h. 1357 * 1358 * If manual termination was specified with an EEPROM setting then 1359 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1360 * to be 'ored' into SCSI_CFG1. 1361 */ 1362 if ((cfg->termination & ADW_TERM_SE) == 0) { 1363 /* SE automatic termination control is enabled. */ 1364 switch(scsi_cfg1 & ADW_C_DET_SE) { 1365 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1366 case 0x1: case 0x2: case 0x3: 1367 cfg->termination |= ADW_TERM_SE; 1368 break; 1369 1370 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1371 case 0x0: 1372 cfg->termination |= ADW_TERM_SE_HI; 1373 break; 1374 } 1375 } 1376 1377 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1378 /* LVD automatic termination control is enabled. */ 1379 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1380 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1381 case 0x4: case 0x8: case 0xC: 1382 cfg->termination |= ADW_TERM_LVD; 1383 break; 1384 1385 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1386 case 0x0: 1387 break; 1388 } 1389 } 1390 1391 /* 1392 * Clear any set TERM_SE and TERM_LVD bits. 1393 */ 1394 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1395 1396 /* 1397 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1398 */ 1399 scsi_cfg1 |= (~cfg->termination & 0xF0); 1400 1401 /* 1402 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1403 * HVD/LVD/SE bits and set possibly modified termination control bits 1404 * in the Microcode SCSI_CFG1 Register Value. 1405 */ 1406 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1407 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1408 1409 /* 1410 * Set SCSI_CFG1 Microcode Default Value 1411 * 1412 * Set possibly modified termination control and reset DIS_TERM_DRV 1413 * bits in the Microcode SCSI_CFG1 Register Value. 1414 * 1415 * The microcode will set the SCSI_CFG1 register using this value 1416 * after it is started below. 1417 */ 1418 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1419 1420 /* 1421 * Set MEM_CFG Microcode Default Value 1422 * 1423 * The microcode will set the MEM_CFG register using this value 1424 * after it is started below. 1425 * 1426 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1427 * are defined. 1428 * 1429 * ASC-38C0800 has 16KB internal memory. 1430 */ 1431 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1432 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1433 1434 return 0; 1435 } 1436 1437 1438 int 1439 AdwASC38C1600Cabling(iot, ioh, cfg) 1440 bus_space_tag_t iot; 1441 bus_space_handle_t ioh; 1442 ADW_DVC_CFG *cfg; 1443 { 1444 u_int16_t scsi_cfg1; 1445 1446 1447 /* 1448 * Determine SCSI_CFG1 Microcode Default Value. 1449 * 1450 * The microcode will set the SCSI_CFG1 register using this value 1451 * after it is started below. 1452 * Each ASC-38C1600 function has only two cable detect bits. 1453 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1454 */ 1455 1456 /* Read current SCSI_CFG1 Register value. */ 1457 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1458 1459 /* 1460 * If the cable is reversed all of the SCSI_CTRL register signals 1461 * will be set. Check for and return an error if this condition is 1462 * found. 1463 */ 1464 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1465 return ADW_IERR_REVERSED_CABLE; 1466 } 1467 1468 /* 1469 * Each ASC-38C1600 function has two connectors. Only an HVD device 1470 * can not be connected to either connector. An LVD device or SE device 1471 * may be connected to either connecor. If an SE device is connected, 1472 * then at most Ultra speed (20 MHz) can be used on both connectors. 1473 * 1474 * If an HVD device is attached, return an error. 1475 */ 1476 if (scsi_cfg1 & ADW_HVD) { 1477 return ADW_IERR_HVD_DEVICE; 1478 } 1479 1480 /* 1481 * Each function in the ASC-38C1600 uses only the SE cable detect and 1482 * termination because there are two connectors for each function. 1483 * Each function may use either LVD or SE mode. 1484 * Corresponding the SE automatic termination control EEPROM bits are 1485 * used for each function. 1486 * Each function has its own EEPROM. If SE automatic control is enabled 1487 * for the function, then set the termination value based on a table 1488 * listed in adwlib.h. 1489 * 1490 * If manual termination is specified in the EEPROM for the function, 1491 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1492 * ready to be 'ored' into SCSI_CFG1. 1493 */ 1494 if ((cfg->termination & ADW_TERM_SE) == 0) { 1495 /* SE automatic termination control is enabled. */ 1496 switch(scsi_cfg1 & ADW_C_DET_SE) { 1497 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1498 case 0x1: case 0x2: case 0x3: 1499 cfg->termination |= ADW_TERM_SE; 1500 break; 1501 1502 case 0x0: 1503 #if 0 1504 /* !!!!TODO!!!! */ 1505 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1506 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1507 } 1508 else 1509 #endif 1510 { 1511 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1512 cfg->termination |= ADW_TERM_SE_HI; 1513 } 1514 break; 1515 } 1516 } 1517 1518 /* 1519 * Clear any set TERM_SE bits. 1520 */ 1521 scsi_cfg1 &= ~ADW_TERM_SE; 1522 1523 /* 1524 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1525 */ 1526 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1527 1528 /* 1529 * Clear Big Endian and Terminator Polarity bits and set possibly 1530 * modified termination control bits in the Microcode SCSI_CFG1 1531 * Register Value. 1532 */ 1533 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1534 1535 /* 1536 * Set SCSI_CFG1 Microcode Default Value 1537 * 1538 * Set possibly modified termination control bits in the Microcode 1539 * SCSI_CFG1 Register Value. 1540 * 1541 * The microcode will set the SCSI_CFG1 register using this value 1542 * after it is started below. 1543 */ 1544 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1545 1546 /* 1547 * Set MEM_CFG Microcode Default Value 1548 * 1549 * The microcode will set the MEM_CFG register using this value 1550 * after it is started below. 1551 * 1552 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1553 * are defined. 1554 * 1555 * ASC-38C1600 has 32KB internal memory. 1556 */ 1557 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1558 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1559 1560 return 0; 1561 } 1562 1563 1564 /* 1565 * Read EEPROM configuration into the specified buffer. 1566 * 1567 * Return a checksum based on the EEPROM configuration read. 1568 */ 1569 static u_int16_t 1570 AdwGetEEPROMConfig(iot, ioh, cfg_buf) 1571 bus_space_tag_t iot; 1572 bus_space_handle_t ioh; 1573 ADW_EEPROM *cfg_buf; 1574 { 1575 u_int16_t wval, chksum; 1576 u_int16_t *wbuf; 1577 int eep_addr; 1578 1579 1580 wbuf = (u_int16_t *) cfg_buf; 1581 chksum = 0; 1582 1583 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1584 eep_addr < ASC_EEP_DVC_CFG_END; 1585 eep_addr++, wbuf++) { 1586 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1587 chksum += wval; 1588 *wbuf = wval; 1589 } 1590 1591 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1592 wbuf++; 1593 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1594 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1595 eep_addr++, wbuf++) { 1596 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1597 } 1598 1599 return chksum; 1600 } 1601 1602 1603 /* 1604 * Read the EEPROM from specified location 1605 */ 1606 static u_int16_t 1607 AdwReadEEPWord(iot, ioh, eep_word_addr) 1608 bus_space_tag_t iot; 1609 bus_space_handle_t ioh; 1610 int eep_word_addr; 1611 { 1612 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1613 ASC_EEP_CMD_READ | eep_word_addr); 1614 AdwWaitEEPCmd(iot, ioh); 1615 1616 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1617 } 1618 1619 1620 /* 1621 * Wait for EEPROM command to complete 1622 */ 1623 static void 1624 AdwWaitEEPCmd(iot, ioh) 1625 bus_space_tag_t iot; 1626 bus_space_handle_t ioh; 1627 { 1628 int eep_delay_ms; 1629 1630 1631 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1632 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1633 ASC_EEP_CMD_DONE) { 1634 break; 1635 } 1636 AdwSleepMilliSecond(1); 1637 } 1638 1639 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1640 } 1641 1642 1643 /* 1644 * Write the EEPROM from 'cfg_buf'. 1645 */ 1646 static void 1647 AdwSetEEPROMConfig(iot, ioh, cfg_buf) 1648 bus_space_tag_t iot; 1649 bus_space_handle_t ioh; 1650 ADW_EEPROM *cfg_buf; 1651 { 1652 u_int16_t *wbuf; 1653 u_int16_t addr, chksum; 1654 1655 1656 wbuf = (u_int16_t *) cfg_buf; 1657 chksum = 0; 1658 1659 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1660 AdwWaitEEPCmd(iot, ioh); 1661 1662 /* 1663 * Write EEPROM from word 0 to word 20 1664 */ 1665 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1666 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1667 chksum += *wbuf; 1668 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1670 ASC_EEP_CMD_WRITE | addr); 1671 AdwWaitEEPCmd(iot, ioh); 1672 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1673 } 1674 1675 /* 1676 * Write EEPROM checksum at word 21 1677 */ 1678 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1679 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1680 ASC_EEP_CMD_WRITE | addr); 1681 AdwWaitEEPCmd(iot, ioh); 1682 wbuf++; /* skip over check_sum */ 1683 1684 /* 1685 * Write EEPROM OEM name at words 22 to 29 1686 */ 1687 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1688 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1689 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1690 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1691 ASC_EEP_CMD_WRITE | addr); 1692 AdwWaitEEPCmd(iot, ioh); 1693 } 1694 1695 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1696 ASC_EEP_CMD_WRITE_DISABLE); 1697 AdwWaitEEPCmd(iot, ioh); 1698 1699 return; 1700 } 1701 1702 1703 /* 1704 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1705 * 1706 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1707 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1708 * RISC to notify it a new command is ready to be executed. 1709 * 1710 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1711 * set to SCSI_MAX_RETRY. 1712 * 1713 * Return: 1714 * ADW_SUCCESS(1) - The request was successfully queued. 1715 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1716 * request completes. 1717 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1718 * host IC error. 1719 */ 1720 int 1721 AdwExeScsiQueue(sc, scsiq) 1722 ADW_SOFTC *sc; 1723 ADW_SCSI_REQ_Q *scsiq; 1724 { 1725 bus_space_tag_t iot = sc->sc_iot; 1726 bus_space_handle_t ioh = sc->sc_ioh; 1727 ADW_CCB *ccb; 1728 long req_size; 1729 u_int32_t req_paddr; 1730 ADW_CARRIER *new_carrp; 1731 1732 /* 1733 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1734 */ 1735 if (scsiq->target_id > ADW_MAX_TID) { 1736 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1737 scsiq->done_status = QD_WITH_ERROR; 1738 return ADW_ERROR; 1739 } 1740 1741 /* 1742 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1743 */ 1744 1745 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1746 1747 /* 1748 * Allocate a carrier and initialize fields. 1749 */ 1750 if ((new_carrp = sc->carr_freelist) == NULL) { 1751 return ADW_BUSY; 1752 } 1753 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1754 ASC_GET_CARRP(new_carrp->next_ba)); 1755 sc->carr_pending_cnt++; 1756 1757 /* 1758 * Set the carrier to be a stopper by setting 'next_ba' 1759 * to the stopper value. The current stopper will be changed 1760 * below to point to the new stopper. 1761 */ 1762 new_carrp->next_ba = htole32(ASC_CQ_STOPPER); 1763 1764 req_size = sizeof(ADW_SCSI_REQ_Q); 1765 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1766 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1767 1768 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1769 scsiq->scsiq_rptr = htole32(req_paddr); 1770 1771 /* 1772 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1773 * order during initialization. 1774 */ 1775 scsiq->carr_ba = sc->icq_sp->carr_ba; 1776 scsiq->carr_va = sc->icq_sp->carr_ba; 1777 1778 /* 1779 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1780 * the microcode. The newly allocated stopper will become the new 1781 * stopper. 1782 */ 1783 sc->icq_sp->areq_ba = htole32(req_paddr); 1784 1785 /* 1786 * Set the 'next_ba' pointer for the old stopper to be the 1787 * physical address of the new stopper. The RISC can only 1788 * follow physical addresses. 1789 */ 1790 sc->icq_sp->next_ba = new_carrp->carr_ba; 1791 1792 #if ADW_DEBUG 1793 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1794 sc->icq_sp->carr_id, 1795 sc->icq_sp->carr_ba, 1796 sc->icq_sp->areq_ba, 1797 sc->icq_sp->next_ba); 1798 #endif 1799 /* 1800 * Set the host adapter stopper pointer to point to the new carrier. 1801 */ 1802 sc->icq_sp = new_carrp; 1803 1804 if (sc->chip_type == ADW_CHIP_ASC3550 || 1805 sc->chip_type == ADW_CHIP_ASC38C0800) { 1806 /* 1807 * Tickle the RISC to tell it to read its Command Queue Head 1808 * pointer. 1809 */ 1810 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1811 if (sc->chip_type == ADW_CHIP_ASC3550) { 1812 /* 1813 * Clear the tickle value. In the ASC-3550 the RISC flag 1814 * command 'clr_tickle_a' does not work unless the host 1815 * value is cleared. 1816 */ 1817 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1818 ADW_TICKLE_NOP); 1819 } 1820 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1821 /* 1822 * Notify the RISC a carrier is ready by writing the physical 1823 * address of the new carrier stopper to the COMMA register. 1824 */ 1825 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1826 le32toh(new_carrp->carr_ba)); 1827 } 1828 1829 /* 1830 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1831 */ 1832 1833 return ADW_SUCCESS; 1834 } 1835 1836 1837 void 1838 AdwResetChip(iot, ioh) 1839 bus_space_tag_t iot; 1840 bus_space_handle_t ioh; 1841 { 1842 1843 /* 1844 * Reset Chip. 1845 */ 1846 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1847 ADW_CTRL_REG_CMD_RESET); 1848 AdwSleepMilliSecond(100); 1849 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1850 ADW_CTRL_REG_CMD_WR_IO_REG); 1851 } 1852 1853 1854 /* 1855 * Reset SCSI Bus and purge all outstanding requests. 1856 * 1857 * Return Value: 1858 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1859 * ADW_FALSE(0) - Microcode command failed. 1860 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1861 * may be hung which requires driver recovery. 1862 */ 1863 int 1864 AdwResetCCB(sc) 1865 ADW_SOFTC *sc; 1866 { 1867 int status; 1868 1869 /* 1870 * Send the SCSI Bus Reset idle start idle command which asserts 1871 * the SCSI Bus Reset signal. 1872 */ 1873 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1874 if (status != ADW_TRUE) { 1875 return status; 1876 } 1877 1878 /* 1879 * Delay for the specified SCSI Bus Reset hold time. 1880 * 1881 * The hold time delay is done on the host because the RISC has no 1882 * microsecond accurate timer. 1883 */ 1884 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1885 1886 /* 1887 * Send the SCSI Bus Reset end idle command which de-asserts 1888 * the SCSI Bus Reset signal and purges any pending requests. 1889 */ 1890 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1891 if (status != ADW_TRUE) { 1892 return status; 1893 } 1894 1895 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1896 1897 return status; 1898 } 1899 1900 1901 /* 1902 * Reset chip and SCSI Bus. 1903 * 1904 * Return Value: 1905 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1906 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1907 */ 1908 int 1909 AdwResetSCSIBus(sc) 1910 ADW_SOFTC *sc; 1911 { 1912 bus_space_tag_t iot = sc->sc_iot; 1913 bus_space_handle_t ioh = sc->sc_ioh; 1914 int status; 1915 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1916 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1917 u_int16_t bios_sig; 1918 1919 1920 /* 1921 * Save current per TID negotiated values. 1922 */ 1923 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1924 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1925 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1926 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1927 } 1928 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1929 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1930 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1931 max_cmd[tid]); 1932 } 1933 1934 /* 1935 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1936 * by clearing the BIOS signature word. 1937 * The initialization functions assumes a SCSI Bus Reset is not 1938 * needed if the BIOS signature word is present. 1939 */ 1940 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1941 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1942 1943 /* 1944 * Stop chip and reset it. 1945 */ 1946 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1947 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1948 ADW_CTRL_REG_CMD_RESET); 1949 AdwSleepMilliSecond(100); 1950 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1951 ADW_CTRL_REG_CMD_WR_IO_REG); 1952 1953 /* 1954 * Reset Adv Library error code, if any, and try 1955 * re-initializing the chip. 1956 * Then translate initialization return value to status value. 1957 */ 1958 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1959 1960 /* 1961 * Restore the BIOS signature word. 1962 */ 1963 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1964 1965 /* 1966 * Restore per TID negotiated values. 1967 */ 1968 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1969 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1970 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1971 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1972 } 1973 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1974 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1975 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1976 max_cmd[tid]); 1977 } 1978 1979 return status; 1980 } 1981 1982 1983 /* 1984 * Adv Library Interrupt Service Routine 1985 * 1986 * This function is called by a driver's interrupt service routine. 1987 * The function disables and re-enables interrupts. 1988 * 1989 * When a microcode idle command is completed, the ADV_DVC_VAR 1990 * 'idle_cmd_done' field is set to ADW_TRUE. 1991 * 1992 * Note: AdwISR() can be called when interrupts are disabled or even 1993 * when there is no hardware interrupt condition present. It will 1994 * always check for completed idle commands and microcode requests. 1995 * This is an important feature that shouldn't be changed because it 1996 * allows commands to be completed from polling mode loops. 1997 * 1998 * Return: 1999 * ADW_TRUE(1) - interrupt was pending 2000 * ADW_FALSE(0) - no interrupt was pending 2001 */ 2002 int 2003 AdwISR(sc) 2004 ADW_SOFTC *sc; 2005 { 2006 bus_space_tag_t iot = sc->sc_iot; 2007 bus_space_handle_t ioh = sc->sc_ioh; 2008 u_int8_t int_stat; 2009 u_int16_t target_bit; 2010 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 2011 u_int32_t irq_next_pa; 2012 ADW_SCSI_REQ_Q *scsiq; 2013 ADW_CCB *ccb; 2014 int s; 2015 2016 2017 s = splbio(); 2018 2019 /* Reading the register clears the interrupt. */ 2020 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 2021 2022 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 2023 ADW_INTR_STATUS_INTRC)) == 0) { 2024 splx(s); 2025 return ADW_FALSE; 2026 } 2027 2028 /* 2029 * Notify the driver of an asynchronous microcode condition by 2030 * calling the ADV_DVC_VAR.async_callback function. The function 2031 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2032 */ 2033 if (int_stat & ADW_INTR_STATUS_INTRB) { 2034 u_int8_t intrb_code; 2035 2036 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2037 2038 if (sc->chip_type == ADW_CHIP_ASC3550 || 2039 sc->chip_type == ADW_CHIP_ASC38C0800) { 2040 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2041 sc->carr_pending_cnt != 0) { 2042 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2043 IOPB_TICKLE, ADW_TICKLE_A); 2044 if (sc->chip_type == ADW_CHIP_ASC3550) { 2045 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2046 IOPB_TICKLE, ADW_TICKLE_NOP); 2047 } 2048 } 2049 } 2050 2051 if (sc->async_callback != 0) { 2052 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2053 } 2054 } 2055 2056 /* 2057 * Check if the IRQ stopper carrier contains a completed request. 2058 */ 2059 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0) 2060 { 2061 #if ADW_DEBUG 2062 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2063 sc->irq_sp->carr_id, 2064 sc->irq_sp->carr_ba, 2065 sc->irq_sp->areq_ba, 2066 sc->irq_sp->next_ba); 2067 #endif 2068 /* 2069 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2070 * structure. 2071 * The RISC will have set 'areq_ba' to a virtual address. 2072 * 2073 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2074 * field to the carrier ADV_CARR_T.areq_ba field. 2075 * The conversion below complements the conversion of 2076 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2077 */ 2078 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2079 scsiq = &ccb->scsiq; 2080 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2081 2082 /* 2083 * Request finished with good status and the queue was not 2084 * DMAed to host memory by the firmware. Set all status fields 2085 * to indicate good status. 2086 */ 2087 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) { 2088 scsiq->done_status = QD_NO_ERROR; 2089 scsiq->host_status = scsiq->scsi_status = 0; 2090 scsiq->data_cnt = 0L; 2091 } 2092 2093 /* 2094 * Advance the stopper pointer to the next carrier 2095 * ignoring the lower four bits. Free the previous 2096 * stopper carrier. 2097 */ 2098 free_carrp = sc->irq_sp; 2099 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2100 2101 free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL 2102 : sc->carr_freelist->carr_ba; 2103 sc->carr_freelist = free_carrp; 2104 sc->carr_pending_cnt--; 2105 2106 2107 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2108 2109 /* 2110 * Clear request microcode control flag. 2111 */ 2112 scsiq->cntl = 0; 2113 2114 /* 2115 * Check Condition handling 2116 */ 2117 /* 2118 * If the command that completed was a SCSI INQUIRY and 2119 * LUN 0 was sent the command, then process the INQUIRY 2120 * command information for the device. 2121 */ 2122 if (scsiq->done_status == QD_NO_ERROR && 2123 scsiq->cdb[0] == INQUIRY && 2124 scsiq->target_lun == 0) { 2125 AdwInquiryHandling(sc, scsiq); 2126 } 2127 2128 /* 2129 * Notify the driver of the completed request by passing 2130 * the ADW_SCSI_REQ_Q pointer to its callback function. 2131 */ 2132 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2133 /* 2134 * Note: After the driver callback function is called, 'scsiq' 2135 * can no longer be referenced. 2136 * 2137 * Fall through and continue processing other completed 2138 * requests... 2139 */ 2140 } 2141 2142 splx(s); 2143 2144 return ADW_TRUE; 2145 } 2146 2147 2148 /* 2149 * Send an idle command to the chip and wait for completion. 2150 * 2151 * Command completion is polled for once per microsecond. 2152 * 2153 * The function can be called from anywhere including an interrupt handler. 2154 * But the function is not re-entrant, so it uses the splbio/splx() 2155 * functions to prevent reentrancy. 2156 * 2157 * Return Values: 2158 * ADW_TRUE - command completed successfully 2159 * ADW_FALSE - command failed 2160 * ADW_ERROR - command timed out 2161 */ 2162 int 2163 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 2164 ADW_SOFTC *sc; 2165 u_int16_t idle_cmd; 2166 u_int32_t idle_cmd_parameter; 2167 { 2168 bus_space_tag_t iot = sc->sc_iot; 2169 bus_space_handle_t ioh = sc->sc_ioh; 2170 u_int16_t result; 2171 u_int32_t i, j, s; 2172 2173 s = splbio(); 2174 2175 /* 2176 * Clear the idle command status which is set by the microcode 2177 * to a non-zero value to indicate when the command is completed. 2178 */ 2179 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2180 2181 /* 2182 * Write the idle command value after the idle command parameter 2183 * has been written to avoid a race condition. If the order is not 2184 * followed, the microcode may process the idle command before the 2185 * parameters have been written to LRAM. 2186 */ 2187 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2188 idle_cmd_parameter); 2189 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2190 2191 /* 2192 * Tickle the RISC to tell it to process the idle command. 2193 */ 2194 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2195 if (sc->chip_type == ADW_CHIP_ASC3550) { 2196 /* 2197 * Clear the tickle value. In the ASC-3550 the RISC flag 2198 * command 'clr_tickle_b' does not work unless the host 2199 * value is cleared. 2200 */ 2201 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2202 } 2203 2204 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2205 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2206 /* Poll once each microsecond for command completion. */ 2207 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2208 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2209 result); 2210 if (result != 0) { 2211 splx(s); 2212 return result; 2213 } 2214 AdwDelayMicroSecond(1); 2215 } 2216 } 2217 2218 splx(s); 2219 return ADW_ERROR; 2220 } 2221 2222 2223 /* 2224 * Inquiry Information Byte 7 Handling 2225 * 2226 * Handle SCSI Inquiry Command information for a device by setting 2227 * microcode operating variables that affect WDTR, SDTR, and Tag 2228 * Queuing. 2229 */ 2230 static void 2231 AdwInquiryHandling(sc, scsiq) 2232 ADW_SOFTC *sc; 2233 ADW_SCSI_REQ_Q *scsiq; 2234 { 2235 #ifndef FAILSAFE 2236 bus_space_tag_t iot = sc->sc_iot; 2237 bus_space_handle_t ioh = sc->sc_ioh; 2238 u_int8_t tid; 2239 struct scsipi_inquiry_data *inq; 2240 u_int16_t tidmask; 2241 u_int16_t cfg_word; 2242 2243 2244 /* 2245 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2246 * to be available. 2247 * 2248 * If less than 8 bytes of INQUIRY information were requested or less 2249 * than 8 bytes were transferred, then return. cdb[4] is the request 2250 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2251 * microcode to the transfer residual count. 2252 */ 2253 2254 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2255 return; 2256 } 2257 2258 tid = scsiq->target_id; 2259 2260 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2261 2262 /* 2263 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2264 */ 2265 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2266 ((inq->version & SID_ANSII) < 2)) { 2267 return; 2268 } else { 2269 /* 2270 * INQUIRY Byte 7 Handling 2271 * 2272 * Use a device's INQUIRY byte 7 to determine whether it 2273 * supports WDTR, SDTR, and Tag Queuing. If the feature 2274 * is enabled in the EEPROM and the device supports the 2275 * feature, then enable it in the microcode. 2276 */ 2277 2278 tidmask = ADW_TID_TO_TIDMASK(tid); 2279 2280 /* 2281 * Wide Transfers 2282 * 2283 * If the EEPROM enabled WDTR for the device and the device 2284 * supports wide bus (16 bit) transfers, then turn on the 2285 * device's 'wdtr_able' bit and write the new value to the 2286 * microcode. 2287 */ 2288 #ifdef SCSI_ADW_WDTR_DISABLE 2289 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2290 #endif /* SCSI_ADW_WDTR_DISABLE */ 2291 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2292 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2293 cfg_word); 2294 if ((cfg_word & tidmask) == 0) { 2295 cfg_word |= tidmask; 2296 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2297 cfg_word); 2298 2299 /* 2300 * Clear the microcode "SDTR negotiation" and 2301 * "WDTR negotiation" done indicators for the 2302 * target to cause it to negotiate with the new 2303 * setting set above. 2304 * WDTR when accepted causes the target to enter 2305 * asynchronous mode, so SDTR must be negotiated 2306 */ 2307 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2308 cfg_word); 2309 cfg_word &= ~tidmask; 2310 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2311 cfg_word); 2312 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2313 cfg_word); 2314 cfg_word &= ~tidmask; 2315 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2316 cfg_word); 2317 } 2318 } 2319 2320 /* 2321 * Synchronous Transfers 2322 * 2323 * If the EEPROM enabled SDTR for the device and the device 2324 * supports synchronous transfers, then turn on the device's 2325 * 'sdtr_able' bit. Write the new value to the microcode. 2326 */ 2327 #ifdef SCSI_ADW_SDTR_DISABLE 2328 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2329 #endif /* SCSI_ADW_SDTR_DISABLE */ 2330 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2331 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2332 if ((cfg_word & tidmask) == 0) { 2333 cfg_word |= tidmask; 2334 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2335 cfg_word); 2336 2337 /* 2338 * Clear the microcode "SDTR negotiation" 2339 * done indicator for the target to cause it 2340 * to negotiate with the new setting set above. 2341 */ 2342 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2343 cfg_word); 2344 cfg_word &= ~tidmask; 2345 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2346 cfg_word); 2347 } 2348 } 2349 /* 2350 * If the Inquiry data included enough space for the SPI-3 2351 * Clocking field, then check if DT mode is supported. 2352 */ 2353 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2354 (scsiq->cdb[4] >= 57 || 2355 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2356 /* 2357 * PPR (Parallel Protocol Request) Capable 2358 * 2359 * If the device supports DT mode, then it must be 2360 * PPR capable. 2361 * The PPR message will be used in place of the SDTR 2362 * and WDTR messages to negotiate synchronous speed 2363 * and offset, transfer width, and protocol options. 2364 */ 2365 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2366 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2367 sc->ppr_able); 2368 sc->ppr_able |= tidmask; 2369 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2370 sc->ppr_able); 2371 } 2372 } 2373 2374 /* 2375 * If the EEPROM enabled Tag Queuing for the device and the 2376 * device supports Tag Queueing, then turn on the device's 2377 * 'tagqng_enable' bit in the microcode and set the microcode 2378 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2379 * value. 2380 * 2381 * Tag Queuing is disabled for the BIOS which runs in polled 2382 * mode and would see no benefit from Tag Queuing. Also by 2383 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2384 * bugs will at least work with the BIOS. 2385 */ 2386 #ifdef SCSI_ADW_TAGQ_DISABLE 2387 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2388 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2389 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2390 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2391 cfg_word); 2392 cfg_word |= tidmask; 2393 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2394 cfg_word); 2395 2396 ADW_WRITE_BYTE_LRAM(iot, ioh, 2397 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2398 sc->max_dvc_qng); 2399 } 2400 } 2401 #endif /* FAILSAFE */ 2402 } 2403 2404 2405 static void 2406 AdwSleepMilliSecond(n) 2407 u_int32_t n; 2408 { 2409 2410 DELAY(n * 1000); 2411 } 2412 2413 2414 static void 2415 AdwDelayMicroSecond(n) 2416 u_int32_t n; 2417 { 2418 2419 DELAY(n); 2420 } 2421 2422
Indexes created Thu Sep 25 16:09:42 GMT 2025