adwlib.c revision 1.39
1 /* $NetBSD: adwlib.c,v 1.39 2009/03/14 15:36:17 dsl Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.39 2009/03/14 15:36:17 dsl Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/queue.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsiconf.h> 70 71 #include <dev/pci/pcidevs.h> 72 73 #include <uvm/uvm_extern.h> 74 75 #include <dev/ic/adwlib.h> 76 #include <dev/ic/adwmcode.h> 77 #include <dev/ic/adw.h> 78 79 80 /* Static Functions */ 81 82 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t); 83 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, u_int8_t); 84 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 85 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 86 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 87 88 static u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 89 ADW_EEPROM *); 90 static void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 91 ADW_EEPROM *); 92 static u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int); 93 static void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t); 94 95 static void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 96 97 static void AdwSleepMilliSecond(u_int32_t); 98 static void AdwDelayMicroSecond(u_int32_t); 99 100 101 /* 102 * EEPROM Configuration. 103 * 104 * All drivers should use this structure to set the default EEPROM 105 * configuration. The BIOS now uses this structure when it is built. 106 * Additional structure information can be found in adwlib.h where 107 * the structure is defined. 108 */ 109 static const ADW_EEPROM adw_3550_Default_EEPROM = { 110 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 111 0x0000, /* 01 cfg_msw */ 112 0xFFFF, /* 02 disc_enable */ 113 0xFFFF, /* 03 wdtr_able */ 114 { 0xFFFF }, /* 04 sdtr_able */ 115 0xFFFF, /* 05 start_motor */ 116 0xFFFF, /* 06 tagqng_able */ 117 0xFFFF, /* 07 bios_scan */ 118 0, /* 08 scam_tolerant */ 119 7, /* 09 adapter_scsi_id */ 120 0, /* bios_boot_delay */ 121 3, /* 10 scsi_reset_delay */ 122 0, /* bios_id_lun */ 123 0, /* 11 termination */ 124 0, /* reserved1 */ 125 0xFFE7, /* 12 bios_ctrl */ 126 { 0xFFFF }, /* 13 ultra_able */ 127 { 0 }, /* 14 reserved2 */ 128 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 129 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 130 0, /* 16 dvc_cntl */ 131 { 0 }, /* 17 bug_fix */ 132 { 0,0,0 }, /* 18-20 serial_number[3] */ 133 0, /* 21 check_sum */ 134 { /* 22-29 oem_name[16] */ 135 0,0,0,0,0,0,0,0, 136 0,0,0,0,0,0,0,0 137 }, 138 0, /* 30 dvc_err_code */ 139 0, /* 31 adv_err_code */ 140 0, /* 32 adv_err_addr */ 141 0, /* 33 saved_dvc_err_code */ 142 0, /* 34 saved_adv_err_code */ 143 0, /* 35 saved_adv_err_addr */ 144 { /* 36-55 reserved1[16] */ 145 0,0,0,0,0,0,0,0,0,0, 146 0,0,0,0,0,0,0,0,0,0 147 }, 148 0, /* 56 cisptr_lsw */ 149 0, /* 57 cisprt_msw */ 150 0, /* 58 subsysvid */ 151 0, /* 59 subsysid */ 152 { 0,0,0,0 } /* 60-63 reserved2[4] */ 153 }; 154 155 static const ADW_EEPROM adw_38C0800_Default_EEPROM = { 156 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 157 0x0000, /* 01 cfg_msw */ 158 0xFFFF, /* 02 disc_enable */ 159 0xFFFF, /* 03 wdtr_able */ 160 { 0x4444 }, /* 04 sdtr_speed1 */ 161 0xFFFF, /* 05 start_motor */ 162 0xFFFF, /* 06 tagqng_able */ 163 0xFFFF, /* 07 bios_scan */ 164 0, /* 08 scam_tolerant */ 165 7, /* 09 adapter_scsi_id */ 166 0, /* bios_boot_delay */ 167 3, /* 10 scsi_reset_delay */ 168 0, /* bios_id_lun */ 169 0, /* 11 termination_se */ 170 0, /* termination_lvd */ 171 0xFFE7, /* 12 bios_ctrl */ 172 { 0x4444 }, /* 13 sdtr_speed2 */ 173 { 0x4444 }, /* 14 sdtr_speed3 */ 174 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 175 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 176 0, /* 16 dvc_cntl */ 177 { 0x4444 }, /* 17 sdtr_speed4 */ 178 { 0,0,0 }, /* 18-20 serial_number[3] */ 179 0, /* 21 check_sum */ 180 { /* 22-29 oem_name[16] */ 181 0,0,0,0,0,0,0,0, 182 0,0,0,0,0,0,0,0 183 }, 184 0, /* 30 dvc_err_code */ 185 0, /* 31 adv_err_code */ 186 0, /* 32 adv_err_addr */ 187 0, /* 33 saved_dvc_err_code */ 188 0, /* 34 saved_adv_err_code */ 189 0, /* 35 saved_adv_err_addr */ 190 { /* 36-55 reserved1[16] */ 191 0,0,0,0,0,0,0,0,0,0, 192 0,0,0,0,0,0,0,0,0,0 193 }, 194 0, /* 56 cisptr_lsw */ 195 0, /* 57 cisprt_msw */ 196 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 197 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 198 { 0,0,0,0 } /* 60-63 reserved2[4] */ 199 }; 200 201 static const ADW_EEPROM adw_38C1600_Default_EEPROM = { 202 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 203 0x0000, /* 01 cfg_msw */ 204 0xFFFF, /* 02 disc_enable */ 205 0xFFFF, /* 03 wdtr_able */ 206 { 0x5555 }, /* 04 sdtr_speed1 */ 207 0xFFFF, /* 05 start_motor */ 208 0xFFFF, /* 06 tagqng_able */ 209 0xFFFF, /* 07 bios_scan */ 210 0, /* 08 scam_tolerant */ 211 7, /* 09 adapter_scsi_id */ 212 0, /* bios_boot_delay */ 213 3, /* 10 scsi_reset_delay */ 214 0, /* bios_id_lun */ 215 0, /* 11 termination_se */ 216 0, /* termination_lvd */ 217 0xFFE7, /* 12 bios_ctrl */ 218 { 0x5555 }, /* 13 sdtr_speed2 */ 219 { 0x5555 }, /* 14 sdtr_speed3 */ 220 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 221 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 222 0, /* 16 dvc_cntl */ 223 { 0x5555 }, /* 17 sdtr_speed4 */ 224 { 0,0,0 }, /* 18-20 serial_number[3] */ 225 0, /* 21 check_sum */ 226 { /* 22-29 oem_name[16] */ 227 0,0,0,0,0,0,0,0, 228 0,0,0,0,0,0,0,0 229 }, 230 0, /* 30 dvc_err_code */ 231 0, /* 31 adv_err_code */ 232 0, /* 32 adv_err_addr */ 233 0, /* 33 saved_dvc_err_code */ 234 0, /* 34 saved_adv_err_code */ 235 0, /* 35 saved_adv_err_addr */ 236 { /* 36-55 reserved1[16] */ 237 0,0,0,0,0,0,0,0,0,0, 238 0,0,0,0,0,0,0,0,0,0 239 }, 240 0, /* 56 cisptr_lsw */ 241 0, /* 57 cisprt_msw */ 242 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 243 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 244 { 0,0,0,0 } /* 60-63 reserved2[4] */ 245 }; 246 247 248 /* 249 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 250 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 251 * all of this is done. 252 * 253 * For a non-fatal error return a warning code. If there are no warnings 254 * then 0 is returned. 255 * 256 * Note: Chip is stopped on entry. 257 */ 258 int 259 AdwInitFromEEPROM(ADW_SOFTC *sc) 260 { 261 bus_space_tag_t iot = sc->sc_iot; 262 bus_space_handle_t ioh = sc->sc_ioh; 263 ADW_EEPROM eep_config; 264 u_int16_t warn_code; 265 u_int16_t sdtr_speed = 0; 266 u_int8_t tid, termination; 267 int i, j; 268 269 270 warn_code = 0; 271 272 /* 273 * Read the board's EEPROM configuration. 274 * 275 * Set default values if a bad checksum is found. 276 * 277 * XXX - Don't handle big-endian access to EEPROM yet. 278 */ 279 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 280 warn_code |= ADW_WARN_EEPROM_CHKSUM; 281 282 /* 283 * Set EEPROM default values. 284 */ 285 switch(sc->chip_type) { 286 case ADW_CHIP_ASC3550: 287 eep_config = adw_3550_Default_EEPROM; 288 break; 289 case ADW_CHIP_ASC38C0800: 290 eep_config = adw_38C0800_Default_EEPROM; 291 break; 292 case ADW_CHIP_ASC38C1600: 293 eep_config = adw_38C1600_Default_EEPROM; 294 295 #if 0 296 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 297 #endif 298 if (sc->cfg.pci_slot_info != 0) { 299 u_int8_t lsw_msb; 300 301 lsw_msb = eep_config.cfg_lsw >> 8; 302 /* 303 * Set Function 1 EEPROM Word 0 MSB 304 * 305 * Clear the BIOS_ENABLE (bit 14) and 306 * INTAB (bit 11) EEPROM bits. 307 * 308 * Disable Bit 14 (BIOS_ENABLE) to fix 309 * SPARC Ultra 60 and old Mac system booting 310 * problem. The Expansion ROM must 311 * be disabled in Function 1 for these systems. 312 */ 313 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 314 ADW_EEPROM_INTAB) >> 8) & 0xFF); 315 /* 316 * Set the INTAB (bit 11) if the GPIO 0 input 317 * indicates the Function 1 interrupt line is 318 * wired to INTA. 319 * 320 * Set/Clear Bit 11 (INTAB) from 321 * the GPIO bit 0 input: 322 * 1 - Function 1 intr line wired to INT A. 323 * 0 - Function 1 intr line wired to INT B. 324 * 325 * Note: Adapter boards always have Function 0 326 * wired to INTA. 327 * Put all 5 GPIO bits in input mode and then 328 * read their input values. 329 */ 330 ADW_WRITE_BYTE_REGISTER(iot, ioh, 331 IOPB_GPIO_CNTL, 0); 332 if (ADW_READ_BYTE_REGISTER(iot, ioh, 333 IOPB_GPIO_DATA) & 0x01) { 334 /* 335 * Function 1 interrupt wired to INTA; 336 * Set EEPROM bit. 337 */ 338 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 339 & 0xFF; 340 } 341 eep_config.cfg_lsw &= 0x00FF; 342 eep_config.cfg_lsw |= lsw_msb << 8; 343 } 344 break; 345 } 346 347 /* 348 * Assume the 6 byte board serial number that was read 349 * from EEPROM is correct even if the EEPROM checksum 350 * failed. 351 */ 352 for (i=2, j=1; i>=0; i--, j++) { 353 eep_config.serial_number[i] = 354 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 355 } 356 357 AdwSetEEPROMConfig(iot, ioh, &eep_config); 358 } 359 /* 360 * Set sc and sc->cfg variables from the EEPROM configuration 361 * that was read. 362 * 363 * This is the mapping of EEPROM fields to Adw Library fields. 364 */ 365 sc->wdtr_able = eep_config.wdtr_able; 366 if (sc->chip_type == ADW_CHIP_ASC3550) { 367 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 368 sc->ultra_able = eep_config.sdtr2.ultra_able; 369 } else { 370 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 371 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 372 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 373 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 374 } 375 sc->ppr_able = 0; 376 sc->tagqng_able = eep_config.tagqng_able; 377 sc->cfg.disc_enable = eep_config.disc_enable; 378 sc->max_host_qng = eep_config.max_host_qng; 379 sc->max_dvc_qng = eep_config.max_dvc_qng; 380 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 381 sc->start_motor = eep_config.start_motor; 382 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 383 sc->bios_ctrl = eep_config.bios_ctrl; 384 sc->no_scam = eep_config.scam_tolerant; 385 sc->cfg.serial1 = eep_config.serial_number[0]; 386 sc->cfg.serial2 = eep_config.serial_number[1]; 387 sc->cfg.serial3 = eep_config.serial_number[2]; 388 389 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 390 sc->chip_type == ADW_CHIP_ASC38C1600) { 391 sc->sdtr_able = 0; 392 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 393 if (tid == 0) { 394 sdtr_speed = sc->sdtr_speed1; 395 } else if (tid == 4) { 396 sdtr_speed = sc->sdtr_speed2; 397 } else if (tid == 8) { 398 sdtr_speed = sc->sdtr_speed3; 399 } else if (tid == 12) { 400 sdtr_speed = sc->sdtr_speed4; 401 } 402 if (sdtr_speed & ADW_MAX_TID) { 403 sc->sdtr_able |= (1 << tid); 404 } 405 sdtr_speed >>= 4; 406 } 407 } 408 409 /* 410 * Set the host maximum queuing (max. 253, min. 16) and the per device 411 * maximum queuing (max. 63, min. 4). 412 */ 413 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 414 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 415 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 416 { 417 /* If the value is zero, assume it is uninitialized. */ 418 if (eep_config.max_host_qng == 0) { 419 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 420 } else { 421 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 422 } 423 } 424 425 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 426 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 427 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 428 /* If the value is zero, assume it is uninitialized. */ 429 if (eep_config.max_dvc_qng == 0) { 430 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 431 } else { 432 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 433 } 434 } 435 436 /* 437 * If 'max_dvc_qng' is greater than 'max_host_qng', then 438 * set 'max_dvc_qng' to 'max_host_qng'. 439 */ 440 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 441 eep_config.max_dvc_qng = eep_config.max_host_qng; 442 } 443 444 /* 445 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 446 * values based on possibly adjusted EEPROM values. 447 */ 448 sc->max_host_qng = eep_config.max_host_qng; 449 sc->max_dvc_qng = eep_config.max_dvc_qng; 450 451 452 /* 453 * If the EEPROM 'termination' field is set to automatic (0), then set 454 * the ADV_DVC_CFG 'termination' field to automatic also. 455 * 456 * If the termination is specified with a non-zero 'termination' 457 * value check that a legal value is set and set the ADV_DVC_CFG 458 * 'termination' field appropriately. 459 */ 460 461 switch(sc->chip_type) { 462 case ADW_CHIP_ASC3550: 463 sc->cfg.termination = 0; /* auto termination */ 464 switch(eep_config.termination_se) { 465 case 3: 466 /* Enable manual control with low on / high on. */ 467 sc->cfg.termination |= ADW_TERM_CTL_L; 468 case 2: 469 /* Enable manual control with low off / high on. */ 470 sc->cfg.termination |= ADW_TERM_CTL_H; 471 case 1: 472 /* Enable manual control with low off / high off. */ 473 sc->cfg.termination |= ADW_TERM_CTL_SEL; 474 case 0: 475 break; 476 default: 477 warn_code |= ADW_WARN_EEPROM_TERMINATION; 478 } 479 break; 480 481 case ADW_CHIP_ASC38C0800: 482 case ADW_CHIP_ASC38C1600: 483 switch(eep_config.termination_se) { 484 case 0: 485 /* auto termination for SE */ 486 termination = 0; 487 break; 488 case 1: 489 /* Enable manual control with low off / high off. */ 490 termination = 0; 491 break; 492 case 2: 493 /* Enable manual control with low off / high on. */ 494 termination = ADW_TERM_SE_HI; 495 break; 496 case 3: 497 /* Enable manual control with low on / high on. */ 498 termination = ADW_TERM_SE; 499 break; 500 default: 501 /* 502 * The EEPROM 'termination_se' field contains a 503 * bad value. Use automatic termination instead. 504 */ 505 termination = 0; 506 warn_code |= ADW_WARN_EEPROM_TERMINATION; 507 } 508 509 switch(eep_config.termination_lvd) { 510 case 0: 511 /* auto termination for LVD */ 512 sc->cfg.termination = termination; 513 break; 514 case 1: 515 /* Enable manual control with low off / high off. */ 516 sc->cfg.termination = termination; 517 break; 518 case 2: 519 /* Enable manual control with low off / high on. */ 520 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 521 break; 522 case 3: 523 /* Enable manual control with low on / high on. */ 524 sc->cfg.termination = termination | ADW_TERM_LVD; 525 break; 526 default: 527 /* 528 * The EEPROM 'termination_lvd' field contains a 529 * bad value. Use automatic termination instead. 530 */ 531 sc->cfg.termination = termination; 532 warn_code |= ADW_WARN_EEPROM_TERMINATION; 533 } 534 break; 535 } 536 537 return warn_code; 538 } 539 540 541 /* 542 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 543 * 544 * On failure return the error code. 545 */ 546 int 547 AdwInitDriver(ADW_SOFTC *sc) 548 { 549 bus_space_tag_t iot = sc->sc_iot; 550 bus_space_handle_t ioh = sc->sc_ioh; 551 u_int16_t error_code; 552 int word; 553 int i; 554 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 555 0x40-0x8F. */ 556 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 557 u_int8_t max_cmd[ADW_MAX_TID + 1]; 558 u_int8_t tid; 559 560 561 error_code = 0; 562 563 /* 564 * Save the RISC memory BIOS region before writing the microcode. 565 * The BIOS may already be loaded and using its RISC LRAM region 566 * so its region must be saved and restored. 567 * 568 * Note: This code makes the assumption, which is currently true, 569 * that a chip reset does not clear RISC LRAM. 570 */ 571 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 572 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 573 } 574 575 /* 576 * Save current per TID negotiated values. 577 */ 578 switch (sc->chip_type) { 579 case ADW_CHIP_ASC3550: 580 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 581 582 u_int16_t bios_version, major, minor; 583 584 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 585 ADW_MC_BIOSMEM) / 2]; 586 major = (bios_version >> 12) & 0xF; 587 minor = (bios_version >> 8) & 0xF; 588 if (major < 3 || (major == 3 && minor == 1)) { 589 /* 590 * BIOS 3.1 and earlier location of 591 * 'wdtr_able' variable. 592 */ 593 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 594 } else { 595 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 596 wdtr_able); 597 } 598 } 599 break; 600 601 case ADW_CHIP_ASC38C1600: 602 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 603 /* FALLTHROUGH */ 604 case ADW_CHIP_ASC38C0800: 605 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 606 break; 607 } 608 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 609 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 610 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 611 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 612 max_cmd[tid]); 613 } 614 615 /* 616 * Perform a RAM Built-In Self Test 617 */ 618 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 619 return error_code; 620 } 621 622 /* 623 * Load the Microcode 624 */ 625 ; 626 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 627 return error_code; 628 } 629 630 /* 631 * Read microcode version and date. 632 */ 633 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 634 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 635 636 /* 637 * If the PCI Configuration Command Register "Parity Error Response 638 * Control" Bit was clear (0), then set the microcode variable 639 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 640 * to ignore DMA parity errors. 641 */ 642 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 643 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 644 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 645 word | CONTROL_FLAG_IGNORE_PERR); 646 } 647 648 switch (sc->chip_type) { 649 case ADW_CHIP_ASC3550: 650 /* 651 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 652 * FIFO threshold of 128 bytes. 653 * This register is only accessible to the host. 654 */ 655 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 656 START_CTL_EMFU | READ_CMD_MRM); 657 break; 658 659 case ADW_CHIP_ASC38C0800: 660 /* 661 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 662 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 663 * cable detection and then we are able to read C_DET[3:0]. 664 * 665 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 666 * Microcode Default Value' section below. 667 */ 668 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 669 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 670 | ADW_DIS_TERM_DRV); 671 672 /* 673 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 674 * START_CTL_TH [3:2] bits for the default FIFO threshold. 675 * 676 * Note: ASC-38C0800 FIFO threshold has been changed to 677 * 256 bytes. 678 * 679 * For DMA Errata #4 set the BC_THRESH_ENB bit. 680 */ 681 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 682 BC_THRESH_ENB | FIFO_THRESH_80B 683 | START_CTL_TH | READ_CMD_MRM); 684 break; 685 686 case ADW_CHIP_ASC38C1600: 687 /* 688 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 689 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 690 * cable detection and then we are able to read C_DET[3:0]. 691 * 692 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 693 * Microcode Default Value' section below. 694 */ 695 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 696 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 697 | ADW_DIS_TERM_DRV); 698 699 /* 700 * If the BIOS control flag AIPP (Asynchronous Information 701 * Phase Protection) disable bit is not set, then set the 702 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 703 * enable AIPP checking and encoding. 704 */ 705 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 706 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 707 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 708 word | CONTROL_FLAG_ENABLE_AIPP); 709 } 710 711 /* 712 * For ASC-38C1600 use DMA_CFG0 default values: 713 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 714 */ 715 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 716 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 717 break; 718 } 719 720 /* 721 * Microcode operating variables for WDTR, SDTR, and command tag 722 * queuing will be set in AdvInquiryHandling() based on what a 723 * device reports it is capable of in Inquiry byte 7. 724 * 725 * If SCSI Bus Resets have been disabled, then directly set 726 * SDTR and WDTR from the EEPROM configuration. This will allow 727 * the BIOS and warm boot to work without a SCSI bus hang on 728 * the Inquiry caused by host and target mismatched DTR values. 729 * Without the SCSI Bus Reset, before an Inquiry a device can't 730 * be assumed to be in Asynchronous, Narrow mode. 731 */ 732 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 733 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 734 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 735 } 736 737 /* 738 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 739 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 740 * bitmask. These values determine the maximum SDTR speed negotiated 741 * with a device. 742 * 743 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 744 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 745 * without determining here whether the device supports SDTR. 746 */ 747 switch (sc->chip_type) { 748 case ADW_CHIP_ASC3550: 749 word = 0; 750 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 751 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 752 /* Set Ultra speed for TID 'tid'. */ 753 word |= (0x3 << (4 * (tid % 4))); 754 } else { 755 /* Set Fast speed for TID 'tid'. */ 756 word |= (0x2 << (4 * (tid % 4))); 757 } 758 /* Check if done with sdtr_speed1. */ 759 if (tid == 3) { 760 ADW_WRITE_WORD_LRAM(iot, ioh, 761 ADW_MC_SDTR_SPEED1, word); 762 word = 0; 763 /* Check if done with sdtr_speed2. */ 764 } else if (tid == 7) { 765 ADW_WRITE_WORD_LRAM(iot, ioh, 766 ADW_MC_SDTR_SPEED2, word); 767 word = 0; 768 /* Check if done with sdtr_speed3. */ 769 } else if (tid == 11) { 770 ADW_WRITE_WORD_LRAM(iot, ioh, 771 ADW_MC_SDTR_SPEED3, word); 772 word = 0; 773 /* Check if done with sdtr_speed4. */ 774 } else if (tid == 15) { 775 ADW_WRITE_WORD_LRAM(iot, ioh, 776 ADW_MC_SDTR_SPEED4, word); 777 /* End of loop. */ 778 } 779 } 780 781 /* 782 * Set microcode operating variable for the 783 * disconnect per TID bitmask. 784 */ 785 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 786 sc->cfg.disc_enable); 787 break; 788 789 case ADW_CHIP_ASC38C0800: 790 /* FALLTHROUGH */ 791 case ADW_CHIP_ASC38C1600: 792 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 793 sc->cfg.disc_enable); 794 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 795 sc->sdtr_speed1); 796 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 797 sc->sdtr_speed2); 798 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 799 sc->sdtr_speed3); 800 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 801 sc->sdtr_speed4); 802 break; 803 } 804 805 806 /* 807 * Set SCSI_CFG0 Microcode Default Value. 808 * 809 * The microcode will set the SCSI_CFG0 register using this value 810 * after it is started below. 811 */ 812 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 813 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 814 ADW_OUR_ID_EN | sc->chip_scsi_id); 815 816 817 switch(sc->chip_type) { 818 case ADW_CHIP_ASC3550: 819 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 820 break; 821 822 case ADW_CHIP_ASC38C0800: 823 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 824 break; 825 826 case ADW_CHIP_ASC38C1600: 827 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 828 break; 829 } 830 if(error_code) { 831 return error_code; 832 } 833 834 /* 835 * Set SEL_MASK Microcode Default Value 836 * 837 * The microcode will set the SEL_MASK register using this value 838 * after it is started below. 839 */ 840 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 841 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 842 843 /* 844 * Create and Initialize Host->RISC Carrier lists 845 */ 846 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 847 sc->sc_control->carriers); 848 849 /* 850 * Set-up the Host->RISC Initiator Command Queue (ICQ). 851 */ 852 853 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 854 return ADW_IERR_NO_CARRIER; 855 } 856 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 857 ASC_GET_CARRP(sc->icq_sp->next_ba)); 858 859 /* 860 * The first command issued will be placed in the stopper carrier. 861 */ 862 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER); 863 864 /* 865 * Set RISC ICQ physical address start value. 866 */ 867 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba)); 868 869 /* 870 * Initialize the COMMA register to the same value otherwise 871 * the RISC will prematurely detect a command is available. 872 */ 873 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 874 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 875 le32toh(sc->icq_sp->carr_ba)); 876 } 877 878 /* 879 * Set-up the RISC->Host Initiator Response Queue (IRQ). 880 */ 881 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 882 return ADW_IERR_NO_CARRIER; 883 } 884 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 885 ASC_GET_CARRP(sc->irq_sp->next_ba)); 886 887 /* 888 * The first command completed by the RISC will be placed in 889 * the stopper. 890 * 891 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 892 * completed the RISC will set the ASC_RQ_DONE bit. 893 */ 894 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER); 895 896 /* 897 * Set RISC IRQ physical address start value. 898 */ 899 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba)); 900 sc->carr_pending_cnt = 0; 901 902 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 903 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 904 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 905 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 906 907 /* finally, finally, gentlemen, start your engine */ 908 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 909 910 /* 911 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 912 * Resets should be performed. The RISC has to be running 913 * to issue a SCSI Bus Reset. 914 */ 915 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 916 { 917 /* 918 * If the BIOS Signature is present in memory, restore the 919 * BIOS Handshake Configuration Table and do not perform 920 * a SCSI Bus Reset. 921 */ 922 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 923 0x55AA) { 924 /* 925 * Restore per TID negotiated values. 926 */ 927 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 928 wdtr_able); 929 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 930 sdtr_able); 931 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 932 tagqng_able); 933 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 934 ADW_WRITE_BYTE_LRAM(iot, ioh, 935 ADW_MC_NUMBER_OF_MAX_CMD + tid, 936 max_cmd[tid]); 937 } 938 } else { 939 if (AdwResetCCB(sc) != ADW_TRUE) { 940 error_code = ADW_WARN_BUSRESET_ERROR; 941 } 942 } 943 } 944 945 return error_code; 946 } 947 948 949 int 950 AdwRamSelfTest(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t chip_type) 951 { 952 int i; 953 u_int8_t byte; 954 955 956 if ((chip_type == ADW_CHIP_ASC38C0800) || 957 (chip_type == ADW_CHIP_ASC38C1600)) { 958 /* 959 * RAM BIST (RAM Built-In Self Test) 960 * 961 * Address : I/O base + offset 0x38h register (byte). 962 * Function: Bit 7-6(RW) : RAM mode 963 * Normal Mode : 0x00 964 * Pre-test Mode : 0x40 965 * RAM Test Mode : 0x80 966 * Bit 5 : unused 967 * Bit 4(RO) : Done bit 968 * Bit 3-0(RO) : Status 969 * Host Error : 0x08 970 * Int_RAM Error : 0x04 971 * RISC Error : 0x02 972 * SCSI Error : 0x01 973 * No Error : 0x00 974 * 975 * Note: RAM BIST code should be put right here, before loading 976 * the microcode and after saving the RISC memory BIOS region. 977 */ 978 979 /* 980 * LRAM Pre-test 981 * 982 * Write PRE_TEST_MODE (0x40) to register and wait for 983 * 10 milliseconds. 984 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 985 * return an error. Reset to NORMAL_MODE (0x00) and do again. 986 * If cannot reset to NORMAL_MODE, return an error too. 987 */ 988 for (i = 0; i < 2; i++) { 989 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 990 PRE_TEST_MODE); 991 /* Wait for 10ms before reading back. */ 992 AdwSleepMilliSecond(10); 993 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 994 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 995 PRE_TEST_VALUE) { 996 return ADW_IERR_BIST_PRE_TEST; 997 } 998 999 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 1000 NORMAL_MODE); 1001 /* Wait for 10ms before reading back. */ 1002 AdwSleepMilliSecond(10); 1003 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1004 != NORMAL_VALUE) { 1005 return ADW_IERR_BIST_PRE_TEST; 1006 } 1007 } 1008 1009 /* 1010 * LRAM Test - It takes about 1.5 ms to run through the test. 1011 * 1012 * Write RAM_TEST_MODE (0x80) to register and wait for 1013 * 10 milliseconds. 1014 * If Done bit not set or Status not 0, save register byte, 1015 * set the err_code, and return an error. 1016 */ 1017 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1018 /* Wait for 10ms before checking status. */ 1019 AdwSleepMilliSecond(10); 1020 1021 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1022 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1023 /* Get here if Done bit not set or Status not 0. */ 1024 return ADW_IERR_BIST_RAM_TEST; 1025 } 1026 1027 /* We need to reset back to normal mode after LRAM test passes*/ 1028 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1029 } 1030 1031 return 0; 1032 } 1033 1034 1035 int 1036 AdwLoadMCode(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t *bios_mem, u_int8_t chip_type) 1037 { 1038 const u_int8_t *mcode_data; 1039 u_int32_t mcode_chksum; 1040 u_int16_t mcode_size; 1041 u_int32_t sum; 1042 u_int16_t code_sum; 1043 int begin_addr; 1044 int end_addr; 1045 int word; 1046 int adw_memsize; 1047 int adw_mcode_expanded_size; 1048 int i, j; 1049 1050 1051 switch(chip_type) { 1052 case ADW_CHIP_ASC3550: 1053 mcode_data = (const u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1054 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1055 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1056 adw_memsize = ADW_3550_MEMSIZE; 1057 break; 1058 1059 case ADW_CHIP_ASC38C0800: 1060 mcode_data = (const u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1061 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1062 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1063 adw_memsize = ADW_38C0800_MEMSIZE; 1064 break; 1065 1066 case ADW_CHIP_ASC38C1600: 1067 mcode_data = (const u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1068 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1069 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1070 adw_memsize = ADW_38C1600_MEMSIZE; 1071 break; 1072 1073 default: 1074 return (EINVAL); 1075 } 1076 1077 /* 1078 * Write the microcode image to RISC memory starting at address 0. 1079 */ 1080 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1081 1082 /* Assume the following compressed format of the microcode buffer: 1083 * 1084 * 254 word (508 byte) table indexed by byte code followed 1085 * by the following byte codes: 1086 * 1087 * 1-Byte Code: 1088 * 00: Emit word 0 in table. 1089 * 01: Emit word 1 in table. 1090 * . 1091 * FD: Emit word 253 in table. 1092 * 1093 * Multi-Byte Code: 1094 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1095 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1096 */ 1097 word = 0; 1098 for (i = 253 * 2; i < mcode_size; i++) { 1099 if (mcode_data[i] == 0xff) { 1100 for (j = 0; j < mcode_data[i + 1]; j++) { 1101 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1102 (((u_int16_t)mcode_data[i + 3] << 8) | 1103 mcode_data[i + 2])); 1104 word++; 1105 } 1106 i += 3; 1107 } else if (mcode_data[i] == 0xfe) { 1108 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1109 (((u_int16_t)mcode_data[i + 2] << 8) | 1110 mcode_data[i + 1])); 1111 i += 2; 1112 word++; 1113 } else { 1114 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1115 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1116 mcode_data[mcode_data[i] * 2])); 1117 word++; 1118 } 1119 } 1120 1121 /* 1122 * Set 'word' for later use to clear the rest of memory and save 1123 * the expanded mcode size. 1124 */ 1125 word *= 2; 1126 adw_mcode_expanded_size = word; 1127 1128 /* 1129 * Clear the rest of the Internal RAM. 1130 */ 1131 for (; word < adw_memsize; word += 2) { 1132 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1133 } 1134 1135 /* 1136 * Verify the microcode checksum. 1137 */ 1138 sum = 0; 1139 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1140 1141 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1142 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1143 } 1144 1145 if (sum != mcode_chksum) { 1146 return ADW_IERR_MCODE_CHKSUM; 1147 } 1148 1149 /* 1150 * Restore the RISC memory BIOS region. 1151 */ 1152 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1153 if(chip_type == ADW_CHIP_ASC3550) { 1154 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1155 bios_mem[i]); 1156 } else { 1157 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1158 bios_mem[i]); 1159 } 1160 } 1161 1162 /* 1163 * Calculate and write the microcode code checksum to the microcode 1164 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1165 */ 1166 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1167 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1168 code_sum = 0; 1169 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1170 for (word = begin_addr; word < end_addr; word += 2) { 1171 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1172 } 1173 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1174 1175 /* 1176 * Set the chip type. 1177 */ 1178 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1179 1180 return 0; 1181 } 1182 1183 1184 int 1185 AdwASC3550Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1186 { 1187 u_int16_t scsi_cfg1; 1188 1189 1190 /* 1191 * Determine SCSI_CFG1 Microcode Default Value. 1192 * 1193 * The microcode will set the SCSI_CFG1 register using this value 1194 * after it is started below. 1195 */ 1196 1197 /* Read current SCSI_CFG1 Register value. */ 1198 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1199 1200 /* 1201 * If all three connectors are in use in ASC3550, return an error. 1202 */ 1203 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1204 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1205 return ADW_IERR_ILLEGAL_CONNECTION; 1206 } 1207 1208 /* 1209 * If the cable is reversed all of the SCSI_CTRL register signals 1210 * will be set. Check for and return an error if this condition is 1211 * found. 1212 */ 1213 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1214 return ADW_IERR_REVERSED_CABLE; 1215 } 1216 1217 /* 1218 * If this is a differential board and a single-ended device 1219 * is attached to one of the connectors, return an error. 1220 */ 1221 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1222 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1223 return ADW_IERR_SINGLE_END_DEVICE; 1224 } 1225 1226 /* 1227 * If automatic termination control is enabled, then set the 1228 * termination value based on a table listed in a_condor.h. 1229 * 1230 * If manual termination was specified with an EEPROM setting 1231 * then 'termination' was set-up in AdwInitFromEEPROM() and 1232 * is ready to be 'ored' into SCSI_CFG1. 1233 */ 1234 if (cfg->termination == 0) { 1235 /* 1236 * The software always controls termination by setting 1237 * TERM_CTL_SEL. 1238 * If TERM_CTL_SEL were set to 0, the hardware would set 1239 * termination. 1240 */ 1241 cfg->termination |= ADW_TERM_CTL_SEL; 1242 1243 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1244 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1245 case 0x3: case 0x7: case 0xB: 1246 case 0xD: case 0xE: case 0xF: 1247 cfg->termination |= 1248 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1249 break; 1250 1251 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1252 case 0x1: case 0x5: case 0x9: 1253 case 0xA: case 0xC: 1254 cfg->termination |= ADW_TERM_CTL_H; 1255 break; 1256 1257 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1258 case 0x2: case 0x6: 1259 break; 1260 } 1261 } 1262 1263 /* 1264 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1265 */ 1266 scsi_cfg1 &= ~ADW_TERM_CTL; 1267 1268 /* 1269 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1270 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1271 * referenced, because the hardware internally inverts 1272 * the Termination High and Low bits if TERM_POL is set. 1273 */ 1274 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1275 1276 /* 1277 * Set SCSI_CFG1 Microcode Default Value 1278 * 1279 * Set filter value and possibly modified termination control 1280 * bits in the Microcode SCSI_CFG1 Register Value. 1281 * 1282 * The microcode will set the SCSI_CFG1 register using this value 1283 * after it is started below. 1284 */ 1285 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1286 ADW_FLTR_DISABLE | scsi_cfg1); 1287 1288 /* 1289 * Set MEM_CFG Microcode Default Value 1290 * 1291 * The microcode will set the MEM_CFG register using this value 1292 * after it is started below. 1293 * 1294 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1295 * are defined. 1296 * 1297 * ASC-3550 has 8KB internal memory. 1298 */ 1299 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1300 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1301 1302 return 0; 1303 } 1304 1305 1306 int 1307 AdwASC38C0800Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1308 { 1309 u_int16_t scsi_cfg1; 1310 1311 1312 /* 1313 * Determine SCSI_CFG1 Microcode Default Value. 1314 * 1315 * The microcode will set the SCSI_CFG1 register using this value 1316 * after it is started below. 1317 */ 1318 1319 /* Read current SCSI_CFG1 Register value. */ 1320 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1321 1322 /* 1323 * If the cable is reversed all of the SCSI_CTRL register signals 1324 * will be set. Check for and return an error if this condition is 1325 * found. 1326 */ 1327 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1328 return ADW_IERR_REVERSED_CABLE; 1329 } 1330 1331 /* 1332 * All kind of combinations of devices attached to one of four 1333 * connectors are acceptable except HVD device attached. 1334 * For example, LVD device can be attached to SE connector while 1335 * SE device attached to LVD connector. 1336 * If LVD device attached to SE connector, it only runs up to 1337 * Ultra speed. 1338 * 1339 * If an HVD device is attached to one of LVD connectors, return 1340 * an error. 1341 * However, there is no way to detect HVD device attached to 1342 * SE connectors. 1343 */ 1344 if (scsi_cfg1 & ADW_HVD) { 1345 return ADW_IERR_HVD_DEVICE; 1346 } 1347 1348 /* 1349 * If either SE or LVD automatic termination control is enabled, then 1350 * set the termination value based on a table listed in a_condor.h. 1351 * 1352 * If manual termination was specified with an EEPROM setting then 1353 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1354 * to be 'ored' into SCSI_CFG1. 1355 */ 1356 if ((cfg->termination & ADW_TERM_SE) == 0) { 1357 /* SE automatic termination control is enabled. */ 1358 switch(scsi_cfg1 & ADW_C_DET_SE) { 1359 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1360 case 0x1: case 0x2: case 0x3: 1361 cfg->termination |= ADW_TERM_SE; 1362 break; 1363 1364 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1365 case 0x0: 1366 cfg->termination |= ADW_TERM_SE_HI; 1367 break; 1368 } 1369 } 1370 1371 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1372 /* LVD automatic termination control is enabled. */ 1373 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1374 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1375 case 0x4: case 0x8: case 0xC: 1376 cfg->termination |= ADW_TERM_LVD; 1377 break; 1378 1379 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1380 case 0x0: 1381 break; 1382 } 1383 } 1384 1385 /* 1386 * Clear any set TERM_SE and TERM_LVD bits. 1387 */ 1388 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1389 1390 /* 1391 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1392 */ 1393 scsi_cfg1 |= (~cfg->termination & 0xF0); 1394 1395 /* 1396 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1397 * HVD/LVD/SE bits and set possibly modified termination control bits 1398 * in the Microcode SCSI_CFG1 Register Value. 1399 */ 1400 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1401 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1402 1403 /* 1404 * Set SCSI_CFG1 Microcode Default Value 1405 * 1406 * Set possibly modified termination control and reset DIS_TERM_DRV 1407 * bits in the Microcode SCSI_CFG1 Register Value. 1408 * 1409 * The microcode will set the SCSI_CFG1 register using this value 1410 * after it is started below. 1411 */ 1412 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1413 1414 /* 1415 * Set MEM_CFG Microcode Default Value 1416 * 1417 * The microcode will set the MEM_CFG register using this value 1418 * after it is started below. 1419 * 1420 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1421 * are defined. 1422 * 1423 * ASC-38C0800 has 16KB internal memory. 1424 */ 1425 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1426 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1427 1428 return 0; 1429 } 1430 1431 1432 int 1433 AdwASC38C1600Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1434 { 1435 u_int16_t scsi_cfg1; 1436 1437 1438 /* 1439 * Determine SCSI_CFG1 Microcode Default Value. 1440 * 1441 * The microcode will set the SCSI_CFG1 register using this value 1442 * after it is started below. 1443 * Each ASC-38C1600 function has only two cable detect bits. 1444 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1445 */ 1446 1447 /* Read current SCSI_CFG1 Register value. */ 1448 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1449 1450 /* 1451 * If the cable is reversed all of the SCSI_CTRL register signals 1452 * will be set. Check for and return an error if this condition is 1453 * found. 1454 */ 1455 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1456 return ADW_IERR_REVERSED_CABLE; 1457 } 1458 1459 /* 1460 * Each ASC-38C1600 function has two connectors. Only an HVD device 1461 * cannot be connected to either connector. An LVD device or SE device 1462 * may be connected to either connector. If an SE device is connected, 1463 * then at most Ultra speed (20 MHz) can be used on both connectors. 1464 * 1465 * If an HVD device is attached, return an error. 1466 */ 1467 if (scsi_cfg1 & ADW_HVD) { 1468 return ADW_IERR_HVD_DEVICE; 1469 } 1470 1471 /* 1472 * Each function in the ASC-38C1600 uses only the SE cable detect and 1473 * termination because there are two connectors for each function. 1474 * Each function may use either LVD or SE mode. 1475 * Corresponding the SE automatic termination control EEPROM bits are 1476 * used for each function. 1477 * Each function has its own EEPROM. If SE automatic control is enabled 1478 * for the function, then set the termination value based on a table 1479 * listed in adwlib.h. 1480 * 1481 * If manual termination is specified in the EEPROM for the function, 1482 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1483 * ready to be 'ored' into SCSI_CFG1. 1484 */ 1485 if ((cfg->termination & ADW_TERM_SE) == 0) { 1486 /* SE automatic termination control is enabled. */ 1487 switch(scsi_cfg1 & ADW_C_DET_SE) { 1488 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1489 case 0x1: case 0x2: case 0x3: 1490 cfg->termination |= ADW_TERM_SE; 1491 break; 1492 1493 case 0x0: 1494 #if 0 1495 /* !!!!TODO!!!! */ 1496 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1497 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1498 } 1499 else 1500 #endif 1501 { 1502 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1503 cfg->termination |= ADW_TERM_SE_HI; 1504 } 1505 break; 1506 } 1507 } 1508 1509 /* 1510 * Clear any set TERM_SE bits. 1511 */ 1512 scsi_cfg1 &= ~ADW_TERM_SE; 1513 1514 /* 1515 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1516 */ 1517 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1518 1519 /* 1520 * Clear Big Endian and Terminator Polarity bits and set possibly 1521 * modified termination control bits in the Microcode SCSI_CFG1 1522 * Register Value. 1523 */ 1524 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1525 1526 /* 1527 * Set SCSI_CFG1 Microcode Default Value 1528 * 1529 * Set possibly modified termination control bits in the Microcode 1530 * SCSI_CFG1 Register Value. 1531 * 1532 * The microcode will set the SCSI_CFG1 register using this value 1533 * after it is started below. 1534 */ 1535 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1536 1537 /* 1538 * Set MEM_CFG Microcode Default Value 1539 * 1540 * The microcode will set the MEM_CFG register using this value 1541 * after it is started below. 1542 * 1543 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1544 * are defined. 1545 * 1546 * ASC-38C1600 has 32KB internal memory. 1547 */ 1548 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1549 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1550 1551 return 0; 1552 } 1553 1554 1555 /* 1556 * Read EEPROM configuration into the specified buffer. 1557 * 1558 * Return a checksum based on the EEPROM configuration read. 1559 */ 1560 static u_int16_t 1561 AdwGetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1562 { 1563 u_int16_t wval, chksum; 1564 u_int16_t *wbuf; 1565 int eep_addr; 1566 1567 1568 wbuf = (u_int16_t *) cfg_buf; 1569 chksum = 0; 1570 1571 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1572 eep_addr < ASC_EEP_DVC_CFG_END; 1573 eep_addr++, wbuf++) { 1574 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1575 chksum += wval; 1576 *wbuf = wval; 1577 } 1578 1579 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1580 wbuf++; 1581 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1582 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1583 eep_addr++, wbuf++) { 1584 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1585 } 1586 1587 return chksum; 1588 } 1589 1590 1591 /* 1592 * Read the EEPROM from specified location 1593 */ 1594 static u_int16_t 1595 AdwReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, int eep_word_addr) 1596 { 1597 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1598 ASC_EEP_CMD_READ | eep_word_addr); 1599 AdwWaitEEPCmd(iot, ioh); 1600 1601 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1602 } 1603 1604 1605 /* 1606 * Wait for EEPROM command to complete 1607 */ 1608 static void 1609 AdwWaitEEPCmd(bus_space_tag_t iot, bus_space_handle_t ioh) 1610 { 1611 int eep_delay_ms; 1612 1613 1614 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1615 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1616 ASC_EEP_CMD_DONE) { 1617 break; 1618 } 1619 AdwSleepMilliSecond(1); 1620 } 1621 1622 (void)ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1623 } 1624 1625 1626 /* 1627 * Write the EEPROM from 'cfg_buf'. 1628 */ 1629 static void 1630 AdwSetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1631 { 1632 u_int16_t *wbuf; 1633 u_int16_t addr, chksum; 1634 1635 1636 wbuf = (u_int16_t *) cfg_buf; 1637 chksum = 0; 1638 1639 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1640 AdwWaitEEPCmd(iot, ioh); 1641 1642 /* 1643 * Write EEPROM from word 0 to word 20 1644 */ 1645 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1646 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1647 chksum += *wbuf; 1648 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1649 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1650 ASC_EEP_CMD_WRITE | addr); 1651 AdwWaitEEPCmd(iot, ioh); 1652 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1653 } 1654 1655 /* 1656 * Write EEPROM checksum at word 21 1657 */ 1658 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1659 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1660 ASC_EEP_CMD_WRITE | addr); 1661 AdwWaitEEPCmd(iot, ioh); 1662 wbuf++; /* skip over check_sum */ 1663 1664 /* 1665 * Write EEPROM OEM name at words 22 to 29 1666 */ 1667 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1668 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1670 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1671 ASC_EEP_CMD_WRITE | addr); 1672 AdwWaitEEPCmd(iot, ioh); 1673 } 1674 1675 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1676 ASC_EEP_CMD_WRITE_DISABLE); 1677 AdwWaitEEPCmd(iot, ioh); 1678 1679 return; 1680 } 1681 1682 1683 /* 1684 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1685 * 1686 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1687 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1688 * RISC to notify it a new command is ready to be executed. 1689 * 1690 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1691 * set to SCSI_MAX_RETRY. 1692 * 1693 * Return: 1694 * ADW_SUCCESS(1) - The request was successfully queued. 1695 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1696 * request completes. 1697 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1698 * host IC error. 1699 */ 1700 int 1701 AdwExeScsiQueue(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 1702 { 1703 bus_space_tag_t iot = sc->sc_iot; 1704 bus_space_handle_t ioh = sc->sc_ioh; 1705 ADW_CCB *ccb; 1706 u_int32_t req_paddr; 1707 ADW_CARRIER *new_carrp; 1708 1709 /* 1710 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1711 */ 1712 if (scsiq->target_id > ADW_MAX_TID) { 1713 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1714 scsiq->done_status = QD_WITH_ERROR; 1715 return ADW_ERROR; 1716 } 1717 1718 /* 1719 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1720 */ 1721 1722 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1723 1724 /* 1725 * Allocate a carrier and initialize fields. 1726 */ 1727 if ((new_carrp = sc->carr_freelist) == NULL) { 1728 return ADW_BUSY; 1729 } 1730 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1731 ASC_GET_CARRP(new_carrp->next_ba)); 1732 sc->carr_pending_cnt++; 1733 1734 /* 1735 * Set the carrier to be a stopper by setting 'next_ba' 1736 * to the stopper value. The current stopper will be changed 1737 * below to point to the new stopper. 1738 */ 1739 new_carrp->next_ba = htole32(ASC_CQ_STOPPER); 1740 1741 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1742 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1743 1744 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1745 scsiq->scsiq_rptr = htole32(req_paddr); 1746 1747 /* 1748 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1749 * order during initialization. 1750 */ 1751 scsiq->carr_ba = sc->icq_sp->carr_ba; 1752 scsiq->carr_va = sc->icq_sp->carr_ba; 1753 1754 /* 1755 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1756 * the microcode. The newly allocated stopper will become the new 1757 * stopper. 1758 */ 1759 sc->icq_sp->areq_ba = htole32(req_paddr); 1760 1761 /* 1762 * Set the 'next_ba' pointer for the old stopper to be the 1763 * physical address of the new stopper. The RISC can only 1764 * follow physical addresses. 1765 */ 1766 sc->icq_sp->next_ba = new_carrp->carr_ba; 1767 1768 #if ADW_DEBUG 1769 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1770 sc->icq_sp->carr_id, 1771 sc->icq_sp->carr_ba, 1772 sc->icq_sp->areq_ba, 1773 sc->icq_sp->next_ba); 1774 #endif 1775 /* 1776 * Set the host adapter stopper pointer to point to the new carrier. 1777 */ 1778 sc->icq_sp = new_carrp; 1779 1780 if (sc->chip_type == ADW_CHIP_ASC3550 || 1781 sc->chip_type == ADW_CHIP_ASC38C0800) { 1782 /* 1783 * Tickle the RISC to tell it to read its Command Queue Head 1784 * pointer. 1785 */ 1786 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1787 if (sc->chip_type == ADW_CHIP_ASC3550) { 1788 /* 1789 * Clear the tickle value. In the ASC-3550 the RISC flag 1790 * command 'clr_tickle_a' does not work unless the host 1791 * value is cleared. 1792 */ 1793 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1794 ADW_TICKLE_NOP); 1795 } 1796 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1797 /* 1798 * Notify the RISC a carrier is ready by writing the physical 1799 * address of the new carrier stopper to the COMMA register. 1800 */ 1801 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1802 le32toh(new_carrp->carr_ba)); 1803 } 1804 1805 /* 1806 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1807 */ 1808 1809 return ADW_SUCCESS; 1810 } 1811 1812 1813 void 1814 AdwResetChip(bus_space_tag_t iot, bus_space_handle_t ioh) 1815 { 1816 1817 /* 1818 * Reset Chip. 1819 */ 1820 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1821 ADW_CTRL_REG_CMD_RESET); 1822 AdwSleepMilliSecond(100); 1823 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1824 ADW_CTRL_REG_CMD_WR_IO_REG); 1825 } 1826 1827 1828 /* 1829 * Reset SCSI Bus and purge all outstanding requests. 1830 * 1831 * Return Value: 1832 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1833 * ADW_FALSE(0) - Microcode command failed. 1834 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1835 * may be hung which requires driver recovery. 1836 */ 1837 int 1838 AdwResetCCB(ADW_SOFTC *sc) 1839 { 1840 int status; 1841 1842 /* 1843 * Send the SCSI Bus Reset idle start idle command which asserts 1844 * the SCSI Bus Reset signal. 1845 */ 1846 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1847 if (status != ADW_TRUE) { 1848 return status; 1849 } 1850 1851 /* 1852 * Delay for the specified SCSI Bus Reset hold time. 1853 * 1854 * The hold time delay is done on the host because the RISC has no 1855 * microsecond accurate timer. 1856 */ 1857 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1858 1859 /* 1860 * Send the SCSI Bus Reset end idle command which de-asserts 1861 * the SCSI Bus Reset signal and purges any pending requests. 1862 */ 1863 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1864 if (status != ADW_TRUE) { 1865 return status; 1866 } 1867 1868 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1869 1870 return status; 1871 } 1872 1873 1874 /* 1875 * Reset chip and SCSI Bus. 1876 * 1877 * Return Value: 1878 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1879 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1880 */ 1881 int 1882 AdwResetSCSIBus(ADW_SOFTC *sc) 1883 { 1884 bus_space_tag_t iot = sc->sc_iot; 1885 bus_space_handle_t ioh = sc->sc_ioh; 1886 int status; 1887 u_int16_t wdtr_able, sdtr_able, tagqng_able; 1888 u_int16_t ppr_able = 0; /* XXX: gcc */ 1889 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1890 u_int16_t bios_sig; 1891 1892 1893 /* 1894 * Save current per TID negotiated values. 1895 */ 1896 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1897 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1898 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1899 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1900 } 1901 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1902 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1903 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1904 max_cmd[tid]); 1905 } 1906 1907 /* 1908 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1909 * by clearing the BIOS signature word. 1910 * The initialization functions assumes a SCSI Bus Reset is not 1911 * needed if the BIOS signature word is present. 1912 */ 1913 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1914 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1915 1916 /* 1917 * Stop chip and reset it. 1918 */ 1919 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1920 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1921 ADW_CTRL_REG_CMD_RESET); 1922 AdwSleepMilliSecond(100); 1923 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1924 ADW_CTRL_REG_CMD_WR_IO_REG); 1925 1926 /* 1927 * Reset Adv Library error code, if any, and try 1928 * re-initializing the chip. 1929 * Then translate initialization return value to status value. 1930 */ 1931 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1932 1933 /* 1934 * Restore the BIOS signature word. 1935 */ 1936 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1937 1938 /* 1939 * Restore per TID negotiated values. 1940 */ 1941 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1942 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1943 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1944 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1945 } 1946 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1947 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1948 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1949 max_cmd[tid]); 1950 } 1951 1952 return status; 1953 } 1954 1955 1956 /* 1957 * Adv Library Interrupt Service Routine 1958 * 1959 * This function is called by a driver's interrupt service routine. 1960 * The function disables and re-enables interrupts. 1961 * 1962 * When a microcode idle command is completed, the ADV_DVC_VAR 1963 * 'idle_cmd_done' field is set to ADW_TRUE. 1964 * 1965 * Note: AdwISR() can be called when interrupts are disabled or even 1966 * when there is no hardware interrupt condition present. It will 1967 * always check for completed idle commands and microcode requests. 1968 * This is an important feature that shouldn't be changed because it 1969 * allows commands to be completed from polling mode loops. 1970 * 1971 * Return: 1972 * ADW_TRUE(1) - interrupt was pending 1973 * ADW_FALSE(0) - no interrupt was pending 1974 */ 1975 int 1976 AdwISR(ADW_SOFTC *sc) 1977 { 1978 bus_space_tag_t iot = sc->sc_iot; 1979 bus_space_handle_t ioh = sc->sc_ioh; 1980 u_int8_t int_stat; 1981 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 1982 u_int32_t irq_next_pa; 1983 ADW_SCSI_REQ_Q *scsiq; 1984 ADW_CCB *ccb; 1985 int s; 1986 1987 1988 s = splbio(); 1989 1990 /* Reading the register clears the interrupt. */ 1991 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 1992 1993 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 1994 ADW_INTR_STATUS_INTRC)) == 0) { 1995 splx(s); 1996 return ADW_FALSE; 1997 } 1998 1999 /* 2000 * Notify the driver of an asynchronous microcode condition by 2001 * calling the ADV_DVC_VAR.async_callback function. The function 2002 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2003 */ 2004 if (int_stat & ADW_INTR_STATUS_INTRB) { 2005 u_int8_t intrb_code; 2006 2007 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2008 2009 if (sc->chip_type == ADW_CHIP_ASC3550 || 2010 sc->chip_type == ADW_CHIP_ASC38C0800) { 2011 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2012 sc->carr_pending_cnt != 0) { 2013 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2014 IOPB_TICKLE, ADW_TICKLE_A); 2015 if (sc->chip_type == ADW_CHIP_ASC3550) { 2016 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2017 IOPB_TICKLE, ADW_TICKLE_NOP); 2018 } 2019 } 2020 } 2021 2022 if (sc->async_callback != 0) { 2023 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2024 } 2025 } 2026 2027 /* 2028 * Check if the IRQ stopper carrier contains a completed request. 2029 */ 2030 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0) 2031 { 2032 #if ADW_DEBUG 2033 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2034 sc->irq_sp->carr_id, 2035 sc->irq_sp->carr_ba, 2036 sc->irq_sp->areq_ba, 2037 sc->irq_sp->next_ba); 2038 #endif 2039 /* 2040 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2041 * structure. 2042 * The RISC will have set 'areq_ba' to a virtual address. 2043 * 2044 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2045 * field to the carrier ADV_CARR_T.areq_ba field. 2046 * The conversion below complements the conversion of 2047 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2048 */ 2049 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2050 scsiq = &ccb->scsiq; 2051 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2052 2053 /* 2054 * Request finished with good status and the queue was not 2055 * DMAed to host memory by the firmware. Set all status fields 2056 * to indicate good status. 2057 */ 2058 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) { 2059 scsiq->done_status = QD_NO_ERROR; 2060 scsiq->host_status = scsiq->scsi_status = 0; 2061 scsiq->data_cnt = 0L; 2062 } 2063 2064 /* 2065 * Advance the stopper pointer to the next carrier 2066 * ignoring the lower four bits. Free the previous 2067 * stopper carrier. 2068 */ 2069 free_carrp = sc->irq_sp; 2070 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2071 2072 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0 2073 : sc->carr_freelist->carr_ba; 2074 sc->carr_freelist = free_carrp; 2075 sc->carr_pending_cnt--; 2076 2077 /* 2078 * Clear request microcode control flag. 2079 */ 2080 scsiq->cntl = 0; 2081 2082 /* 2083 * Check Condition handling 2084 */ 2085 /* 2086 * If the command that completed was a SCSI INQUIRY and 2087 * LUN 0 was sent the command, then process the INQUIRY 2088 * command information for the device. 2089 */ 2090 if (scsiq->done_status == QD_NO_ERROR && 2091 scsiq->cdb[0] == INQUIRY && 2092 scsiq->target_lun == 0) { 2093 AdwInquiryHandling(sc, scsiq); 2094 } 2095 2096 /* 2097 * Notify the driver of the completed request by passing 2098 * the ADW_SCSI_REQ_Q pointer to its callback function. 2099 */ 2100 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2101 /* 2102 * Note: After the driver callback function is called, 'scsiq' 2103 * can no longer be referenced. 2104 * 2105 * Fall through and continue processing other completed 2106 * requests... 2107 */ 2108 } 2109 2110 splx(s); 2111 2112 return ADW_TRUE; 2113 } 2114 2115 2116 /* 2117 * Send an idle command to the chip and wait for completion. 2118 * 2119 * Command completion is polled for once per microsecond. 2120 * 2121 * The function can be called from anywhere including an interrupt handler. 2122 * But the function is not re-entrant, so it uses the splbio/splx() 2123 * functions to prevent reentrancy. 2124 * 2125 * Return Values: 2126 * ADW_TRUE - command completed successfully 2127 * ADW_FALSE - command failed 2128 * ADW_ERROR - command timed out 2129 */ 2130 int 2131 AdwSendIdleCmd(ADW_SOFTC *sc, u_int16_t idle_cmd, u_int32_t idle_cmd_parameter) 2132 { 2133 bus_space_tag_t iot = sc->sc_iot; 2134 bus_space_handle_t ioh = sc->sc_ioh; 2135 u_int16_t result; 2136 u_int32_t i, j, s; 2137 2138 s = splbio(); 2139 2140 /* 2141 * Clear the idle command status which is set by the microcode 2142 * to a non-zero value to indicate when the command is completed. 2143 */ 2144 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2145 2146 /* 2147 * Write the idle command value after the idle command parameter 2148 * has been written to avoid a race condition. If the order is not 2149 * followed, the microcode may process the idle command before the 2150 * parameters have been written to LRAM. 2151 */ 2152 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2153 idle_cmd_parameter); 2154 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2155 2156 /* 2157 * Tickle the RISC to tell it to process the idle command. 2158 */ 2159 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2160 if (sc->chip_type == ADW_CHIP_ASC3550) { 2161 /* 2162 * Clear the tickle value. In the ASC-3550 the RISC flag 2163 * command 'clr_tickle_b' does not work unless the host 2164 * value is cleared. 2165 */ 2166 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2167 } 2168 2169 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2170 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2171 /* Poll once each microsecond for command completion. */ 2172 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2173 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2174 result); 2175 if (result != 0) { 2176 splx(s); 2177 return result; 2178 } 2179 AdwDelayMicroSecond(1); 2180 } 2181 } 2182 2183 splx(s); 2184 return ADW_ERROR; 2185 } 2186 2187 2188 /* 2189 * Inquiry Information Byte 7 Handling 2190 * 2191 * Handle SCSI Inquiry Command information for a device by setting 2192 * microcode operating variables that affect WDTR, SDTR, and Tag 2193 * Queuing. 2194 */ 2195 static void 2196 AdwInquiryHandling(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 2197 { 2198 #ifndef FAILSAFE 2199 bus_space_tag_t iot = sc->sc_iot; 2200 bus_space_handle_t ioh = sc->sc_ioh; 2201 u_int8_t tid; 2202 struct scsipi_inquiry_data *inq; 2203 u_int16_t tidmask; 2204 u_int16_t cfg_word; 2205 2206 2207 /* 2208 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2209 * to be available. 2210 * 2211 * If less than 8 bytes of INQUIRY information were requested or less 2212 * than 8 bytes were transferred, then return. cdb[4] is the request 2213 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2214 * microcode to the transfer residual count. 2215 */ 2216 2217 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2218 return; 2219 } 2220 2221 tid = scsiq->target_id; 2222 2223 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2224 2225 /* 2226 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2227 */ 2228 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2229 ((inq->version & SID_ANSII) < 2)) { 2230 return; 2231 } else { 2232 /* 2233 * INQUIRY Byte 7 Handling 2234 * 2235 * Use a device's INQUIRY byte 7 to determine whether it 2236 * supports WDTR, SDTR, and Tag Queuing. If the feature 2237 * is enabled in the EEPROM and the device supports the 2238 * feature, then enable it in the microcode. 2239 */ 2240 2241 tidmask = ADW_TID_TO_TIDMASK(tid); 2242 2243 /* 2244 * Wide Transfers 2245 * 2246 * If the EEPROM enabled WDTR for the device and the device 2247 * supports wide bus (16 bit) transfers, then turn on the 2248 * device's 'wdtr_able' bit and write the new value to the 2249 * microcode. 2250 */ 2251 #ifdef SCSI_ADW_WDTR_DISABLE 2252 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2253 #endif /* SCSI_ADW_WDTR_DISABLE */ 2254 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2255 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2256 cfg_word); 2257 if ((cfg_word & tidmask) == 0) { 2258 cfg_word |= tidmask; 2259 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2260 cfg_word); 2261 2262 /* 2263 * Clear the microcode "SDTR negotiation" and 2264 * "WDTR negotiation" done indicators for the 2265 * target to cause it to negotiate with the new 2266 * setting set above. 2267 * WDTR when accepted causes the target to enter 2268 * asynchronous mode, so SDTR must be negotiated 2269 */ 2270 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2271 cfg_word); 2272 cfg_word &= ~tidmask; 2273 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2274 cfg_word); 2275 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2276 cfg_word); 2277 cfg_word &= ~tidmask; 2278 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2279 cfg_word); 2280 } 2281 } 2282 2283 /* 2284 * Synchronous Transfers 2285 * 2286 * If the EEPROM enabled SDTR for the device and the device 2287 * supports synchronous transfers, then turn on the device's 2288 * 'sdtr_able' bit. Write the new value to the microcode. 2289 */ 2290 #ifdef SCSI_ADW_SDTR_DISABLE 2291 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2292 #endif /* SCSI_ADW_SDTR_DISABLE */ 2293 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2294 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2295 if ((cfg_word & tidmask) == 0) { 2296 cfg_word |= tidmask; 2297 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2298 cfg_word); 2299 2300 /* 2301 * Clear the microcode "SDTR negotiation" 2302 * done indicator for the target to cause it 2303 * to negotiate with the new setting set above. 2304 */ 2305 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2306 cfg_word); 2307 cfg_word &= ~tidmask; 2308 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2309 cfg_word); 2310 } 2311 } 2312 /* 2313 * If the Inquiry data included enough space for the SPI-3 2314 * Clocking field, then check if DT mode is supported. 2315 */ 2316 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2317 (scsiq->cdb[4] >= 57 || 2318 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2319 /* 2320 * PPR (Parallel Protocol Request) Capable 2321 * 2322 * If the device supports DT mode, then it must be 2323 * PPR capable. 2324 * The PPR message will be used in place of the SDTR 2325 * and WDTR messages to negotiate synchronous speed 2326 * and offset, transfer width, and protocol options. 2327 */ 2328 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2329 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2330 sc->ppr_able); 2331 sc->ppr_able |= tidmask; 2332 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2333 sc->ppr_able); 2334 } 2335 } 2336 2337 /* 2338 * If the EEPROM enabled Tag Queuing for the device and the 2339 * device supports Tag Queueing, then turn on the device's 2340 * 'tagqng_enable' bit in the microcode and set the microcode 2341 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2342 * value. 2343 * 2344 * Tag Queuing is disabled for the BIOS which runs in polled 2345 * mode and would see no benefit from Tag Queuing. Also by 2346 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2347 * bugs will at least work with the BIOS. 2348 */ 2349 #ifdef SCSI_ADW_TAGQ_DISABLE 2350 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2351 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2352 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2353 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2354 cfg_word); 2355 cfg_word |= tidmask; 2356 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2357 cfg_word); 2358 2359 ADW_WRITE_BYTE_LRAM(iot, ioh, 2360 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2361 sc->max_dvc_qng); 2362 } 2363 } 2364 #endif /* FAILSAFE */ 2365 } 2366 2367 2368 static void 2369 AdwSleepMilliSecond(u_int32_t n) 2370 { 2371 2372 DELAY(n * 1000); 2373 } 2374 2375 2376 static void 2377 AdwDelayMicroSecond(u_int32_t n) 2378 { 2379 2380 DELAY(n); 2381 } 2382 2383
Indexes created Thu Sep 25 16:09:42 GMT 2025