adwlib.c revision 1.42
1 /* $NetBSD: adwlib.c,v 1.42 2019/02/03 03:19:27 mrg Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-2000 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.42 2019/02/03 03:19:27 mrg Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/queue.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsiconf.h> 70 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/ic/adwlib.h> 74 #include <dev/ic/adwmcode.h> 75 #include <dev/ic/adw.h> 76 77 78 /* Static Functions */ 79 80 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t); 81 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, u_int8_t); 82 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 83 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 84 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 85 86 static u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 87 ADW_EEPROM *); 88 static void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 89 ADW_EEPROM *); 90 static u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int); 91 static void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t); 92 93 static void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 94 95 static void AdwSleepMilliSecond(u_int32_t); 96 static void AdwDelayMicroSecond(u_int32_t); 97 98 99 /* 100 * EEPROM Configuration. 101 * 102 * All drivers should use this structure to set the default EEPROM 103 * configuration. The BIOS now uses this structure when it is built. 104 * Additional structure information can be found in adwlib.h where 105 * the structure is defined. 106 */ 107 static const ADW_EEPROM adw_3550_Default_EEPROM = { 108 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 109 0x0000, /* 01 cfg_msw */ 110 0xFFFF, /* 02 disc_enable */ 111 0xFFFF, /* 03 wdtr_able */ 112 { 0xFFFF }, /* 04 sdtr_able */ 113 0xFFFF, /* 05 start_motor */ 114 0xFFFF, /* 06 tagqng_able */ 115 0xFFFF, /* 07 bios_scan */ 116 0, /* 08 scam_tolerant */ 117 7, /* 09 adapter_scsi_id */ 118 0, /* bios_boot_delay */ 119 3, /* 10 scsi_reset_delay */ 120 0, /* bios_id_lun */ 121 0, /* 11 termination */ 122 0, /* reserved1 */ 123 0xFFE7, /* 12 bios_ctrl */ 124 { 0xFFFF }, /* 13 ultra_able */ 125 { 0 }, /* 14 reserved2 */ 126 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 127 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 128 0, /* 16 dvc_cntl */ 129 { 0 }, /* 17 bug_fix */ 130 { 0,0,0 }, /* 18-20 serial_number[3] */ 131 0, /* 21 check_sum */ 132 { /* 22-29 oem_name[16] */ 133 0,0,0,0,0,0,0,0, 134 0,0,0,0,0,0,0,0 135 }, 136 0, /* 30 dvc_err_code */ 137 0, /* 31 adv_err_code */ 138 0, /* 32 adv_err_addr */ 139 0, /* 33 saved_dvc_err_code */ 140 0, /* 34 saved_adv_err_code */ 141 0, /* 35 saved_adv_err_addr */ 142 { /* 36-55 reserved1[16] */ 143 0,0,0,0,0,0,0,0,0,0, 144 0,0,0,0,0,0,0,0,0,0 145 }, 146 0, /* 56 cisptr_lsw */ 147 0, /* 57 cisprt_msw */ 148 0, /* 58 subsysvid */ 149 0, /* 59 subsysid */ 150 { 0,0,0,0 } /* 60-63 reserved2[4] */ 151 }; 152 153 static const ADW_EEPROM adw_38C0800_Default_EEPROM = { 154 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 155 0x0000, /* 01 cfg_msw */ 156 0xFFFF, /* 02 disc_enable */ 157 0xFFFF, /* 03 wdtr_able */ 158 { 0x4444 }, /* 04 sdtr_speed1 */ 159 0xFFFF, /* 05 start_motor */ 160 0xFFFF, /* 06 tagqng_able */ 161 0xFFFF, /* 07 bios_scan */ 162 0, /* 08 scam_tolerant */ 163 7, /* 09 adapter_scsi_id */ 164 0, /* bios_boot_delay */ 165 3, /* 10 scsi_reset_delay */ 166 0, /* bios_id_lun */ 167 0, /* 11 termination_se */ 168 0, /* termination_lvd */ 169 0xFFE7, /* 12 bios_ctrl */ 170 { 0x4444 }, /* 13 sdtr_speed2 */ 171 { 0x4444 }, /* 14 sdtr_speed3 */ 172 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 173 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 174 0, /* 16 dvc_cntl */ 175 { 0x4444 }, /* 17 sdtr_speed4 */ 176 { 0,0,0 }, /* 18-20 serial_number[3] */ 177 0, /* 21 check_sum */ 178 { /* 22-29 oem_name[16] */ 179 0,0,0,0,0,0,0,0, 180 0,0,0,0,0,0,0,0 181 }, 182 0, /* 30 dvc_err_code */ 183 0, /* 31 adv_err_code */ 184 0, /* 32 adv_err_addr */ 185 0, /* 33 saved_dvc_err_code */ 186 0, /* 34 saved_adv_err_code */ 187 0, /* 35 saved_adv_err_addr */ 188 { /* 36-55 reserved1[16] */ 189 0,0,0,0,0,0,0,0,0,0, 190 0,0,0,0,0,0,0,0,0,0 191 }, 192 0, /* 56 cisptr_lsw */ 193 0, /* 57 cisprt_msw */ 194 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 195 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 196 { 0,0,0,0 } /* 60-63 reserved2[4] */ 197 }; 198 199 static const ADW_EEPROM adw_38C1600_Default_EEPROM = { 200 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 201 0x0000, /* 01 cfg_msw */ 202 0xFFFF, /* 02 disc_enable */ 203 0xFFFF, /* 03 wdtr_able */ 204 { 0x5555 }, /* 04 sdtr_speed1 */ 205 0xFFFF, /* 05 start_motor */ 206 0xFFFF, /* 06 tagqng_able */ 207 0xFFFF, /* 07 bios_scan */ 208 0, /* 08 scam_tolerant */ 209 7, /* 09 adapter_scsi_id */ 210 0, /* bios_boot_delay */ 211 3, /* 10 scsi_reset_delay */ 212 0, /* bios_id_lun */ 213 0, /* 11 termination_se */ 214 0, /* termination_lvd */ 215 0xFFE7, /* 12 bios_ctrl */ 216 { 0x5555 }, /* 13 sdtr_speed2 */ 217 { 0x5555 }, /* 14 sdtr_speed3 */ 218 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 219 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 220 0, /* 16 dvc_cntl */ 221 { 0x5555 }, /* 17 sdtr_speed4 */ 222 { 0,0,0 }, /* 18-20 serial_number[3] */ 223 0, /* 21 check_sum */ 224 { /* 22-29 oem_name[16] */ 225 0,0,0,0,0,0,0,0, 226 0,0,0,0,0,0,0,0 227 }, 228 0, /* 30 dvc_err_code */ 229 0, /* 31 adv_err_code */ 230 0, /* 32 adv_err_addr */ 231 0, /* 33 saved_dvc_err_code */ 232 0, /* 34 saved_adv_err_code */ 233 0, /* 35 saved_adv_err_addr */ 234 { /* 36-55 reserved1[16] */ 235 0,0,0,0,0,0,0,0,0,0, 236 0,0,0,0,0,0,0,0,0,0 237 }, 238 0, /* 56 cisptr_lsw */ 239 0, /* 57 cisprt_msw */ 240 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 241 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 242 { 0,0,0,0 } /* 60-63 reserved2[4] */ 243 }; 244 245 246 /* 247 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 248 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 249 * all of this is done. 250 * 251 * For a non-fatal error return a warning code. If there are no warnings 252 * then 0 is returned. 253 * 254 * Note: Chip is stopped on entry. 255 */ 256 int 257 AdwInitFromEEPROM(ADW_SOFTC *sc) 258 { 259 bus_space_tag_t iot = sc->sc_iot; 260 bus_space_handle_t ioh = sc->sc_ioh; 261 ADW_EEPROM eep_config; 262 u_int16_t warn_code; 263 u_int16_t sdtr_speed = 0; 264 u_int8_t tid, termination; 265 int i, j; 266 267 268 warn_code = 0; 269 270 /* 271 * Read the board's EEPROM configuration. 272 * 273 * Set default values if a bad checksum is found. 274 * 275 * XXX - Don't handle big-endian access to EEPROM yet. 276 */ 277 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 278 warn_code |= ADW_WARN_EEPROM_CHKSUM; 279 280 /* 281 * Set EEPROM default values. 282 */ 283 switch(sc->chip_type) { 284 case ADW_CHIP_ASC3550: 285 eep_config = adw_3550_Default_EEPROM; 286 break; 287 case ADW_CHIP_ASC38C0800: 288 eep_config = adw_38C0800_Default_EEPROM; 289 break; 290 case ADW_CHIP_ASC38C1600: 291 eep_config = adw_38C1600_Default_EEPROM; 292 293 #if 0 294 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 295 #endif 296 if (sc->cfg.pci_slot_info != 0) { 297 u_int8_t lsw_msb; 298 299 lsw_msb = eep_config.cfg_lsw >> 8; 300 /* 301 * Set Function 1 EEPROM Word 0 MSB 302 * 303 * Clear the BIOS_ENABLE (bit 14) and 304 * INTAB (bit 11) EEPROM bits. 305 * 306 * Disable Bit 14 (BIOS_ENABLE) to fix 307 * SPARC Ultra 60 and old Mac system booting 308 * problem. The Expansion ROM must 309 * be disabled in Function 1 for these systems. 310 */ 311 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 312 ADW_EEPROM_INTAB) >> 8) & 0xFF); 313 /* 314 * Set the INTAB (bit 11) if the GPIO 0 input 315 * indicates the Function 1 interrupt line is 316 * wired to INTA. 317 * 318 * Set/Clear Bit 11 (INTAB) from 319 * the GPIO bit 0 input: 320 * 1 - Function 1 intr line wired to INT A. 321 * 0 - Function 1 intr line wired to INT B. 322 * 323 * Note: Adapter boards always have Function 0 324 * wired to INTA. 325 * Put all 5 GPIO bits in input mode and then 326 * read their input values. 327 */ 328 ADW_WRITE_BYTE_REGISTER(iot, ioh, 329 IOPB_GPIO_CNTL, 0); 330 if (ADW_READ_BYTE_REGISTER(iot, ioh, 331 IOPB_GPIO_DATA) & 0x01) { 332 /* 333 * Function 1 interrupt wired to INTA; 334 * Set EEPROM bit. 335 */ 336 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 337 & 0xFF; 338 } 339 eep_config.cfg_lsw &= 0x00FF; 340 eep_config.cfg_lsw |= lsw_msb << 8; 341 } 342 break; 343 } 344 345 /* 346 * Assume the 6 byte board serial number that was read 347 * from EEPROM is correct even if the EEPROM checksum 348 * failed. 349 */ 350 for (i=2, j=1; i>=0; i--, j++) { 351 eep_config.serial_number[i] = 352 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 353 } 354 355 AdwSetEEPROMConfig(iot, ioh, &eep_config); 356 } 357 /* 358 * Set sc and sc->cfg variables from the EEPROM configuration 359 * that was read. 360 * 361 * This is the mapping of EEPROM fields to Adw Library fields. 362 */ 363 sc->wdtr_able = eep_config.wdtr_able; 364 if (sc->chip_type == ADW_CHIP_ASC3550) { 365 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 366 sc->ultra_able = eep_config.sdtr2.ultra_able; 367 } else { 368 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 369 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 370 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 371 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 372 } 373 sc->ppr_able = 0; 374 sc->tagqng_able = eep_config.tagqng_able; 375 sc->cfg.disc_enable = eep_config.disc_enable; 376 sc->max_host_qng = eep_config.max_host_qng; 377 sc->max_dvc_qng = eep_config.max_dvc_qng; 378 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 379 sc->start_motor = eep_config.start_motor; 380 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 381 sc->bios_ctrl = eep_config.bios_ctrl; 382 sc->no_scam = eep_config.scam_tolerant; 383 sc->cfg.serial1 = eep_config.serial_number[0]; 384 sc->cfg.serial2 = eep_config.serial_number[1]; 385 sc->cfg.serial3 = eep_config.serial_number[2]; 386 387 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 388 sc->chip_type == ADW_CHIP_ASC38C1600) { 389 sc->sdtr_able = 0; 390 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 391 if (tid == 0) { 392 sdtr_speed = sc->sdtr_speed1; 393 } else if (tid == 4) { 394 sdtr_speed = sc->sdtr_speed2; 395 } else if (tid == 8) { 396 sdtr_speed = sc->sdtr_speed3; 397 } else if (tid == 12) { 398 sdtr_speed = sc->sdtr_speed4; 399 } 400 if (sdtr_speed & ADW_MAX_TID) { 401 sc->sdtr_able |= (1 << tid); 402 } 403 sdtr_speed >>= 4; 404 } 405 } 406 407 /* 408 * Set the host maximum queuing (max. 253, min. 16) and the per device 409 * maximum queuing (max. 63, min. 4). 410 */ 411 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 412 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 413 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 414 { 415 /* If the value is zero, assume it is uninitialized. */ 416 if (eep_config.max_host_qng == 0) { 417 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 418 } else { 419 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 420 } 421 } 422 423 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 424 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 425 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 426 /* If the value is zero, assume it is uninitialized. */ 427 if (eep_config.max_dvc_qng == 0) { 428 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 429 } else { 430 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 431 } 432 } 433 434 /* 435 * If 'max_dvc_qng' is greater than 'max_host_qng', then 436 * set 'max_dvc_qng' to 'max_host_qng'. 437 */ 438 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 439 eep_config.max_dvc_qng = eep_config.max_host_qng; 440 } 441 442 /* 443 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 444 * values based on possibly adjusted EEPROM values. 445 */ 446 sc->max_host_qng = eep_config.max_host_qng; 447 sc->max_dvc_qng = eep_config.max_dvc_qng; 448 449 450 /* 451 * If the EEPROM 'termination' field is set to automatic (0), then set 452 * the ADV_DVC_CFG 'termination' field to automatic also. 453 * 454 * If the termination is specified with a non-zero 'termination' 455 * value check that a legal value is set and set the ADV_DVC_CFG 456 * 'termination' field appropriately. 457 */ 458 459 switch(sc->chip_type) { 460 case ADW_CHIP_ASC3550: 461 sc->cfg.termination = 0; /* auto termination */ 462 switch(eep_config.termination_se) { 463 case 3: 464 /* Enable manual control with low on / high on. */ 465 sc->cfg.termination |= ADW_TERM_CTL_L; 466 /* FALLTHROUGH */ 467 case 2: 468 /* Enable manual control with low off / high on. */ 469 sc->cfg.termination |= ADW_TERM_CTL_H; 470 /* FALLTHROUGH */ 471 case 1: 472 /* Enable manual control with low off / high off. */ 473 sc->cfg.termination |= ADW_TERM_CTL_SEL; 474 /* FALLTHROUGH */ 475 case 0: 476 break; 477 default: 478 warn_code |= ADW_WARN_EEPROM_TERMINATION; 479 } 480 break; 481 482 case ADW_CHIP_ASC38C0800: 483 case ADW_CHIP_ASC38C1600: 484 switch(eep_config.termination_se) { 485 case 0: 486 /* auto termination for SE */ 487 termination = 0; 488 break; 489 case 1: 490 /* Enable manual control with low off / high off. */ 491 termination = 0; 492 break; 493 case 2: 494 /* Enable manual control with low off / high on. */ 495 termination = ADW_TERM_SE_HI; 496 break; 497 case 3: 498 /* Enable manual control with low on / high on. */ 499 termination = ADW_TERM_SE; 500 break; 501 default: 502 /* 503 * The EEPROM 'termination_se' field contains a 504 * bad value. Use automatic termination instead. 505 */ 506 termination = 0; 507 warn_code |= ADW_WARN_EEPROM_TERMINATION; 508 } 509 510 switch(eep_config.termination_lvd) { 511 case 0: 512 /* auto termination for LVD */ 513 sc->cfg.termination = termination; 514 break; 515 case 1: 516 /* Enable manual control with low off / high off. */ 517 sc->cfg.termination = termination; 518 break; 519 case 2: 520 /* Enable manual control with low off / high on. */ 521 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 522 break; 523 case 3: 524 /* Enable manual control with low on / high on. */ 525 sc->cfg.termination = termination | ADW_TERM_LVD; 526 break; 527 default: 528 /* 529 * The EEPROM 'termination_lvd' field contains a 530 * bad value. Use automatic termination instead. 531 */ 532 sc->cfg.termination = termination; 533 warn_code |= ADW_WARN_EEPROM_TERMINATION; 534 } 535 break; 536 } 537 538 return warn_code; 539 } 540 541 542 /* 543 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 544 * 545 * On failure return the error code. 546 */ 547 int 548 AdwInitDriver(ADW_SOFTC *sc) 549 { 550 bus_space_tag_t iot = sc->sc_iot; 551 bus_space_handle_t ioh = sc->sc_ioh; 552 u_int16_t error_code; 553 int word; 554 int i; 555 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 556 0x40-0x8F. */ 557 u_int16_t wdtr_able = 0, sdtr_able, /* ppr_able, */ tagqng_able; 558 u_int8_t max_cmd[ADW_MAX_TID + 1]; 559 u_int8_t tid; 560 561 562 error_code = 0; 563 564 /* 565 * Save the RISC memory BIOS region before writing the microcode. 566 * The BIOS may already be loaded and using its RISC LRAM region 567 * so its region must be saved and restored. 568 * 569 * Note: This code makes the assumption, which is currently true, 570 * that a chip reset does not clear RISC LRAM. 571 */ 572 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 573 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 574 } 575 576 /* 577 * Save current per TID negotiated values. 578 */ 579 switch (sc->chip_type) { 580 case ADW_CHIP_ASC3550: 581 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 582 583 u_int16_t bios_version, major, minor; 584 585 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 586 ADW_MC_BIOSMEM) / 2]; 587 major = (bios_version >> 12) & 0xF; 588 minor = (bios_version >> 8) & 0xF; 589 if (major < 3 || (major == 3 && minor == 1)) { 590 /* 591 * BIOS 3.1 and earlier location of 592 * 'wdtr_able' variable. 593 */ 594 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 595 } else { 596 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 597 wdtr_able); 598 } 599 } 600 break; 601 602 case ADW_CHIP_ASC38C1600: 603 /* ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); */ 604 /* FALLTHROUGH */ 605 case ADW_CHIP_ASC38C0800: 606 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 607 break; 608 } 609 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 610 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 611 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 612 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 613 max_cmd[tid]); 614 } 615 616 /* 617 * Perform a RAM Built-In Self Test 618 */ 619 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 620 return error_code; 621 } 622 623 /* 624 * Load the Microcode 625 */ 626 ; 627 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 628 return error_code; 629 } 630 631 /* 632 * Read microcode version and date. 633 */ 634 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 635 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 636 637 /* 638 * If the PCI Configuration Command Register "Parity Error Response 639 * Control" Bit was clear (0), then set the microcode variable 640 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 641 * to ignore DMA parity errors. 642 */ 643 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 644 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 645 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 646 word | CONTROL_FLAG_IGNORE_PERR); 647 } 648 649 switch (sc->chip_type) { 650 case ADW_CHIP_ASC3550: 651 /* 652 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 653 * FIFO threshold of 128 bytes. 654 * This register is only accessible to the host. 655 */ 656 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 657 START_CTL_EMFU | READ_CMD_MRM); 658 break; 659 660 case ADW_CHIP_ASC38C0800: 661 /* 662 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 663 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 664 * cable detection and then we are able to read C_DET[3:0]. 665 * 666 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 667 * Microcode Default Value' section below. 668 */ 669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 670 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 671 | ADW_DIS_TERM_DRV); 672 673 /* 674 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 675 * START_CTL_TH [3:2] bits for the default FIFO threshold. 676 * 677 * Note: ASC-38C0800 FIFO threshold has been changed to 678 * 256 bytes. 679 * 680 * For DMA Errata #4 set the BC_THRESH_ENB bit. 681 */ 682 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 683 BC_THRESH_ENB | FIFO_THRESH_80B 684 | START_CTL_TH | READ_CMD_MRM); 685 break; 686 687 case ADW_CHIP_ASC38C1600: 688 /* 689 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 690 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 691 * cable detection and then we are able to read C_DET[3:0]. 692 * 693 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 694 * Microcode Default Value' section below. 695 */ 696 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 697 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 698 | ADW_DIS_TERM_DRV); 699 700 /* 701 * If the BIOS control flag AIPP (Asynchronous Information 702 * Phase Protection) disable bit is not set, then set the 703 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 704 * enable AIPP checking and encoding. 705 */ 706 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 707 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 708 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 709 word | CONTROL_FLAG_ENABLE_AIPP); 710 } 711 712 /* 713 * For ASC-38C1600 use DMA_CFG0 default values: 714 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 715 */ 716 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 717 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 718 break; 719 } 720 721 /* 722 * Microcode operating variables for WDTR, SDTR, and command tag 723 * queuing will be set in AdvInquiryHandling() based on what a 724 * device reports it is capable of in Inquiry byte 7. 725 * 726 * If SCSI Bus Resets have been disabled, then directly set 727 * SDTR and WDTR from the EEPROM configuration. This will allow 728 * the BIOS and warm boot to work without a SCSI bus hang on 729 * the Inquiry caused by host and target mismatched DTR values. 730 * Without the SCSI Bus Reset, before an Inquiry a device can't 731 * be assumed to be in Asynchronous, Narrow mode. 732 */ 733 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 734 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 735 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 736 } 737 738 /* 739 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 740 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 741 * bitmask. These values determine the maximum SDTR speed negotiated 742 * with a device. 743 * 744 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 745 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 746 * without determining here whether the device supports SDTR. 747 */ 748 switch (sc->chip_type) { 749 case ADW_CHIP_ASC3550: 750 word = 0; 751 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 752 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 753 /* Set Ultra speed for TID 'tid'. */ 754 word |= (0x3 << (4 * (tid % 4))); 755 } else { 756 /* Set Fast speed for TID 'tid'. */ 757 word |= (0x2 << (4 * (tid % 4))); 758 } 759 /* Check if done with sdtr_speed1. */ 760 if (tid == 3) { 761 ADW_WRITE_WORD_LRAM(iot, ioh, 762 ADW_MC_SDTR_SPEED1, word); 763 word = 0; 764 /* Check if done with sdtr_speed2. */ 765 } else if (tid == 7) { 766 ADW_WRITE_WORD_LRAM(iot, ioh, 767 ADW_MC_SDTR_SPEED2, word); 768 word = 0; 769 /* Check if done with sdtr_speed3. */ 770 } else if (tid == 11) { 771 ADW_WRITE_WORD_LRAM(iot, ioh, 772 ADW_MC_SDTR_SPEED3, word); 773 word = 0; 774 /* Check if done with sdtr_speed4. */ 775 } else if (tid == 15) { 776 ADW_WRITE_WORD_LRAM(iot, ioh, 777 ADW_MC_SDTR_SPEED4, word); 778 /* End of loop. */ 779 } 780 } 781 782 /* 783 * Set microcode operating variable for the 784 * disconnect per TID bitmask. 785 */ 786 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 787 sc->cfg.disc_enable); 788 break; 789 790 case ADW_CHIP_ASC38C0800: 791 /* FALLTHROUGH */ 792 case ADW_CHIP_ASC38C1600: 793 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 794 sc->cfg.disc_enable); 795 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 796 sc->sdtr_speed1); 797 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 798 sc->sdtr_speed2); 799 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 800 sc->sdtr_speed3); 801 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 802 sc->sdtr_speed4); 803 break; 804 } 805 806 807 /* 808 * Set SCSI_CFG0 Microcode Default Value. 809 * 810 * The microcode will set the SCSI_CFG0 register using this value 811 * after it is started below. 812 */ 813 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 814 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 815 ADW_OUR_ID_EN | sc->chip_scsi_id); 816 817 818 switch(sc->chip_type) { 819 case ADW_CHIP_ASC3550: 820 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 821 break; 822 823 case ADW_CHIP_ASC38C0800: 824 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 825 break; 826 827 case ADW_CHIP_ASC38C1600: 828 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 829 break; 830 } 831 if(error_code) { 832 return error_code; 833 } 834 835 /* 836 * Set SEL_MASK Microcode Default Value 837 * 838 * The microcode will set the SEL_MASK register using this value 839 * after it is started below. 840 */ 841 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 842 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 843 844 /* 845 * Create and Initialize Host->RISC Carrier lists 846 */ 847 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 848 sc->sc_control->carriers); 849 850 /* 851 * Set-up the Host->RISC Initiator Command Queue (ICQ). 852 */ 853 854 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 855 return ADW_IERR_NO_CARRIER; 856 } 857 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 858 ASC_GET_CARRP(sc->icq_sp->next_ba)); 859 860 /* 861 * The first command issued will be placed in the stopper carrier. 862 */ 863 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER); 864 865 /* 866 * Set RISC ICQ physical address start value. 867 */ 868 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba)); 869 870 /* 871 * Initialize the COMMA register to the same value otherwise 872 * the RISC will prematurely detect a command is available. 873 */ 874 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 875 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 876 le32toh(sc->icq_sp->carr_ba)); 877 } 878 879 /* 880 * Set-up the RISC->Host Initiator Response Queue (IRQ). 881 */ 882 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 883 return ADW_IERR_NO_CARRIER; 884 } 885 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 886 ASC_GET_CARRP(sc->irq_sp->next_ba)); 887 888 /* 889 * The first command completed by the RISC will be placed in 890 * the stopper. 891 * 892 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 893 * completed the RISC will set the ASC_RQ_DONE bit. 894 */ 895 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER); 896 897 /* 898 * Set RISC IRQ physical address start value. 899 */ 900 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba)); 901 sc->carr_pending_cnt = 0; 902 903 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 904 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 905 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 906 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 907 908 /* finally, finally, gentlemen, start your engine */ 909 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 910 911 /* 912 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 913 * Resets should be performed. The RISC has to be running 914 * to issue a SCSI Bus Reset. 915 */ 916 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 917 { 918 /* 919 * If the BIOS Signature is present in memory, restore the 920 * BIOS Handshake Configuration Table and do not perform 921 * a SCSI Bus Reset. 922 */ 923 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 924 0x55AA) { 925 /* 926 * Restore per TID negotiated values. 927 */ 928 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 929 wdtr_able); 930 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 931 sdtr_able); 932 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 933 tagqng_able); 934 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 935 ADW_WRITE_BYTE_LRAM(iot, ioh, 936 ADW_MC_NUMBER_OF_MAX_CMD + tid, 937 max_cmd[tid]); 938 } 939 } else { 940 if (AdwResetCCB(sc) != ADW_TRUE) { 941 error_code = ADW_WARN_BUSRESET_ERROR; 942 } 943 } 944 } 945 946 return error_code; 947 } 948 949 950 int 951 AdwRamSelfTest(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t chip_type) 952 { 953 int i; 954 u_int8_t byte; 955 956 957 if ((chip_type == ADW_CHIP_ASC38C0800) || 958 (chip_type == ADW_CHIP_ASC38C1600)) { 959 /* 960 * RAM BIST (RAM Built-In Self Test) 961 * 962 * Address : I/O base + offset 0x38h register (byte). 963 * Function: Bit 7-6(RW) : RAM mode 964 * Normal Mode : 0x00 965 * Pre-test Mode : 0x40 966 * RAM Test Mode : 0x80 967 * Bit 5 : unused 968 * Bit 4(RO) : Done bit 969 * Bit 3-0(RO) : Status 970 * Host Error : 0x08 971 * Int_RAM Error : 0x04 972 * RISC Error : 0x02 973 * SCSI Error : 0x01 974 * No Error : 0x00 975 * 976 * Note: RAM BIST code should be put right here, before loading 977 * the microcode and after saving the RISC memory BIOS region. 978 */ 979 980 /* 981 * LRAM Pre-test 982 * 983 * Write PRE_TEST_MODE (0x40) to register and wait for 984 * 10 milliseconds. 985 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 986 * return an error. Reset to NORMAL_MODE (0x00) and do again. 987 * If cannot reset to NORMAL_MODE, return an error too. 988 */ 989 for (i = 0; i < 2; i++) { 990 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 991 PRE_TEST_MODE); 992 /* Wait for 10ms before reading back. */ 993 AdwSleepMilliSecond(10); 994 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 995 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 996 PRE_TEST_VALUE) { 997 return ADW_IERR_BIST_PRE_TEST; 998 } 999 1000 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 1001 NORMAL_MODE); 1002 /* Wait for 10ms before reading back. */ 1003 AdwSleepMilliSecond(10); 1004 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 1005 != NORMAL_VALUE) { 1006 return ADW_IERR_BIST_PRE_TEST; 1007 } 1008 } 1009 1010 /* 1011 * LRAM Test - It takes about 1.5 ms to run through the test. 1012 * 1013 * Write RAM_TEST_MODE (0x80) to register and wait for 1014 * 10 milliseconds. 1015 * If Done bit not set or Status not 0, save register byte, 1016 * set the err_code, and return an error. 1017 */ 1018 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1019 /* Wait for 10ms before checking status. */ 1020 AdwSleepMilliSecond(10); 1021 1022 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1023 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1024 /* Get here if Done bit not set or Status not 0. */ 1025 return ADW_IERR_BIST_RAM_TEST; 1026 } 1027 1028 /* We need to reset back to normal mode after LRAM test passes*/ 1029 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1030 } 1031 1032 return 0; 1033 } 1034 1035 1036 int 1037 AdwLoadMCode(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t *bios_mem, u_int8_t chip_type) 1038 { 1039 const u_int8_t *mcode_data; 1040 u_int32_t mcode_chksum; 1041 u_int16_t mcode_size; 1042 u_int32_t sum; 1043 u_int16_t code_sum; 1044 int begin_addr; 1045 int end_addr; 1046 int word; 1047 int adw_memsize; 1048 int adw_mcode_expanded_size; 1049 int i, j; 1050 1051 1052 switch(chip_type) { 1053 case ADW_CHIP_ASC3550: 1054 mcode_data = (const u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1055 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1056 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1057 adw_memsize = ADW_3550_MEMSIZE; 1058 break; 1059 1060 case ADW_CHIP_ASC38C0800: 1061 mcode_data = (const u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1062 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1063 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1064 adw_memsize = ADW_38C0800_MEMSIZE; 1065 break; 1066 1067 case ADW_CHIP_ASC38C1600: 1068 mcode_data = (const u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1069 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1070 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1071 adw_memsize = ADW_38C1600_MEMSIZE; 1072 break; 1073 1074 default: 1075 return (EINVAL); 1076 } 1077 1078 /* 1079 * Write the microcode image to RISC memory starting at address 0. 1080 */ 1081 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1082 1083 /* Assume the following compressed format of the microcode buffer: 1084 * 1085 * 254 word (508 byte) table indexed by byte code followed 1086 * by the following byte codes: 1087 * 1088 * 1-Byte Code: 1089 * 00: Emit word 0 in table. 1090 * 01: Emit word 1 in table. 1091 * . 1092 * FD: Emit word 253 in table. 1093 * 1094 * Multi-Byte Code: 1095 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1096 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1097 */ 1098 word = 0; 1099 for (i = 253 * 2; i < mcode_size; i++) { 1100 if (mcode_data[i] == 0xff) { 1101 for (j = 0; j < mcode_data[i + 1]; j++) { 1102 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1103 (((u_int16_t)mcode_data[i + 3] << 8) | 1104 mcode_data[i + 2])); 1105 word++; 1106 } 1107 i += 3; 1108 } else if (mcode_data[i] == 0xfe) { 1109 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1110 (((u_int16_t)mcode_data[i + 2] << 8) | 1111 mcode_data[i + 1])); 1112 i += 2; 1113 word++; 1114 } else { 1115 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1116 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1117 mcode_data[mcode_data[i] * 2])); 1118 word++; 1119 } 1120 } 1121 1122 /* 1123 * Set 'word' for later use to clear the rest of memory and save 1124 * the expanded mcode size. 1125 */ 1126 word *= 2; 1127 adw_mcode_expanded_size = word; 1128 1129 /* 1130 * Clear the rest of the Internal RAM. 1131 */ 1132 for (; word < adw_memsize; word += 2) { 1133 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1134 } 1135 1136 /* 1137 * Verify the microcode checksum. 1138 */ 1139 sum = 0; 1140 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1141 1142 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1143 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1144 } 1145 1146 if (sum != mcode_chksum) { 1147 return ADW_IERR_MCODE_CHKSUM; 1148 } 1149 1150 /* 1151 * Restore the RISC memory BIOS region. 1152 */ 1153 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1154 if(chip_type == ADW_CHIP_ASC3550) { 1155 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1156 bios_mem[i]); 1157 } else { 1158 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1159 bios_mem[i]); 1160 } 1161 } 1162 1163 /* 1164 * Calculate and write the microcode code checksum to the microcode 1165 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1166 */ 1167 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1168 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1169 code_sum = 0; 1170 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1171 for (word = begin_addr; word < end_addr; word += 2) { 1172 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1173 } 1174 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1175 1176 /* 1177 * Set the chip type. 1178 */ 1179 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1180 1181 return 0; 1182 } 1183 1184 1185 int 1186 AdwASC3550Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1187 { 1188 u_int16_t scsi_cfg1; 1189 1190 1191 /* 1192 * Determine SCSI_CFG1 Microcode Default Value. 1193 * 1194 * The microcode will set the SCSI_CFG1 register using this value 1195 * after it is started below. 1196 */ 1197 1198 /* Read current SCSI_CFG1 Register value. */ 1199 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1200 1201 /* 1202 * If all three connectors are in use in ASC3550, return an error. 1203 */ 1204 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1205 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1206 return ADW_IERR_ILLEGAL_CONNECTION; 1207 } 1208 1209 /* 1210 * If the cable is reversed all of the SCSI_CTRL register signals 1211 * will be set. Check for and return an error if this condition is 1212 * found. 1213 */ 1214 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1215 return ADW_IERR_REVERSED_CABLE; 1216 } 1217 1218 /* 1219 * If this is a differential board and a single-ended device 1220 * is attached to one of the connectors, return an error. 1221 */ 1222 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1223 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1224 return ADW_IERR_SINGLE_END_DEVICE; 1225 } 1226 1227 /* 1228 * If automatic termination control is enabled, then set the 1229 * termination value based on a table listed in a_condor.h. 1230 * 1231 * If manual termination was specified with an EEPROM setting 1232 * then 'termination' was set-up in AdwInitFromEEPROM() and 1233 * is ready to be 'ored' into SCSI_CFG1. 1234 */ 1235 if (cfg->termination == 0) { 1236 /* 1237 * The software always controls termination by setting 1238 * TERM_CTL_SEL. 1239 * If TERM_CTL_SEL were set to 0, the hardware would set 1240 * termination. 1241 */ 1242 cfg->termination |= ADW_TERM_CTL_SEL; 1243 1244 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1245 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1246 case 0x3: case 0x7: case 0xB: 1247 case 0xD: case 0xE: case 0xF: 1248 cfg->termination |= 1249 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1250 break; 1251 1252 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1253 case 0x1: case 0x5: case 0x9: 1254 case 0xA: case 0xC: 1255 cfg->termination |= ADW_TERM_CTL_H; 1256 break; 1257 1258 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1259 case 0x2: case 0x6: 1260 break; 1261 } 1262 } 1263 1264 /* 1265 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1266 */ 1267 scsi_cfg1 &= ~ADW_TERM_CTL; 1268 1269 /* 1270 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1271 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1272 * referenced, because the hardware internally inverts 1273 * the Termination High and Low bits if TERM_POL is set. 1274 */ 1275 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1276 1277 /* 1278 * Set SCSI_CFG1 Microcode Default Value 1279 * 1280 * Set filter value and possibly modified termination control 1281 * bits in the Microcode SCSI_CFG1 Register Value. 1282 * 1283 * The microcode will set the SCSI_CFG1 register using this value 1284 * after it is started below. 1285 */ 1286 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1287 ADW_FLTR_DISABLE | scsi_cfg1); 1288 1289 /* 1290 * Set MEM_CFG Microcode Default Value 1291 * 1292 * The microcode will set the MEM_CFG register using this value 1293 * after it is started below. 1294 * 1295 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1296 * are defined. 1297 * 1298 * ASC-3550 has 8KB internal memory. 1299 */ 1300 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1301 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1302 1303 return 0; 1304 } 1305 1306 1307 int 1308 AdwASC38C0800Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1309 { 1310 u_int16_t scsi_cfg1; 1311 1312 1313 /* 1314 * Determine SCSI_CFG1 Microcode Default Value. 1315 * 1316 * The microcode will set the SCSI_CFG1 register using this value 1317 * after it is started below. 1318 */ 1319 1320 /* Read current SCSI_CFG1 Register value. */ 1321 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1322 1323 /* 1324 * If the cable is reversed all of the SCSI_CTRL register signals 1325 * will be set. Check for and return an error if this condition is 1326 * found. 1327 */ 1328 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1329 return ADW_IERR_REVERSED_CABLE; 1330 } 1331 1332 /* 1333 * All kind of combinations of devices attached to one of four 1334 * connectors are acceptable except HVD device attached. 1335 * For example, LVD device can be attached to SE connector while 1336 * SE device attached to LVD connector. 1337 * If LVD device attached to SE connector, it only runs up to 1338 * Ultra speed. 1339 * 1340 * If an HVD device is attached to one of LVD connectors, return 1341 * an error. 1342 * However, there is no way to detect HVD device attached to 1343 * SE connectors. 1344 */ 1345 if (scsi_cfg1 & ADW_HVD) { 1346 return ADW_IERR_HVD_DEVICE; 1347 } 1348 1349 /* 1350 * If either SE or LVD automatic termination control is enabled, then 1351 * set the termination value based on a table listed in a_condor.h. 1352 * 1353 * If manual termination was specified with an EEPROM setting then 1354 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1355 * to be 'ored' into SCSI_CFG1. 1356 */ 1357 if ((cfg->termination & ADW_TERM_SE) == 0) { 1358 /* SE automatic termination control is enabled. */ 1359 switch(scsi_cfg1 & ADW_C_DET_SE) { 1360 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1361 case 0x1: case 0x2: case 0x3: 1362 cfg->termination |= ADW_TERM_SE; 1363 break; 1364 1365 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1366 case 0x0: 1367 cfg->termination |= ADW_TERM_SE_HI; 1368 break; 1369 } 1370 } 1371 1372 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1373 /* LVD automatic termination control is enabled. */ 1374 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1375 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1376 case 0x4: case 0x8: case 0xC: 1377 cfg->termination |= ADW_TERM_LVD; 1378 break; 1379 1380 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1381 case 0x0: 1382 break; 1383 } 1384 } 1385 1386 /* 1387 * Clear any set TERM_SE and TERM_LVD bits. 1388 */ 1389 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1390 1391 /* 1392 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1393 */ 1394 scsi_cfg1 |= (~cfg->termination & 0xF0); 1395 1396 /* 1397 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1398 * HVD/LVD/SE bits and set possibly modified termination control bits 1399 * in the Microcode SCSI_CFG1 Register Value. 1400 */ 1401 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1402 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1403 1404 /* 1405 * Set SCSI_CFG1 Microcode Default Value 1406 * 1407 * Set possibly modified termination control and reset DIS_TERM_DRV 1408 * bits in the Microcode SCSI_CFG1 Register Value. 1409 * 1410 * The microcode will set the SCSI_CFG1 register using this value 1411 * after it is started below. 1412 */ 1413 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1414 1415 /* 1416 * Set MEM_CFG Microcode Default Value 1417 * 1418 * The microcode will set the MEM_CFG register using this value 1419 * after it is started below. 1420 * 1421 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1422 * are defined. 1423 * 1424 * ASC-38C0800 has 16KB internal memory. 1425 */ 1426 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1427 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1428 1429 return 0; 1430 } 1431 1432 1433 int 1434 AdwASC38C1600Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1435 { 1436 u_int16_t scsi_cfg1; 1437 1438 1439 /* 1440 * Determine SCSI_CFG1 Microcode Default Value. 1441 * 1442 * The microcode will set the SCSI_CFG1 register using this value 1443 * after it is started below. 1444 * Each ASC-38C1600 function has only two cable detect bits. 1445 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1446 */ 1447 1448 /* Read current SCSI_CFG1 Register value. */ 1449 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1450 1451 /* 1452 * If the cable is reversed all of the SCSI_CTRL register signals 1453 * will be set. Check for and return an error if this condition is 1454 * found. 1455 */ 1456 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1457 return ADW_IERR_REVERSED_CABLE; 1458 } 1459 1460 /* 1461 * Each ASC-38C1600 function has two connectors. Only an HVD device 1462 * cannot be connected to either connector. An LVD device or SE device 1463 * may be connected to either connector. If an SE device is connected, 1464 * then at most Ultra speed (20 MHz) can be used on both connectors. 1465 * 1466 * If an HVD device is attached, return an error. 1467 */ 1468 if (scsi_cfg1 & ADW_HVD) { 1469 return ADW_IERR_HVD_DEVICE; 1470 } 1471 1472 /* 1473 * Each function in the ASC-38C1600 uses only the SE cable detect and 1474 * termination because there are two connectors for each function. 1475 * Each function may use either LVD or SE mode. 1476 * Corresponding the SE automatic termination control EEPROM bits are 1477 * used for each function. 1478 * Each function has its own EEPROM. If SE automatic control is enabled 1479 * for the function, then set the termination value based on a table 1480 * listed in adwlib.h. 1481 * 1482 * If manual termination is specified in the EEPROM for the function, 1483 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1484 * ready to be 'ored' into SCSI_CFG1. 1485 */ 1486 if ((cfg->termination & ADW_TERM_SE) == 0) { 1487 /* SE automatic termination control is enabled. */ 1488 switch(scsi_cfg1 & ADW_C_DET_SE) { 1489 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1490 case 0x1: case 0x2: case 0x3: 1491 cfg->termination |= ADW_TERM_SE; 1492 break; 1493 1494 case 0x0: 1495 #if 0 1496 /* !!!!TODO!!!! */ 1497 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1498 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1499 } 1500 else 1501 #endif 1502 { 1503 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1504 cfg->termination |= ADW_TERM_SE_HI; 1505 } 1506 break; 1507 } 1508 } 1509 1510 /* 1511 * Clear any set TERM_SE bits. 1512 */ 1513 scsi_cfg1 &= ~ADW_TERM_SE; 1514 1515 /* 1516 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1517 */ 1518 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1519 1520 /* 1521 * Clear Big Endian and Terminator Polarity bits and set possibly 1522 * modified termination control bits in the Microcode SCSI_CFG1 1523 * Register Value. 1524 */ 1525 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1526 1527 /* 1528 * Set SCSI_CFG1 Microcode Default Value 1529 * 1530 * Set possibly modified termination control bits in the Microcode 1531 * SCSI_CFG1 Register Value. 1532 * 1533 * The microcode will set the SCSI_CFG1 register using this value 1534 * after it is started below. 1535 */ 1536 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1537 1538 /* 1539 * Set MEM_CFG Microcode Default Value 1540 * 1541 * The microcode will set the MEM_CFG register using this value 1542 * after it is started below. 1543 * 1544 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1545 * are defined. 1546 * 1547 * ASC-38C1600 has 32KB internal memory. 1548 */ 1549 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1550 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1551 1552 return 0; 1553 } 1554 1555 1556 /* 1557 * Read EEPROM configuration into the specified buffer. 1558 * 1559 * Return a checksum based on the EEPROM configuration read. 1560 */ 1561 static u_int16_t 1562 AdwGetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1563 { 1564 u_int16_t wval, chksum; 1565 u_int16_t *wbuf; 1566 int eep_addr; 1567 1568 1569 wbuf = (u_int16_t *) cfg_buf; 1570 chksum = 0; 1571 1572 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1573 eep_addr < ASC_EEP_DVC_CFG_END; 1574 eep_addr++, wbuf++) { 1575 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1576 chksum += wval; 1577 *wbuf = wval; 1578 } 1579 1580 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1581 wbuf++; 1582 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1583 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1584 eep_addr++, wbuf++) { 1585 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1586 } 1587 1588 return chksum; 1589 } 1590 1591 1592 /* 1593 * Read the EEPROM from specified location 1594 */ 1595 static u_int16_t 1596 AdwReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, int eep_word_addr) 1597 { 1598 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1599 ASC_EEP_CMD_READ | eep_word_addr); 1600 AdwWaitEEPCmd(iot, ioh); 1601 1602 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1603 } 1604 1605 1606 /* 1607 * Wait for EEPROM command to complete 1608 */ 1609 static void 1610 AdwWaitEEPCmd(bus_space_tag_t iot, bus_space_handle_t ioh) 1611 { 1612 int eep_delay_ms; 1613 1614 1615 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1616 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1617 ASC_EEP_CMD_DONE) { 1618 break; 1619 } 1620 AdwSleepMilliSecond(1); 1621 } 1622 1623 (void)ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1624 } 1625 1626 1627 /* 1628 * Write the EEPROM from 'cfg_buf'. 1629 */ 1630 static void 1631 AdwSetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1632 { 1633 u_int16_t *wbuf; 1634 u_int16_t addr, chksum; 1635 1636 1637 wbuf = (u_int16_t *) cfg_buf; 1638 chksum = 0; 1639 1640 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1641 AdwWaitEEPCmd(iot, ioh); 1642 1643 /* 1644 * Write EEPROM from word 0 to word 20 1645 */ 1646 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1647 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1648 chksum += *wbuf; 1649 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1650 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1651 ASC_EEP_CMD_WRITE | addr); 1652 AdwWaitEEPCmd(iot, ioh); 1653 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1654 } 1655 1656 /* 1657 * Write EEPROM checksum at word 21 1658 */ 1659 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1660 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1661 ASC_EEP_CMD_WRITE | addr); 1662 AdwWaitEEPCmd(iot, ioh); 1663 wbuf++; /* skip over check_sum */ 1664 1665 /* 1666 * Write EEPROM OEM name at words 22 to 29 1667 */ 1668 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1669 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1670 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1671 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1672 ASC_EEP_CMD_WRITE | addr); 1673 AdwWaitEEPCmd(iot, ioh); 1674 } 1675 1676 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1677 ASC_EEP_CMD_WRITE_DISABLE); 1678 AdwWaitEEPCmd(iot, ioh); 1679 1680 return; 1681 } 1682 1683 1684 /* 1685 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1686 * 1687 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1688 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1689 * RISC to notify it a new command is ready to be executed. 1690 * 1691 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1692 * set to SCSI_MAX_RETRY. 1693 * 1694 * Return: 1695 * ADW_SUCCESS(1) - The request was successfully queued. 1696 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1697 * request completes. 1698 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1699 * host IC error. 1700 */ 1701 int 1702 AdwExeScsiQueue(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 1703 { 1704 bus_space_tag_t iot = sc->sc_iot; 1705 bus_space_handle_t ioh = sc->sc_ioh; 1706 ADW_CCB *ccb; 1707 u_int32_t req_paddr; 1708 ADW_CARRIER *new_carrp; 1709 1710 /* 1711 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1712 */ 1713 if (scsiq->target_id > ADW_MAX_TID) { 1714 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1715 scsiq->done_status = QD_WITH_ERROR; 1716 return ADW_ERROR; 1717 } 1718 1719 /* 1720 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1721 */ 1722 1723 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1724 1725 /* 1726 * Allocate a carrier and initialize fields. 1727 */ 1728 if ((new_carrp = sc->carr_freelist) == NULL) { 1729 return ADW_BUSY; 1730 } 1731 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1732 ASC_GET_CARRP(new_carrp->next_ba)); 1733 sc->carr_pending_cnt++; 1734 1735 /* 1736 * Set the carrier to be a stopper by setting 'next_ba' 1737 * to the stopper value. The current stopper will be changed 1738 * below to point to the new stopper. 1739 */ 1740 new_carrp->next_ba = htole32(ASC_CQ_STOPPER); 1741 1742 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1743 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1744 1745 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1746 scsiq->scsiq_rptr = htole32(req_paddr); 1747 1748 /* 1749 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1750 * order during initialization. 1751 */ 1752 scsiq->carr_ba = sc->icq_sp->carr_ba; 1753 scsiq->carr_va = sc->icq_sp->carr_ba; 1754 1755 /* 1756 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1757 * the microcode. The newly allocated stopper will become the new 1758 * stopper. 1759 */ 1760 sc->icq_sp->areq_ba = htole32(req_paddr); 1761 1762 /* 1763 * Set the 'next_ba' pointer for the old stopper to be the 1764 * physical address of the new stopper. The RISC can only 1765 * follow physical addresses. 1766 */ 1767 sc->icq_sp->next_ba = new_carrp->carr_ba; 1768 1769 #if ADW_DEBUG 1770 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1771 sc->icq_sp->carr_id, 1772 sc->icq_sp->carr_ba, 1773 sc->icq_sp->areq_ba, 1774 sc->icq_sp->next_ba); 1775 #endif 1776 /* 1777 * Set the host adapter stopper pointer to point to the new carrier. 1778 */ 1779 sc->icq_sp = new_carrp; 1780 1781 if (sc->chip_type == ADW_CHIP_ASC3550 || 1782 sc->chip_type == ADW_CHIP_ASC38C0800) { 1783 /* 1784 * Tickle the RISC to tell it to read its Command Queue Head 1785 * pointer. 1786 */ 1787 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1788 if (sc->chip_type == ADW_CHIP_ASC3550) { 1789 /* 1790 * Clear the tickle value. In the ASC-3550 the RISC flag 1791 * command 'clr_tickle_a' does not work unless the host 1792 * value is cleared. 1793 */ 1794 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1795 ADW_TICKLE_NOP); 1796 } 1797 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1798 /* 1799 * Notify the RISC a carrier is ready by writing the physical 1800 * address of the new carrier stopper to the COMMA register. 1801 */ 1802 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1803 le32toh(new_carrp->carr_ba)); 1804 } 1805 1806 /* 1807 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1808 */ 1809 1810 return ADW_SUCCESS; 1811 } 1812 1813 1814 void 1815 AdwResetChip(bus_space_tag_t iot, bus_space_handle_t ioh) 1816 { 1817 1818 /* 1819 * Reset Chip. 1820 */ 1821 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1822 ADW_CTRL_REG_CMD_RESET); 1823 AdwSleepMilliSecond(100); 1824 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1825 ADW_CTRL_REG_CMD_WR_IO_REG); 1826 } 1827 1828 1829 /* 1830 * Reset SCSI Bus and purge all outstanding requests. 1831 * 1832 * Return Value: 1833 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1834 * ADW_FALSE(0) - Microcode command failed. 1835 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1836 * may be hung which requires driver recovery. 1837 */ 1838 int 1839 AdwResetCCB(ADW_SOFTC *sc) 1840 { 1841 int status; 1842 1843 /* 1844 * Send the SCSI Bus Reset idle start idle command which asserts 1845 * the SCSI Bus Reset signal. 1846 */ 1847 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1848 if (status != ADW_TRUE) { 1849 return status; 1850 } 1851 1852 /* 1853 * Delay for the specified SCSI Bus Reset hold time. 1854 * 1855 * The hold time delay is done on the host because the RISC has no 1856 * microsecond accurate timer. 1857 */ 1858 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1859 1860 /* 1861 * Send the SCSI Bus Reset end idle command which de-asserts 1862 * the SCSI Bus Reset signal and purges any pending requests. 1863 */ 1864 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1865 if (status != ADW_TRUE) { 1866 return status; 1867 } 1868 1869 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1870 1871 return status; 1872 } 1873 1874 1875 /* 1876 * Reset chip and SCSI Bus. 1877 * 1878 * Return Value: 1879 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1880 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1881 */ 1882 int 1883 AdwResetSCSIBus(ADW_SOFTC *sc) 1884 { 1885 bus_space_tag_t iot = sc->sc_iot; 1886 bus_space_handle_t ioh = sc->sc_ioh; 1887 int status; 1888 u_int16_t wdtr_able, sdtr_able, tagqng_able; 1889 u_int16_t ppr_able = 0; /* XXX: gcc */ 1890 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1891 u_int16_t bios_sig; 1892 1893 1894 /* 1895 * Save current per TID negotiated values. 1896 */ 1897 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1898 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1899 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1900 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1901 } 1902 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1903 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1904 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1905 max_cmd[tid]); 1906 } 1907 1908 /* 1909 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1910 * by clearing the BIOS signature word. 1911 * The initialization functions assumes a SCSI Bus Reset is not 1912 * needed if the BIOS signature word is present. 1913 */ 1914 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1915 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1916 1917 /* 1918 * Stop chip and reset it. 1919 */ 1920 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1921 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1922 ADW_CTRL_REG_CMD_RESET); 1923 AdwSleepMilliSecond(100); 1924 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1925 ADW_CTRL_REG_CMD_WR_IO_REG); 1926 1927 /* 1928 * Reset Adv Library error code, if any, and try 1929 * re-initializing the chip. 1930 * Then translate initialization return value to status value. 1931 */ 1932 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1933 1934 /* 1935 * Restore the BIOS signature word. 1936 */ 1937 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1938 1939 /* 1940 * Restore per TID negotiated values. 1941 */ 1942 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1943 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1944 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1945 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1946 } 1947 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1948 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1949 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1950 max_cmd[tid]); 1951 } 1952 1953 return status; 1954 } 1955 1956 1957 /* 1958 * Adv Library Interrupt Service Routine 1959 * 1960 * This function is called by a driver's interrupt service routine. 1961 * The function disables and re-enables interrupts. 1962 * 1963 * When a microcode idle command is completed, the ADV_DVC_VAR 1964 * 'idle_cmd_done' field is set to ADW_TRUE. 1965 * 1966 * Note: AdwISR() can be called when interrupts are disabled or even 1967 * when there is no hardware interrupt condition present. It will 1968 * always check for completed idle commands and microcode requests. 1969 * This is an important feature that shouldn't be changed because it 1970 * allows commands to be completed from polling mode loops. 1971 * 1972 * Return: 1973 * ADW_TRUE(1) - interrupt was pending 1974 * ADW_FALSE(0) - no interrupt was pending 1975 */ 1976 int 1977 AdwISR(ADW_SOFTC *sc) 1978 { 1979 bus_space_tag_t iot = sc->sc_iot; 1980 bus_space_handle_t ioh = sc->sc_ioh; 1981 u_int8_t int_stat; 1982 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 1983 u_int32_t irq_next_pa; 1984 ADW_SCSI_REQ_Q *scsiq; 1985 ADW_CCB *ccb; 1986 int s; 1987 1988 1989 s = splbio(); 1990 1991 /* Reading the register clears the interrupt. */ 1992 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 1993 1994 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 1995 ADW_INTR_STATUS_INTRC)) == 0) { 1996 splx(s); 1997 return ADW_FALSE; 1998 } 1999 2000 /* 2001 * Notify the driver of an asynchronous microcode condition by 2002 * calling the ADV_DVC_VAR.async_callback function. The function 2003 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2004 */ 2005 if (int_stat & ADW_INTR_STATUS_INTRB) { 2006 u_int8_t intrb_code; 2007 2008 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2009 2010 if (sc->chip_type == ADW_CHIP_ASC3550 || 2011 sc->chip_type == ADW_CHIP_ASC38C0800) { 2012 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2013 sc->carr_pending_cnt != 0) { 2014 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2015 IOPB_TICKLE, ADW_TICKLE_A); 2016 if (sc->chip_type == ADW_CHIP_ASC3550) { 2017 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2018 IOPB_TICKLE, ADW_TICKLE_NOP); 2019 } 2020 } 2021 } 2022 2023 if (sc->async_callback != 0) { 2024 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2025 } 2026 } 2027 2028 /* 2029 * Check if the IRQ stopper carrier contains a completed request. 2030 */ 2031 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0) 2032 { 2033 #if ADW_DEBUG 2034 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2035 sc->irq_sp->carr_id, 2036 sc->irq_sp->carr_ba, 2037 sc->irq_sp->areq_ba, 2038 sc->irq_sp->next_ba); 2039 #endif 2040 /* 2041 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2042 * structure. 2043 * The RISC will have set 'areq_ba' to a virtual address. 2044 * 2045 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2046 * field to the carrier ADV_CARR_T.areq_ba field. 2047 * The conversion below complements the conversion of 2048 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2049 */ 2050 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2051 scsiq = &ccb->scsiq; 2052 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2053 2054 /* 2055 * Request finished with good status and the queue was not 2056 * DMAed to host memory by the firmware. Set all status fields 2057 * to indicate good status. 2058 */ 2059 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) { 2060 scsiq->done_status = QD_NO_ERROR; 2061 scsiq->host_status = scsiq->scsi_status = 0; 2062 scsiq->data_cnt = 0L; 2063 } 2064 2065 /* 2066 * Advance the stopper pointer to the next carrier 2067 * ignoring the lower four bits. Free the previous 2068 * stopper carrier. 2069 */ 2070 free_carrp = sc->irq_sp; 2071 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2072 2073 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0 2074 : sc->carr_freelist->carr_ba; 2075 sc->carr_freelist = free_carrp; 2076 sc->carr_pending_cnt--; 2077 2078 /* 2079 * Clear request microcode control flag. 2080 */ 2081 scsiq->cntl = 0; 2082 2083 /* 2084 * Check Condition handling 2085 */ 2086 /* 2087 * If the command that completed was a SCSI INQUIRY and 2088 * LUN 0 was sent the command, then process the INQUIRY 2089 * command information for the device. 2090 */ 2091 if (scsiq->done_status == QD_NO_ERROR && 2092 scsiq->cdb[0] == INQUIRY && 2093 scsiq->target_lun == 0) { 2094 AdwInquiryHandling(sc, scsiq); 2095 } 2096 2097 /* 2098 * Notify the driver of the completed request by passing 2099 * the ADW_SCSI_REQ_Q pointer to its callback function. 2100 */ 2101 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2102 /* 2103 * Note: After the driver callback function is called, 'scsiq' 2104 * can no longer be referenced. 2105 * 2106 * Fall through and continue processing other completed 2107 * requests... 2108 */ 2109 } 2110 2111 splx(s); 2112 2113 return ADW_TRUE; 2114 } 2115 2116 2117 /* 2118 * Send an idle command to the chip and wait for completion. 2119 * 2120 * Command completion is polled for once per microsecond. 2121 * 2122 * The function can be called from anywhere including an interrupt handler. 2123 * But the function is not re-entrant, so it uses the splbio/splx() 2124 * functions to prevent reentrancy. 2125 * 2126 * Return Values: 2127 * ADW_TRUE - command completed successfully 2128 * ADW_FALSE - command failed 2129 * ADW_ERROR - command timed out 2130 */ 2131 int 2132 AdwSendIdleCmd(ADW_SOFTC *sc, u_int16_t idle_cmd, u_int32_t idle_cmd_parameter) 2133 { 2134 bus_space_tag_t iot = sc->sc_iot; 2135 bus_space_handle_t ioh = sc->sc_ioh; 2136 u_int16_t result; 2137 u_int32_t i, j, s; 2138 2139 s = splbio(); 2140 2141 /* 2142 * Clear the idle command status which is set by the microcode 2143 * to a non-zero value to indicate when the command is completed. 2144 */ 2145 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2146 2147 /* 2148 * Write the idle command value after the idle command parameter 2149 * has been written to avoid a race condition. If the order is not 2150 * followed, the microcode may process the idle command before the 2151 * parameters have been written to LRAM. 2152 */ 2153 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2154 idle_cmd_parameter); 2155 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2156 2157 /* 2158 * Tickle the RISC to tell it to process the idle command. 2159 */ 2160 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2161 if (sc->chip_type == ADW_CHIP_ASC3550) { 2162 /* 2163 * Clear the tickle value. In the ASC-3550 the RISC flag 2164 * command 'clr_tickle_b' does not work unless the host 2165 * value is cleared. 2166 */ 2167 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2168 } 2169 2170 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2171 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2172 /* Poll once each microsecond for command completion. */ 2173 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2174 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2175 result); 2176 if (result != 0) { 2177 splx(s); 2178 return result; 2179 } 2180 AdwDelayMicroSecond(1); 2181 } 2182 } 2183 2184 splx(s); 2185 return ADW_ERROR; 2186 } 2187 2188 2189 /* 2190 * Inquiry Information Byte 7 Handling 2191 * 2192 * Handle SCSI Inquiry Command information for a device by setting 2193 * microcode operating variables that affect WDTR, SDTR, and Tag 2194 * Queuing. 2195 */ 2196 static void 2197 AdwInquiryHandling(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 2198 { 2199 #ifndef FAILSAFE 2200 bus_space_tag_t iot = sc->sc_iot; 2201 bus_space_handle_t ioh = sc->sc_ioh; 2202 u_int8_t tid; 2203 struct scsipi_inquiry_data *inq; 2204 u_int16_t tidmask; 2205 u_int16_t cfg_word; 2206 2207 2208 /* 2209 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2210 * to be available. 2211 * 2212 * If less than 8 bytes of INQUIRY information were requested or less 2213 * than 8 bytes were transferred, then return. cdb[4] is the request 2214 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2215 * microcode to the transfer residual count. 2216 */ 2217 2218 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2219 return; 2220 } 2221 2222 tid = scsiq->target_id; 2223 2224 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2225 2226 /* 2227 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2228 */ 2229 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2230 ((inq->version & SID_ANSII) < 2)) { 2231 return; 2232 } else { 2233 /* 2234 * INQUIRY Byte 7 Handling 2235 * 2236 * Use a device's INQUIRY byte 7 to determine whether it 2237 * supports WDTR, SDTR, and Tag Queuing. If the feature 2238 * is enabled in the EEPROM and the device supports the 2239 * feature, then enable it in the microcode. 2240 */ 2241 2242 tidmask = ADW_TID_TO_TIDMASK(tid); 2243 2244 /* 2245 * Wide Transfers 2246 * 2247 * If the EEPROM enabled WDTR for the device and the device 2248 * supports wide bus (16 bit) transfers, then turn on the 2249 * device's 'wdtr_able' bit and write the new value to the 2250 * microcode. 2251 */ 2252 #ifdef SCSI_ADW_WDTR_DISABLE 2253 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2254 #endif /* SCSI_ADW_WDTR_DISABLE */ 2255 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2256 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2257 cfg_word); 2258 if ((cfg_word & tidmask) == 0) { 2259 cfg_word |= tidmask; 2260 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2261 cfg_word); 2262 2263 /* 2264 * Clear the microcode "SDTR negotiation" and 2265 * "WDTR negotiation" done indicators for the 2266 * target to cause it to negotiate with the new 2267 * setting set above. 2268 * WDTR when accepted causes the target to enter 2269 * asynchronous mode, so SDTR must be negotiated 2270 */ 2271 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2272 cfg_word); 2273 cfg_word &= ~tidmask; 2274 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2275 cfg_word); 2276 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2277 cfg_word); 2278 cfg_word &= ~tidmask; 2279 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2280 cfg_word); 2281 } 2282 } 2283 2284 /* 2285 * Synchronous Transfers 2286 * 2287 * If the EEPROM enabled SDTR for the device and the device 2288 * supports synchronous transfers, then turn on the device's 2289 * 'sdtr_able' bit. Write the new value to the microcode. 2290 */ 2291 #ifdef SCSI_ADW_SDTR_DISABLE 2292 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2293 #endif /* SCSI_ADW_SDTR_DISABLE */ 2294 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2295 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2296 if ((cfg_word & tidmask) == 0) { 2297 cfg_word |= tidmask; 2298 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2299 cfg_word); 2300 2301 /* 2302 * Clear the microcode "SDTR negotiation" 2303 * done indicator for the target to cause it 2304 * to negotiate with the new setting set above. 2305 */ 2306 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2307 cfg_word); 2308 cfg_word &= ~tidmask; 2309 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2310 cfg_word); 2311 } 2312 } 2313 /* 2314 * If the Inquiry data included enough space for the SPI-3 2315 * Clocking field, then check if DT mode is supported. 2316 */ 2317 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2318 (scsiq->cdb[4] >= 57 || 2319 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2320 /* 2321 * PPR (Parallel Protocol Request) Capable 2322 * 2323 * If the device supports DT mode, then it must be 2324 * PPR capable. 2325 * The PPR message will be used in place of the SDTR 2326 * and WDTR messages to negotiate synchronous speed 2327 * and offset, transfer width, and protocol options. 2328 */ 2329 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2330 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2331 sc->ppr_able); 2332 sc->ppr_able |= tidmask; 2333 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2334 sc->ppr_able); 2335 } 2336 } 2337 2338 /* 2339 * If the EEPROM enabled Tag Queuing for the device and the 2340 * device supports Tag Queueing, then turn on the device's 2341 * 'tagqng_enable' bit in the microcode and set the microcode 2342 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2343 * value. 2344 * 2345 * Tag Queuing is disabled for the BIOS which runs in polled 2346 * mode and would see no benefit from Tag Queuing. Also by 2347 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2348 * bugs will at least work with the BIOS. 2349 */ 2350 #ifdef SCSI_ADW_TAGQ_DISABLE 2351 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2352 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2353 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2354 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2355 cfg_word); 2356 cfg_word |= tidmask; 2357 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2358 cfg_word); 2359 2360 ADW_WRITE_BYTE_LRAM(iot, ioh, 2361 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2362 sc->max_dvc_qng); 2363 } 2364 } 2365 #endif /* FAILSAFE */ 2366 } 2367 2368 2369 static void 2370 AdwSleepMilliSecond(u_int32_t n) 2371 { 2372 2373 DELAY(n * 1000); 2374 } 2375 2376 2377 static void 2378 AdwDelayMicroSecond(u_int32_t n) 2379 { 2380 2381 DELAY(n); 2382 } 2383 2384
Indexes created Mon Sep 22 21:09:42 GMT 2025