adwlib.c revision 1.44
1 /* $NetBSD: adwlib.c,v 1.44 2019/12/15 16:48:27 tsutsui Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from: 34 */ 35 /* 36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 37 * 38 * Copyright (c) 1995-2000 Advanced System Products, Inc. 39 * All Rights Reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that redistributions of source 43 * code retain the above copyright notice and this comment without 44 * modification. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.44 2019/12/15 16:48:27 tsutsui Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/queue.h> 55 #include <sys/device.h> 56 57 #include <sys/bus.h> 58 #include <sys/intr.h> 59 60 #include <dev/scsipi/scsi_all.h> 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsiconf.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/ic/adwlib.h> 67 #include <dev/ic/adwmcode.h> 68 #include <dev/ic/adw.h> 69 70 71 /* Static Functions */ 72 73 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t); 74 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, u_int8_t); 75 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 76 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 77 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 78 79 static u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 80 ADW_EEPROM *); 81 static void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 82 ADW_EEPROM *); 83 static u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int); 84 static void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t); 85 86 static void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 87 88 static void AdwSleepMilliSecond(u_int32_t); 89 static void AdwDelayMicroSecond(u_int32_t); 90 91 92 /* 93 * EEPROM Configuration. 94 * 95 * All drivers should use this structure to set the default EEPROM 96 * configuration. The BIOS now uses this structure when it is built. 97 * Additional structure information can be found in adwlib.h where 98 * the structure is defined. 99 */ 100 static const ADW_EEPROM adw_3550_Default_EEPROM = { 101 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 102 0x0000, /* 01 cfg_msw */ 103 0xFFFF, /* 02 disc_enable */ 104 0xFFFF, /* 03 wdtr_able */ 105 { 0xFFFF }, /* 04 sdtr_able */ 106 0xFFFF, /* 05 start_motor */ 107 0xFFFF, /* 06 tagqng_able */ 108 0xFFFF, /* 07 bios_scan */ 109 0, /* 08 scam_tolerant */ 110 7, /* 09 adapter_scsi_id */ 111 0, /* bios_boot_delay */ 112 3, /* 10 scsi_reset_delay */ 113 0, /* bios_id_lun */ 114 0, /* 11 termination */ 115 0, /* reserved1 */ 116 0xFFE7, /* 12 bios_ctrl */ 117 { 0xFFFF }, /* 13 ultra_able */ 118 { 0 }, /* 14 reserved2 */ 119 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 120 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 121 0, /* 16 dvc_cntl */ 122 { 0 }, /* 17 bug_fix */ 123 { 0,0,0 }, /* 18-20 serial_number[3] */ 124 0, /* 21 check_sum */ 125 { /* 22-29 oem_name[16] */ 126 0,0,0,0,0,0,0,0, 127 0,0,0,0,0,0,0,0 128 }, 129 0, /* 30 dvc_err_code */ 130 0, /* 31 adv_err_code */ 131 0, /* 32 adv_err_addr */ 132 0, /* 33 saved_dvc_err_code */ 133 0, /* 34 saved_adv_err_code */ 134 0, /* 35 saved_adv_err_addr */ 135 { /* 36-55 reserved1[16] */ 136 0,0,0,0,0,0,0,0,0,0, 137 0,0,0,0,0,0,0,0,0,0 138 }, 139 0, /* 56 cisptr_lsw */ 140 0, /* 57 cisprt_msw */ 141 0, /* 58 subsysvid */ 142 0, /* 59 subsysid */ 143 { 0,0,0,0 } /* 60-63 reserved2[4] */ 144 }; 145 146 static const ADW_EEPROM adw_38C0800_Default_EEPROM = { 147 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 148 0x0000, /* 01 cfg_msw */ 149 0xFFFF, /* 02 disc_enable */ 150 0xFFFF, /* 03 wdtr_able */ 151 { 0x4444 }, /* 04 sdtr_speed1 */ 152 0xFFFF, /* 05 start_motor */ 153 0xFFFF, /* 06 tagqng_able */ 154 0xFFFF, /* 07 bios_scan */ 155 0, /* 08 scam_tolerant */ 156 7, /* 09 adapter_scsi_id */ 157 0, /* bios_boot_delay */ 158 3, /* 10 scsi_reset_delay */ 159 0, /* bios_id_lun */ 160 0, /* 11 termination_se */ 161 0, /* termination_lvd */ 162 0xFFE7, /* 12 bios_ctrl */ 163 { 0x4444 }, /* 13 sdtr_speed2 */ 164 { 0x4444 }, /* 14 sdtr_speed3 */ 165 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 166 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 167 0, /* 16 dvc_cntl */ 168 { 0x4444 }, /* 17 sdtr_speed4 */ 169 { 0,0,0 }, /* 18-20 serial_number[3] */ 170 0, /* 21 check_sum */ 171 { /* 22-29 oem_name[16] */ 172 0,0,0,0,0,0,0,0, 173 0,0,0,0,0,0,0,0 174 }, 175 0, /* 30 dvc_err_code */ 176 0, /* 31 adv_err_code */ 177 0, /* 32 adv_err_addr */ 178 0, /* 33 saved_dvc_err_code */ 179 0, /* 34 saved_adv_err_code */ 180 0, /* 35 saved_adv_err_addr */ 181 { /* 36-55 reserved1[16] */ 182 0,0,0,0,0,0,0,0,0,0, 183 0,0,0,0,0,0,0,0,0,0 184 }, 185 0, /* 56 cisptr_lsw */ 186 0, /* 57 cisprt_msw */ 187 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 188 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 189 { 0,0,0,0 } /* 60-63 reserved2[4] */ 190 }; 191 192 static const ADW_EEPROM adw_38C1600_Default_EEPROM = { 193 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 194 0x0000, /* 01 cfg_msw */ 195 0xFFFF, /* 02 disc_enable */ 196 0xFFFF, /* 03 wdtr_able */ 197 { 0x5555 }, /* 04 sdtr_speed1 */ 198 0xFFFF, /* 05 start_motor */ 199 0xFFFF, /* 06 tagqng_able */ 200 0xFFFF, /* 07 bios_scan */ 201 0, /* 08 scam_tolerant */ 202 7, /* 09 adapter_scsi_id */ 203 0, /* bios_boot_delay */ 204 3, /* 10 scsi_reset_delay */ 205 0, /* bios_id_lun */ 206 0, /* 11 termination_se */ 207 0, /* termination_lvd */ 208 0xFFE7, /* 12 bios_ctrl */ 209 { 0x5555 }, /* 13 sdtr_speed2 */ 210 { 0x5555 }, /* 14 sdtr_speed3 */ 211 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 212 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 213 0, /* 16 dvc_cntl */ 214 { 0x5555 }, /* 17 sdtr_speed4 */ 215 { 0,0,0 }, /* 18-20 serial_number[3] */ 216 0, /* 21 check_sum */ 217 { /* 22-29 oem_name[16] */ 218 0,0,0,0,0,0,0,0, 219 0,0,0,0,0,0,0,0 220 }, 221 0, /* 30 dvc_err_code */ 222 0, /* 31 adv_err_code */ 223 0, /* 32 adv_err_addr */ 224 0, /* 33 saved_dvc_err_code */ 225 0, /* 34 saved_adv_err_code */ 226 0, /* 35 saved_adv_err_addr */ 227 { /* 36-55 reserved1[16] */ 228 0,0,0,0,0,0,0,0,0,0, 229 0,0,0,0,0,0,0,0,0,0 230 }, 231 0, /* 56 cisptr_lsw */ 232 0, /* 57 cisprt_msw */ 233 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 234 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 235 { 0,0,0,0 } /* 60-63 reserved2[4] */ 236 }; 237 238 239 /* 240 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 241 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 242 * all of this is done. 243 * 244 * For a non-fatal error return a warning code. If there are no warnings 245 * then 0 is returned. 246 * 247 * Note: Chip is stopped on entry. 248 */ 249 int 250 AdwInitFromEEPROM(ADW_SOFTC *sc) 251 { 252 bus_space_tag_t iot = sc->sc_iot; 253 bus_space_handle_t ioh = sc->sc_ioh; 254 ADW_EEPROM eep_config; 255 u_int16_t warn_code; 256 u_int16_t sdtr_speed = 0; 257 u_int8_t tid, termination; 258 int i, j; 259 260 261 warn_code = 0; 262 263 /* 264 * Read the board's EEPROM configuration. 265 * 266 * Set default values if a bad checksum is found. 267 * 268 * XXX - Don't handle big-endian access to EEPROM yet. 269 */ 270 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 271 warn_code |= ADW_WARN_EEPROM_CHKSUM; 272 273 /* 274 * Set EEPROM default values. 275 */ 276 switch(sc->chip_type) { 277 case ADW_CHIP_ASC3550: 278 eep_config = adw_3550_Default_EEPROM; 279 break; 280 case ADW_CHIP_ASC38C0800: 281 eep_config = adw_38C0800_Default_EEPROM; 282 break; 283 case ADW_CHIP_ASC38C1600: 284 eep_config = adw_38C1600_Default_EEPROM; 285 286 #if 0 287 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 288 #endif 289 if (sc->cfg.pci_slot_info != 0) { 290 u_int8_t lsw_msb; 291 292 lsw_msb = eep_config.cfg_lsw >> 8; 293 /* 294 * Set Function 1 EEPROM Word 0 MSB 295 * 296 * Clear the BIOS_ENABLE (bit 14) and 297 * INTAB (bit 11) EEPROM bits. 298 * 299 * Disable Bit 14 (BIOS_ENABLE) to fix 300 * SPARC Ultra 60 and old Mac system booting 301 * problem. The Expansion ROM must 302 * be disabled in Function 1 for these systems. 303 */ 304 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 305 ADW_EEPROM_INTAB) >> 8) & 0xFF); 306 /* 307 * Set the INTAB (bit 11) if the GPIO 0 input 308 * indicates the Function 1 interrupt line is 309 * wired to INTA. 310 * 311 * Set/Clear Bit 11 (INTAB) from 312 * the GPIO bit 0 input: 313 * 1 - Function 1 intr line wired to INT A. 314 * 0 - Function 1 intr line wired to INT B. 315 * 316 * Note: Adapter boards always have Function 0 317 * wired to INTA. 318 * Put all 5 GPIO bits in input mode and then 319 * read their input values. 320 */ 321 ADW_WRITE_BYTE_REGISTER(iot, ioh, 322 IOPB_GPIO_CNTL, 0); 323 if (ADW_READ_BYTE_REGISTER(iot, ioh, 324 IOPB_GPIO_DATA) & 0x01) { 325 /* 326 * Function 1 interrupt wired to INTA; 327 * Set EEPROM bit. 328 */ 329 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 330 & 0xFF; 331 } 332 eep_config.cfg_lsw &= 0x00FF; 333 eep_config.cfg_lsw |= lsw_msb << 8; 334 } 335 break; 336 } 337 338 /* 339 * Assume the 6 byte board serial number that was read 340 * from EEPROM is correct even if the EEPROM checksum 341 * failed. 342 */ 343 for (i=2, j=1; i>=0; i--, j++) { 344 eep_config.serial_number[i] = 345 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 346 } 347 348 AdwSetEEPROMConfig(iot, ioh, &eep_config); 349 } 350 /* 351 * Set sc and sc->cfg variables from the EEPROM configuration 352 * that was read. 353 * 354 * This is the mapping of EEPROM fields to Adw Library fields. 355 */ 356 sc->wdtr_able = eep_config.wdtr_able; 357 if (sc->chip_type == ADW_CHIP_ASC3550) { 358 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 359 sc->ultra_able = eep_config.sdtr2.ultra_able; 360 } else { 361 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 362 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 363 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 364 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 365 } 366 sc->ppr_able = 0; 367 sc->tagqng_able = eep_config.tagqng_able; 368 sc->cfg.disc_enable = eep_config.disc_enable; 369 sc->max_host_qng = eep_config.max_host_qng; 370 sc->max_dvc_qng = eep_config.max_dvc_qng; 371 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 372 sc->start_motor = eep_config.start_motor; 373 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 374 sc->bios_ctrl = eep_config.bios_ctrl; 375 sc->no_scam = eep_config.scam_tolerant; 376 sc->cfg.serial1 = eep_config.serial_number[0]; 377 sc->cfg.serial2 = eep_config.serial_number[1]; 378 sc->cfg.serial3 = eep_config.serial_number[2]; 379 380 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 381 sc->chip_type == ADW_CHIP_ASC38C1600) { 382 sc->sdtr_able = 0; 383 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 384 if (tid == 0) { 385 sdtr_speed = sc->sdtr_speed1; 386 } else if (tid == 4) { 387 sdtr_speed = sc->sdtr_speed2; 388 } else if (tid == 8) { 389 sdtr_speed = sc->sdtr_speed3; 390 } else if (tid == 12) { 391 sdtr_speed = sc->sdtr_speed4; 392 } 393 if (sdtr_speed & ADW_MAX_TID) { 394 sc->sdtr_able |= (1 << tid); 395 } 396 sdtr_speed >>= 4; 397 } 398 } 399 400 /* 401 * Set the host maximum queuing (max. 253, min. 16) and the per device 402 * maximum queuing (max. 63, min. 4). 403 */ 404 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 405 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 406 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 407 { 408 /* If the value is zero, assume it is uninitialized. */ 409 if (eep_config.max_host_qng == 0) { 410 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 411 } else { 412 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 413 } 414 } 415 416 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 417 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 418 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 419 /* If the value is zero, assume it is uninitialized. */ 420 if (eep_config.max_dvc_qng == 0) { 421 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 422 } else { 423 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 424 } 425 } 426 427 /* 428 * If 'max_dvc_qng' is greater than 'max_host_qng', then 429 * set 'max_dvc_qng' to 'max_host_qng'. 430 */ 431 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 432 eep_config.max_dvc_qng = eep_config.max_host_qng; 433 } 434 435 /* 436 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 437 * values based on possibly adjusted EEPROM values. 438 */ 439 sc->max_host_qng = eep_config.max_host_qng; 440 sc->max_dvc_qng = eep_config.max_dvc_qng; 441 442 443 /* 444 * If the EEPROM 'termination' field is set to automatic (0), then set 445 * the ADV_DVC_CFG 'termination' field to automatic also. 446 * 447 * If the termination is specified with a non-zero 'termination' 448 * value check that a legal value is set and set the ADV_DVC_CFG 449 * 'termination' field appropriately. 450 */ 451 452 switch(sc->chip_type) { 453 case ADW_CHIP_ASC3550: 454 sc->cfg.termination = 0; /* auto termination */ 455 switch(eep_config.termination_se) { 456 case 3: 457 /* Enable manual control with low on / high on. */ 458 sc->cfg.termination |= ADW_TERM_CTL_L; 459 /* FALLTHROUGH */ 460 case 2: 461 /* Enable manual control with low off / high on. */ 462 sc->cfg.termination |= ADW_TERM_CTL_H; 463 /* FALLTHROUGH */ 464 case 1: 465 /* Enable manual control with low off / high off. */ 466 sc->cfg.termination |= ADW_TERM_CTL_SEL; 467 /* FALLTHROUGH */ 468 case 0: 469 break; 470 default: 471 warn_code |= ADW_WARN_EEPROM_TERMINATION; 472 } 473 break; 474 475 case ADW_CHIP_ASC38C0800: 476 case ADW_CHIP_ASC38C1600: 477 switch(eep_config.termination_se) { 478 case 0: 479 /* auto termination for SE */ 480 termination = 0; 481 break; 482 case 1: 483 /* Enable manual control with low off / high off. */ 484 termination = 0; 485 break; 486 case 2: 487 /* Enable manual control with low off / high on. */ 488 termination = ADW_TERM_SE_HI; 489 break; 490 case 3: 491 /* Enable manual control with low on / high on. */ 492 termination = ADW_TERM_SE; 493 break; 494 default: 495 /* 496 * The EEPROM 'termination_se' field contains a 497 * bad value. Use automatic termination instead. 498 */ 499 termination = 0; 500 warn_code |= ADW_WARN_EEPROM_TERMINATION; 501 } 502 503 switch(eep_config.termination_lvd) { 504 case 0: 505 /* auto termination for LVD */ 506 sc->cfg.termination = termination; 507 break; 508 case 1: 509 /* Enable manual control with low off / high off. */ 510 sc->cfg.termination = termination; 511 break; 512 case 2: 513 /* Enable manual control with low off / high on. */ 514 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 515 break; 516 case 3: 517 /* Enable manual control with low on / high on. */ 518 sc->cfg.termination = termination | ADW_TERM_LVD; 519 break; 520 default: 521 /* 522 * The EEPROM 'termination_lvd' field contains a 523 * bad value. Use automatic termination instead. 524 */ 525 sc->cfg.termination = termination; 526 warn_code |= ADW_WARN_EEPROM_TERMINATION; 527 } 528 break; 529 } 530 531 return warn_code; 532 } 533 534 535 /* 536 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 537 * 538 * On failure return the error code. 539 */ 540 int 541 AdwInitDriver(ADW_SOFTC *sc) 542 { 543 bus_space_tag_t iot = sc->sc_iot; 544 bus_space_handle_t ioh = sc->sc_ioh; 545 u_int16_t error_code; 546 int word; 547 int i; 548 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 549 0x40-0x8F. */ 550 u_int16_t wdtr_able = 0, sdtr_able, /* ppr_able, */ tagqng_able; 551 u_int8_t max_cmd[ADW_MAX_TID + 1]; 552 u_int8_t tid; 553 554 555 error_code = 0; 556 557 /* 558 * Save the RISC memory BIOS region before writing the microcode. 559 * The BIOS may already be loaded and using its RISC LRAM region 560 * so its region must be saved and restored. 561 * 562 * Note: This code makes the assumption, which is currently true, 563 * that a chip reset does not clear RISC LRAM. 564 */ 565 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 566 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 567 } 568 569 /* 570 * Save current per TID negotiated values. 571 */ 572 switch (sc->chip_type) { 573 case ADW_CHIP_ASC3550: 574 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 575 576 u_int16_t bios_version, major, minor; 577 578 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 579 ADW_MC_BIOSMEM) / 2]; 580 major = (bios_version >> 12) & 0xF; 581 minor = (bios_version >> 8) & 0xF; 582 if (major < 3 || (major == 3 && minor == 1)) { 583 /* 584 * BIOS 3.1 and earlier location of 585 * 'wdtr_able' variable. 586 */ 587 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 588 } else { 589 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 590 wdtr_able); 591 } 592 } 593 break; 594 595 case ADW_CHIP_ASC38C1600: 596 /* ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); */ 597 /* FALLTHROUGH */ 598 case ADW_CHIP_ASC38C0800: 599 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 600 break; 601 } 602 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 603 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 604 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 605 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 606 max_cmd[tid]); 607 } 608 609 /* 610 * Perform a RAM Built-In Self Test 611 */ 612 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 613 return error_code; 614 } 615 616 /* 617 * Load the Microcode 618 */ 619 ; 620 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 621 return error_code; 622 } 623 624 /* 625 * Read microcode version and date. 626 */ 627 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 628 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 629 630 /* 631 * If the PCI Configuration Command Register "Parity Error Response 632 * Control" Bit was clear (0), then set the microcode variable 633 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 634 * to ignore DMA parity errors. 635 */ 636 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 637 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 638 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 639 word | CONTROL_FLAG_IGNORE_PERR); 640 } 641 642 switch (sc->chip_type) { 643 case ADW_CHIP_ASC3550: 644 /* 645 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 646 * FIFO threshold of 128 bytes. 647 * This register is only accessible to the host. 648 */ 649 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 650 START_CTL_EMFU | READ_CMD_MRM); 651 break; 652 653 case ADW_CHIP_ASC38C0800: 654 /* 655 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 656 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 657 * cable detection and then we are able to read C_DET[3:0]. 658 * 659 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 660 * Microcode Default Value' section below. 661 */ 662 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 663 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 664 | ADW_DIS_TERM_DRV); 665 666 /* 667 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 668 * START_CTL_TH [3:2] bits for the default FIFO threshold. 669 * 670 * Note: ASC-38C0800 FIFO threshold has been changed to 671 * 256 bytes. 672 * 673 * For DMA Errata #4 set the BC_THRESH_ENB bit. 674 */ 675 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 676 BC_THRESH_ENB | FIFO_THRESH_80B 677 | START_CTL_TH | READ_CMD_MRM); 678 break; 679 680 case ADW_CHIP_ASC38C1600: 681 /* 682 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 683 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 684 * cable detection and then we are able to read C_DET[3:0]. 685 * 686 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 687 * Microcode Default Value' section below. 688 */ 689 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 690 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 691 | ADW_DIS_TERM_DRV); 692 693 /* 694 * If the BIOS control flag AIPP (Asynchronous Information 695 * Phase Protection) disable bit is not set, then set the 696 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 697 * enable AIPP checking and encoding. 698 */ 699 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 700 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 701 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 702 word | CONTROL_FLAG_ENABLE_AIPP); 703 } 704 705 /* 706 * For ASC-38C1600 use DMA_CFG0 default values: 707 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 708 */ 709 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 710 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 711 break; 712 } 713 714 /* 715 * Microcode operating variables for WDTR, SDTR, and command tag 716 * queuing will be set in AdvInquiryHandling() based on what a 717 * device reports it is capable of in Inquiry byte 7. 718 * 719 * If SCSI Bus Resets have been disabled, then directly set 720 * SDTR and WDTR from the EEPROM configuration. This will allow 721 * the BIOS and warm boot to work without a SCSI bus hang on 722 * the Inquiry caused by host and target mismatched DTR values. 723 * Without the SCSI Bus Reset, before an Inquiry a device can't 724 * be assumed to be in Asynchronous, Narrow mode. 725 */ 726 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 727 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 728 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 729 } 730 731 /* 732 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 733 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 734 * bitmask. These values determine the maximum SDTR speed negotiated 735 * with a device. 736 * 737 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 738 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 739 * without determining here whether the device supports SDTR. 740 */ 741 switch (sc->chip_type) { 742 case ADW_CHIP_ASC3550: 743 word = 0; 744 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 745 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 746 /* Set Ultra speed for TID 'tid'. */ 747 word |= (0x3 << (4 * (tid % 4))); 748 } else { 749 /* Set Fast speed for TID 'tid'. */ 750 word |= (0x2 << (4 * (tid % 4))); 751 } 752 /* Check if done with sdtr_speed1. */ 753 if (tid == 3) { 754 ADW_WRITE_WORD_LRAM(iot, ioh, 755 ADW_MC_SDTR_SPEED1, word); 756 word = 0; 757 /* Check if done with sdtr_speed2. */ 758 } else if (tid == 7) { 759 ADW_WRITE_WORD_LRAM(iot, ioh, 760 ADW_MC_SDTR_SPEED2, word); 761 word = 0; 762 /* Check if done with sdtr_speed3. */ 763 } else if (tid == 11) { 764 ADW_WRITE_WORD_LRAM(iot, ioh, 765 ADW_MC_SDTR_SPEED3, word); 766 word = 0; 767 /* Check if done with sdtr_speed4. */ 768 } else if (tid == 15) { 769 ADW_WRITE_WORD_LRAM(iot, ioh, 770 ADW_MC_SDTR_SPEED4, word); 771 /* End of loop. */ 772 } 773 } 774 775 /* 776 * Set microcode operating variable for the 777 * disconnect per TID bitmask. 778 */ 779 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 780 sc->cfg.disc_enable); 781 break; 782 783 case ADW_CHIP_ASC38C0800: 784 /* FALLTHROUGH */ 785 case ADW_CHIP_ASC38C1600: 786 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 787 sc->cfg.disc_enable); 788 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 789 sc->sdtr_speed1); 790 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 791 sc->sdtr_speed2); 792 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 793 sc->sdtr_speed3); 794 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 795 sc->sdtr_speed4); 796 break; 797 } 798 799 800 /* 801 * Set SCSI_CFG0 Microcode Default Value. 802 * 803 * The microcode will set the SCSI_CFG0 register using this value 804 * after it is started below. 805 */ 806 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 807 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 808 ADW_OUR_ID_EN | sc->chip_scsi_id); 809 810 811 switch(sc->chip_type) { 812 case ADW_CHIP_ASC3550: 813 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 814 break; 815 816 case ADW_CHIP_ASC38C0800: 817 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 818 break; 819 820 case ADW_CHIP_ASC38C1600: 821 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 822 break; 823 } 824 if(error_code) { 825 return error_code; 826 } 827 828 /* 829 * Set SEL_MASK Microcode Default Value 830 * 831 * The microcode will set the SEL_MASK register using this value 832 * after it is started below. 833 */ 834 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 835 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 836 837 /* 838 * Create and Initialize Host->RISC Carrier lists 839 */ 840 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 841 sc->sc_control->carriers); 842 843 /* 844 * Set-up the Host->RISC Initiator Command Queue (ICQ). 845 */ 846 847 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 848 return ADW_IERR_NO_CARRIER; 849 } 850 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 851 ASC_GET_CARRP(sc->icq_sp->next_ba)); 852 853 /* 854 * The first command issued will be placed in the stopper carrier. 855 */ 856 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER); 857 858 /* 859 * Set RISC ICQ physical address start value. 860 */ 861 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba)); 862 863 /* 864 * Initialize the COMMA register to the same value otherwise 865 * the RISC will prematurely detect a command is available. 866 */ 867 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 868 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 869 le32toh(sc->icq_sp->carr_ba)); 870 } 871 872 /* 873 * Set-up the RISC->Host Initiator Response Queue (IRQ). 874 */ 875 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 876 return ADW_IERR_NO_CARRIER; 877 } 878 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 879 ASC_GET_CARRP(sc->irq_sp->next_ba)); 880 881 /* 882 * The first command completed by the RISC will be placed in 883 * the stopper. 884 * 885 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 886 * completed the RISC will set the ASC_RQ_DONE bit. 887 */ 888 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER); 889 890 /* 891 * Set RISC IRQ physical address start value. 892 */ 893 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba)); 894 sc->carr_pending_cnt = 0; 895 896 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 897 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 898 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 899 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 900 901 /* finally, finally, gentlemen, start your engine */ 902 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 903 904 /* 905 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 906 * Resets should be performed. The RISC has to be running 907 * to issue a SCSI Bus Reset. 908 */ 909 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 910 { 911 /* 912 * If the BIOS Signature is present in memory, restore the 913 * BIOS Handshake Configuration Table and do not perform 914 * a SCSI Bus Reset. 915 */ 916 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 917 0x55AA) { 918 /* 919 * Restore per TID negotiated values. 920 */ 921 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 922 wdtr_able); 923 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 924 sdtr_able); 925 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 926 tagqng_able); 927 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 928 ADW_WRITE_BYTE_LRAM(iot, ioh, 929 ADW_MC_NUMBER_OF_MAX_CMD + tid, 930 max_cmd[tid]); 931 } 932 } else { 933 if (AdwResetCCB(sc) != ADW_TRUE) { 934 error_code = ADW_WARN_BUSRESET_ERROR; 935 } 936 } 937 } 938 939 return error_code; 940 } 941 942 943 int 944 AdwRamSelfTest(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t chip_type) 945 { 946 int i; 947 u_int8_t byte; 948 949 950 if ((chip_type == ADW_CHIP_ASC38C0800) || 951 (chip_type == ADW_CHIP_ASC38C1600)) { 952 /* 953 * RAM BIST (RAM Built-In Self Test) 954 * 955 * Address : I/O base + offset 0x38h register (byte). 956 * Function: Bit 7-6(RW) : RAM mode 957 * Normal Mode : 0x00 958 * Pre-test Mode : 0x40 959 * RAM Test Mode : 0x80 960 * Bit 5 : unused 961 * Bit 4(RO) : Done bit 962 * Bit 3-0(RO) : Status 963 * Host Error : 0x08 964 * Int_RAM Error : 0x04 965 * RISC Error : 0x02 966 * SCSI Error : 0x01 967 * No Error : 0x00 968 * 969 * Note: RAM BIST code should be put right here, before loading 970 * the microcode and after saving the RISC memory BIOS region. 971 */ 972 973 /* 974 * LRAM Pre-test 975 * 976 * Write PRE_TEST_MODE (0x40) to register and wait for 977 * 10 milliseconds. 978 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 979 * return an error. Reset to NORMAL_MODE (0x00) and do again. 980 * If cannot reset to NORMAL_MODE, return an error too. 981 */ 982 for (i = 0; i < 2; i++) { 983 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 984 PRE_TEST_MODE); 985 /* Wait for 10ms before reading back. */ 986 AdwSleepMilliSecond(10); 987 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 988 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 989 PRE_TEST_VALUE) { 990 return ADW_IERR_BIST_PRE_TEST; 991 } 992 993 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 994 NORMAL_MODE); 995 /* Wait for 10ms before reading back. */ 996 AdwSleepMilliSecond(10); 997 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 998 != NORMAL_VALUE) { 999 return ADW_IERR_BIST_PRE_TEST; 1000 } 1001 } 1002 1003 /* 1004 * LRAM Test - It takes about 1.5 ms to run through the test. 1005 * 1006 * Write RAM_TEST_MODE (0x80) to register and wait for 1007 * 10 milliseconds. 1008 * If Done bit not set or Status not 0, save register byte, 1009 * set the err_code, and return an error. 1010 */ 1011 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1012 /* Wait for 10ms before checking status. */ 1013 AdwSleepMilliSecond(10); 1014 1015 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1016 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1017 /* Get here if Done bit not set or Status not 0. */ 1018 return ADW_IERR_BIST_RAM_TEST; 1019 } 1020 1021 /* We need to reset back to normal mode after LRAM test passes*/ 1022 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1023 } 1024 1025 return 0; 1026 } 1027 1028 1029 int 1030 AdwLoadMCode(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t *bios_mem, u_int8_t chip_type) 1031 { 1032 const u_int8_t *mcode_data; 1033 u_int32_t mcode_chksum; 1034 u_int16_t mcode_size; 1035 u_int32_t sum; 1036 u_int16_t code_sum; 1037 int begin_addr; 1038 int end_addr; 1039 int word; 1040 int adw_memsize; 1041 int adw_mcode_expanded_size; 1042 int i, j; 1043 1044 1045 switch(chip_type) { 1046 case ADW_CHIP_ASC3550: 1047 mcode_data = (const u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1048 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1049 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1050 adw_memsize = ADW_3550_MEMSIZE; 1051 break; 1052 1053 case ADW_CHIP_ASC38C0800: 1054 mcode_data = (const u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1055 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1056 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1057 adw_memsize = ADW_38C0800_MEMSIZE; 1058 break; 1059 1060 case ADW_CHIP_ASC38C1600: 1061 mcode_data = (const u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1062 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1063 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1064 adw_memsize = ADW_38C1600_MEMSIZE; 1065 break; 1066 1067 default: 1068 return (EINVAL); 1069 } 1070 1071 /* 1072 * Write the microcode image to RISC memory starting at address 0. 1073 */ 1074 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1075 1076 /* Assume the following compressed format of the microcode buffer: 1077 * 1078 * 254 word (508 byte) table indexed by byte code followed 1079 * by the following byte codes: 1080 * 1081 * 1-Byte Code: 1082 * 00: Emit word 0 in table. 1083 * 01: Emit word 1 in table. 1084 * . 1085 * FD: Emit word 253 in table. 1086 * 1087 * Multi-Byte Code: 1088 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1089 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1090 */ 1091 word = 0; 1092 for (i = 253 * 2; i < mcode_size; i++) { 1093 if (mcode_data[i] == 0xff) { 1094 for (j = 0; j < mcode_data[i + 1]; j++) { 1095 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1096 (((u_int16_t)mcode_data[i + 3] << 8) | 1097 mcode_data[i + 2])); 1098 word++; 1099 } 1100 i += 3; 1101 } else if (mcode_data[i] == 0xfe) { 1102 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1103 (((u_int16_t)mcode_data[i + 2] << 8) | 1104 mcode_data[i + 1])); 1105 i += 2; 1106 word++; 1107 } else { 1108 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1109 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1110 mcode_data[mcode_data[i] * 2])); 1111 word++; 1112 } 1113 } 1114 1115 /* 1116 * Set 'word' for later use to clear the rest of memory and save 1117 * the expanded mcode size. 1118 */ 1119 word *= 2; 1120 adw_mcode_expanded_size = word; 1121 1122 /* 1123 * Clear the rest of the Internal RAM. 1124 */ 1125 for (; word < adw_memsize; word += 2) { 1126 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1127 } 1128 1129 /* 1130 * Verify the microcode checksum. 1131 */ 1132 sum = 0; 1133 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1134 1135 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1136 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1137 } 1138 1139 if (sum != mcode_chksum) { 1140 return ADW_IERR_MCODE_CHKSUM; 1141 } 1142 1143 /* 1144 * Restore the RISC memory BIOS region. 1145 */ 1146 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1147 if(chip_type == ADW_CHIP_ASC3550) { 1148 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1149 bios_mem[i]); 1150 } else { 1151 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1152 bios_mem[i]); 1153 } 1154 } 1155 1156 /* 1157 * Calculate and write the microcode code checksum to the microcode 1158 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1159 */ 1160 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1161 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1162 code_sum = 0; 1163 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1164 for (word = begin_addr; word < end_addr; word += 2) { 1165 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1166 } 1167 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1168 1169 /* 1170 * Set the chip type. 1171 */ 1172 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1173 1174 return 0; 1175 } 1176 1177 1178 int 1179 AdwASC3550Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1180 { 1181 u_int16_t scsi_cfg1; 1182 1183 1184 /* 1185 * Determine SCSI_CFG1 Microcode Default Value. 1186 * 1187 * The microcode will set the SCSI_CFG1 register using this value 1188 * after it is started below. 1189 */ 1190 1191 /* Read current SCSI_CFG1 Register value. */ 1192 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1193 1194 /* 1195 * If all three connectors are in use in ASC3550, return an error. 1196 */ 1197 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1198 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1199 return ADW_IERR_ILLEGAL_CONNECTION; 1200 } 1201 1202 /* 1203 * If the cable is reversed all of the SCSI_CTRL register signals 1204 * will be set. Check for and return an error if this condition is 1205 * found. 1206 */ 1207 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1208 return ADW_IERR_REVERSED_CABLE; 1209 } 1210 1211 /* 1212 * If this is a differential board and a single-ended device 1213 * is attached to one of the connectors, return an error. 1214 */ 1215 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1216 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1217 return ADW_IERR_SINGLE_END_DEVICE; 1218 } 1219 1220 /* 1221 * If automatic termination control is enabled, then set the 1222 * termination value based on a table listed in a_condor.h. 1223 * 1224 * If manual termination was specified with an EEPROM setting 1225 * then 'termination' was set-up in AdwInitFromEEPROM() and 1226 * is ready to be 'ored' into SCSI_CFG1. 1227 */ 1228 if (cfg->termination == 0) { 1229 /* 1230 * The software always controls termination by setting 1231 * TERM_CTL_SEL. 1232 * If TERM_CTL_SEL were set to 0, the hardware would set 1233 * termination. 1234 */ 1235 cfg->termination |= ADW_TERM_CTL_SEL; 1236 1237 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1238 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1239 case 0x3: case 0x7: case 0xB: 1240 case 0xD: case 0xE: case 0xF: 1241 cfg->termination |= 1242 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1243 break; 1244 1245 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1246 case 0x1: case 0x5: case 0x9: 1247 case 0xA: case 0xC: 1248 cfg->termination |= ADW_TERM_CTL_H; 1249 break; 1250 1251 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1252 case 0x2: case 0x6: 1253 break; 1254 } 1255 } 1256 1257 /* 1258 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1259 */ 1260 scsi_cfg1 &= ~ADW_TERM_CTL; 1261 1262 /* 1263 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1264 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1265 * referenced, because the hardware internally inverts 1266 * the Termination High and Low bits if TERM_POL is set. 1267 */ 1268 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1269 1270 /* 1271 * Set SCSI_CFG1 Microcode Default Value 1272 * 1273 * Set filter value and possibly modified termination control 1274 * bits in the Microcode SCSI_CFG1 Register Value. 1275 * 1276 * The microcode will set the SCSI_CFG1 register using this value 1277 * after it is started below. 1278 */ 1279 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1280 ADW_FLTR_DISABLE | scsi_cfg1); 1281 1282 /* 1283 * Set MEM_CFG Microcode Default Value 1284 * 1285 * The microcode will set the MEM_CFG register using this value 1286 * after it is started below. 1287 * 1288 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1289 * are defined. 1290 * 1291 * ASC-3550 has 8KB internal memory. 1292 */ 1293 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1294 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1295 1296 return 0; 1297 } 1298 1299 1300 int 1301 AdwASC38C0800Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1302 { 1303 u_int16_t scsi_cfg1; 1304 1305 1306 /* 1307 * Determine SCSI_CFG1 Microcode Default Value. 1308 * 1309 * The microcode will set the SCSI_CFG1 register using this value 1310 * after it is started below. 1311 */ 1312 1313 /* Read current SCSI_CFG1 Register value. */ 1314 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1315 1316 /* 1317 * If the cable is reversed all of the SCSI_CTRL register signals 1318 * will be set. Check for and return an error if this condition is 1319 * found. 1320 */ 1321 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1322 return ADW_IERR_REVERSED_CABLE; 1323 } 1324 1325 /* 1326 * All kind of combinations of devices attached to one of four 1327 * connectors are acceptable except HVD device attached. 1328 * For example, LVD device can be attached to SE connector while 1329 * SE device attached to LVD connector. 1330 * If LVD device attached to SE connector, it only runs up to 1331 * Ultra speed. 1332 * 1333 * If an HVD device is attached to one of LVD connectors, return 1334 * an error. 1335 * However, there is no way to detect HVD device attached to 1336 * SE connectors. 1337 */ 1338 if (scsi_cfg1 & ADW_HVD) { 1339 return ADW_IERR_HVD_DEVICE; 1340 } 1341 1342 /* 1343 * If either SE or LVD automatic termination control is enabled, then 1344 * set the termination value based on a table listed in a_condor.h. 1345 * 1346 * If manual termination was specified with an EEPROM setting then 1347 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1348 * to be 'ored' into SCSI_CFG1. 1349 */ 1350 if ((cfg->termination & ADW_TERM_SE) == 0) { 1351 /* SE automatic termination control is enabled. */ 1352 switch(scsi_cfg1 & ADW_C_DET_SE) { 1353 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1354 case 0x1: case 0x2: case 0x3: 1355 cfg->termination |= ADW_TERM_SE; 1356 break; 1357 1358 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1359 case 0x0: 1360 cfg->termination |= ADW_TERM_SE_HI; 1361 break; 1362 } 1363 } 1364 1365 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1366 /* LVD automatic termination control is enabled. */ 1367 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1368 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1369 case 0x4: case 0x8: case 0xC: 1370 cfg->termination |= ADW_TERM_LVD; 1371 break; 1372 1373 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1374 case 0x0: 1375 break; 1376 } 1377 } 1378 1379 /* 1380 * Clear any set TERM_SE and TERM_LVD bits. 1381 */ 1382 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1383 1384 /* 1385 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1386 */ 1387 scsi_cfg1 |= (~cfg->termination & 0xF0); 1388 1389 /* 1390 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1391 * HVD/LVD/SE bits and set possibly modified termination control bits 1392 * in the Microcode SCSI_CFG1 Register Value. 1393 */ 1394 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1395 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1396 1397 /* 1398 * Set SCSI_CFG1 Microcode Default Value 1399 * 1400 * Set possibly modified termination control and reset DIS_TERM_DRV 1401 * bits in the Microcode SCSI_CFG1 Register Value. 1402 * 1403 * The microcode will set the SCSI_CFG1 register using this value 1404 * after it is started below. 1405 */ 1406 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1407 1408 /* 1409 * Set MEM_CFG Microcode Default Value 1410 * 1411 * The microcode will set the MEM_CFG register using this value 1412 * after it is started below. 1413 * 1414 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1415 * are defined. 1416 * 1417 * ASC-38C0800 has 16KB internal memory. 1418 */ 1419 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1420 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1421 1422 return 0; 1423 } 1424 1425 1426 int 1427 AdwASC38C1600Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1428 { 1429 u_int16_t scsi_cfg1; 1430 1431 1432 /* 1433 * Determine SCSI_CFG1 Microcode Default Value. 1434 * 1435 * The microcode will set the SCSI_CFG1 register using this value 1436 * after it is started below. 1437 * Each ASC-38C1600 function has only two cable detect bits. 1438 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1439 */ 1440 1441 /* Read current SCSI_CFG1 Register value. */ 1442 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1443 1444 /* 1445 * If the cable is reversed all of the SCSI_CTRL register signals 1446 * will be set. Check for and return an error if this condition is 1447 * found. 1448 */ 1449 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1450 return ADW_IERR_REVERSED_CABLE; 1451 } 1452 1453 /* 1454 * Each ASC-38C1600 function has two connectors. Only an HVD device 1455 * cannot be connected to either connector. An LVD device or SE device 1456 * may be connected to either connector. If an SE device is connected, 1457 * then at most Ultra speed (20 MHz) can be used on both connectors. 1458 * 1459 * If an HVD device is attached, return an error. 1460 */ 1461 if (scsi_cfg1 & ADW_HVD) { 1462 return ADW_IERR_HVD_DEVICE; 1463 } 1464 1465 /* 1466 * Each function in the ASC-38C1600 uses only the SE cable detect and 1467 * termination because there are two connectors for each function. 1468 * Each function may use either LVD or SE mode. 1469 * Corresponding the SE automatic termination control EEPROM bits are 1470 * used for each function. 1471 * Each function has its own EEPROM. If SE automatic control is enabled 1472 * for the function, then set the termination value based on a table 1473 * listed in adwlib.h. 1474 * 1475 * If manual termination is specified in the EEPROM for the function, 1476 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1477 * ready to be 'ored' into SCSI_CFG1. 1478 */ 1479 if ((cfg->termination & ADW_TERM_SE) == 0) { 1480 /* SE automatic termination control is enabled. */ 1481 switch(scsi_cfg1 & ADW_C_DET_SE) { 1482 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1483 case 0x1: case 0x2: case 0x3: 1484 cfg->termination |= ADW_TERM_SE; 1485 break; 1486 1487 case 0x0: 1488 #if 0 1489 /* !!!!TODO!!!! */ 1490 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1491 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1492 } 1493 else 1494 #endif 1495 { 1496 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1497 cfg->termination |= ADW_TERM_SE_HI; 1498 } 1499 break; 1500 } 1501 } 1502 1503 /* 1504 * Clear any set TERM_SE bits. 1505 */ 1506 scsi_cfg1 &= ~ADW_TERM_SE; 1507 1508 /* 1509 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1510 */ 1511 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1512 1513 /* 1514 * Clear Big Endian and Terminator Polarity bits and set possibly 1515 * modified termination control bits in the Microcode SCSI_CFG1 1516 * Register Value. 1517 */ 1518 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1519 1520 /* 1521 * Set SCSI_CFG1 Microcode Default Value 1522 * 1523 * Set possibly modified termination control bits in the Microcode 1524 * SCSI_CFG1 Register Value. 1525 * 1526 * The microcode will set the SCSI_CFG1 register using this value 1527 * after it is started below. 1528 */ 1529 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1530 1531 /* 1532 * Set MEM_CFG Microcode Default Value 1533 * 1534 * The microcode will set the MEM_CFG register using this value 1535 * after it is started below. 1536 * 1537 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1538 * are defined. 1539 * 1540 * ASC-38C1600 has 32KB internal memory. 1541 */ 1542 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1543 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1544 1545 return 0; 1546 } 1547 1548 1549 /* 1550 * Read EEPROM configuration into the specified buffer. 1551 * 1552 * Return a checksum based on the EEPROM configuration read. 1553 */ 1554 static u_int16_t 1555 AdwGetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1556 { 1557 u_int16_t wval, chksum; 1558 u_int16_t *wbuf; 1559 int eep_addr; 1560 1561 1562 wbuf = (u_int16_t *) cfg_buf; 1563 chksum = 0; 1564 1565 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1566 eep_addr < ASC_EEP_DVC_CFG_END; 1567 eep_addr++, wbuf++) { 1568 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1569 chksum += wval; 1570 *wbuf = wval; 1571 } 1572 1573 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1574 wbuf++; 1575 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1576 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1577 eep_addr++, wbuf++) { 1578 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1579 } 1580 1581 return chksum; 1582 } 1583 1584 1585 /* 1586 * Read the EEPROM from specified location 1587 */ 1588 static u_int16_t 1589 AdwReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, int eep_word_addr) 1590 { 1591 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1592 ASC_EEP_CMD_READ | eep_word_addr); 1593 AdwWaitEEPCmd(iot, ioh); 1594 1595 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1596 } 1597 1598 1599 /* 1600 * Wait for EEPROM command to complete 1601 */ 1602 static void 1603 AdwWaitEEPCmd(bus_space_tag_t iot, bus_space_handle_t ioh) 1604 { 1605 int eep_delay_ms; 1606 1607 1608 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1609 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1610 ASC_EEP_CMD_DONE) { 1611 break; 1612 } 1613 AdwSleepMilliSecond(1); 1614 } 1615 1616 (void)ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1617 } 1618 1619 1620 /* 1621 * Write the EEPROM from 'cfg_buf'. 1622 */ 1623 static void 1624 AdwSetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1625 { 1626 u_int16_t *wbuf; 1627 u_int16_t addr, chksum; 1628 1629 1630 wbuf = (u_int16_t *) cfg_buf; 1631 chksum = 0; 1632 1633 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1634 AdwWaitEEPCmd(iot, ioh); 1635 1636 /* 1637 * Write EEPROM from word 0 to word 20 1638 */ 1639 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1640 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1641 chksum += *wbuf; 1642 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1643 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1644 ASC_EEP_CMD_WRITE | addr); 1645 AdwWaitEEPCmd(iot, ioh); 1646 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1647 } 1648 1649 /* 1650 * Write EEPROM checksum at word 21 1651 */ 1652 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1653 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1654 ASC_EEP_CMD_WRITE | addr); 1655 AdwWaitEEPCmd(iot, ioh); 1656 wbuf++; /* skip over check_sum */ 1657 1658 /* 1659 * Write EEPROM OEM name at words 22 to 29 1660 */ 1661 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1662 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1663 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1664 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1665 ASC_EEP_CMD_WRITE | addr); 1666 AdwWaitEEPCmd(iot, ioh); 1667 } 1668 1669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1670 ASC_EEP_CMD_WRITE_DISABLE); 1671 AdwWaitEEPCmd(iot, ioh); 1672 1673 return; 1674 } 1675 1676 1677 /* 1678 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1679 * 1680 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1681 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1682 * RISC to notify it a new command is ready to be executed. 1683 * 1684 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1685 * set to SCSI_MAX_RETRY. 1686 * 1687 * Return: 1688 * ADW_SUCCESS(1) - The request was successfully queued. 1689 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1690 * request completes. 1691 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1692 * host IC error. 1693 */ 1694 int 1695 AdwExeScsiQueue(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 1696 { 1697 bus_space_tag_t iot = sc->sc_iot; 1698 bus_space_handle_t ioh = sc->sc_ioh; 1699 ADW_CCB *ccb; 1700 u_int32_t req_paddr; 1701 ADW_CARRIER *new_carrp; 1702 1703 /* 1704 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1705 */ 1706 if (scsiq->target_id > ADW_MAX_TID) { 1707 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1708 scsiq->done_status = QD_WITH_ERROR; 1709 return ADW_ERROR; 1710 } 1711 1712 /* 1713 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1714 */ 1715 1716 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1717 1718 /* 1719 * Allocate a carrier and initialize fields. 1720 */ 1721 if ((new_carrp = sc->carr_freelist) == NULL) { 1722 return ADW_BUSY; 1723 } 1724 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1725 ASC_GET_CARRP(new_carrp->next_ba)); 1726 sc->carr_pending_cnt++; 1727 1728 /* 1729 * Set the carrier to be a stopper by setting 'next_ba' 1730 * to the stopper value. The current stopper will be changed 1731 * below to point to the new stopper. 1732 */ 1733 new_carrp->next_ba = htole32(ASC_CQ_STOPPER); 1734 1735 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1736 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1737 1738 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1739 scsiq->scsiq_rptr = htole32(req_paddr); 1740 1741 /* 1742 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1743 * order during initialization. 1744 */ 1745 scsiq->carr_ba = sc->icq_sp->carr_ba; 1746 scsiq->carr_va = sc->icq_sp->carr_ba; 1747 1748 /* 1749 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1750 * the microcode. The newly allocated stopper will become the new 1751 * stopper. 1752 */ 1753 sc->icq_sp->areq_ba = htole32(req_paddr); 1754 1755 /* 1756 * Set the 'next_ba' pointer for the old stopper to be the 1757 * physical address of the new stopper. The RISC can only 1758 * follow physical addresses. 1759 */ 1760 sc->icq_sp->next_ba = new_carrp->carr_ba; 1761 1762 #if ADW_DEBUG 1763 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1764 sc->icq_sp->carr_id, 1765 sc->icq_sp->carr_ba, 1766 sc->icq_sp->areq_ba, 1767 sc->icq_sp->next_ba); 1768 #endif 1769 /* 1770 * Set the host adapter stopper pointer to point to the new carrier. 1771 */ 1772 sc->icq_sp = new_carrp; 1773 1774 if (sc->chip_type == ADW_CHIP_ASC3550 || 1775 sc->chip_type == ADW_CHIP_ASC38C0800) { 1776 /* 1777 * Tickle the RISC to tell it to read its Command Queue Head 1778 * pointer. 1779 */ 1780 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1781 if (sc->chip_type == ADW_CHIP_ASC3550) { 1782 /* 1783 * Clear the tickle value. In the ASC-3550 the RISC flag 1784 * command 'clr_tickle_a' does not work unless the host 1785 * value is cleared. 1786 */ 1787 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1788 ADW_TICKLE_NOP); 1789 } 1790 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1791 /* 1792 * Notify the RISC a carrier is ready by writing the physical 1793 * address of the new carrier stopper to the COMMA register. 1794 */ 1795 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1796 le32toh(new_carrp->carr_ba)); 1797 } 1798 1799 /* 1800 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1801 */ 1802 1803 return ADW_SUCCESS; 1804 } 1805 1806 1807 void 1808 AdwResetChip(bus_space_tag_t iot, bus_space_handle_t ioh) 1809 { 1810 1811 /* 1812 * Reset Chip. 1813 */ 1814 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1815 ADW_CTRL_REG_CMD_RESET); 1816 AdwSleepMilliSecond(100); 1817 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1818 ADW_CTRL_REG_CMD_WR_IO_REG); 1819 } 1820 1821 1822 /* 1823 * Reset SCSI Bus and purge all outstanding requests. 1824 * 1825 * Return Value: 1826 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1827 * ADW_FALSE(0) - Microcode command failed. 1828 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1829 * may be hung which requires driver recovery. 1830 */ 1831 int 1832 AdwResetCCB(ADW_SOFTC *sc) 1833 { 1834 int status; 1835 1836 /* 1837 * Send the SCSI Bus Reset idle start idle command which asserts 1838 * the SCSI Bus Reset signal. 1839 */ 1840 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1841 if (status != ADW_TRUE) { 1842 return status; 1843 } 1844 1845 /* 1846 * Delay for the specified SCSI Bus Reset hold time. 1847 * 1848 * The hold time delay is done on the host because the RISC has no 1849 * microsecond accurate timer. 1850 */ 1851 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1852 1853 /* 1854 * Send the SCSI Bus Reset end idle command which de-asserts 1855 * the SCSI Bus Reset signal and purges any pending requests. 1856 */ 1857 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1858 if (status != ADW_TRUE) { 1859 return status; 1860 } 1861 1862 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1863 1864 return status; 1865 } 1866 1867 1868 /* 1869 * Reset chip and SCSI Bus. 1870 * 1871 * Return Value: 1872 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1873 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1874 */ 1875 int 1876 AdwResetSCSIBus(ADW_SOFTC *sc) 1877 { 1878 bus_space_tag_t iot = sc->sc_iot; 1879 bus_space_handle_t ioh = sc->sc_ioh; 1880 int status; 1881 u_int16_t wdtr_able, sdtr_able, tagqng_able; 1882 u_int16_t ppr_able = 0; /* XXX: gcc */ 1883 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1884 u_int16_t bios_sig; 1885 1886 1887 /* 1888 * Save current per TID negotiated values. 1889 */ 1890 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1891 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1892 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1893 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1894 } 1895 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1896 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1897 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1898 max_cmd[tid]); 1899 } 1900 1901 /* 1902 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1903 * by clearing the BIOS signature word. 1904 * The initialization functions assumes a SCSI Bus Reset is not 1905 * needed if the BIOS signature word is present. 1906 */ 1907 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1908 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1909 1910 /* 1911 * Stop chip and reset it. 1912 */ 1913 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1914 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1915 ADW_CTRL_REG_CMD_RESET); 1916 AdwSleepMilliSecond(100); 1917 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1918 ADW_CTRL_REG_CMD_WR_IO_REG); 1919 1920 /* 1921 * Reset Adv Library error code, if any, and try 1922 * re-initializing the chip. 1923 * Then translate initialization return value to status value. 1924 */ 1925 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1926 1927 /* 1928 * Restore the BIOS signature word. 1929 */ 1930 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1931 1932 /* 1933 * Restore per TID negotiated values. 1934 */ 1935 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1936 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1937 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1938 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1939 } 1940 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1941 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1942 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1943 max_cmd[tid]); 1944 } 1945 1946 return status; 1947 } 1948 1949 1950 /* 1951 * Adv Library Interrupt Service Routine 1952 * 1953 * This function is called by a driver's interrupt service routine. 1954 * The function disables and re-enables interrupts. 1955 * 1956 * When a microcode idle command is completed, the ADV_DVC_VAR 1957 * 'idle_cmd_done' field is set to ADW_TRUE. 1958 * 1959 * Note: AdwISR() can be called when interrupts are disabled or even 1960 * when there is no hardware interrupt condition present. It will 1961 * always check for completed idle commands and microcode requests. 1962 * This is an important feature that shouldn't be changed because it 1963 * allows commands to be completed from polling mode loops. 1964 * 1965 * Return: 1966 * ADW_TRUE(1) - interrupt was pending 1967 * ADW_FALSE(0) - no interrupt was pending 1968 */ 1969 int 1970 AdwISR(ADW_SOFTC *sc) 1971 { 1972 bus_space_tag_t iot = sc->sc_iot; 1973 bus_space_handle_t ioh = sc->sc_ioh; 1974 u_int8_t int_stat; 1975 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 1976 u_int32_t irq_next_pa; 1977 ADW_SCSI_REQ_Q *scsiq; 1978 ADW_CCB *ccb; 1979 int s; 1980 1981 1982 s = splbio(); 1983 1984 /* Reading the register clears the interrupt. */ 1985 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 1986 1987 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 1988 ADW_INTR_STATUS_INTRC)) == 0) { 1989 splx(s); 1990 return ADW_FALSE; 1991 } 1992 1993 /* 1994 * Notify the driver of an asynchronous microcode condition by 1995 * calling the ADV_DVC_VAR.async_callback function. The function 1996 * is passed the microcode ADW_MC_INTRB_CODE byte value. 1997 */ 1998 if (int_stat & ADW_INTR_STATUS_INTRB) { 1999 u_int8_t intrb_code; 2000 2001 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2002 2003 if (sc->chip_type == ADW_CHIP_ASC3550 || 2004 sc->chip_type == ADW_CHIP_ASC38C0800) { 2005 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2006 sc->carr_pending_cnt != 0) { 2007 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2008 IOPB_TICKLE, ADW_TICKLE_A); 2009 if (sc->chip_type == ADW_CHIP_ASC3550) { 2010 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2011 IOPB_TICKLE, ADW_TICKLE_NOP); 2012 } 2013 } 2014 } 2015 2016 if (sc->async_callback != 0) { 2017 (*sc->async_callback)(sc, intrb_code); 2018 } 2019 } 2020 2021 /* 2022 * Check if the IRQ stopper carrier contains a completed request. 2023 */ 2024 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0) 2025 { 2026 #if ADW_DEBUG 2027 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2028 sc->irq_sp->carr_id, 2029 sc->irq_sp->carr_ba, 2030 sc->irq_sp->areq_ba, 2031 sc->irq_sp->next_ba); 2032 #endif 2033 /* 2034 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2035 * structure. 2036 * The RISC will have set 'areq_ba' to a virtual address. 2037 * 2038 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2039 * field to the carrier ADV_CARR_T.areq_ba field. 2040 * The conversion below complements the conversion of 2041 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2042 */ 2043 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2044 scsiq = &ccb->scsiq; 2045 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2046 2047 /* 2048 * Request finished with good status and the queue was not 2049 * DMAed to host memory by the firmware. Set all status fields 2050 * to indicate good status. 2051 */ 2052 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) { 2053 scsiq->done_status = QD_NO_ERROR; 2054 scsiq->host_status = scsiq->scsi_status = 0; 2055 scsiq->data_cnt = 0L; 2056 } 2057 2058 /* 2059 * Advance the stopper pointer to the next carrier 2060 * ignoring the lower four bits. Free the previous 2061 * stopper carrier. 2062 */ 2063 free_carrp = sc->irq_sp; 2064 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2065 2066 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0 2067 : sc->carr_freelist->carr_ba; 2068 sc->carr_freelist = free_carrp; 2069 sc->carr_pending_cnt--; 2070 2071 /* 2072 * Clear request microcode control flag. 2073 */ 2074 scsiq->cntl = 0; 2075 2076 /* 2077 * Check Condition handling 2078 */ 2079 /* 2080 * If the command that completed was a SCSI INQUIRY and 2081 * LUN 0 was sent the command, then process the INQUIRY 2082 * command information for the device. 2083 */ 2084 if (scsiq->done_status == QD_NO_ERROR && 2085 scsiq->cdb[0] == INQUIRY && 2086 scsiq->target_lun == 0) { 2087 AdwInquiryHandling(sc, scsiq); 2088 } 2089 2090 /* 2091 * Notify the driver of the completed request by passing 2092 * the ADW_SCSI_REQ_Q pointer to its callback function. 2093 */ 2094 (*sc->isr_callback)(sc, scsiq); 2095 /* 2096 * Note: After the driver callback function is called, 'scsiq' 2097 * can no longer be referenced. 2098 * 2099 * Fall through and continue processing other completed 2100 * requests... 2101 */ 2102 } 2103 2104 splx(s); 2105 2106 return ADW_TRUE; 2107 } 2108 2109 2110 /* 2111 * Send an idle command to the chip and wait for completion. 2112 * 2113 * Command completion is polled for once per microsecond. 2114 * 2115 * The function can be called from anywhere including an interrupt handler. 2116 * But the function is not re-entrant, so it uses the splbio/splx() 2117 * functions to prevent reentrancy. 2118 * 2119 * Return Values: 2120 * ADW_TRUE - command completed successfully 2121 * ADW_FALSE - command failed 2122 * ADW_ERROR - command timed out 2123 */ 2124 int 2125 AdwSendIdleCmd(ADW_SOFTC *sc, u_int16_t idle_cmd, u_int32_t idle_cmd_parameter) 2126 { 2127 bus_space_tag_t iot = sc->sc_iot; 2128 bus_space_handle_t ioh = sc->sc_ioh; 2129 u_int16_t result; 2130 u_int32_t i, j, s; 2131 2132 s = splbio(); 2133 2134 /* 2135 * Clear the idle command status which is set by the microcode 2136 * to a non-zero value to indicate when the command is completed. 2137 */ 2138 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2139 2140 /* 2141 * Write the idle command value after the idle command parameter 2142 * has been written to avoid a race condition. If the order is not 2143 * followed, the microcode may process the idle command before the 2144 * parameters have been written to LRAM. 2145 */ 2146 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2147 idle_cmd_parameter); 2148 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2149 2150 /* 2151 * Tickle the RISC to tell it to process the idle command. 2152 */ 2153 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2154 if (sc->chip_type == ADW_CHIP_ASC3550) { 2155 /* 2156 * Clear the tickle value. In the ASC-3550 the RISC flag 2157 * command 'clr_tickle_b' does not work unless the host 2158 * value is cleared. 2159 */ 2160 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2161 } 2162 2163 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2164 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2165 /* Poll once each microsecond for command completion. */ 2166 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2167 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2168 result); 2169 if (result != 0) { 2170 splx(s); 2171 return result; 2172 } 2173 AdwDelayMicroSecond(1); 2174 } 2175 } 2176 2177 splx(s); 2178 return ADW_ERROR; 2179 } 2180 2181 2182 /* 2183 * Inquiry Information Byte 7 Handling 2184 * 2185 * Handle SCSI Inquiry Command information for a device by setting 2186 * microcode operating variables that affect WDTR, SDTR, and Tag 2187 * Queuing. 2188 */ 2189 static void 2190 AdwInquiryHandling(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 2191 { 2192 #ifndef FAILSAFE 2193 bus_space_tag_t iot = sc->sc_iot; 2194 bus_space_handle_t ioh = sc->sc_ioh; 2195 u_int8_t tid; 2196 struct scsipi_inquiry_data *inq; 2197 u_int16_t tidmask; 2198 u_int16_t cfg_word; 2199 2200 2201 /* 2202 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2203 * to be available. 2204 * 2205 * If less than 8 bytes of INQUIRY information were requested or less 2206 * than 8 bytes were transferred, then return. cdb[4] is the request 2207 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2208 * microcode to the transfer residual count. 2209 */ 2210 2211 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2212 return; 2213 } 2214 2215 tid = scsiq->target_id; 2216 2217 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2218 2219 /* 2220 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2221 */ 2222 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2223 ((inq->version & SID_ANSII) < 2)) { 2224 return; 2225 } else { 2226 /* 2227 * INQUIRY Byte 7 Handling 2228 * 2229 * Use a device's INQUIRY byte 7 to determine whether it 2230 * supports WDTR, SDTR, and Tag Queuing. If the feature 2231 * is enabled in the EEPROM and the device supports the 2232 * feature, then enable it in the microcode. 2233 */ 2234 2235 tidmask = ADW_TID_TO_TIDMASK(tid); 2236 2237 /* 2238 * Wide Transfers 2239 * 2240 * If the EEPROM enabled WDTR for the device and the device 2241 * supports wide bus (16 bit) transfers, then turn on the 2242 * device's 'wdtr_able' bit and write the new value to the 2243 * microcode. 2244 */ 2245 #ifdef SCSI_ADW_WDTR_DISABLE 2246 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2247 #endif /* SCSI_ADW_WDTR_DISABLE */ 2248 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2249 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2250 cfg_word); 2251 if ((cfg_word & tidmask) == 0) { 2252 cfg_word |= tidmask; 2253 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2254 cfg_word); 2255 2256 /* 2257 * Clear the microcode "SDTR negotiation" and 2258 * "WDTR negotiation" done indicators for the 2259 * target to cause it to negotiate with the new 2260 * setting set above. 2261 * WDTR when accepted causes the target to enter 2262 * asynchronous mode, so SDTR must be negotiated 2263 */ 2264 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2265 cfg_word); 2266 cfg_word &= ~tidmask; 2267 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2268 cfg_word); 2269 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2270 cfg_word); 2271 cfg_word &= ~tidmask; 2272 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2273 cfg_word); 2274 } 2275 } 2276 2277 /* 2278 * Synchronous Transfers 2279 * 2280 * If the EEPROM enabled SDTR for the device and the device 2281 * supports synchronous transfers, then turn on the device's 2282 * 'sdtr_able' bit. Write the new value to the microcode. 2283 */ 2284 #ifdef SCSI_ADW_SDTR_DISABLE 2285 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2286 #endif /* SCSI_ADW_SDTR_DISABLE */ 2287 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2288 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2289 if ((cfg_word & tidmask) == 0) { 2290 cfg_word |= tidmask; 2291 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2292 cfg_word); 2293 2294 /* 2295 * Clear the microcode "SDTR negotiation" 2296 * done indicator for the target to cause it 2297 * to negotiate with the new setting set above. 2298 */ 2299 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2300 cfg_word); 2301 cfg_word &= ~tidmask; 2302 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2303 cfg_word); 2304 } 2305 } 2306 /* 2307 * If the Inquiry data included enough space for the SPI-3 2308 * Clocking field, then check if DT mode is supported. 2309 */ 2310 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2311 (scsiq->cdb[4] >= 57 || 2312 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2313 /* 2314 * PPR (Parallel Protocol Request) Capable 2315 * 2316 * If the device supports DT mode, then it must be 2317 * PPR capable. 2318 * The PPR message will be used in place of the SDTR 2319 * and WDTR messages to negotiate synchronous speed 2320 * and offset, transfer width, and protocol options. 2321 */ 2322 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2323 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2324 sc->ppr_able); 2325 sc->ppr_able |= tidmask; 2326 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2327 sc->ppr_able); 2328 } 2329 } 2330 2331 /* 2332 * If the EEPROM enabled Tag Queuing for the device and the 2333 * device supports Tag Queueing, then turn on the device's 2334 * 'tagqng_enable' bit in the microcode and set the microcode 2335 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2336 * value. 2337 * 2338 * Tag Queuing is disabled for the BIOS which runs in polled 2339 * mode and would see no benefit from Tag Queuing. Also by 2340 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2341 * bugs will at least work with the BIOS. 2342 */ 2343 #ifdef SCSI_ADW_TAGQ_DISABLE 2344 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2345 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2346 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2347 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2348 cfg_word); 2349 cfg_word |= tidmask; 2350 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2351 cfg_word); 2352 2353 ADW_WRITE_BYTE_LRAM(iot, ioh, 2354 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2355 sc->max_dvc_qng); 2356 } 2357 } 2358 #endif /* FAILSAFE */ 2359 } 2360 2361 2362 static void 2363 AdwSleepMilliSecond(u_int32_t n) 2364 { 2365 2366 DELAY(n * 1000); 2367 } 2368 2369 2370 static void 2371 AdwDelayMicroSecond(u_int32_t n) 2372 { 2373 2374 DELAY(n); 2375 } 2376 2377
Indexes created Mon Oct 20 01:09:56 GMT 2025