adwlib.c revision 1.9
1 /* $NetBSD: adwlib.c,v 1.9 2000/02/04 16:23:14 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1999 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_param.h> 73 #include <vm/pmap.h> 74 75 #include <dev/ic/adwlib.h> 76 #include <dev/ic/adw.h> 77 #include <dev/ic/adwmcode.h> 78 79 80 /* Static Functions */ 81 82 static u_int16_t AdvGet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 83 ADW_EEP_3550_CONFIG *)); 84 static u_int16_t AdvGet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_EEP_38C0800_CONFIG *)); 86 static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 87 static void AdvWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 88 static void AdvSet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 89 ADW_EEP_3550_CONFIG *)); 90 static void AdvSet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, 91 ADW_EEP_38C0800_CONFIG *)); 92 static void AdvInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 93 94 static void AdvSleepMilliSecond __P((u_int32_t)); 95 static void AdvDelayMicroSecond __P((u_int32_t)); 96 97 98 /* 99 * EEPROM Configuration. 100 * 101 * All drivers should use this structure to set the default EEPROM 102 * configuration. The BIOS now uses this structure when it is built. 103 * Additional structure information can be found in advlib.h where 104 * the structure is defined. 105 */ 106 static ADW_EEP_3550_CONFIG 107 Default_3550_EEPROM_Config = { 108 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 109 0x0000, /* cfg_msw */ 110 0xFFFF, /* disc_enable */ 111 0xFFFF, /* wdtr_able */ 112 0xFFFF, /* sdtr_able */ 113 0xFFFF, /* start_motor */ 114 0xFFFF, /* tagqng_able */ 115 0xFFFF, /* bios_scan */ 116 0, /* scam_tolerant */ 117 7, /* adapter_scsi_id */ 118 0, /* bios_boot_delay */ 119 3, /* scsi_reset_delay */ 120 0, /* bios_id_lun */ 121 0, /* termination */ 122 0, /* reserved1 */ 123 0xFFE7, /* bios_ctrl */ 124 0xFFFF, /* ultra_able */ 125 0, /* reserved2 */ 126 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 127 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 128 0, /* dvc_cntl */ 129 0, /* bug_fix */ 130 0, /* serial_number_word1 */ 131 0, /* serial_number_word2 */ 132 0, /* serial_number_word3 */ 133 0, /* check_sum */ 134 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* oem_name[16] */ 135 0, /* dvc_err_code */ 136 0, /* adv_err_code */ 137 0, /* adv_err_addr */ 138 0, /* saved_dvc_err_code */ 139 0, /* saved_adv_err_code */ 140 0, /* saved_adv_err_addr */ 141 0 /* num_of_err */ 142 }; 143 144 static ADW_EEP_38C0800_CONFIG 145 Default_38C0800_EEPROM_Config = { 146 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 147 0x0000, /* 01 cfg_msw */ 148 0xFFFF, /* 02 disc_enable */ 149 0xFFFF, /* 03 wdtr_able */ 150 0x4444, /* 04 sdtr_speed1 */ 151 0xFFFF, /* 05 start_motor */ 152 0xFFFF, /* 06 tagqng_able */ 153 0xFFFF, /* 07 bios_scan */ 154 0, /* 08 scam_tolerant */ 155 7, /* 09 adapter_scsi_id */ 156 0, /* bios_boot_delay */ 157 3, /* 10 scsi_reset_delay */ 158 0, /* bios_id_lun */ 159 0, /* 11 termination_se */ 160 0, /* termination_lvd */ 161 0xFFE7, /* 12 bios_ctrl */ 162 0x4444, /* 13 sdtr_speed2 */ 163 0x4444, /* 14 sdtr_speed3 */ 164 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 165 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 166 0, /* 16 dvc_cntl */ 167 0x4444, /* 17 sdtr_speed4 */ 168 0, /* 18 serial_number_word1 */ 169 0, /* 19 serial_number_word2 */ 170 0, /* 20 serial_number_word3 */ 171 0, /* 21 check_sum */ 172 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ 173 0, /* 30 dvc_err_code */ 174 0, /* 31 adv_err_code */ 175 0, /* 32 adv_err_addr */ 176 0, /* 33 saved_dvc_err_code */ 177 0, /* 34 saved_adv_err_code */ 178 0, /* 35 saved_adv_err_addr */ 179 0, /* 36 reserved */ 180 0, /* 37 reserved */ 181 0, /* 38 reserved */ 182 0, /* 39 reserved */ 183 0, /* 40 reserved */ 184 0, /* 41 reserved */ 185 0, /* 42 reserved */ 186 0, /* 43 reserved */ 187 0, /* 44 reserved */ 188 0, /* 45 reserved */ 189 0, /* 46 reserved */ 190 0, /* 47 reserved */ 191 0, /* 48 reserved */ 192 0, /* 49 reserved */ 193 0, /* 50 reserved */ 194 0, /* 51 reserved */ 195 0, /* 52 reserved */ 196 0, /* 53 reserved */ 197 0, /* 54 reserved */ 198 0, /* 55 reserved */ 199 0, /* 56 cisptr_lsw */ 200 0, /* 57 cisprt_msw */ 201 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 202 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 203 0, /* 60 reserved */ 204 0, /* 61 reserved */ 205 0, /* 62 reserved */ 206 0 /* 63 reserved */ 207 }; 208 209 /* 210 * Initialize the ASC3550. 211 * 212 * On failure set the ADW_SOFTC field 'err_code' and return ADW_ERROR. 213 * 214 * For a non-fatal error return a warning code. If there are no warnings 215 * then 0 is returned. 216 */ 217 int 218 AdvInitAsc3550Driver(sc) 219 ADW_SOFTC *sc; 220 { 221 bus_space_tag_t iot = sc->sc_iot; 222 bus_space_handle_t ioh = sc->sc_ioh; 223 u_int16_t warn_code; 224 u_int32_t sum; 225 int begin_addr; 226 int end_addr; 227 u_int16_t code_sum; 228 int word; 229 int i, j; 230 int adv_asc3550_expanded_size; 231 u_int16_t scsi_cfg1; 232 u_int8_t tid; 233 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 234 0x40-0x8F. */ 235 u_int16_t wdtr_able = 0, sdtr_able, tagqng_able; 236 u_int8_t max_cmd[ADW_MAX_TID + 1]; 237 238 239 warn_code = 0; 240 241 /* 242 * Save the RISC memory BIOS region before writing the microcode. 243 * The BIOS may already be loaded and using its RISC LRAM region 244 * so its region must be saved and restored. 245 * 246 * Note: This code makes the assumption, which is currently true, 247 * that a chip reset does not clear RISC LRAM. 248 */ 249 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 250 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2*i), bios_mem[i]); 251 } 252 253 /* 254 * Save current per TID negotiated values. 255 */ 256 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA) { 257 258 u_int16_t bios_version, major, minor; 259 260 bios_version = bios_mem[(ASC_MC_BIOS_VERSION-ASC_MC_BIOSMEM)/2]; 261 major = (bios_version >> 12) & 0xF; 262 minor = (bios_version >> 8) & 0xF; 263 if (major < 3 || (major == 3 && minor == 1)) { 264 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 265 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 266 } else { 267 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 268 } 269 } 270 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 271 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 272 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 273 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 274 max_cmd[tid]); 275 } 276 277 /* 278 * Load the Microcode 279 * 280 * Write the microcode image to RISC memory starting at address 0. 281 */ 282 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 283 284 /* Assume the following compressed format of the microcode buffer: 285 * 286 * 254 word (508 byte) table indexed by byte code followed 287 * by the following byte codes: 288 * 289 * 1-Byte Code: 290 * 00: Emit word 0 in table. 291 * 01: Emit word 1 in table. 292 * . 293 * FD: Emit word 253 in table. 294 * 295 * Multi-Byte Code: 296 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 297 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 298 */ 299 word = 0; 300 for (i = 253 * 2; i < adv_asc3550_mcode_size; i++) { 301 if (adv_asc3550_mcode[i] == 0xff) { 302 for (j = 0; j < adv_asc3550_mcode[i + 1]; j++) { 303 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 304 (((u_int16_t)adv_asc3550_mcode[i + 3] << 8) | 305 adv_asc3550_mcode[i + 2])); 306 word++; 307 } 308 i += 3; 309 } else if (adv_asc3550_mcode[i] == 0xfe) { 310 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 311 (((u_int16_t)adv_asc3550_mcode[i + 2] << 8) | 312 adv_asc3550_mcode[i + 1])); 313 i += 2; 314 word++; 315 } else { 316 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 317 adv_asc3550_mcode[(adv_asc3550_mcode[i] * 2) + 1] <<8) | 318 adv_asc3550_mcode[adv_asc3550_mcode[i] * 2])); 319 word++; 320 } 321 } 322 323 /* 324 * Set 'word' for later use to clear the rest of memory and save 325 * the expanded mcode size. 326 */ 327 word *= 2; 328 adv_asc3550_expanded_size = word; 329 330 /* 331 * Clear the rest of ASC-3550 Internal RAM (8KB). 332 */ 333 for (; word < ADV_3550_MEMSIZE; word += 2) { 334 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 335 } 336 337 /* 338 * Verify the microcode checksum. 339 */ 340 sum = 0; 341 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 342 343 for (word = 0; word < adv_asc3550_expanded_size; word += 2) { 344 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 345 } 346 347 if (sum != adv_asc3550_mcode_chksum) { 348 return ASC_IERR_MCODE_CHKSUM; 349 } 350 351 /* 352 * Restore the RISC memory BIOS region. 353 */ 354 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 355 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 356 bios_mem[i]); 357 } 358 359 /* 360 * Calculate and write the microcode code checksum to the microcode 361 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 362 */ 363 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 364 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 365 code_sum = 0; 366 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 367 for (word = begin_addr; word < end_addr; word += 2) { 368 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 369 } 370 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 371 372 /* 373 * Read and save microcode version and date. 374 */ 375 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 376 sc->cfg.mcode_date); 377 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 378 sc->cfg.mcode_version); 379 380 /* 381 * Set the chip type to indicate the ASC3550. 382 */ 383 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 384 385 /* 386 * If the PCI Configuration Command Register "Parity Error Response 387 * Control" Bit was clear (0), then set the microcode variable 388 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 389 * to ignore DMA parity errors. 390 */ 391 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 392 /* 393 * Note: Don't remove the use of a temporary variable in 394 * the following code, otherwise some C compiler 395 * might turn the following lines into a no-op. 396 */ 397 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 398 word |= CONTROL_FLAG_IGNORE_PERR; 399 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 400 } 401 402 /* 403 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 404 * threshold of 128 bytes. This register is only accessible to the host. 405 */ 406 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 407 START_CTL_EMFU | READ_CMD_MRM); 408 409 /* 410 * Microcode operating variables for WDTR, SDTR, and command tag 411 * queuing will be set in AdvInquiryHandling() based on what a 412 * device reports it is capable of in Inquiry byte 7. 413 * 414 * If SCSI Bus Resets haev been disabled, then directly set 415 * SDTR and WDTR from the EEPROM configuration. This will allow 416 * the BIOS and warm boot to work without a SCSI bus hang on 417 * the Inquiry caused by host and target mismatched DTR values. 418 * Without the SCSI Bus Reset, before an Inquiry a device can't 419 * be assumed to be in Asynchronous, Narrow mode. 420 */ 421 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 422 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 423 sc->wdtr_able); 424 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 425 sc->sdtr_able); 426 } 427 428 /* 429 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 430 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 431 * bitmask. These values determine the maximum SDTR speed negotiated 432 * with a device. 433 * 434 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 435 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 436 * without determining here whether the device supports SDTR. 437 * 438 * 4-bit speed SDTR speed name 439 * =========== =============== 440 * 0000b (0x0) SDTR disabled 441 * 0001b (0x1) 5 Mhz 442 * 0010b (0x2) 10 Mhz 443 * 0011b (0x3) 20 Mhz (Ultra) 444 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 445 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 446 * 0110b (0x6) Undefined 447 * . 448 * 1111b (0xF) Undefined 449 */ 450 word = 0; 451 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 452 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 453 /* Set Ultra speed for TID 'tid'. */ 454 word |= (0x3 << (4 * (tid % 4))); 455 } else { 456 /* Set Fast speed for TID 'tid'. */ 457 word |= (0x2 << (4 * (tid % 4))); 458 } 459 /* Check if done with sdtr_speed1. */ 460 if (tid == 3) { 461 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, word); 462 word = 0; 463 /* Check if done with sdtr_speed2. */ 464 } else if (tid == 7) { 465 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, word); 466 word = 0; 467 /* Check if done with sdtr_speed3. */ 468 } else if (tid == 11) { 469 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, word); 470 word = 0; 471 /* Check if done with sdtr_speed4. */ 472 } else if (tid == 15) { 473 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, word); 474 /* End of loop. */ 475 } 476 } 477 478 /* 479 * Set microcode operating variable for the disconnect per TID bitmask. 480 */ 481 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 482 483 484 /* 485 * Set SCSI_CFG0 Microcode Default Value. 486 * 487 * The microcode will set the SCSI_CFG0 register using this value 488 * after it is started below. 489 */ 490 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 491 ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | 492 sc->chip_scsi_id); 493 494 /* 495 * Determine SCSI_CFG1 Microcode Default Value. 496 * 497 * The microcode will set the SCSI_CFG1 register using this value 498 * after it is started below. 499 */ 500 501 /* Read current SCSI_CFG1 Register value. */ 502 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 503 504 /* 505 * If all three connectors are in use, return an error. 506 */ 507 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 508 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 509 return ASC_IERR_ILLEGAL_CONNECTION; 510 } 511 512 /* 513 * If the internal narrow cable is reversed all of the SCSI_CTRL 514 * register signals will be set. Check for and return an error if 515 * this condition is found. 516 */ 517 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 518 0x3F07) { 519 return ASC_IERR_REVERSED_CABLE; 520 } 521 522 /* 523 * If this is a differential board and a single-ended device 524 * is attached to one of the connectors, return an error. 525 */ 526 if ((scsi_cfg1 & ADW_DIFF_MODE) && (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 527 return ASC_IERR_SINGLE_END_DEVICE; 528 } 529 530 /* 531 * If automatic termination control is enabled, then set the 532 * termination value based on a table listed in a_condor.h. 533 * 534 * If manual termination was specified with an EEPROM setting 535 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 536 * is ready to be 'ored' into SCSI_CFG1. 537 */ 538 if (sc->cfg.termination == 0) { 539 /* 540 * The software always controls termination by setting TERM_CTL_SEL. 541 * If TERM_CTL_SEL were set to 0, the hardware would set termination. 542 */ 543 sc->cfg.termination |= ADW_TERM_CTL_SEL; 544 545 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 546 /* TERM_CTL_H: on, TERM_CTL_L: on */ 547 case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF: 548 sc->cfg.termination |= (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 549 break; 550 551 /* TERM_CTL_H: on, TERM_CTL_L: off */ 552 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC: 553 sc->cfg.termination |= ADW_TERM_CTL_H; 554 break; 555 556 /* TERM_CTL_H: off, TERM_CTL_L: off */ 557 case 0x2: case 0x6: 558 break; 559 } 560 } 561 562 /* 563 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 564 */ 565 scsi_cfg1 &= ~ADW_TERM_CTL; 566 567 /* 568 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 569 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 570 * referenced, because the hardware internally inverts 571 * the Termination High and Low bits if TERM_POL is set. 572 */ 573 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~sc->cfg.termination & ADW_TERM_CTL)); 574 575 /* 576 * Set SCSI_CFG1 Microcode Default Value 577 * 578 * Set filter value and possibly modified termination control 579 * bits in the Microcode SCSI_CFG1 Register Value. 580 * 581 * The microcode will set the SCSI_CFG1 register using this value 582 * after it is started below. 583 */ 584 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, 585 ADW_FLTR_DISABLE | scsi_cfg1); 586 587 /* 588 * Set MEM_CFG Microcode Default Value 589 * 590 * The microcode will set the MEM_CFG register using this value 591 * after it is started below. 592 * 593 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 594 * are defined. 595 * 596 * ASC-3550 has 8KB internal memory. 597 */ 598 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 599 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 600 601 /* 602 * Set SEL_MASK Microcode Default Value 603 * 604 * The microcode will set the SEL_MASK register using this value 605 * after it is started below. 606 */ 607 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 608 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 609 610 611 /* 612 * Set-up the Host->RISC Initiator Command Queue (ICQ). 613 */ 614 615 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 616 return ASC_IERR_NO_CARRIER; 617 } 618 sc->carr_freelist = adw_carrier_phys_kv(sc, 619 ASC_GET_CARRP(sc->icq_sp->next_vpa)); 620 621 /* 622 * The first command issued will be placed in the stopper carrier. 623 */ 624 sc->icq_sp->next_vpa = ASC_CQ_STOPPER; 625 626 /* 627 * Set RISC ICQ physical address start value. 628 */ 629 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); 630 631 /* 632 * Set-up the RISC->Host Initiator Response Queue (IRQ). 633 */ 634 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 635 return ASC_IERR_NO_CARRIER; 636 } 637 sc->carr_freelist = adw_carrier_phys_kv(sc, 638 ASC_GET_CARRP(sc->irq_sp->next_vpa)); 639 640 /* 641 * The first command completed by the RISC will be placed in 642 * the stopper. 643 * 644 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 645 * completed the RISC will set the ASC_RQ_STOPPER bit. 646 */ 647 sc->irq_sp->next_vpa = ASC_CQ_STOPPER; 648 649 /* 650 * Set RISC IRQ physical address start value. 651 */ 652 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); 653 sc->carr_pending_cnt = 0; 654 655 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 656 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 657 658 /* 659 * Note: Don't remove the use of a temporary variable in 660 * the following code, otherwise some C compiler 661 * might turn the following lines into a no-op. 662 */ 663 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 664 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 665 666 /* finally, finally, gentlemen, start your engine */ 667 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 668 669 /* 670 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 671 * Resets should be performed. The RISC has to be running 672 * to issue a SCSI Bus Reset. 673 */ 674 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 675 { 676 /* 677 * If the BIOS Signature is present in memory, restore the 678 * BIOS Handshake Configuration Table and do not perform 679 * a SCSI Bus Reset. 680 */ 681 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 682 0x55AA) { 683 /* 684 * Restore per TID negotiated values. 685 */ 686 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 687 wdtr_able); 688 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 689 sdtr_able); 690 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 691 tagqng_able); 692 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 693 ADW_WRITE_BYTE_LRAM(iot, ioh, 694 ASC_MC_NUMBER_OF_MAX_CMD + tid, 695 max_cmd[tid]); 696 } 697 } else { 698 if (AdvResetCCB(sc) != ADW_TRUE) { 699 warn_code = ASC_WARN_BUSRESET_ERROR; 700 } 701 } 702 } 703 704 return warn_code; 705 } 706 707 /* 708 * Initialize the ASC-38C0800. 709 * 710 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 711 * 712 * For a non-fatal error return a warning code. If there are no warnings 713 * then 0 is returned. 714 */ 715 int 716 AdvInitAsc38C0800Driver(sc) 717 ADW_SOFTC *sc; 718 { 719 bus_space_tag_t iot = sc->sc_iot; 720 bus_space_handle_t ioh = sc->sc_ioh; 721 u_int16_t warn_code; 722 u_int32_t sum; 723 int begin_addr; 724 int end_addr; 725 u_int16_t code_sum; 726 int word; 727 int i, j; 728 int adv_asc38C0800_expanded_size; 729 u_int16_t scsi_cfg1; 730 u_int8_t byte; 731 u_int8_t tid; 732 u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 733 0x40-0x8F. */ 734 u_int16_t wdtr_able, sdtr_able, tagqng_able; 735 u_int8_t max_cmd[ADW_MAX_TID + 1]; 736 737 738 warn_code = 0; 739 740 /* 741 * Save the RISC memory BIOS region before writing the microcode. 742 * The BIOS may already be loaded and using its RISC LRAM region 743 * so its region must be saved and restored. 744 * 745 * Note: This code makes the assumption, which is currently true, 746 * that a chip reset does not clear RISC LRAM. 747 */ 748 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 749 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]); 750 } 751 752 /* 753 * Save current per TID negotiated values. 754 */ 755 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 756 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 757 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 758 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 759 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 760 max_cmd[tid]); 761 } 762 763 /* 764 * RAM BIST (RAM Built-In Self Test) 765 * 766 * Address : I/O base + offset 0x38h register (byte). 767 * Function: Bit 7-6(RW) : RAM mode 768 * Normal Mode : 0x00 769 * Pre-test Mode : 0x40 770 * RAM Test Mode : 0x80 771 * Bit 5 : unused 772 * Bit 4(RO) : Done bit 773 * Bit 3-0(RO) : Status 774 * Host Error : 0x08 775 * Int_RAM Error : 0x04 776 * RISC Error : 0x02 777 * SCSI Error : 0x01 778 * No Error : 0x00 779 * 780 * Note: RAM BIST code should be put right here, before loading the 781 * microcode and after saving the RISC memory BIOS region. 782 */ 783 784 /* 785 * LRAM Pre-test 786 * 787 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 788 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 789 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 790 * to NORMAL_MODE, return an error too. 791 */ 792 for (i = 0; i < 2; i++) { 793 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); 794 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 795 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 796 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 797 PRE_TEST_VALUE) { 798 return ASC_IERR_BIST_PRE_TEST; 799 } 800 801 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 802 AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ 803 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 804 != NORMAL_VALUE) { 805 return ASC_IERR_BIST_PRE_TEST; 806 } 807 } 808 809 /* 810 * LRAM Test - It takes about 1.5 ms to run through the test. 811 * 812 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 813 * If Done bit not set or Status not 0, save register byte, set the 814 * err_code, and return an error. 815 */ 816 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 817 AdvSleepMilliSecond(10); /* Wait for 10ms before checking status. */ 818 819 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 820 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 821 /* Get here if Done bit not set or Status not 0. */ 822 return ASC_IERR_BIST_RAM_TEST; 823 } 824 825 /* We need to reset back to normal mode after LRAM test passes. */ 826 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 827 828 /* 829 * Load the Microcode 830 * 831 * Write the microcode image to RISC memory starting at address 0. 832 * 833 */ 834 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 835 836 /* Assume the following compressed format of the microcode buffer: 837 * 838 * 254 word (508 byte) table indexed by byte code followed 839 * by the following byte codes: 840 * 841 * 1-Byte Code: 842 * 00: Emit word 0 in table. 843 * 01: Emit word 1 in table. 844 * . 845 * FD: Emit word 253 in table. 846 * 847 * Multi-Byte Code: 848 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 849 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 850 */ 851 word = 0; 852 for (i = 253 * 2; i < adv_asc38C0800_mcode_size; i++) { 853 if (adv_asc38C0800_mcode[i] == 0xff) { 854 for (j = 0; j < adv_asc38C0800_mcode[i + 1]; j++) { 855 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 856 (((u_int16_t) 857 adv_asc38C0800_mcode[i + 3] << 8) | 858 adv_asc38C0800_mcode[i + 2])); 859 word++; 860 } 861 i += 3; 862 } else if (adv_asc38C0800_mcode[i] == 0xfe) { 863 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 864 adv_asc38C0800_mcode[i + 2] << 8) | 865 adv_asc38C0800_mcode[i + 1])); 866 i += 2; 867 word++; 868 } else { 869 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 870 adv_asc38C0800_mcode[(adv_asc38C0800_mcode[i] * 2) + 1] << 8) | 871 adv_asc38C0800_mcode[adv_asc38C0800_mcode[i] * 2])); 872 word++; 873 } 874 } 875 876 /* 877 * Set 'word' for later use to clear the rest of memory and save 878 * the expanded mcode size. 879 */ 880 word *= 2; 881 adv_asc38C0800_expanded_size = word; 882 883 /* 884 * Clear the rest of ASC-38C0800 Internal RAM (16KB). 885 */ 886 for (; word < ADV_38C0800_MEMSIZE; word += 2) { 887 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 888 } 889 890 /* 891 * Verify the microcode checksum. 892 */ 893 sum = 0; 894 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 895 896 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2) { 897 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 898 } 899 900 if (sum != adv_asc38C0800_mcode_chksum) { 901 return ASC_IERR_MCODE_CHKSUM; 902 } 903 904 /* 905 * Restore the RISC memory BIOS region. 906 */ 907 for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { 908 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), 909 bios_mem[i]); 910 } 911 912 /* 913 * Calculate and write the microcode code checksum to the microcode 914 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 915 */ 916 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 917 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 918 code_sum = 0; 919 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 920 for (word = begin_addr; word < end_addr; word += 2) { 921 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 922 } 923 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 924 925 /* 926 * Read microcode version and date. 927 */ 928 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, 929 sc->cfg.mcode_date); 930 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, 931 sc->cfg.mcode_version); 932 933 /* 934 * Set the chip type to indicate the ASC38C0800. 935 */ 936 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 937 938 /* 939 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 940 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 941 * cable detection and then we are able to read C_DET[3:0]. 942 * 943 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 944 * Microcode Default Value' section below. 945 */ 946 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 947 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 948 scsi_cfg1 | ADW_DIS_TERM_DRV); 949 950 /* 951 * If the PCI Configuration Command Register "Parity Error Response 952 * Control" Bit was clear (0), then set the microcode variable 953 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 954 * to ignore DMA parity errors. 955 */ 956 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 957 /* 958 * Note: Don't remove the use of a temporary variable in 959 * the following code, otherwise some C compiler 960 * might turn the following lines into a no-op. 961 */ 962 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 963 word |= CONTROL_FLAG_IGNORE_PERR; 964 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 965 } 966 967 /* 968 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] 969 * bits for the default FIFO threshold. 970 * 971 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 972 * 973 * For DMA Errata #4 set the BC_THRESH_ENB bit. 974 */ 975 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 976 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 977 978 /* 979 * Microcode operating variables for WDTR, SDTR, and command tag 980 * queuing will be set in AdvInquiryHandling() based on what a 981 * device reports it is capable of in Inquiry byte 7. 982 * 983 * If SCSI Bus Resets have been disabled, then directly set 984 * SDTR and WDTR from the EEPROM configuration. This will allow 985 * the BIOS and warm boot to work without a SCSI bus hang on 986 * the Inquiry caused by host and target mismatched DTR values. 987 * Without the SCSI Bus Reset, before an Inquiry a device can't 988 * be assumed to be in Asynchronous, Narrow mode. 989 */ 990 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 991 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, sc->wdtr_able); 992 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sc->sdtr_able); 993 } 994 995 /* 996 * Set microcode operating variables for DISC and SDTR_SPEED1, 997 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 998 * configuration values. 999 * 1000 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 1001 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 1002 * without determining here whether the device supports SDTR. 1003 */ 1004 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 1005 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, sc->sdtr_speed1); 1006 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, sc->sdtr_speed2); 1007 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, sc->sdtr_speed3); 1008 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, sc->sdtr_speed4); 1009 1010 /* 1011 * Set SCSI_CFG0 Microcode Default Value. 1012 * 1013 * The microcode will set the SCSI_CFG0 register using this value 1014 * after it is started below. 1015 */ 1016 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 1017 ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | 1018 sc->chip_scsi_id); 1019 1020 /* 1021 * Determine SCSI_CFG1 Microcode Default Value. 1022 * 1023 * The microcode will set the SCSI_CFG1 register using this value 1024 * after it is started below. 1025 */ 1026 1027 /* Read current SCSI_CFG1 Register value. */ 1028 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1029 1030 /* 1031 * If the internal narrow cable is reversed all of the SCSI_CTRL 1032 * register signals will be set. Check for and return an error if 1033 * this condition is found. 1034 */ 1035 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 1036 0x3F07) { 1037 return ASC_IERR_REVERSED_CABLE; 1038 } 1039 1040 /* 1041 * All kind of combinations of devices attached to one of four connectors 1042 * are acceptable except HVD device attached. For example, LVD device can 1043 * be attached to SE connector while SE device attached to LVD connector. 1044 * If LVD device attached to SE connector, it only runs up to Ultra speed. 1045 * 1046 * If an HVD device is attached to one of LVD connectors, return an error. 1047 * However, there is no way to detect HVD device attached to SE connectors. 1048 */ 1049 if (scsi_cfg1 & ADW_HVD) { 1050 return ASC_IERR_HVD_DEVICE; 1051 } 1052 1053 /* 1054 * If either SE or LVD automatic termination control is enabled, then 1055 * set the termination value based on a table listed in a_condor.h. 1056 * 1057 * If manual termination was specified with an EEPROM setting then 1058 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to 1059 * be 'ored' into SCSI_CFG1. 1060 */ 1061 if ((sc->cfg.termination & ADW_TERM_SE) == 0) { 1062 /* SE automatic termination control is enabled. */ 1063 switch(scsi_cfg1 & ADW_C_DET_SE) { 1064 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1065 case 0x1: case 0x2: case 0x3: 1066 sc->cfg.termination |= ADW_TERM_SE; 1067 break; 1068 1069 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1070 case 0x0: 1071 sc->cfg.termination |= ADW_TERM_SE_HI; 1072 break; 1073 } 1074 } 1075 1076 if ((sc->cfg.termination & ADW_TERM_LVD) == 0) { 1077 /* LVD automatic termination control is enabled. */ 1078 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1079 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1080 case 0x4: case 0x8: case 0xC: 1081 sc->cfg.termination |= ADW_TERM_LVD; 1082 break; 1083 1084 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1085 case 0x0: 1086 break; 1087 } 1088 } 1089 1090 /* 1091 * Clear any set TERM_SE and TERM_LVD bits. 1092 */ 1093 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1094 1095 /* 1096 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1097 */ 1098 scsi_cfg1 |= (~sc->cfg.termination & 0xF0); 1099 1100 /* 1101 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits 1102 * and set possibly modified termination control bits in the Microcode 1103 * SCSI_CFG1 Register Value. 1104 */ 1105 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1106 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1107 1108 /* 1109 * Set SCSI_CFG1 Microcode Default Value 1110 * 1111 * Set possibly modified termination control and reset DIS_TERM_DRV 1112 * bits in the Microcode SCSI_CFG1 Register Value. 1113 * 1114 * The microcode will set the SCSI_CFG1 register using this value 1115 * after it is started below. 1116 */ 1117 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1118 1119 /* 1120 * Set MEM_CFG Microcode Default Value 1121 * 1122 * The microcode will set the MEM_CFG register using this value 1123 * after it is started below. 1124 * 1125 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1126 * are defined. 1127 * 1128 * ASC-38C0800 has 16KB internal memory. 1129 */ 1130 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, 1131 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1132 1133 /* 1134 * Set SEL_MASK Microcode Default Value 1135 * 1136 * The microcode will set the SEL_MASK register using this value 1137 * after it is started below. 1138 */ 1139 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 1140 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 1141 1142 1143 /* 1144 * Set-up the Host->RISC Initiator Command Queue (ICQ). 1145 */ 1146 1147 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 1148 return ASC_IERR_NO_CARRIER; 1149 } 1150 sc->carr_freelist = adw_carrier_phys_kv(sc, 1151 ASC_GET_CARRP(sc->icq_sp->next_vpa)); 1152 1153 1154 /* 1155 * The first command issued will be placed in the stopper carrier. 1156 */ 1157 sc->icq_sp->next_vpa = ASC_CQ_STOPPER; 1158 1159 /* 1160 * Set RISC ICQ physical address start value. 1161 */ 1162 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); 1163 1164 /* 1165 * Set-up the RISC->Host Initiator Response Queue (IRQ). 1166 */ 1167 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 1168 return ASC_IERR_NO_CARRIER; 1169 } 1170 sc->carr_freelist = adw_carrier_phys_kv(sc, 1171 ASC_GET_CARRP(sc->irq_sp->next_vpa)); 1172 1173 /* 1174 * The first command completed by the RISC will be placed in 1175 * the stopper. 1176 * 1177 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 1178 * completed the RISC will set the ASC_RQ_STOPPER bit. 1179 */ 1180 sc->irq_sp->next_vpa = ASC_CQ_STOPPER; 1181 1182 /* 1183 * Set RISC IRQ physical address start value. 1184 */ 1185 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); 1186 sc->carr_pending_cnt = 0; 1187 1188 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 1189 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 1190 /* 1191 * Note: Don't remove the use of a temporary variable in 1192 * the following code, otherwise some C compiler 1193 * might turn the following lines into a no-op. 1194 */ 1195 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 1196 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 1197 1198 /* finally, finally, gentlemen, start your engine */ 1199 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 1200 1201 /* 1202 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 1203 * Resets should be performed. The RISC has to be running 1204 * to issue a SCSI Bus Reset. 1205 */ 1206 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 1207 /* 1208 * If the BIOS Signature is present in memory, restore the 1209 * BIOS Handshake Configuration Table and do not perform 1210 * a SCSI Bus Reset. 1211 */ 1212 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 1213 0x55AA) { 1214 /* 1215 * Restore per TID negotiated values. 1216 */ 1217 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 1218 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 1219 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1220 tagqng_able); 1221 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1222 ADW_WRITE_BYTE_LRAM(iot, ioh, 1223 ASC_MC_NUMBER_OF_MAX_CMD + tid, 1224 max_cmd[tid]); 1225 } 1226 } else { 1227 if (AdvResetCCB(sc) != ADW_TRUE) { 1228 warn_code = ASC_WARN_BUSRESET_ERROR; 1229 } 1230 } 1231 } 1232 1233 return warn_code; 1234 } 1235 1236 1237 /* 1238 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1239 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1240 * all of this is done. 1241 * 1242 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1243 * 1244 * For a non-fatal error return a warning code. If there are no warnings 1245 * then 0 is returned. 1246 * 1247 * Note: Chip is stopped on entry. 1248 */ 1249 int 1250 AdvInitFrom3550EEP(sc) 1251 ADW_SOFTC *sc; 1252 { 1253 bus_space_tag_t iot = sc->sc_iot; 1254 bus_space_handle_t ioh = sc->sc_ioh; 1255 u_int16_t warn_code; 1256 ADW_EEP_3550_CONFIG eep_config; 1257 int i; 1258 1259 1260 warn_code = 0; 1261 1262 /* 1263 * Read the board's EEPROM configuration. 1264 * 1265 * Set default values if a bad checksum is found. 1266 */ 1267 if (AdvGet3550EEPConfig(iot, ioh, &eep_config) != eep_config.check_sum){ 1268 warn_code |= ASC_WARN_EEPROM_CHKSUM; 1269 1270 /* 1271 * Set EEPROM default values. 1272 */ 1273 for (i = 0; i < sizeof(ADW_EEP_3550_CONFIG); i++) { 1274 *((u_int8_t *) &eep_config + i) = 1275 *((u_int8_t *) &Default_3550_EEPROM_Config + i); 1276 } 1277 1278 /* 1279 * Assume the 6 byte board serial number that was read 1280 * from EEPROM is correct even if the EEPROM checksum 1281 * failed. 1282 */ 1283 eep_config.serial_number_word3 = 1284 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 1285 1286 eep_config.serial_number_word2 = 1287 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 1288 1289 eep_config.serial_number_word1 = 1290 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 1291 1292 AdvSet3550EEPConfig(iot, ioh, &eep_config); 1293 } 1294 /* 1295 * Set sc_VAR and sc_CFG variables from the 1296 * EEPROM configuration that was read. 1297 * 1298 * This is the mapping of EEPROM fields to Adv Library fields. 1299 */ 1300 sc->wdtr_able = eep_config.wdtr_able; 1301 sc->sdtr_able = eep_config.sdtr_able; 1302 sc->ultra_able = eep_config.ultra_able; 1303 sc->tagqng_able = eep_config.tagqng_able; 1304 sc->cfg.disc_enable = eep_config.disc_enable; 1305 sc->max_host_qng = eep_config.max_host_qng; 1306 sc->max_dvc_qng = eep_config.max_dvc_qng; 1307 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 1308 sc->start_motor = eep_config.start_motor; 1309 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 1310 sc->bios_ctrl = eep_config.bios_ctrl; 1311 sc->no_scam = eep_config.scam_tolerant; 1312 sc->cfg.serial1 = eep_config.serial_number_word1; 1313 sc->cfg.serial2 = eep_config.serial_number_word2; 1314 sc->cfg.serial3 = eep_config.serial_number_word3; 1315 1316 /* 1317 * Set the host maximum queuing (max. 253, min. 16) and the per device 1318 * maximum queuing (max. 63, min. 4). 1319 */ 1320 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 1321 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1322 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) 1323 { 1324 /* If the value is zero, assume it is uninitialized. */ 1325 if (eep_config.max_host_qng == 0) { 1326 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1327 } else { 1328 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 1329 } 1330 } 1331 1332 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 1333 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1334 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 1335 /* If the value is zero, assume it is uninitialized. */ 1336 if (eep_config.max_dvc_qng == 0) { 1337 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1338 } else { 1339 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 1340 } 1341 } 1342 1343 /* 1344 * If 'max_dvc_qng' is greater than 'max_host_qng', then 1345 * set 'max_dvc_qng' to 'max_host_qng'. 1346 */ 1347 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 1348 eep_config.max_dvc_qng = eep_config.max_host_qng; 1349 } 1350 1351 /* 1352 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 1353 * values based on possibly adjusted EEPROM values. 1354 */ 1355 sc->max_host_qng = eep_config.max_host_qng; 1356 sc->max_dvc_qng = eep_config.max_dvc_qng; 1357 1358 1359 /* 1360 * If the EEPROM 'termination' field is set to automatic (0), then set 1361 * the ADV_DVC_CFG 'termination' field to automatic also. 1362 * 1363 * If the termination is specified with a non-zero 'termination' 1364 * value check that a legal value is set and set the ADV_DVC_CFG 1365 * 'termination' field appropriately. 1366 */ 1367 if (eep_config.termination == 0) { 1368 sc->cfg.termination = 0; /* auto termination */ 1369 } else { 1370 /* Enable manual control with low off / high off. */ 1371 if (eep_config.termination == 1) { 1372 sc->cfg.termination = ADW_TERM_CTL_SEL; 1373 1374 /* Enable manual control with low off / high on. */ 1375 } else if (eep_config.termination == 2) { 1376 sc->cfg.termination = ADW_TERM_CTL_SEL | ADW_TERM_CTL_H; 1377 1378 /* Enable manual control with low on / high on. */ 1379 } else if (eep_config.termination == 3) { 1380 sc->cfg.termination = ADW_TERM_CTL_SEL | 1381 ADW_TERM_CTL_H | ADW_TERM_CTL_L; 1382 } else { 1383 /* 1384 * The EEPROM 'termination' field contains a bad value. Use 1385 * automatic termination instead. 1386 */ 1387 sc->cfg.termination = 0; 1388 warn_code |= ASC_WARN_EEPROM_TERMINATION; 1389 } 1390 } 1391 1392 return warn_code; 1393 } 1394 1395 1396 /* 1397 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 1398 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 1399 * all of this is done. 1400 * 1401 * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. 1402 * 1403 * For a non-fatal error return a warning code. If there are no warnings 1404 * then 0 is returned. 1405 * 1406 * Note: Chip is stopped on entry. 1407 */ 1408 int 1409 AdvInitFrom38C0800EEP(sc) 1410 ADW_SOFTC *sc; 1411 { 1412 bus_space_tag_t iot = sc->sc_iot; 1413 bus_space_handle_t ioh = sc->sc_ioh; 1414 u_int16_t warn_code; 1415 ADW_EEP_38C0800_CONFIG eep_config; 1416 int i; 1417 u_int8_t tid, termination; 1418 u_int16_t sdtr_speed = 0; 1419 1420 1421 warn_code = 0; 1422 1423 /* 1424 * Read the board's EEPROM configuration. 1425 * 1426 * Set default values if a bad checksum is found. 1427 */ 1428 if (AdvGet38C0800EEPConfig(iot, ioh, &eep_config) != 1429 eep_config.check_sum) { 1430 warn_code |= ASC_WARN_EEPROM_CHKSUM; 1431 1432 /* 1433 * Set EEPROM default values. 1434 */ 1435 for (i = 0; i < sizeof(ADW_EEP_38C0800_CONFIG); i++) { 1436 *((u_int8_t *) &eep_config + i) = 1437 *((u_int8_t *)&Default_38C0800_EEPROM_Config+i); 1438 } 1439 1440 /* 1441 * Assume the 6 byte board serial number that was read 1442 * from EEPROM is correct even if the EEPROM checksum 1443 * failed. 1444 */ 1445 eep_config.serial_number_word3 = 1446 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 1447 1448 eep_config.serial_number_word2 = 1449 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 1450 1451 eep_config.serial_number_word1 = 1452 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 1453 1454 AdvSet38C0800EEPConfig(iot, ioh, &eep_config); 1455 } 1456 /* 1457 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 1458 * EEPROM configuration that was read. 1459 * 1460 * This is the mapping of EEPROM fields to Adv Library fields. 1461 */ 1462 sc->wdtr_able = eep_config.wdtr_able; 1463 sc->sdtr_speed1 = eep_config.sdtr_speed1; 1464 sc->sdtr_speed2 = eep_config.sdtr_speed2; 1465 sc->sdtr_speed3 = eep_config.sdtr_speed3; 1466 sc->sdtr_speed4 = eep_config.sdtr_speed4; 1467 sc->tagqng_able = eep_config.tagqng_able; 1468 sc->cfg.disc_enable = eep_config.disc_enable; 1469 sc->max_host_qng = eep_config.max_host_qng; 1470 sc->max_dvc_qng = eep_config.max_dvc_qng; 1471 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 1472 sc->start_motor = eep_config.start_motor; 1473 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 1474 sc->bios_ctrl = eep_config.bios_ctrl; 1475 sc->no_scam = eep_config.scam_tolerant; 1476 sc->cfg.serial1 = eep_config.serial_number_word1; 1477 sc->cfg.serial2 = eep_config.serial_number_word2; 1478 sc->cfg.serial3 = eep_config.serial_number_word3; 1479 1480 /* 1481 * For every Target ID if any of its 'sdtr_speed[1234]' bits 1482 * are set, then set an 'sdtr_able' bit for it. 1483 */ 1484 sc->sdtr_able = 0; 1485 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1486 if (tid == 0) { 1487 sdtr_speed = sc->sdtr_speed1; 1488 } else if (tid == 4) { 1489 sdtr_speed = sc->sdtr_speed2; 1490 } else if (tid == 8) { 1491 sdtr_speed = sc->sdtr_speed3; 1492 } else if (tid == 12) { 1493 sdtr_speed = sc->sdtr_speed4; 1494 } 1495 if (sdtr_speed & ADW_MAX_TID) { 1496 sc->sdtr_able |= (1 << tid); 1497 } 1498 sdtr_speed >>= 4; 1499 } 1500 1501 /* 1502 * Set the host maximum queuing (max. 253, min. 16) and the per device 1503 * maximum queuing (max. 63, min. 4). 1504 */ 1505 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 1506 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1507 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 1508 /* If the value is zero, assume it is uninitialized. */ 1509 if (eep_config.max_host_qng == 0) { 1510 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 1511 } else { 1512 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 1513 } 1514 } 1515 1516 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 1517 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1518 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 1519 /* If the value is zero, assume it is uninitialized. */ 1520 if (eep_config.max_dvc_qng == 0) { 1521 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 1522 } else { 1523 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 1524 } 1525 } 1526 1527 /* 1528 * If 'max_dvc_qng' is greater than 'max_host_qng', then 1529 * set 'max_dvc_qng' to 'max_host_qng'. 1530 */ 1531 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 1532 eep_config.max_dvc_qng = eep_config.max_host_qng; 1533 } 1534 1535 /* 1536 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 1537 * values based on possibly adjusted EEPROM values. 1538 */ 1539 sc->max_host_qng = eep_config.max_host_qng; 1540 sc->max_dvc_qng = eep_config.max_dvc_qng; 1541 1542 /* 1543 * If the EEPROM 'termination' field is set to automatic (0), then set 1544 * the ADV_DVC_CFG 'termination' field to automatic also. 1545 * 1546 * If the termination is specified with a non-zero 'termination' 1547 * value check that a legal value is set and set the ADV_DVC_CFG 1548 * 'termination' field appropriately. 1549 */ 1550 if (eep_config.termination_se == 0) { 1551 termination = 0; /* auto termination for SE */ 1552 } else { 1553 /* Enable manual control with low off / high off. */ 1554 if (eep_config.termination_se == 1) { 1555 termination = 0; 1556 1557 /* Enable manual control with low off / high on. */ 1558 } else if (eep_config.termination_se == 2) { 1559 termination = ADW_TERM_SE_HI; 1560 1561 /* Enable manual control with low on / high on. */ 1562 } else if (eep_config.termination_se == 3) { 1563 termination = ADW_TERM_SE; 1564 } else { 1565 /* 1566 * The EEPROM 'termination_se' field contains 1567 * a bad value. 1568 * Use automatic termination instead. 1569 */ 1570 termination = 0; 1571 warn_code |= ASC_WARN_EEPROM_TERMINATION; 1572 } 1573 } 1574 1575 if (eep_config.termination_lvd == 0) { 1576 /* auto termination for LVD */ 1577 sc->cfg.termination = termination; 1578 } else 1579 { 1580 /* Enable manual control with low off / high off. */ 1581 if (eep_config.termination_lvd == 1) { 1582 sc->cfg.termination = termination; 1583 1584 /* Enable manual control with low off / high on. */ 1585 } else if (eep_config.termination_lvd == 2) { 1586 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 1587 1588 /* Enable manual control with low on / high on. */ 1589 } else if (eep_config.termination_lvd == 3) { 1590 sc->cfg.termination = termination | ADW_TERM_LVD; 1591 } else { 1592 /* 1593 * The EEPROM 'termination_lvd' field contains a bad value. 1594 * Use automatic termination instead. 1595 */ 1596 sc->cfg.termination = termination; 1597 warn_code |= ASC_WARN_EEPROM_TERMINATION; 1598 } 1599 } 1600 1601 return warn_code; 1602 } 1603 1604 1605 /* 1606 * Read EEPROM configuration into the specified buffer. 1607 * 1608 * Return a checksum based on the EEPROM configuration read. 1609 */ 1610 static u_int16_t 1611 AdvGet3550EEPConfig(iot, ioh, cfg_buf) 1612 bus_space_tag_t iot; 1613 bus_space_handle_t ioh; 1614 ADW_EEP_3550_CONFIG *cfg_buf; 1615 { 1616 u_int16_t wval, chksum; 1617 u_int16_t *wbuf; 1618 int eep_addr; 1619 1620 1621 wbuf = (u_int16_t *) cfg_buf; 1622 chksum = 0; 1623 1624 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1625 eep_addr < ASC_EEP_DVC_CFG_END; 1626 eep_addr++, wbuf++) { 1627 wval = AdvReadEEPWord(iot, ioh, eep_addr); 1628 chksum += wval; 1629 *wbuf = wval; 1630 } 1631 1632 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 1633 wbuf++; 1634 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1635 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1636 eep_addr++, wbuf++) { 1637 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 1638 } 1639 1640 return chksum; 1641 } 1642 1643 1644 /* 1645 * Read EEPROM configuration into the specified buffer. 1646 * 1647 * Return a checksum based on the EEPROM configuration read. 1648 */ 1649 static u_int16_t 1650 AdvGet38C0800EEPConfig(iot, ioh, cfg_buf) 1651 bus_space_tag_t iot; 1652 bus_space_handle_t ioh; 1653 ADW_EEP_38C0800_CONFIG *cfg_buf; 1654 { 1655 u_int16_t wval, chksum; 1656 u_int16_t *wbuf; 1657 int eep_addr; 1658 1659 1660 wbuf = (u_int16_t *) cfg_buf; 1661 chksum = 0; 1662 1663 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1664 eep_addr < ASC_EEP_DVC_CFG_END; 1665 eep_addr++, wbuf++) { 1666 wval = AdvReadEEPWord(iot, ioh, eep_addr); 1667 chksum += wval; 1668 *wbuf = wval; 1669 } 1670 1671 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 1672 wbuf++; 1673 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1674 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1675 eep_addr++, wbuf++) { 1676 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 1677 } 1678 1679 return chksum; 1680 } 1681 1682 1683 /* 1684 * Read the EEPROM from specified location 1685 */ 1686 static u_int16_t 1687 AdvReadEEPWord(iot, ioh, eep_word_addr) 1688 bus_space_tag_t iot; 1689 bus_space_handle_t ioh; 1690 int eep_word_addr; 1691 { 1692 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1693 ASC_EEP_CMD_READ | eep_word_addr); 1694 AdvWaitEEPCmd(iot, ioh); 1695 1696 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1697 } 1698 1699 1700 /* 1701 * Wait for EEPROM command to complete 1702 */ 1703 static void 1704 AdvWaitEEPCmd(iot, ioh) 1705 bus_space_tag_t iot; 1706 bus_space_handle_t ioh; 1707 { 1708 int eep_delay_ms; 1709 1710 1711 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1712 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1713 ASC_EEP_CMD_DONE) { 1714 break; 1715 } 1716 AdvSleepMilliSecond(1); 1717 } 1718 1719 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1720 } 1721 1722 1723 /* 1724 * Write the EEPROM from 'cfg_buf'. 1725 */ 1726 static void 1727 AdvSet3550EEPConfig(iot, ioh, cfg_buf) 1728 bus_space_tag_t iot; 1729 bus_space_handle_t ioh; 1730 ADW_EEP_3550_CONFIG *cfg_buf; 1731 { 1732 u_int16_t *wbuf; 1733 u_int16_t addr, chksum; 1734 1735 1736 wbuf = (u_int16_t *) cfg_buf; 1737 chksum = 0; 1738 1739 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1740 AdvWaitEEPCmd(iot, ioh); 1741 1742 /* 1743 * Write EEPROM from word 0 to word 20 1744 */ 1745 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1746 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1747 chksum += *wbuf; 1748 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1749 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1750 ASC_EEP_CMD_WRITE | addr); 1751 AdvWaitEEPCmd(iot, ioh); 1752 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 1753 } 1754 1755 /* 1756 * Write EEPROM checksum at word 21 1757 */ 1758 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1759 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1760 ASC_EEP_CMD_WRITE | addr); 1761 AdvWaitEEPCmd(iot, ioh); 1762 wbuf++; /* skip over check_sum */ 1763 1764 /* 1765 * Write EEPROM OEM name at words 22 to 29 1766 */ 1767 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1768 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1769 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1770 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1771 ASC_EEP_CMD_WRITE | addr); 1772 AdvWaitEEPCmd(iot, ioh); 1773 } 1774 1775 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1776 ASC_EEP_CMD_WRITE_DISABLE); 1777 AdvWaitEEPCmd(iot, ioh); 1778 1779 return; 1780 } 1781 1782 1783 /* 1784 * Write the EEPROM from 'cfg_buf'. 1785 */ 1786 static void 1787 AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) 1788 bus_space_tag_t iot; 1789 bus_space_handle_t ioh; 1790 ADW_EEP_38C0800_CONFIG *cfg_buf; 1791 { 1792 u_int16_t *wbuf; 1793 u_int16_t addr, chksum; 1794 1795 1796 wbuf = (u_int16_t *) cfg_buf; 1797 chksum = 0; 1798 1799 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1800 AdvWaitEEPCmd(iot, ioh); 1801 1802 /* 1803 * Write EEPROM from word 0 to word 20 1804 */ 1805 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1806 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1807 chksum += *wbuf; 1808 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1809 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1810 ASC_EEP_CMD_WRITE | addr); 1811 AdvWaitEEPCmd(iot, ioh); 1812 AdvSleepMilliSecond(ASC_EEP_DELAY_MS); 1813 } 1814 1815 /* 1816 * Write EEPROM checksum at word 21 1817 */ 1818 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1819 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1820 ASC_EEP_CMD_WRITE | addr); 1821 AdvWaitEEPCmd(iot, ioh); 1822 wbuf++; /* skip over check_sum */ 1823 1824 /* 1825 * Write EEPROM OEM name at words 22 to 29 1826 */ 1827 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1828 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1829 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1830 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1831 ASC_EEP_CMD_WRITE | addr); 1832 AdvWaitEEPCmd(iot, ioh); 1833 } 1834 1835 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1836 ASC_EEP_CMD_WRITE_DISABLE); 1837 AdvWaitEEPCmd(iot, ioh); 1838 1839 return; 1840 } 1841 1842 1843 /* 1844 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 1845 * 1846 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1847 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1848 * RISC to notify it a new command is ready to be executed. 1849 * 1850 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1851 * set to SCSI_MAX_RETRY. 1852 * 1853 * Return: 1854 * ADW_SUCCESS(1) - The request was successfully queued. 1855 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1856 * request completes. 1857 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1858 * host IC error. 1859 */ 1860 int 1861 AdvExeScsiQueue(sc, scsiq) 1862 ADW_SOFTC *sc; 1863 ADW_SCSI_REQ_Q *scsiq; 1864 { 1865 bus_space_tag_t iot = sc->sc_iot; 1866 bus_space_handle_t ioh = sc->sc_ioh; 1867 ADW_CCB *ccb; 1868 long req_size; 1869 u_int32_t req_paddr; 1870 ADW_CARRIER *new_carrp/*, *ccb_carr; 1871 int i*/; 1872 1873 1874 /* 1875 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1876 */ 1877 if (scsiq->target_id > ADW_MAX_TID) { 1878 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1879 scsiq->done_status = QD_WITH_ERROR; 1880 return ADW_ERROR; 1881 } 1882 1883 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1884 ccb->carr_list = sc->icq_sp; 1885 1886 /* 1887 * Allocate a carrier ensuring at least one carrier always 1888 * remains on the freelist and initialize fields. 1889 */ 1890 if ((new_carrp = sc->carr_freelist) == NULL) { 1891 return ADW_BUSY; 1892 } 1893 sc->carr_freelist = adw_carrier_phys_kv(sc, 1894 ASC_GET_CARRP(new_carrp->next_vpa)); 1895 sc->carr_pending_cnt++; 1896 1897 /* 1898 * Set the carrier to be a stopper by setting 'next_vpa' 1899 * to the stopper value. The current stopper will be changed 1900 * below to point to the new stopper. 1901 */ 1902 new_carrp->next_vpa = ASC_CQ_STOPPER; 1903 1904 req_size = sizeof(ADW_SCSI_REQ_Q); 1905 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1906 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1907 1908 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1909 scsiq->scsiq_rptr = req_paddr; 1910 1911 /* 1912 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian 1913 * order during initialization. 1914 */ 1915 scsiq->carr_pa = sc->icq_sp->carr_pa; 1916 scsiq->carr_va = sc->icq_sp->carr_pa; 1917 1918 /* 1919 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1920 * the microcode. The newly allocated stopper will become the new 1921 * stopper. 1922 */ 1923 sc->icq_sp->areq_vpa = req_paddr; 1924 1925 /* 1926 * Set the 'next_vpa' pointer for the old stopper to be the 1927 * physical address of the new stopper. The RISC can only 1928 * follow physical addresses. 1929 */ 1930 sc->icq_sp->next_vpa = new_carrp->carr_pa; 1931 1932 /* 1933 * Set the host adapter stopper pointer to point to the new carrier. 1934 */ 1935 sc->icq_sp = new_carrp; 1936 1937 /* ccb_carr = ccb->carr_list; 1938 while(ccb_carr != ASC_CQ_STOPPER) { 1939 bus_dmamap_load(sc->sc_dmat, ccb_carr->dmamap_xfer, 1940 ccb_carr, ADW_CARRIER_SIZE, 1941 NULL, BUS_DMA_NOWAIT); 1942 bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, 1943 ccb_carr->dmamap_xfer->dm_mapsize, 1944 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1945 ccb_carr = adw_carrier_phys_kv(sc, 1946 ASC_GET_CARRP(ccb_carr->next_vpa)); 1947 } 1948 1949 ccb_carr = sc->irq_sp; 1950 for(i=0; i<2 && ccb_carr != ASC_CQ_STOPPER; i++) { 1951 bus_dmamap_load(sc->sc_dmat, ccb_carr->dmamap_xfer, 1952 ccb_carr, ADW_CARRIER_SIZE, 1953 NULL, BUS_DMA_NOWAIT); 1954 bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, 1955 ccb_carr->dmamap_xfer->dm_mapsize, 1956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1957 ccb_carr = adw_carrier_phys_kv(sc, 1958 ASC_GET_CARRP(ccb_carr->next_vpa)); 1959 } 1960 */ 1961 bus_dmamap_load(sc->sc_dmat, sc->sc_control->dmamap_xfer, 1962 sc->sc_control->carriers, ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 1963 NULL, BUS_DMA_NOWAIT); 1964 bus_dmamap_sync(sc->sc_dmat, sc->sc_control->dmamap_xfer, 0, 1965 sc->sc_control->dmamap_xfer->dm_mapsize, 1966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1967 1968 /* 1969 * Tickle the RISC to tell it to read its Command Queue Head pointer. 1970 */ 1971 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); 1972 if (sc->chip_type == ADV_CHIP_ASC3550) 1973 { 1974 /* 1975 * Clear the tickle value. In the ASC-3550 the RISC flag 1976 * command 'clr_tickle_a' does not work unless the host 1977 * value is cleared. 1978 */ 1979 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 1980 } 1981 1982 return ADW_SUCCESS; 1983 } 1984 1985 1986 void 1987 AdvResetChip(iot, ioh) 1988 bus_space_tag_t iot; 1989 bus_space_handle_t ioh; 1990 { 1991 1992 /* 1993 * Reset Chip. 1994 */ 1995 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1996 ADW_CTRL_REG_CMD_RESET); 1997 AdvSleepMilliSecond(100); 1998 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1999 ADW_CTRL_REG_CMD_WR_IO_REG); 2000 } 2001 2002 2003 /* 2004 * Reset SCSI Bus and purge all outstanding requests. 2005 * 2006 * Return Value: 2007 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 2008 * ADW_FALSE(0) - Microcode command failed. 2009 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 2010 * may be hung which requires driver recovery. 2011 */ 2012 int 2013 AdvResetCCB(sc) 2014 ADW_SOFTC *sc; 2015 { 2016 int status; 2017 2018 /* 2019 * Send the SCSI Bus Reset idle start idle command which asserts 2020 * the SCSI Bus Reset signal. 2021 */ 2022 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 2023 if (status != ADW_TRUE) 2024 { 2025 return status; 2026 } 2027 2028 /* 2029 * Delay for the specified SCSI Bus Reset hold time. 2030 * 2031 * The hold time delay is done on the host because the RISC has no 2032 * microsecond accurate timer. 2033 */ 2034 AdvDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 2035 2036 /* 2037 * Send the SCSI Bus Reset end idle command which de-asserts 2038 * the SCSI Bus Reset signal and purges any pending requests. 2039 */ 2040 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 2041 if (status != ADW_TRUE) 2042 { 2043 return status; 2044 } 2045 2046 AdvSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 2047 2048 return status; 2049 } 2050 2051 2052 /* 2053 * Reset chip and SCSI Bus. 2054 * 2055 * Return Value: 2056 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 2057 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 2058 */ 2059 int 2060 AdvResetSCSIBus(sc) 2061 ADW_SOFTC *sc; 2062 { 2063 bus_space_tag_t iot = sc->sc_iot; 2064 bus_space_handle_t ioh = sc->sc_ioh; 2065 int status; 2066 u_int16_t wdtr_able, sdtr_able, tagqng_able; 2067 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 2068 u_int16_t bios_sig; 2069 2070 2071 /* 2072 * Save current per TID negotiated values. 2073 */ 2074 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 2075 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 2076 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 2077 for (tid = 0; tid <= ADW_MAX_TID; tid++) 2078 { 2079 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 2080 max_cmd[tid]); 2081 } 2082 2083 /* 2084 * Force the AdvInitAsc3550/38C0800Driver() function to 2085 * perform a SCSI Bus Reset by clearing the BIOS signature word. 2086 * The initialization functions assumes a SCSI Bus Reset is not 2087 * needed if the BIOS signature word is present. 2088 */ 2089 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); 2090 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, 0); 2091 2092 /* 2093 * Stop chip and reset it. 2094 */ 2095 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 2096 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2097 ADW_CTRL_REG_CMD_RESET); 2098 AdvSleepMilliSecond(100); 2099 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 2100 ADW_CTRL_REG_CMD_WR_IO_REG); 2101 2102 /* 2103 * Reset Adv Library error code, if any, and try 2104 * re-initializing the chip. 2105 */ 2106 if (sc->chip_type == ADV_CHIP_ASC38C0800) { 2107 status = AdvInitAsc38C0800Driver(sc); 2108 } else { 2109 status = AdvInitAsc3550Driver(sc); 2110 } 2111 2112 /* Translate initialization return value to status value. */ 2113 if (status == 0) { 2114 status = ADW_TRUE; 2115 } else { 2116 status = ADW_FALSE; 2117 } 2118 2119 /* 2120 * Restore the BIOS signature word. 2121 */ 2122 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); 2123 2124 /* 2125 * Restore per TID negotiated values. 2126 */ 2127 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); 2128 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); 2129 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); 2130 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 2131 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, 2132 max_cmd[tid]); 2133 } 2134 2135 return status; 2136 } 2137 2138 2139 /* 2140 * Adv Library Interrupt Service Routine 2141 * 2142 * This function is called by a driver's interrupt service routine. 2143 * The function disables and re-enables interrupts. 2144 * 2145 * When a microcode idle command is completed, the ADV_DVC_VAR 2146 * 'idle_cmd_done' field is set to ADW_TRUE. 2147 * 2148 * Note: AdvISR() can be called when interrupts are disabled or even 2149 * when there is no hardware interrupt condition present. It will 2150 * always check for completed idle commands and microcode requests. 2151 * This is an important feature that shouldn't be changed because it 2152 * allows commands to be completed from polling mode loops. 2153 * 2154 * Return: 2155 * ADW_TRUE(1) - interrupt was pending 2156 * ADW_FALSE(0) - no interrupt was pending 2157 */ 2158 int 2159 AdvISR(sc) 2160 ADW_SOFTC *sc; 2161 { 2162 bus_space_tag_t iot = sc->sc_iot; 2163 bus_space_handle_t ioh = sc->sc_ioh; 2164 u_int8_t int_stat; 2165 u_int16_t target_bit; 2166 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 2167 u_int32_t irq_next_pa; 2168 ADW_SCSI_REQ_Q *scsiq; 2169 ADW_CCB *ccb; 2170 // int i; 2171 2172 2173 /* Reading the register clears the interrupt. */ 2174 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 2175 2176 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 2177 ADW_INTR_STATUS_INTRC)) == 0) { 2178 return ADW_FALSE; 2179 } 2180 2181 bus_dmamap_sync(sc->sc_dmat, sc->sc_control->dmamap_xfer, 0, 2182 sc->sc_control->dmamap_xfer->dm_mapsize, 2183 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2184 bus_dmamap_unload(sc->sc_dmat, sc->sc_control->dmamap_xfer); 2185 2186 /* ccb_carr = sc->irq_sp; 2187 for(i=0; i<2 && ccb_carr != ASC_CQ_STOPPER; i++) { 2188 bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, 2189 ccb_carr->dmamap_xfer->dm_mapsize, 2190 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2191 bus_dmamap_unload(sc->sc_dmat, ccb_carr->dmamap_xfer); 2192 ccb_carr = adw_carrier_phys_kv(sc, 2193 ASC_GET_CARRP(ccb_carr->next_vpa)); 2194 } 2195 */ 2196 /* 2197 * Notify the driver of an asynchronous microcode condition by 2198 * calling the ADV_DVC_VAR.async_callback function. The function 2199 * is passed the microcode ASC_MC_INTRB_CODE byte value. 2200 */ 2201 if (int_stat & ADW_INTR_STATUS_INTRB) { 2202 u_int8_t intrb_code; 2203 2204 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_INTRB_CODE, intrb_code); 2205 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2206 sc->carr_pending_cnt != 0) { 2207 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); 2208 if (sc->chip_type == ADV_CHIP_ASC3550) { 2209 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 2210 } 2211 } 2212 2213 if (sc->async_callback != 0) { 2214 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2215 } 2216 } 2217 2218 /* 2219 * Check if the IRQ stopper carrier contains a completed request. 2220 */ 2221 while (((irq_next_pa = sc->irq_sp->next_vpa) & ASC_RQ_DONE) != 0) 2222 { 2223 /* 2224 * Get a pointer to the newly completed ADW_SCSI_REQ_Q structure. 2225 * The RISC will have set 'areq_vpa' to a virtual address. 2226 * 2227 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2228 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion 2229 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr' 2230 * in AdvExeScsiQueue(). 2231 */ 2232 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_vpa); 2233 scsiq = &ccb->scsiq; 2234 scsiq->ccb_ptr = sc->irq_sp->areq_vpa; 2235 2236 /* ccb_carr = ccb->carr_list; 2237 while(ccb_carr != ASC_CQ_STOPPER) { 2238 bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, 2239 ccb_carr->dmamap_xfer->dm_mapsize, 2240 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2241 bus_dmamap_unload(sc->sc_dmat, ccb_carr->dmamap_xfer); 2242 ccb_carr = adw_carrier_phys_kv(sc, 2243 ASC_GET_CARRP(ccb_carr->next_vpa)); 2244 } 2245 2246 bus_dmamap_sync(sc->sc_dmat, sc->irq_sp->dmamap_xfer, 0, 2247 sc->irq_sp->dmamap_xfer->dm_mapsize, 2248 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2249 bus_dmamap_unload(sc->sc_dmat, sc->irq_sp->dmamap_xfer); 2250 */ 2251 /* 2252 * Advance the stopper pointer to the next carrier 2253 * ignoring the lower four bits. Free the previous 2254 * stopper carrier. 2255 */ 2256 free_carrp = sc->irq_sp; 2257 sc->irq_sp = adw_carrier_phys_kv(sc, ASC_GET_CARRP(irq_next_pa)); 2258 2259 free_carrp->next_vpa = sc->carr_freelist->carr_pa; 2260 sc->carr_freelist = free_carrp; 2261 sc->carr_pending_cnt--; 2262 2263 2264 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2265 2266 /* 2267 * Clear request microcode control flag. 2268 */ 2269 scsiq->cntl = 0; 2270 2271 /* 2272 * Check Condition handling 2273 */ 2274 /* 2275 * If the command that completed was a SCSI INQUIRY and 2276 * LUN 0 was sent the command, then process the INQUIRY 2277 * command information for the device. 2278 */ 2279 if (scsiq->done_status == QD_NO_ERROR && 2280 scsiq->cdb[0] == INQUIRY && 2281 scsiq->target_lun == 0) { 2282 AdvInquiryHandling(sc, scsiq); 2283 } 2284 2285 /* 2286 * Notify the driver of the completed request by passing 2287 * the ADW_SCSI_REQ_Q pointer to its callback function. 2288 */ 2289 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2290 /* 2291 * Note: After the driver callback function is called, 'scsiq' 2292 * can no longer be referenced. 2293 * 2294 * Fall through and continue processing other completed 2295 * requests... 2296 */ 2297 } 2298 2299 return ADW_TRUE; 2300 } 2301 2302 2303 /* 2304 * Send an idle command to the chip and wait for completion. 2305 * 2306 * Command completion is polled for once per microsecond. 2307 * 2308 * The function can be called from anywhere including an interrupt handler. 2309 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() 2310 * functions to prevent reentrancy. 2311 * 2312 * Return Values: 2313 * ADW_TRUE - command completed successfully 2314 * ADW_FALSE - command failed 2315 * ADW_ERROR - command timed out 2316 */ 2317 int 2318 AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 2319 ADW_SOFTC *sc; 2320 u_int16_t idle_cmd; 2321 u_int32_t idle_cmd_parameter; 2322 { 2323 bus_space_tag_t iot = sc->sc_iot; 2324 bus_space_handle_t ioh = sc->sc_ioh; 2325 int result; 2326 u_int32_t i, j; 2327 2328 2329 /* 2330 * Clear the idle command status which is set by the microcode 2331 * to a non-zero value to indicate when the command is completed. 2332 * The non-zero result is one of the IDLE_CMD_STATUS_* values 2333 * defined in a_advlib.h. 2334 */ 2335 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2336 2337 /* 2338 * Write the idle command value after the idle command parameter 2339 * has been written to avoid a race condition. If the order is not 2340 * followed, the microcode may process the idle command before the 2341 * parameters have been written to LRAM. 2342 */ 2343 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_PARAMETER, 2344 idle_cmd_parameter); 2345 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD, idle_cmd); 2346 2347 /* 2348 * Tickle the RISC to tell it to process the idle command. 2349 */ 2350 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_B); 2351 if (sc->chip_type == ADV_CHIP_ASC3550) { 2352 /* 2353 * Clear the tickle value. In the ASC-3550 the RISC flag 2354 * command 'clr_tickle_b' does not work unless the host 2355 * value is cleared. 2356 */ 2357 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); 2358 } 2359 2360 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2361 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2362 /* Poll once each microsecond for command completion. */ 2363 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2364 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, result); 2365 if (result != 0) { 2366 return result; 2367 } 2368 AdvDelayMicroSecond(1); 2369 } 2370 } 2371 2372 return ADW_ERROR; 2373 } 2374 2375 2376 /* 2377 * Inquiry Information Byte 7 Handling 2378 * 2379 * Handle SCSI Inquiry Command information for a device by setting 2380 * microcode operating variables that affect WDTR, SDTR, and Tag 2381 * Queuing. 2382 */ 2383 static void 2384 AdvInquiryHandling(sc, scsiq) 2385 ADW_SOFTC *sc; 2386 ADW_SCSI_REQ_Q *scsiq; 2387 { 2388 #ifndef FAILSAFE 2389 bus_space_tag_t iot = sc->sc_iot; 2390 bus_space_handle_t ioh = sc->sc_ioh; 2391 u_int8_t tid; 2392 ADW_SCSI_INQUIRY *inq; 2393 u_int16_t tidmask; 2394 u_int16_t cfg_word; 2395 2396 2397 /* 2398 * AdvInquiryHandling() requires up to INQUIRY information Byte 7 2399 * to be available. 2400 * 2401 * If less than 8 bytes of INQUIRY information were requested or less 2402 * than 8 bytes were transferred, then return. cdb[4] is the request 2403 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2404 * microcode to the transfer residual count. 2405 */ 2406 2407 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2408 return; 2409 } 2410 2411 tid = scsiq->target_id; 2412 2413 inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; 2414 2415 /* 2416 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2417 */ 2418 if (inq->rsp_data_fmt < 2 && inq->ansi_apr_ver < 2) { 2419 return; 2420 } else { 2421 /* 2422 * INQUIRY Byte 7 Handling 2423 * 2424 * Use a device's INQUIRY byte 7 to determine whether it 2425 * supports WDTR, SDTR, and Tag Queuing. If the feature 2426 * is enabled in the EEPROM and the device supports the 2427 * feature, then enable it in the microcode. 2428 */ 2429 2430 tidmask = ADW_TID_TO_TIDMASK(tid); 2431 2432 /* 2433 * Wide Transfers 2434 * 2435 * If the EEPROM enabled WDTR for the device and the device 2436 * supports wide bus (16 bit) transfers, then turn on the 2437 * device's 'wdtr_able' bit and write the new value to the 2438 * microcode. 2439 */ 2440 #ifdef SCSI_ADW_WDTR_DISABLE 2441 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2442 #endif /* SCSI_ADW_WDTR_DISABLE */ 2443 if ((sc->wdtr_able & tidmask) && inq->WBus16) { 2444 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 2445 cfg_word); 2446 if ((cfg_word & tidmask) == 0) { 2447 cfg_word |= tidmask; 2448 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 2449 cfg_word); 2450 2451 /* 2452 * Clear the microcode "SDTR negotiation" and "WDTR 2453 * negotiation" done indicators for the target to cause 2454 * it to negotiate with the new setting set above. 2455 * WDTR when accepted causes the target to enter 2456 * asynchronous mode, so SDTR must be negotiated. 2457 */ 2458 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 2459 cfg_word); 2460 cfg_word &= ~tidmask; 2461 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 2462 cfg_word); 2463 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 2464 cfg_word); 2465 cfg_word &= ~tidmask; 2466 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 2467 cfg_word); 2468 } 2469 } 2470 2471 /* 2472 * Synchronous Transfers 2473 * 2474 * If the EEPROM enabled SDTR for the device and the device 2475 * supports synchronous transfers, then turn on the device's 2476 * 'sdtr_able' bit. Write the new value to the microcode. 2477 */ 2478 #ifdef SCSI_ADW_SDTR_DISABLE 2479 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2480 #endif /* SCSI_ADW_SDTR_DISABLE */ 2481 if ((sc->sdtr_able & tidmask) && inq->Sync) { 2482 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, cfg_word); 2483 if ((cfg_word & tidmask) == 0) { 2484 cfg_word |= tidmask; 2485 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 2486 cfg_word); 2487 2488 /* 2489 * Clear the microcode "SDTR negotiation" done indicator 2490 * for the target to cause it to negotiate with the new 2491 * setting set above. 2492 */ 2493 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 2494 cfg_word); 2495 cfg_word &= ~tidmask; 2496 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 2497 cfg_word); 2498 } 2499 } 2500 2501 /* 2502 * If the EEPROM enabled Tag Queuing for the device and the 2503 * device supports Tag Queueing, then turn on the device's 2504 * 'tagqng_enable' bit in the microcode and set the microcode 2505 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2506 * value. 2507 * 2508 * Tag Queuing is disabled for the BIOS which runs in polled 2509 * mode and would see no benefit from Tag Queuing. Also by 2510 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2511 * bugs will at least work with the BIOS. 2512 */ 2513 #ifdef SCSI_ADW_TAGQ_DISABLE 2514 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2515 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2516 if ((sc->tagqng_able & tidmask) && inq->CmdQue) { 2517 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 2518 cfg_word); 2519 cfg_word |= tidmask; 2520 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 2521 cfg_word); 2522 2523 ADW_WRITE_BYTE_LRAM(iot, ioh, 2524 ASC_MC_NUMBER_OF_MAX_CMD + tid, 2525 sc->max_dvc_qng); 2526 } 2527 } 2528 #endif /* FAILSAFE */ 2529 } 2530 2531 2532 static void 2533 AdvSleepMilliSecond(n) 2534 u_int32_t n; 2535 { 2536 2537 DELAY(n * 1000); 2538 } 2539 2540 2541 static void 2542 AdvDelayMicroSecond(n) 2543 u_int32_t n; 2544 { 2545 2546 DELAY(n); 2547 } 2548 2549
Indexes created Sun Sep 21 20:09:37 GMT 2025