adwlib.h revision 1.10
1 /* $NetBSD: adwlib.h,v 1.10 2000/05/10 21:22:34 dante Exp $ */ 2 3 /* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-2000 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55 #ifndef _ADVANSYS_WIDE_LIBRARY_H_ 56 #define _ADVANSYS_WIDE_LIBRARY_H_ 57 58 59 /* 60 * --- Adv Library Constants and Macros 61 */ 62 63 #define ADW_LIB_VERSION_MAJOR 5 64 #define ADW_LIB_VERSION_MINOR 8 65 66 67 /* If the result wraps when calculating tenths, return 0. */ 68 #define ADW_TENTHS(num, den) \ 69 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 70 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 71 72 73 /* 74 * Define Adv Reset Hold Time grater than 25 uSec. 75 * See AdvResetSCSIBus() for more info. 76 */ 77 #define ASC_SCSI_RESET_HOLD_TIME_US 60 78 79 /* 80 * Define Adv EEPROM constants. 81 */ 82 83 #define ASC_EEP_DVC_CFG_BEGIN (0x00) 84 #define ASC_EEP_DVC_CFG_END (0x15) 85 #define ASC_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 86 #define ASC_EEP_MAX_WORD_ADDR (0x1E) 87 88 #define ASC_EEP_DELAY_MS 100 89 90 /* 91 * EEPROM bits reference by the RISC after initialization. 92 */ 93 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 94 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 95 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 96 97 /* 98 * EEPROM configuration format 99 * 100 * Field naming convention: 101 * 102 * *_enable indicates the field enables or disables the feature. The 103 * value is never reset. 104 * 105 * *_able indicates both whether a feature should be enabled or disabled 106 * and whether a device isi capable of the feature. At initialization 107 * this field may be set, but later if a device is found to be incapable 108 * of the feature, the field is cleared. 109 * 110 * Default values are maintained in the structure Default_EEPROM_Config. 111 */ 112 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 113 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 114 /* 115 * For the ASC3550 Bit 13 is Termination Polarity control bit. 116 * For later ICs Bit 13 controls whether the CIS (Card Information 117 * Service Section) is loaded from EEPROM. 118 */ 119 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 120 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 121 122 /* 123 * ASC38C1600 Bit 11 124 * 125 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 126 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 127 * Function 0 will specify INT B. 128 * 129 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 130 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 131 * Function 1 will specify INT A. 132 */ 133 #define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 134 135 typedef struct adw_eep_3550_config 136 { 137 /* Word Offset, Description */ 138 139 u_int16_t cfg_lsw; /* 00 power up initialization */ 140 /* bit 13 set - Term Polarity Control */ 141 /* bit 14 set - BIOS Enable */ 142 /* bit 15 set - Big Endian Mode */ 143 u_int16_t cfg_msw; /* 01 unused */ 144 u_int16_t disc_enable; /* 02 disconnect enable */ 145 u_int16_t wdtr_able; /* 03 Wide DTR able */ 146 u_int16_t sdtr_able; /* 04 Synchronous DTR able */ 147 u_int16_t start_motor; /* 05 send start up motor */ 148 u_int16_t tagqng_able; /* 06 tag queuing able */ 149 u_int16_t bios_scan; /* 07 BIOS device control */ 150 u_int16_t scam_tolerant; /* 08 no scam */ 151 152 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 153 u_int8_t bios_boot_delay; /* power up wait */ 154 155 u_int8_t scsi_reset_delay; /* 10 reset delay */ 156 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 157 /* high nibble is lun */ 158 /* low nibble is scsi id */ 159 160 u_int8_t termination; /* 11 0 - automatic */ 161 /* 1 - low off / high off */ 162 /* 2 - low off / high on */ 163 /* 3 - low on / high on */ 164 /* There is no low on / high off */ 165 166 u_int8_t reserved1; /* reserved byte (not used) */ 167 168 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 169 /* bit 0 BIOS don't act as initiator. */ 170 /* bit 1 BIOS > 1 GB support */ 171 /* bit 2 BIOS > 2 Disk Support */ 172 /* bit 3 BIOS don't support removables */ 173 /* bit 4 BIOS support bootable CD */ 174 /* bit 5 BIOS scan enabled */ 175 /* bit 6 BIOS support multiple LUNs */ 176 /* bit 7 BIOS display of message */ 177 /* bit 8 SCAM disabled */ 178 /* bit 9 Reset SCSI bus during init. */ 179 /* bit 10 */ 180 /* bit 11 No verbose initialization. */ 181 /* bit 12 SCSI parity enabled */ 182 /* bit 13 */ 183 /* bit 14 */ 184 /* bit 15 */ 185 u_int16_t ultra_able; /* 13 ULTRA speed able */ 186 u_int16_t reserved2; /* 14 reserved */ 187 u_int8_t max_host_qng; /* 15 maximum host queuing */ 188 u_int8_t max_dvc_qng; /* maximum per device queuing */ 189 u_int16_t dvc_cntl; /* 16 control bit for driver */ 190 u_int16_t bug_fix; /* 17 control bit for bug fix */ 191 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 192 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 193 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 194 u_int16_t check_sum; /* 21 EEP check sum */ 195 u_int8_t oem_name[16]; /* 22 OEM name */ 196 u_int16_t dvc_err_code; /* 30 last device driver error code */ 197 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 198 u_int16_t adv_err_addr; /* 32 last uc error address */ 199 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 200 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 201 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 202 u_int16_t num_of_err; /* 36 number of error */ 203 } ADW_EEP_3550_CONFIG; 204 205 typedef struct adw_eep_38C0800_config 206 { 207 /* Word Offset, Description */ 208 209 u_int16_t cfg_lsw; /* 00 power up initialization */ 210 /* bit 13 set - Load CIS */ 211 /* bit 14 set - BIOS Enable */ 212 /* bit 15 set - Big Endian Mode */ 213 u_int16_t cfg_msw; /* 01 unused */ 214 u_int16_t disc_enable; /* 02 disconnect enable */ 215 u_int16_t wdtr_able; /* 03 Wide DTR able */ 216 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 217 u_int16_t start_motor; /* 05 send start up motor */ 218 u_int16_t tagqng_able; /* 06 tag queuing able */ 219 u_int16_t bios_scan; /* 07 BIOS device control */ 220 u_int16_t scam_tolerant; /* 08 no scam */ 221 222 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 223 u_int8_t bios_boot_delay; /* power up wait */ 224 225 u_int8_t scsi_reset_delay; /* 10 reset delay */ 226 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 227 /* high nibble is lun */ 228 /* low nibble is scsi id */ 229 230 u_int8_t termination_se; /* 11 0 - automatic */ 231 /* 1 - low off / high off */ 232 /* 2 - low off / high on */ 233 /* 3 - low on / high on */ 234 /* There is no low on / high off */ 235 236 u_int8_t termination_lvd; /* 11 0 - automatic */ 237 /* 1 - low off / high off */ 238 /* 2 - low off / high on */ 239 /* 3 - low on / high on */ 240 /* There is no low on / high off */ 241 242 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 243 /* bit 0 BIOS don't act as initiator. */ 244 /* bit 1 BIOS > 1 GB support */ 245 /* bit 2 BIOS > 2 Disk Support */ 246 /* bit 3 BIOS don't support removables */ 247 /* bit 4 BIOS support bootable CD */ 248 /* bit 5 BIOS scan enabled */ 249 /* bit 6 BIOS support multiple LUNs */ 250 /* bit 7 BIOS display of message */ 251 /* bit 8 SCAM disabled */ 252 /* bit 9 Reset SCSI bus during init. */ 253 /* bit 10 */ 254 /* bit 11 No verbose initialization. */ 255 /* bit 12 SCSI parity enabled */ 256 /* bit 13 */ 257 /* bit 14 */ 258 /* bit 15 */ 259 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 260 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 261 u_int8_t max_host_qng; /* 15 maximum host queueing */ 262 u_int8_t max_dvc_qng; /* maximum per device queuing */ 263 u_int16_t dvc_cntl; /* 16 control bit for driver */ 264 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 265 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 266 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 267 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 268 u_int16_t check_sum; /* 21 EEP check sum */ 269 u_int8_t oem_name[16]; /* 22 OEM name */ 270 u_int16_t dvc_err_code; /* 30 last device driver error code */ 271 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 272 u_int16_t adv_err_addr; /* 32 last uc error address */ 273 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 274 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 275 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 276 u_int16_t reserved36; /* 36 reserved */ 277 u_int16_t reserved37; /* 37 reserved */ 278 u_int16_t reserved38; /* 38 reserved */ 279 u_int16_t reserved39; /* 39 reserved */ 280 u_int16_t reserved40; /* 40 reserved */ 281 u_int16_t reserved41; /* 41 reserved */ 282 u_int16_t reserved42; /* 42 reserved */ 283 u_int16_t reserved43; /* 43 reserved */ 284 u_int16_t reserved44; /* 44 reserved */ 285 u_int16_t reserved45; /* 45 reserved */ 286 u_int16_t reserved46; /* 46 reserved */ 287 u_int16_t reserved47; /* 47 reserved */ 288 u_int16_t reserved48; /* 48 reserved */ 289 u_int16_t reserved49; /* 49 reserved */ 290 u_int16_t reserved50; /* 50 reserved */ 291 u_int16_t reserved51; /* 51 reserved */ 292 u_int16_t reserved52; /* 52 reserved */ 293 u_int16_t reserved53; /* 53 reserved */ 294 u_int16_t reserved54; /* 54 reserved */ 295 u_int16_t reserved55; /* 55 reserved */ 296 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 297 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 298 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 299 u_int16_t subsysid; /* 59 SubSystem ID */ 300 u_int16_t reserved60; /* 60 reserved */ 301 u_int16_t reserved61; /* 61 reserved */ 302 u_int16_t reserved62; /* 62 reserved */ 303 u_int16_t reserved63; /* 63 reserved */ 304 } ADW_EEP_38C0800_CONFIG; 305 306 typedef struct adw_eep_38C1600_config 307 { 308 /* Word Offset, Description */ 309 310 u_int16_t cfg_lsw; /* 00 power up initialization */ 311 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ 312 /* clear - Func. 0 INTA, Func. 1 INTB */ 313 /* bit 13 set - Load CIS */ 314 /* bit 14 set - BIOS Enable */ 315 /* bit 15 set - Big Endian Mode */ 316 u_int16_t cfg_msw; /* 01 unused */ 317 u_int16_t disc_enable; /* 02 disconnect enable */ 318 u_int16_t wdtr_able; /* 03 Wide DTR able */ 319 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 320 u_int16_t start_motor; /* 05 send start up motor */ 321 u_int16_t tagqng_able; /* 06 tag queuing able */ 322 u_int16_t bios_scan; /* 07 BIOS device control */ 323 u_int16_t scam_tolerant; /* 08 no scam */ 324 325 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 326 u_int8_t bios_boot_delay; /* power up wait */ 327 328 u_int8_t scsi_reset_delay; /* 10 reset delay */ 329 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 330 /* high nibble is lun */ 331 /* low nibble is scsi id */ 332 333 u_int8_t termination_se; /* 11 0 - automatic */ 334 /* 1 - low off / high off */ 335 /* 2 - low off / high on */ 336 /* 3 - low on / high on */ 337 /* There is no low on / high off */ 338 339 u_int8_t termination_lvd; /* 11 0 - automatic */ 340 /* 1 - low off / high off */ 341 /* 2 - low off / high on */ 342 /* 3 - low on / high on */ 343 /* There is no low on / high off */ 344 345 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 346 /* bit 0 BIOS don't act as initiator. */ 347 /* bit 1 BIOS > 1 GB support */ 348 /* bit 2 BIOS > 2 Disk Support */ 349 /* bit 3 BIOS don't support removables */ 350 /* bit 4 BIOS support bootable CD */ 351 /* bit 5 BIOS scan enabled */ 352 /* bit 6 BIOS support multiple LUNs */ 353 /* bit 7 BIOS display of message */ 354 /* bit 8 SCAM disabled */ 355 /* bit 9 Reset SCSI bus during init. */ 356 /* bit 10 Basic Integrity Checking disabled */ 357 /* bit 11 No verbose initialization. */ 358 /* bit 12 SCSI parity enabled */ 359 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ 360 /* bit 14 */ 361 /* bit 15 */ 362 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 363 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 364 u_int8_t max_host_qng; /* 15 maximum host queueing */ 365 u_int8_t max_dvc_qng; /* maximum per device queuing */ 366 u_int16_t dvc_cntl; /* 16 control bit for driver */ 367 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 368 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 369 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 370 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 371 u_int16_t check_sum; /* 21 EEP check sum */ 372 u_int8_t oem_name[16]; /* 22 OEM name */ 373 u_int16_t dvc_err_code; /* 30 last device driver error code */ 374 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 375 u_int16_t adv_err_addr; /* 32 last uc error address */ 376 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 377 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 378 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 379 u_int16_t reserved36; /* 36 reserved */ 380 u_int16_t reserved37; /* 37 reserved */ 381 u_int16_t reserved38; /* 38 reserved */ 382 u_int16_t reserved39; /* 39 reserved */ 383 u_int16_t reserved40; /* 40 reserved */ 384 u_int16_t reserved41; /* 41 reserved */ 385 u_int16_t reserved42; /* 42 reserved */ 386 u_int16_t reserved43; /* 43 reserved */ 387 u_int16_t reserved44; /* 44 reserved */ 388 u_int16_t reserved45; /* 45 reserved */ 389 u_int16_t reserved46; /* 46 reserved */ 390 u_int16_t reserved47; /* 47 reserved */ 391 u_int16_t reserved48; /* 48 reserved */ 392 u_int16_t reserved49; /* 49 reserved */ 393 u_int16_t reserved50; /* 50 reserved */ 394 u_int16_t reserved51; /* 51 reserved */ 395 u_int16_t reserved52; /* 52 reserved */ 396 u_int16_t reserved53; /* 53 reserved */ 397 u_int16_t reserved54; /* 54 reserved */ 398 u_int16_t reserved55; /* 55 reserved */ 399 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 400 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 401 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 402 u_int16_t subsysid; /* 59 SubSystem ID */ 403 u_int16_t reserved60; /* 60 reserved */ 404 u_int16_t reserved61; /* 61 reserved */ 405 u_int16_t reserved62; /* 62 reserved */ 406 u_int16_t reserved63; /* 63 reserved */ 407 } ADW_EEP_38C1600_CONFIG; 408 409 410 /* 411 * EEPROM Commands 412 */ 413 #define ASC_EEP_CMD_READ 0x80 414 #define ASC_EEP_CMD_WRITE 0x40 415 #define ASC_EEP_CMD_WRITE_ABLE 0x30 416 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 417 418 #define ASC_EEP_CMD_DONE 0x0200 419 #define ASC_EEP_CMD_DONE_ERR 0x0001 420 421 /* cfg_word */ 422 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000 423 424 /* bios_ctrl */ 425 #define BIOS_CTRL_BIOS 0x0001 426 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 427 #define BIOS_CTRL_GT_2_DISK 0x0004 428 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 429 #define BIOS_CTRL_BOOTABLE_CD 0x0010 430 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 431 #define BIOS_CTRL_DISPLAY_MSG 0x0080 432 #define BIOS_CTRL_NO_SCAM 0x0100 433 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 434 #define BIOS_CTRL_INIT_VERBOSE 0x0800 435 #define BIOS_CTRL_SCSI_PARITY 0x1000 436 #define BIOS_CTRL_AIPP_DIS 0x2000 437 438 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 439 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */ 440 441 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 442 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ 443 444 #define ADV_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */ 445 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ 446 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ 447 448 /* 449 * Byte I/O register address from base of 'iop_base'. 450 */ 451 #define IOPB_INTR_STATUS_REG 0x00 452 #define IOPB_CHIP_ID_1 0x01 453 #define IOPB_INTR_ENABLES 0x02 454 #define IOPB_CHIP_TYPE_REV 0x03 455 #define IOPB_RES_ADDR_4 0x04 456 #define IOPB_RES_ADDR_5 0x05 457 #define IOPB_RAM_DATA 0x06 458 #define IOPB_RES_ADDR_7 0x07 459 #define IOPB_FLAG_REG 0x08 460 #define IOPB_RES_ADDR_9 0x09 461 #define IOPB_RISC_CSR 0x0A 462 #define IOPB_RES_ADDR_B 0x0B 463 #define IOPB_RES_ADDR_C 0x0C 464 #define IOPB_RES_ADDR_D 0x0D 465 #define IOPB_SOFT_OVER_WR 0x0E 466 #define IOPB_RES_ADDR_F 0x0F 467 #define IOPB_MEM_CFG 0x10 468 #define IOPB_RES_ADDR_11 0x11 469 #define IOPB_GPIO_DATA 0x12 470 #define IOPB_RES_ADDR_13 0x13 471 #define IOPB_FLASH_PAGE 0x14 472 #define IOPB_RES_ADDR_15 0x15 473 #define IOPB_GPIO_CNTL 0x16 474 #define IOPB_RES_ADDR_17 0x17 475 #define IOPB_FLASH_DATA 0x18 476 #define IOPB_RES_ADDR_19 0x19 477 #define IOPB_RES_ADDR_1A 0x1A 478 #define IOPB_RES_ADDR_1B 0x1B 479 #define IOPB_RES_ADDR_1C 0x1C 480 #define IOPB_RES_ADDR_1D 0x1D 481 #define IOPB_RES_ADDR_1E 0x1E 482 #define IOPB_RES_ADDR_1F 0x1F 483 #define IOPB_DMA_CFG0 0x20 484 #define IOPB_DMA_CFG1 0x21 485 #define IOPB_TICKLE 0x22 486 #define IOPB_DMA_REG_WR 0x23 487 #define IOPB_SDMA_STATUS 0x24 488 #define IOPB_SCSI_BYTE_CNT 0x25 489 #define IOPB_HOST_BYTE_CNT 0x26 490 #define IOPB_BYTE_LEFT_TO_XFER 0x27 491 #define IOPB_BYTE_TO_XFER_0 0x28 492 #define IOPB_BYTE_TO_XFER_1 0x29 493 #define IOPB_BYTE_TO_XFER_2 0x2A 494 #define IOPB_BYTE_TO_XFER_3 0x2B 495 #define IOPB_ACC_GRP 0x2C 496 #define IOPB_RES_ADDR_2D 0x2D 497 #define IOPB_DEV_ID 0x2E 498 #define IOPB_RES_ADDR_2F 0x2F 499 #define IOPB_SCSI_DATA 0x30 500 #define IOPB_RES_ADDR_31 0x31 501 #define IOPB_RES_ADDR_32 0x32 502 #define IOPB_SCSI_DATA_HSHK 0x33 503 #define IOPB_SCSI_CTRL 0x34 504 #define IOPB_RES_ADDR_35 0x35 505 #define IOPB_RES_ADDR_36 0x36 506 #define IOPB_RES_ADDR_37 0x37 507 #define IOPB_RAM_BIST 0x38 508 #define IOPB_PLL_TEST 0x39 509 #define IOPB_PCI_INT_CFG 0x3A 510 #define IOPB_RES_ADDR_3B 0x3B 511 #define IOPB_RFIFO_CNT 0x3C 512 #define IOPB_RES_ADDR_3D 0x3D 513 #define IOPB_RES_ADDR_3E 0x3E 514 #define IOPB_RES_ADDR_3F 0x3F 515 516 /* 517 * Word I/O register address from base of 'iop_base'. 518 */ 519 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 520 #define IOPW_CTRL_REG 0x02 /* CC */ 521 #define IOPW_RAM_ADDR 0x04 /* LA */ 522 #define IOPW_RAM_DATA 0x06 /* LD */ 523 #define IOPW_RES_ADDR_08 0x08 524 #define IOPW_RISC_CSR 0x0A /* CSR */ 525 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 526 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 527 #define IOPW_RES_ADDR_10 0x10 528 #define IOPW_SEL_MASK 0x12 /* SM */ 529 #define IOPW_RES_ADDR_14 0x14 530 #define IOPW_FLASH_ADDR 0x16 /* FA */ 531 #define IOPW_RES_ADDR_18 0x18 532 #define IOPW_EE_CMD 0x1A /* EC */ 533 #define IOPW_EE_DATA 0x1C /* ED */ 534 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 535 #define IOPW_RES_ADDR_20 0x20 536 #define IOPW_Q_BASE 0x22 /* QB */ 537 #define IOPW_QP 0x24 /* QP */ 538 #define IOPW_IX 0x26 /* IX */ 539 #define IOPW_SP 0x28 /* SP */ 540 #define IOPW_PC 0x2A /* PC */ 541 #define IOPW_RES_ADDR_2C 0x2C 542 #define IOPW_RES_ADDR_2E 0x2E 543 #define IOPW_SCSI_DATA 0x30 /* SD */ 544 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 545 #define IOPW_SCSI_CTRL 0x34 /* SC */ 546 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 547 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 548 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 549 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 550 #define IOPW_RES_ADDR_3C 0x3C 551 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 552 553 /* 554 * Doubleword I/O register address from base of 'iop_base'. 555 */ 556 #define IOPDW_RES_ADDR_0 0x00 557 #define IOPDW_RAM_DATA 0x04 558 #define IOPDW_RES_ADDR_8 0x08 559 #define IOPDW_RES_ADDR_C 0x0C 560 #define IOPDW_RES_ADDR_10 0x10 561 #define IOPDW_COMMA 0x14 562 #define IOPDW_COMMB 0x18 563 #define IOPDW_RES_ADDR_1C 0x1C 564 #define IOPDW_SDMA_ADDR0 0x20 565 #define IOPDW_SDMA_ADDR1 0x24 566 #define IOPDW_SDMA_COUNT 0x28 567 #define IOPDW_SDMA_ERROR 0x2C 568 #define IOPDW_RDMA_ADDR0 0x30 569 #define IOPDW_RDMA_ADDR1 0x34 570 #define IOPDW_RDMA_COUNT 0x38 571 #define IOPDW_RDMA_ERROR 0x3C 572 573 #define ADW_CHIP_ID_BYTE 0x25 574 #define ADW_CHIP_ID_WORD 0x04C1 575 576 #define ADW_SC_SCSI_BUS_RESET 0x2000 577 578 #define ADW_INTR_ENABLE_HOST_INTR 0x01 579 #define ADW_INTR_ENABLE_SEL_INTR 0x02 580 #define ADW_INTR_ENABLE_DPR_INTR 0x04 581 #define ADW_INTR_ENABLE_RTA_INTR 0x08 582 #define ADW_INTR_ENABLE_RMA_INTR 0x10 583 #define ADW_INTR_ENABLE_RST_INTR 0x20 584 #define ADW_INTR_ENABLE_DPE_INTR 0x40 585 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 586 587 #define ADW_INTR_STATUS_INTRA 0x01 588 #define ADW_INTR_STATUS_INTRB 0x02 589 #define ADW_INTR_STATUS_INTRC 0x04 590 591 #define ADW_RISC_CSR_STOP (0x0000) 592 #define ADW_RISC_TEST_COND (0x2000) 593 #define ADW_RISC_CSR_RUN (0x4000) 594 #define ADW_RISC_CSR_SINGLE_STEP (0x8000) 595 596 #define ADW_CTRL_REG_HOST_INTR 0x0100 597 #define ADW_CTRL_REG_SEL_INTR 0x0200 598 #define ADW_CTRL_REG_DPR_INTR 0x0400 599 #define ADW_CTRL_REG_RTA_INTR 0x0800 600 #define ADW_CTRL_REG_RMA_INTR 0x1000 601 #define ADW_CTRL_REG_RES_BIT14 0x2000 602 #define ADW_CTRL_REG_DPE_INTR 0x4000 603 #define ADW_CTRL_REG_POWER_DONE 0x8000 604 #define ADW_CTRL_REG_ANY_INTR 0xFF00 605 606 #define ADW_CTRL_REG_CMD_RESET 0x00C6 607 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 608 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 609 #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 610 #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 611 612 #define ADV_TICKLE_NOP 0x00 613 #define ADV_TICKLE_A 0x01 614 #define ADV_TICKLE_B 0x02 615 #define ADV_TICKLE_C 0x03 616 617 #define ADW_SCSI_CTRL_RSTOUT 0x2000 618 619 #define ADW_IS_INT_PENDING(iot, ioh) \ 620 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) 621 622 /* 623 * SCSI_CFG0 Register bit definitions 624 */ 625 #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 626 #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 627 #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */ 628 #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 629 #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 630 #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */ 631 #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */ 632 #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 633 #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 634 #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 635 #define ADW_OUR_ID 0x000F /* SCSI ID */ 636 637 /* 638 * SCSI_CFG1 Register bit definitions 639 */ 640 #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 641 #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 642 #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 643 #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */ 644 #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 645 #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 646 #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 647 #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */ 648 #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 649 #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 650 #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 651 #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */ 652 #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 653 #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 654 #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 655 656 /* 657 * Addendum for ASC-38C0800 Chip 658 * 659 * The ASC-38C1600 Chip uses the same definitions except that the 660 * bus mode override bits [12:10] have been moved to byte register 661 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 662 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 663 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 664 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 665 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 666 */ 667 #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 668 #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 669 #define ADW_HVD 0x1000 /* HVD Device Detect */ 670 #define ADW_LVD 0x0800 /* LVD Device Detect */ 671 #define ADW_SE 0x0400 /* SE Device Detect */ 672 #define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */ 673 #define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 674 #define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 675 #define ADW_TERM_SE 0x0030 /* SE Termination Bits */ 676 #define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 677 #define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 678 #define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 679 #define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 680 #define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 681 #define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */ 682 #define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 683 #define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 684 685 686 #define CABLE_ILLEGAL_A 0x7 687 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 688 689 #define CABLE_ILLEGAL_B 0xB 690 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 691 692 /* 693 The following table details the SCSI_CFG1 Termination Polarity, 694 Termination Control and Cable Detect bits. 695 696 Cable Detect | Termination 697 Bit 3 2 1 0 | 5 4 | Notes 698 _____________|________|____________________ 699 1 1 1 0 | on on | Internal wide only 700 1 1 0 1 | on on | Internal narrow only 701 1 0 1 1 | on on | External narrow only 702 0 x 1 1 | on on | External wide only 703 1 1 0 0 | on off| Internal wide and internal narrow 704 1 0 1 0 | on off| Internal wide and external narrow 705 0 x 1 0 | off off| Internal wide and external wide 706 1 0 0 1 | on off| Internal narrow and external narrow 707 0 x 0 1 | on off| Internal narrow and external wide 708 1 1 1 1 | on on | No devices are attached 709 x 0 0 0 | on on | Illegal (all 3 connectors are used) 710 0 x 0 0 | on on | Illegal (all 3 connectors are used) 711 712 x means don't-care (either '0' or '1') 713 714 If term_pol (bit 13) is '0' (active-low terminator enable), then: 715 'on' is '0' and 'off' is '1'. 716 717 If term_pol bit is '1' (meaning active-hi terminator enable), then: 718 'on' is '1' and 'off' is '0'. 719 */ 720 721 /* 722 * MEM_CFG Register bit definitions 723 */ 724 #define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 725 #define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */ 726 #define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */ 727 #define ADW_RAM_SZ_2KB 0x00 /* 2 KB */ 728 #define ADW_RAM_SZ_4KB 0x04 /* 4 KB */ 729 #define ADW_RAM_SZ_8KB 0x08 /* 8 KB */ 730 #define ADW_RAM_SZ_16KB 0x0C /* 16 KB */ 731 #define ADW_RAM_SZ_32KB 0x10 /* 32 KB */ 732 #define ADW_RAM_SZ_64KB 0x14 /* 64 KB */ 733 734 /* 735 * DMA_CFG0 Register bit definitions 736 * 737 * This register is only accessible to the host. 738 */ 739 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 740 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 741 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 742 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 743 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 744 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 745 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 746 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 747 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 748 #define START_CTL 0x0C /* DMA start conditions */ 749 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 750 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 751 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 752 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 753 #define READ_CMD 0x03 /* Memory Read Method */ 754 #define READ_CMD_MR 0x00 /* Memory Read */ 755 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 756 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 757 758 /* 759 * ASC-38C0800 RAM BIST Register bit definitions 760 */ 761 #define RAM_TEST_MODE 0x80 762 #define PRE_TEST_MODE 0x40 763 #define NORMAL_MODE 0x00 764 #define RAM_TEST_DONE 0x10 765 #define RAM_TEST_STATUS 0x0F 766 #define RAM_TEST_HOST_ERROR 0x08 767 #define RAM_TEST_INTRAM_ERROR 0x04 768 #define RAM_TEST_RISC_ERROR 0x02 769 #define RAM_TEST_SCSI_ERROR 0x01 770 #define RAM_TEST_SUCCESS 0x00 771 #define PRE_TEST_VALUE 0x05 772 #define NORMAL_VALUE 0x00 773 774 /* 775 * ASC38C1600 Definitions 776 * 777 * IOPB_PCI_INT_CFG Bit Field Definitions 778 */ 779 780 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 781 782 /* 783 * Bit 1 can be set to change the interrupt for the Function to operate in 784 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 785 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 786 * mode, otherwise the operating mode is undefined. 787 */ 788 #define TOTEMPOLE 0x02 789 790 /* 791 * Bit 0 can be used to change the Int Pin for the Function. The value is 792 * 0 by default for both Functions with Function 0 using INT A and Function 793 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 794 * INT A is used. 795 * 796 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 797 * value specified in the PCI Configuration Space. 798 */ 799 #define INTAB 0x01 800 801 802 /* 803 * Adv Library Status Definitions 804 */ 805 #define ADW_TRUE 1 806 #define ADW_FALSE 0 807 #define ADW_NOERROR 1 808 #define ADW_SUCCESS 1 809 #define ADW_BUSY 0 810 #define ADW_ERROR (-1) 811 812 813 /* 814 * ASC_DVC_VAR 'warn_code' values 815 */ 816 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 817 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 818 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 819 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ 820 #define ASC_WARN_ERROR 0xFFFF /* ADW_ERROR return */ 821 822 #define ADW_MAX_TID 15 /* max. target identifier */ 823 #define ADW_MAX_LUN 7 /* max. logical unit number */ 824 825 826 /* 827 * AscInitGetConfig() and AscInitAsc1000Driver() Definitions 828 * 829 * Error code values are set in ASC_DVC_VAR 'err_code'. 830 */ 831 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ 832 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 833 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ 834 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 835 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ 836 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 837 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ 838 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 839 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ 840 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ 841 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ 842 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ 843 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ 844 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ 845 846 /* 847 * Fixed locations of microcode operating variables. 848 */ 849 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 850 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 851 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 852 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 853 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 854 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 855 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 856 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 857 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 858 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 859 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 860 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 861 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 862 #define ASC_MC_CHIP_TYPE 0x009A 863 #define ASC_MC_INTRB_CODE 0x009B 864 #define ASC_MC_WDTR_ABLE 0x009C 865 #define ASC_MC_SDTR_ABLE 0x009E 866 #define ASC_MC_TAGQNG_ABLE 0x00A0 867 #define ASC_MC_DISC_ENABLE 0x00A2 868 #define ASC_MC_IDLE_CMD_STATUS 0x00A4 869 #define ASC_MC_IDLE_CMD 0x00A6 870 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 871 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 872 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 873 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 874 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 875 #define ASC_MC_SDTR_DONE 0x00B6 876 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 877 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 878 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 879 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 880 #define ASC_MC_WDTR_DONE 0x0124 881 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 882 #define ASC_MC_ICQ 0x0160 883 #define ASC_MC_IRQ 0x0164 884 #define ASC_MC_PPR_ABLE 0x017A 885 886 /* 887 * BIOS LRAM variable absolute offsets. 888 */ 889 #define BIOS_CODESEG 0x54 890 #define BIOS_CODELEN 0x56 891 #define BIOS_SIGNATURE 0x58 892 #define BIOS_VERSION 0x5A 893 894 /* 895 * Microcode Control Flags 896 * 897 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 898 * and handled by the microcode. 899 */ 900 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 901 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ 902 903 /* 904 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 905 */ 906 #define HSHK_CFG_WIDE_XFR 0x8000 907 #define HSHK_CFG_RATE 0x0F00 908 #define HSHK_CFG_OFFSET 0x001F 909 910 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 911 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 912 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 913 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 914 915 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 916 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 917 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 918 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 919 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ 920 921 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 922 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 923 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 924 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 925 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 926 /* 927 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 928 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 929 */ 930 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 931 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 932 933 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 934 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 935 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 936 937 /* 938 * Adapter temporary configuration structure 939 * 940 * This structure can be discarded after initialization. Don't add 941 * fields here needed after initialization. 942 * 943 * Field naming convention: 944 * 945 * *_enable indicates the field enables or disables a feature. The 946 * value of the field is never reset. 947 */ 948 typedef struct adw_dvc_cfg { 949 u_int16_t disc_enable; /* enable disconnection */ 950 u_int8_t chip_version; /* chip version */ 951 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 952 u_int16_t pci_device_id; /* PCI device code number */ 953 u_int16_t lib_version; /* Adv Library version number */ 954 u_int16_t control_flag; /* Microcode Control Flag */ 955 u_int16_t mcode_date; /* Microcode date */ 956 u_int16_t mcode_version; /* Microcode version */ 957 u_int16_t pci_slot_info; /* high byte device/function number */ 958 /* bits 7-3 device num., bits 2-0 function num. */ 959 /* low byte bus num. */ 960 u_int16_t serial1; /* EEPROM serial number word 1 */ 961 u_int16_t serial2; /* EEPROM serial number word 2 */ 962 u_int16_t serial3; /* EEPROM serial number word 3 */ 963 } ADW_DVC_CFG; 964 965 966 #define NO_OF_SG_PER_BLOCK 15 967 968 typedef struct adw_sg_block { 969 u_int8_t reserved1; 970 u_int8_t reserved2; 971 u_int8_t reserved3; 972 u_int8_t sg_cnt; /* Valid entries in block. */ 973 u_int32_t sg_ptr; /* links to next sg block */ 974 struct { 975 u_int32_t sg_addr; /* SG element address */ 976 u_int32_t sg_count; /* SG element count */ 977 } sg_list[NO_OF_SG_PER_BLOCK]; 978 } ADW_SG_BLOCK; 979 980 981 /* 982 * Adapter operation variable structure. 983 * 984 * One structure is required per host adapter. 985 * 986 * Field naming convention: 987 * 988 * *_able indicates both whether a feature should be enabled or disabled 989 * and whether a device is capable of the feature. At initialization 990 * this field may be set, but later if a device is found to be incapable 991 * of the feature, the field is cleared. 992 */ 993 #define CCB_HASH_SIZE 32 /* hash table size for phystokv */ 994 #define CCB_HASH_SHIFT 9 995 #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) 996 997 typedef int (* ADW_CALLBACK) (int); 998 999 typedef struct adw_softc { 1000 1001 struct device sc_dev; 1002 1003 bus_space_tag_t sc_iot; 1004 bus_space_handle_t sc_ioh; 1005 bus_dma_tag_t sc_dmat; 1006 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 1007 bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */ 1008 void *sc_ih; 1009 1010 struct adw_control *sc_control; /* control structures */ 1011 1012 struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE]; 1013 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; 1014 TAILQ_HEAD(adw_pending_ccb, adw_ccb) sc_pending_ccb; 1015 struct scsipi_link sc_link; /* prototype for devs */ 1016 struct scsipi_adapter sc_adapter; 1017 1018 TAILQ_HEAD(, scsipi_xfer) sc_queue; 1019 1020 ADW_CALLBACK isr_callback; /* pointer to function, called in AdvISR() */ 1021 ADW_CALLBACK async_callback; /* pointer to function, called in AdvISR() */ 1022 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ 1023 u_int16_t wdtr_able; /* try WDTR for a device */ 1024 u_int16_t sdtr_able; /* try SDTR for a device */ 1025 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */ 1026 u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 1027 u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 1028 u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 1029 u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 1030 u_int16_t tagqng_able; /* try tagged queuing with a device */ 1031 u_int16_t ppr_able; /* PPR message capable per TID bitmask. */ 1032 u_int16_t start_motor; /* start motor command allowed */ 1033 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ 1034 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ 1035 u_int8_t chip_no; /* should be assigned by caller */ 1036 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */ 1037 u_int8_t irq_no; /* IRQ number */ 1038 u_int8_t chip_type; /* chip SCSI target ID */ 1039 u_int16_t no_scam; /* scam_tolerant of EEPROM */ 1040 u_int32_t drv_ptr; /* driver pointer to private structure */ 1041 u_int8_t chip_scsi_id; /* chip SCSI target ID */ 1042 u_int8_t bist_err_code; 1043 u_int16_t carr_pending_cnt; /* Count of pending carriers. */ 1044 struct adw_carrier *carr_freelist; /* Carrier free list. */ 1045 struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */ 1046 struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */ 1047 /* 1048 * Note: The following fields will not be used after initialization. The 1049 * driver may discard the buffer after initialization is done. 1050 */ 1051 ADW_DVC_CFG cfg; /* temporary configuration structure */ 1052 } ADW_SOFTC; 1053 1054 1055 /* 1056 * ADW_SCSI_REQ_Q - microcode request structure 1057 * 1058 * All fields in this structure up to byte 60 are used by the microcode. 1059 * The microcode makes assumptions about the size and ordering of fields 1060 * in this structure. Do not change the structure definition here without 1061 * coordinating the change with the microcode. 1062 */ 1063 typedef struct adw_scsi_req_q { 1064 u_int8_t cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 1065 u_int8_t target_cmd; 1066 u_int8_t target_id; /* Device target identifier. */ 1067 u_int8_t target_lun; /* Device target logical unit number. */ 1068 u_int32_t data_addr; /* Data buffer physical address. */ 1069 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 1070 u_int32_t sense_addr; /* Sense buffer physical address. */ 1071 u_int32_t carr_ba; /* Carrier p-address */ 1072 u_int8_t mflag; /* Adv Library flag field. */ 1073 u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */ 1074 u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 1075 u_int8_t scsi_cntl; 1076 u_int8_t done_status; /* Completion status. (see below) */ 1077 u_int8_t scsi_status; /* SCSI status byte. (see below) */ 1078 u_int8_t host_status; /* ,uCode host status. (see below) */ 1079 u_int8_t sg_working_ix; /* ,uCode working SG variable. */ 1080 u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */ 1081 u_int32_t sg_real_addr; /* SG list physical address. */ 1082 u_int32_t scsiq_rptr; /* Iternal pointer to ADW_SCSI_REQ_Q */ 1083 u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */ 1084 u_int32_t ccb_ptr; /* CCB Physical Address */ 1085 u_int32_t carr_va; /* Carrier v-address (unused) */ 1086 /* 1087 * End of microcode structure - 60 bytes. The rest of the structure 1088 * is used by the Adv Library and ignored by the microcode. 1089 */ 1090 struct scsipi_sense_data *vsense_addr; /* Sense buffer virtual address. */ 1091 u_char *vdata_addr; /* Data buffer virtual address. */ 1092 } ADW_SCSI_REQ_Q; 1093 1094 /* 1095 * ASC_SCSI_REQ_Q 'done_status' return values. 1096 */ 1097 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 1098 #define QD_NO_ERROR 0x01 1099 #define QD_ABORTED_BY_HOST 0x02 1100 #define QD_WITH_ERROR 0x04 1101 1102 /* 1103 * ASC_SCSI_REQ_Q 'host_status' return values. 1104 */ 1105 #define QHSTA_NO_ERROR 0x00 1106 #define QHSTA_M_SEL_TIMEOUT 0x11 1107 #define QHSTA_M_DATA_OVER_RUN 0x12 1108 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 1109 #define QHSTA_M_QUEUE_ABORTED 0x15 1110 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 1111 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 1112 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 1113 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 1114 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 1115 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 1116 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 1117 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 1118 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 1119 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 1120 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 1121 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 1122 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 1123 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 1124 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 1125 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 1126 #define QHSTA_M_WTM_TIMEOUT 0x41 1127 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 1128 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 1129 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 1130 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 1131 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 1132 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 1133 1134 /* 1135 * ASC_SCSI_REQ_Q 'scsi_status' return values. 1136 */ 1137 #define SS_GOOD 0x00 1138 #define SS_CHK_CONDITION 0x02 1139 #define SS_CONDITION_MET 0x04 1140 #define SS_TARGET_BUSY 0x08 1141 #define SS_INTERMID 0x10 1142 #define SS_INTERMID_COND_MET 0x14 1143 #define SS_RSERV_CONFLICT 0x18 1144 #define SS_CMD_TERMINATED 0x22 1145 #define SS_QUEUE_FULL 0x28 1146 1147 1148 /* 1149 * Microcode idle loop commands 1150 */ 1151 #define IDLE_CMD_COMPLETED 0 1152 #define IDLE_CMD_STOP_CHIP 0x0001 1153 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 1154 #define IDLE_CMD_SEND_INT 0x0004 1155 #define IDLE_CMD_ABORT 0x0008 1156 #define IDLE_CMD_DEVICE_RESET 0x0010 1157 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 1158 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 1159 #define IDLE_CMD_SCSIREQ 0x0080 1160 1161 #define IDLE_CMD_STATUS_SUCCESS 0x0001 1162 #define IDLE_CMD_STATUS_FAILURE 0x0002 1163 1164 /* 1165 * AdvSendIdleCmd() flag definitions. 1166 */ 1167 #define ADW_NOWAIT 0x01 1168 1169 /* 1170 * Wait loop time out values. 1171 */ 1172 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */ 1173 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 1174 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 1175 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */ 1176 #define SCSI_MAX_RETRY 10 /* retry count */ 1177 1178 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 1179 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 1180 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 1181 1182 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 1183 1184 1185 /* Read byte from a register. */ 1186 #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \ 1187 bus_space_read_1((iot), (ioh), (reg_off)) 1188 1189 /* Write byte to a register. */ 1190 #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \ 1191 bus_space_write_1((iot), (ioh), (reg_off), (byte)) 1192 1193 /* Read word (2 bytes) from a register. */ 1194 #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \ 1195 bus_space_read_2((iot), (ioh), (reg_off)) 1196 1197 /* Write word (2 bytes) to a register. */ 1198 #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ 1199 bus_space_write_2((iot), (ioh), (reg_off), (word)) 1200 1201 /* Write double word (4 bytes) to a register. */ 1202 #define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \ 1203 bus_space_write_4((iot), (ioh), (reg_off), (dword)) 1204 1205 /* Read byte from LRAM. */ 1206 #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ 1207 do { \ 1208 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1209 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \ 1210 } while (0) 1211 1212 /* Write byte to LRAM. */ 1213 #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \ 1214 do { \ 1215 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1216 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \ 1217 } while (0) 1218 1219 /* Read word (2 bytes) from LRAM. */ 1220 #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \ 1221 do { \ 1222 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1223 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \ 1224 } while (0) 1225 1226 /* Write word (2 bytes) to LRAM. */ 1227 #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \ 1228 do { \ 1229 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1230 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \ 1231 } while (0) 1232 1233 /* Write double word (4 bytes) to LRAM */ 1234 /* Because of unspecified C language ordering don't use auto-increment. */ 1235 #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \ 1236 do { \ 1237 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1238 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 1239 (ushort) ((dword) & 0xFFFF)); \ 1240 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \ 1241 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 1242 (ushort) ((dword >> 16) & 0xFFFF)); \ 1243 } while (0) 1244 1245 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 1246 #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \ 1247 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \ 1248 1249 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 1250 #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \ 1251 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)) 1252 1253 /* 1254 * Define macro to check for Condor signature. 1255 * 1256 * Evaluate to ADW_TRUE if a Condor chip is found the specified port 1257 * address 'iop_base'. Otherwise evalue to ADW_FALSE. 1258 */ 1259 #define ADW_FIND_SIGNATURE(iot, ioh) \ 1260 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \ 1261 ADW_CHIP_ID_BYTE) && \ 1262 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \ 1263 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE) 1264 1265 /* 1266 * Define macro to Return the version number of the chip at 'iop_base'. 1267 * 1268 * The second parameter 'bus_type' is currently unused. 1269 */ 1270 #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \ 1271 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV) 1272 1273 /* 1274 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must 1275 * match the ASC_SCSI_REQ_Q 'srb_ptr' field. 1276 * 1277 * If the request has not yet been sent to the device it will simply be 1278 * aborted from RISC memory. If the request is disconnected it will be 1279 * aborted on reselection by sending an Abort Message to the target ID. 1280 * 1281 * Return value: 1282 * ADW_TRUE(1) - Queue was successfully aborted. 1283 * ADW_FALSE(0) - Queue was not found on the active queue list. 1284 */ 1285 #define ADW_ABORT_CCB(sc, ccb_ptr) \ 1286 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) 1287 1288 /* 1289 * Send a Bus Device Reset Message to the specified target ID. 1290 * 1291 * All outstanding commands will be purged if sending the 1292 * Bus Device Reset Message is successful. 1293 * 1294 * Return Value: 1295 * ADW_TRUE(1) - All requests on the target are purged. 1296 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1297 * are not purged. 1298 */ 1299 #define ADW_RESET_DEVICE(sc, target_id) \ 1300 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) 1301 1302 /* 1303 * SCSI Wide Type definition. 1304 */ 1305 #define ADW_SCSI_BIT_ID_TYPE u_int16_t 1306 1307 /* 1308 * AdvInitScsiTarget() 'cntl_flag' options. 1309 */ 1310 #define ADW_SCAN_LUN 0x01 1311 #define ADW_CAPINFO_NOLUN 0x02 1312 1313 /* 1314 * Convert target id to target id bit mask. 1315 */ 1316 #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) 1317 1318 /* 1319 * SCSI Iquiry structure 1320 */ 1321 #define INQ_CLOCKING_ST_ONLY 0x0 1322 #define INQ_CLOCKING_DT_ONLY 0x1 1323 #define INQ_CLOCKING_ST_AND_DT 0x3 1324 1325 typedef struct { 1326 u_int8_t peri_dvc_type : 5; /* peripheral device type */ 1327 u_int8_t peri_qualifier : 3; /* peripheral qualifier */ 1328 u_int8_t dvc_type_modifier : 7; /* device type modifier (for SCSI I) */ 1329 u_int8_t rmb : 1; /* RMB - removable medium bit */ 1330 u_int8_t ansi_apr_ver : 3; /* ANSI approved version */ 1331 u_int8_t ecma_ver : 3; /* ECMA version */ 1332 u_int8_t iso_ver : 2; /* ISO version */ 1333 u_int8_t rsp_data_fmt : 4; /* response data format */ 1334 /* 0 SCSI 1 */ 1335 /* 1 CCS */ 1336 /* 2 SCSI-2 */ 1337 /* 3-F reserved */ 1338 u_int8_t res1 : 2; /* reserved */ 1339 u_int8_t TemIOP : 1; /* terminate I/O process bit (see 5.6.22) */ 1340 u_int8_t aenc : 1; /* asynch. event notification (processor) */ 1341 u_int8_t add_len; /* additional length */ 1342 u_int8_t res2; /* reserved */ 1343 u_int8_t res3; /* reserved */ 1344 u_int8_t StfRe : 1; /* soft reset implemented */ 1345 u_int8_t CmdQue : 1; /* command queuing */ 1346 u_int8_t res4 : 1; /* reserved */ 1347 u_int8_t Linked : 1; /* linked command for this logical unit */ 1348 u_int8_t Sync : 1; /* synchronous data transfer */ 1349 u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */ 1350 u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */ 1351 u_int8_t RelAdr : 1; /* relative addressing mode */ 1352 u_int8_t vendor_id[8]; /* vendor identification */ 1353 u_int8_t product_id[16]; /* product identification */ 1354 u_int8_t product_rev_level[4]; /* product revision level */ 1355 u_int8_t vendor_specific[20]; /* vendor specific */ 1356 u_int8_t IUS : 1; /* information unit supported */ 1357 u_int8_t QAS : 1; /* quick arbitrate supported */ 1358 u_int8_t Clocking : 2; /* clocking field */ 1359 u_int8_t res5 : 4; /* reserved */ 1360 u_int8_t res6; /* reserved */ 1361 } ADW_SCSI_INQUIRY; /* 58 bytes */ 1362 1363 1364 /* 1365 * Adv Library functions available to drivers. 1366 */ 1367 1368 int AdvInitAsc3550Driver __P((ADW_SOFTC *)); 1369 int AdvInitAsc38C0800Driver __P((ADW_SOFTC *)); 1370 int AdvInitAsc38C1600Driver __P((ADW_SOFTC *)); 1371 int AdvInitFrom3550EEP __P((ADW_SOFTC *)); 1372 int AdvInitFrom38C0800EEP __P((ADW_SOFTC *)); 1373 int AdvInitFrom38C1600EEP __P((ADW_SOFTC *)); 1374 int AdvExeScsiQueue __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 1375 int AdvISR __P((ADW_SOFTC *)); 1376 void AdvResetChip __P((bus_space_tag_t, bus_space_handle_t)); 1377 int AdvSendIdleCmd __P((ADW_SOFTC *, u_int16_t, u_int32_t)); 1378 int AdvResetSCSIBus __P((ADW_SOFTC *)); 1379 int AdvResetCCB __P((ADW_SOFTC *)); 1380 1381 #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */ 1382
Indexes created Wed Sep 24 05:09:52 GMT 2025