adwlib.h revision 1.3
1 /* $NetBSD: adwlib.h,v 1.3 1998/12/09 08:47:18 thorpej Exp $ */ 2 3 /* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-1996 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55 #ifndef _ADVANSYS_WIDE_LIBRARY_H_ 56 #define _ADVANSYS_WIDE_LIBRARY_H_ 57 58 59 /* 60 * --- Adv Library Constants and Macros 61 */ 62 63 #define ADW_LIB_VERSION_MAJOR 3 64 #define ADW_LIB_VERSION_MINOR 45 65 66 /* 67 * Define Adv Reset Hold Time grater than 25 uSec. 68 * See AdvResetSCSIBus() for more info. 69 */ 70 #define ASC_SCSI_RESET_HOLD_TIME_US 60 71 72 /* 73 * Define Adv EEPROM constants. 74 */ 75 76 #define ASC_EEP_DVC_CFG_BEGIN (0x00) 77 #define ASC_EEP_DVC_CFG_END (0x15) 78 #define ASC_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 79 #define ASC_EEP_MAX_WORD_ADDR (0x1E) 80 81 #define ASC_EEP_DELAY_MS 100 82 83 /* 84 * EEPROM bits reference by the RISC after initialization. 85 */ 86 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 87 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 88 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 89 90 /* 91 * EEPROM configuration format 92 * 93 * Field naming convention: 94 * 95 * *_enable indicates the field enables or disables the feature. The 96 * value is never reset. 97 * 98 * *_able indicates both whether a feature should be enabled or disabled 99 * and whether a device isi capable of the feature. At initialization 100 * this field may be set, but later if a device is found to be incapable 101 * of the feature, the field is cleared. 102 * 103 * Default values are maintained in a_init.c in the structure 104 * Default_EEPROM_Config. 105 */ 106 typedef struct adweep_config 107 { 108 /* Word Offset, Description */ 109 110 u_int16_t cfg_lsw; /* 00 power up initialization */ 111 /* bit 13 set - Term Polarity Control */ 112 /* bit 14 set - BIOS Enable */ 113 /* bit 15 set - Big Endian Mode */ 114 u_int16_t cfg_msw; /* 01 unused */ 115 u_int16_t disc_enable; /* 02 disconnect enable */ 116 u_int16_t wdtr_able; /* 03 Wide DTR able */ 117 u_int16_t sdtr_able; /* 04 Synchronous DTR able */ 118 u_int16_t start_motor; /* 05 send start up motor */ 119 u_int16_t tagqng_able; /* 06 tag queuing able */ 120 u_int16_t bios_scan; /* 07 BIOS device control */ 121 u_int16_t scam_tolerant; /* 08 no scam */ 122 123 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 124 u_int8_t bios_boot_delay; /* power up wait */ 125 126 u_int8_t scsi_reset_delay; /* 10 reset delay */ 127 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 128 /* high nibble is lun */ 129 /* low nibble is scsi id */ 130 131 u_int8_t termination; /* 11 0 - automatic */ 132 /* 1 - low off / high off */ 133 /* 2 - low off / high on */ 134 /* 3 - low on / high on */ 135 /* There is no low on / high off */ 136 137 u_int8_t reserved1; /* reserved byte (not used) */ 138 139 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 140 /* bit 0 set: BIOS don't act as initiator. */ 141 /* bit 1 set: BIOS > 1 GB support */ 142 /* bit 2 set: BIOS > 2 Disk Support */ 143 /* bit 3 set: BIOS don't support removables */ 144 /* bit 4 set: BIOS support bootable CD */ 145 /* bit 5 set: */ 146 /* bit 6 set: BIOS support multiple LUNs */ 147 /* bit 7 set: BIOS display of message */ 148 /* bit 8 set: */ 149 /* bit 9 set: Reset SCSI bus during init. */ 150 /* bit 10 set: */ 151 /* bit 11 set: No verbose initialization. */ 152 /* bit 12 set: SCSI parity enabled */ 153 /* bit 13 set: */ 154 /* bit 14 set: */ 155 /* bit 15 set: */ 156 u_int16_t ultra_able; /* 13 ULTRA speed able */ 157 u_int16_t reserved2; /* 14 reserved */ 158 u_int8_t max_host_qng; /* 15 maximum host queuing */ 159 u_int8_t max_dvc_qng; /* maximum per device queuing */ 160 u_int16_t dvc_cntl; /* 16 control bit for driver */ 161 u_int16_t bug_fix; /* 17 control bit for bug fix */ 162 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 163 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 164 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 165 u_int16_t check_sum; /* 21 EEP check sum */ 166 u_int8_t oem_name[16]; /* 22 OEM name */ 167 u_int16_t dvc_err_code; /* 30 last device driver error code */ 168 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 169 u_int16_t adv_err_addr; /* 32 last uc error address */ 170 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 171 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 172 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 173 u_int16_t num_of_err; /* 36 number of error */ 174 } ADWEEP_CONFIG; 175 176 /* 177 * EEPROM Commands 178 */ 179 #define ASC_EEP_CMD_READ 0x80 180 #define ASC_EEP_CMD_WRITE 0x40 181 #define ASC_EEP_CMD_WRITE_ABLE 0x30 182 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 183 184 #define ASC_EEP_CMD_DONE 0x0200 185 #define ASC_EEP_CMD_DONE_ERR 0x0001 186 187 /* cfg_word */ 188 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000 189 190 /* bios_ctrl */ 191 #define BIOS_CTRL_BIOS 0x0001 192 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 193 #define BIOS_CTRL_GT_2_DISK 0x0004 194 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 195 #define BIOS_CTRL_BOOTABLE_CD 0x0010 196 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 197 #define BIOS_CTRL_DISPLAY_MSG 0x0080 198 #define BIOS_CTRL_NO_SCAM 0x0100 199 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 200 #define BIOS_CTRL_INIT_VERBOSE 0x0800 201 #define BIOS_CTRL_SCSI_PARITY 0x1000 202 203 /* 204 * ASC 3550 Internal Memory Size - 8KB 205 */ 206 #define ADW_CONDOR_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 207 208 /* 209 * ASC 3550 I/O Length - 64 bytes 210 */ 211 #define ADW_CONDOR_IOLEN 0x40 /* I/O Port Range in bytes */ 212 213 /* 214 * Byte I/O register address from base of 'iop_base'. 215 */ 216 #define IOPB_INTR_STATUS_REG 0x00 217 #define IOPB_CHIP_ID_1 0x01 218 #define IOPB_INTR_ENABLES 0x02 219 #define IOPB_CHIP_TYPE_REV 0x03 220 #define IOPB_RES_ADDR_4 0x04 221 #define IOPB_RES_ADDR_5 0x05 222 #define IOPB_RAM_DATA 0x06 223 #define IOPB_RES_ADDR_7 0x07 224 #define IOPB_FLAG_REG 0x08 225 #define IOPB_RES_ADDR_9 0x09 226 #define IOPB_RISC_CSR 0x0A 227 #define IOPB_RES_ADDR_B 0x0B 228 #define IOPB_RES_ADDR_C 0x0C 229 #define IOPB_RES_ADDR_D 0x0D 230 #define IOPB_RES_ADDR_E 0x0E 231 #define IOPB_RES_ADDR_F 0x0F 232 #define IOPB_MEM_CFG 0x10 233 #define IOPB_RES_ADDR_11 0x11 234 #define IOPB_RES_ADDR_12 0x12 235 #define IOPB_RES_ADDR_13 0x13 236 #define IOPB_FLASH_PAGE 0x14 237 #define IOPB_RES_ADDR_15 0x15 238 #define IOPB_RES_ADDR_16 0x16 239 #define IOPB_RES_ADDR_17 0x17 240 #define IOPB_FLASH_DATA 0x18 241 #define IOPB_RES_ADDR_19 0x19 242 #define IOPB_RES_ADDR_1A 0x1A 243 #define IOPB_RES_ADDR_1B 0x1B 244 #define IOPB_RES_ADDR_1C 0x1C 245 #define IOPB_RES_ADDR_1D 0x1D 246 #define IOPB_RES_ADDR_1E 0x1E 247 #define IOPB_RES_ADDR_1F 0x1F 248 #define IOPB_DMA_CFG0 0x20 249 #define IOPB_DMA_CFG1 0x21 250 #define IOPB_TICKLE 0x22 251 #define IOPB_DMA_REG_WR 0x23 252 #define IOPB_SDMA_STATUS 0x24 253 #define IOPB_SCSI_BYTE_CNT 0x25 254 #define IOPB_HOST_BYTE_CNT 0x26 255 #define IOPB_BYTE_LEFT_TO_XFER 0x27 256 #define IOPB_BYTE_TO_XFER_0 0x28 257 #define IOPB_BYTE_TO_XFER_1 0x29 258 #define IOPB_BYTE_TO_XFER_2 0x2A 259 #define IOPB_BYTE_TO_XFER_3 0x2B 260 #define IOPB_ACC_GRP 0x2C 261 #define IOPB_RES_ADDR_2D 0x2D 262 #define IOPB_DEV_ID 0x2E 263 #define IOPB_RES_ADDR_2F 0x2F 264 #define IOPB_SCSI_DATA 0x30 265 #define IOPB_RES_ADDR_31 0x31 266 #define IOPB_RES_ADDR_32 0x32 267 #define IOPB_SCSI_DATA_HSHK 0x33 268 #define IOPB_SCSI_CTRL 0x34 269 #define IOPB_RES_ADDR_35 0x35 270 #define IOPB_RES_ADDR_36 0x36 271 #define IOPB_RES_ADDR_37 0x37 272 #define IOPB_RES_ADDR_38 0x38 273 #define IOPB_RES_ADDR_39 0x39 274 #define IOPB_RES_ADDR_3A 0x3A 275 #define IOPB_RES_ADDR_3B 0x3B 276 #define IOPB_RFIFO_CNT 0x3C 277 #define IOPB_RES_ADDR_3D 0x3D 278 #define IOPB_RES_ADDR_3E 0x3E 279 #define IOPB_RES_ADDR_3F 0x3F 280 281 /* 282 * Word I/O register address from base of 'iop_base'. 283 */ 284 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 285 #define IOPW_CTRL_REG 0x02 /* CC */ 286 #define IOPW_RAM_ADDR 0x04 /* LA */ 287 #define IOPW_RAM_DATA 0x06 /* LD */ 288 #define IOPW_RES_ADDR_08 0x08 289 #define IOPW_RISC_CSR 0x0A /* CSR */ 290 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 291 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 292 #define IOPW_RES_ADDR_10 0x10 293 #define IOPW_SEL_MASK 0x12 /* SM */ 294 #define IOPW_RES_ADDR_14 0x14 295 #define IOPW_FLASH_ADDR 0x16 /* FA */ 296 #define IOPW_RES_ADDR_18 0x18 297 #define IOPW_EE_CMD 0x1A /* EC */ 298 #define IOPW_EE_DATA 0x1C /* ED */ 299 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 300 #define IOPW_RES_ADDR_20 0x20 301 #define IOPW_Q_BASE 0x22 /* QB */ 302 #define IOPW_QP 0x24 /* QP */ 303 #define IOPW_IX 0x26 /* IX */ 304 #define IOPW_SP 0x28 /* SP */ 305 #define IOPW_PC 0x2A /* PC */ 306 #define IOPW_RES_ADDR_2C 0x2C 307 #define IOPW_RES_ADDR_2E 0x2E 308 #define IOPW_SCSI_DATA 0x30 /* SD */ 309 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 310 #define IOPW_SCSI_CTRL 0x34 /* SC */ 311 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 312 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 313 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 314 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 315 #define IOPW_RES_ADDR_3C 0x3C 316 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 317 318 /* 319 * Doubleword I/O register address from base of 'iop_base'. 320 */ 321 #define IOPDW_RES_ADDR_0 0x00 322 #define IOPDW_RAM_DATA 0x04 323 #define IOPDW_RES_ADDR_8 0x08 324 #define IOPDW_RES_ADDR_C 0x0C 325 #define IOPDW_RES_ADDR_10 0x10 326 #define IOPDW_RES_ADDR_14 0x14 327 #define IOPDW_RES_ADDR_18 0x18 328 #define IOPDW_RES_ADDR_1C 0x1C 329 #define IOPDW_SDMA_ADDR0 0x20 330 #define IOPDW_SDMA_ADDR1 0x24 331 #define IOPDW_SDMA_COUNT 0x28 332 #define IOPDW_SDMA_ERROR 0x2C 333 #define IOPDW_RDMA_ADDR0 0x30 334 #define IOPDW_RDMA_ADDR1 0x34 335 #define IOPDW_RDMA_COUNT 0x38 336 #define IOPDW_RDMA_ERROR 0x3C 337 338 #define ADW_CHIP_ID_BYTE 0x25 339 #define ADW_CHIP_ID_WORD 0x04C1 340 341 #define ADW_SC_SCSI_BUS_RESET 0x2000 342 343 #define ADW_INTR_ENABLE_HOST_INTR 0x01 344 #define ADW_INTR_ENABLE_SEL_INTR 0x02 345 #define ADW_INTR_ENABLE_DPR_INTR 0x04 346 #define ADW_INTR_ENABLE_RTA_INTR 0x08 347 #define ADW_INTR_ENABLE_RMA_INTR 0x10 348 #define ADW_INTR_ENABLE_RST_INTR 0x20 349 #define ADW_INTR_ENABLE_DPE_INTR 0x40 350 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 351 352 #define ADW_INTR_STATUS_INTRA 0x01 353 #define ADW_INTR_STATUS_INTRB 0x02 354 #define ADW_INTR_STATUS_INTRC 0x04 355 356 #define ADW_RISC_CSR_STOP (0x0000) 357 #define ADW_RISC_TEST_COND (0x2000) 358 #define ADW_RISC_CSR_RUN (0x4000) 359 #define ADW_RISC_CSR_SINGLE_STEP (0x8000) 360 361 #define ADW_CTRL_REG_HOST_INTR 0x0100 362 #define ADW_CTRL_REG_SEL_INTR 0x0200 363 #define ADW_CTRL_REG_DPR_INTR 0x0400 364 #define ADW_CTRL_REG_RTA_INTR 0x0800 365 #define ADW_CTRL_REG_RMA_INTR 0x1000 366 #define ADW_CTRL_REG_RES_BIT14 0x2000 367 #define ADW_CTRL_REG_DPE_INTR 0x4000 368 #define ADW_CTRL_REG_POWER_DONE 0x8000 369 #define ADW_CTRL_REG_ANY_INTR 0xFF00 370 371 #define ADW_CTRL_REG_CMD_RESET 0x00C6 372 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 373 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 374 #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 375 #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 376 377 #define ADW_SCSI_CTRL_RSTOUT 0x2000 378 379 #define ADW_IS_INT_PENDING(iot, ioh) \ 380 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) 381 382 /* 383 * SCSI_CFG0 Register bit definitions 384 */ 385 #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 386 #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 387 #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */ 388 #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 389 #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 390 #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */ 391 #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */ 392 #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 393 #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 394 #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 395 #define ADW_OUR_ID 0x000F /* SCSI ID */ 396 397 /* 398 * SCSI_CFG1 Register bit definitions 399 */ 400 #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 401 #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 402 #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 403 #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */ 404 #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 405 #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 406 #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 407 #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */ 408 #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 409 #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 410 #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 411 #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */ 412 #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 413 #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 414 #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 415 416 #define CABLE_ILLEGAL_A 0x7 417 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 418 419 #define CABLE_ILLEGAL_B 0xB 420 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 421 422 /* 423 The following table details the SCSI_CFG1 Termination Polarity, 424 Termination Control and Cable Detect bits. 425 426 Cable Detect | Termination 427 Bit 3 2 1 0 | 5 4 | Notes 428 _____________|________|____________________ 429 1 1 1 0 | on on | Internal wide only 430 1 1 0 1 | on on | Internal narrow only 431 1 0 1 1 | on on | External narrow only 432 0 x 1 1 | on on | External wide only 433 1 1 0 0 | on off| Internal wide and internal narrow 434 1 0 1 0 | on off| Internal wide and external narrow 435 0 x 1 0 | off off| Internal wide and external wide 436 1 0 0 1 | on off| Internal narrow and external narrow 437 0 x 0 1 | on off| Internal narrow and external wide 438 1 1 1 1 | on on | No devices are attached 439 x 0 0 0 | on on | Illegal (all 3 connectors are used) 440 0 x 0 0 | on on | Illegal (all 3 connectors are used) 441 442 x means don't-care (either '0' or '1') 443 444 If term_pol (bit 13) is '0' (active-low terminator enable), then: 445 'on' is '0' and 'off' is '1'. 446 447 If term_pol bit is '1' (meaning active-hi terminator enable), then: 448 'on' is '1' and 'off' is '0'. 449 */ 450 451 /* 452 * MEM_CFG Register bit definitions 453 */ 454 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 455 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */ 456 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */ 457 #define RAM_SZ_2KB 0x00 /* 2 KB */ 458 #define RAM_SZ_4KB 0x04 /* 4 KB */ 459 #define RAM_SZ_8KB 0x08 /* 8 KB */ 460 #define RAM_SZ_16KB 0x0C /* 16 KB */ 461 #define RAM_SZ_32KB 0x10 /* 32 KB */ 462 #define RAM_SZ_64KB 0x14 /* 64 KB */ 463 464 /* 465 * DMA_CFG0 Register bit definitions 466 * 467 * This register is only accessible to the host. 468 */ 469 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 470 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 471 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 472 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 473 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 474 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 475 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 476 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 477 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 478 #define START_CTL 0x0C /* DMA start conditions */ 479 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 480 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 481 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 482 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 483 #define READ_CMD 0x03 /* Memory Read Method */ 484 #define READ_CMD_MR 0x00 /* Memory Read */ 485 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 486 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 487 488 489 /* 490 * Adv Library Status Definitions 491 */ 492 #define ADW_TRUE 1 493 #define ADW_FALSE 0 494 #define ADW_NOERROR 1 495 #define ADW_SUCCESS 1 496 #define ADW_BUSY 0 497 #define ADW_ERROR (-1) 498 499 500 /* 501 * ASC_DVC_VAR 'warn_code' values 502 */ 503 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 504 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 505 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ 506 #define ASC_WARN_ERROR 0xFFFF /* ADW_ERROR return */ 507 508 #define ADW_MAX_TID 15 /* max. target identifier */ 509 #define ADW_MAX_LUN 7 /* max. logical unit number */ 510 511 512 /* 513 * AscInitGetConfig() and AscInitAsc1000Driver() Definitions 514 * 515 * Error code values are set in ASC_DVC_VAR 'err_code'. 516 */ 517 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ 518 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 519 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 520 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ 521 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 522 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 523 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ 524 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ 525 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ 526 #define ASC_IERR_RW_LRAM 0x8000 /* read/write local RAM error */ 527 528 /* 529 * Fixed locations of microcode operating variables. 530 */ 531 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 532 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 533 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 534 #define ASC_MC_STACK_BEGIN 0x002E /* microcode stack begin */ 535 #define ASC_MC_STACK_END 0x0030 /* microcode stack end */ 536 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 537 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 538 #define ASCV_VER_SERIAL_W 0x003C /* used in dos_init */ 539 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 540 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 541 #define ASC_MC_HALTCODE 0x0094 /* microcode halt code */ 542 #define ASC_MC_CALLERPC 0x0096 /* microcode halt caller PC */ 543 #define ASC_MC_ADAPTER_SCSI_ID 0x0098 /* one ID byte + reserved */ 544 #define ASC_MC_ULTRA_ABLE 0x009C 545 #define ASC_MC_SDTR_ABLE 0x009E /* Sync. Transfer TID bitmask. */ 546 #define ASC_MC_TAGQNG_ABLE 0x00A0 547 #define ASC_MC_DISC_ENABLE 0x00A2 548 #define ASC_MC_IDLE_CMD 0x00A6 549 #define ASC_MC_IDLE_PARA_STAT 0x00A8 550 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 551 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 552 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 553 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 554 #define ASC_MC_RISC_NEXT_READY 0x00B4 555 #define ASC_MC_RISC_NEXT_DONE 0x00B5 556 #define ASC_MC_SDTR_DONE 0x00B6 557 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 558 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 559 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 560 #define ASC_MC_WDTR_ABLE 0x0120 /* Wide Transfer TID bitmask. */ 561 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 562 #define ASC_MC_WDTR_DONE 0x0124 563 #define ASC_MC_HOST_NEXT_READY 0x0128 /* Host Next Ready RQL Entry. */ 564 #define ASC_MC_HOST_NEXT_DONE 0x0129 /* Host Next Done RQL Entry. */ 565 566 /* 567 * BIOS LRAM variable absolute offsets. 568 */ 569 #define BIOS_CODESEG 0x54 570 #define BIOS_CODELEN 0x56 571 #define BIOS_SIGNATURE 0x58 572 #define BIOS_VERSION 0x5A 573 #define BIOS_SIGNATURE 0x58 574 575 /* 576 * Microcode Control Flags 577 * 578 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 579 * and handled by the microcode. 580 */ 581 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 582 583 /* 584 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 585 */ 586 #define HSHK_CFG_WIDE_XFR 0x8000 587 #define HSHK_CFG_RATE 0x0F00 588 #define HSHK_CFG_OFFSET 0x001F 589 590 /* 591 * LRAM RISC Queue Lists (LRAM addresses 0x1200 - 0x19FF) 592 * 593 * Each of the 255 Adv Library/Microcode RISC queue lists or mailboxes 594 * starting at LRAM address 0x1200 is 8 bytes and has the following 595 * structure. Only 253 of these are actually used for command queues. 596 */ 597 598 #define ASC_MC_RISC_Q_LIST_BASE 0x1200 599 #define ASC_MC_RISC_Q_LIST_SIZE 0x0008 600 #define ASC_MC_RISC_Q_TOTAL_CNT 0x00FF /* Num. queue slots in LRAM. */ 601 #define ASC_MC_RISC_Q_FIRST 0x0001 602 #define ASC_MC_RISC_Q_LAST 0x00FF 603 604 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 605 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 606 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 607 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 608 609 /* RISC Queue List structure - 8 bytes */ 610 #define RQL_FWD 0 /* forward pointer (1 byte) */ 611 #define RQL_BWD 1 /* backward pointer (1 byte) */ 612 #define RQL_STATE 2 /* state byte - free, ready, done, aborted (1 byte) */ 613 #define RQL_TID 3 /* request target id (1 byte) */ 614 #define RQL_PHYADDR 4 /* request physical pointer (4 bytes) */ 615 616 /* RISC Queue List state values */ 617 #define ASC_MC_QS_FREE 0x00 618 #define ASC_MC_QS_READY 0x01 619 #define ASC_MC_QS_DONE 0x40 620 #define ASC_MC_QS_ABORTED 0x80 621 622 /* RISC Queue List pointer values */ 623 #define ASC_MC_NULL_Q 0x00 /* NULL_Q == 0 */ 624 #define ASC_MC_BIOS_Q 0xFF /* BIOS_Q = 255 */ 625 626 /* ASC_SCSI_REQ_Q 'cntl' field values */ 627 #define ASC_MC_QC_START_MOTOR 0x02 /* Issue start motor. */ 628 #define ASC_MC_QC_NO_OVERRUN 0x04 /* Don't report overrun. */ 629 #define ASC_MC_QC_FIRST_DMA 0x08 /* Internal microcode flag. */ 630 #define ASC_MC_QC_ABORTED 0x10 /* Request aborted by host. */ 631 #define ASC_MC_QC_REQ_SENSE 0x20 /* Auto-Request Sense. */ 632 #define ASC_MC_QC_DOS_REQ 0x80 /* Request issued by DOS. */ 633 634 635 /* 636 * ASC_SCSI_REQ_Q 'a_flag' definitions 637 * 638 * The Adv Library should limit use to the lower nibble (4 bits) of 639 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag. 640 */ 641 #define ADW_POLL_REQUEST 0x01 /* poll for request completion */ 642 #define ADW_SCSIQ_DONE 0x02 /* request done */ 643 644 /* 645 * Adapter temporary configuration structure 646 * 647 * This structure can be discarded after initialization. Don't add 648 * fields here needed after initialization. 649 * 650 * Field naming convention: 651 * 652 * *_enable indicates the field enables or disables a feature. The 653 * value of the field is never reset. 654 */ 655 typedef struct adw_dvc_cfg { 656 u_int16_t disc_enable; /* enable disconnection */ 657 u_int8_t chip_version; /* chip version */ 658 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 659 u_int16_t pci_device_id; /* PCI device code number */ 660 u_int16_t lib_version; /* Adv Library version number */ 661 u_int16_t control_flag; /* Microcode Control Flag */ 662 u_int16_t mcode_date; /* Microcode date */ 663 u_int16_t mcode_version; /* Microcode version */ 664 u_int16_t pci_slot_info; /* high byte device/function number */ 665 /* bits 7-3 device num., bits 2-0 function num. */ 666 /* low byte bus num. */ 667 u_int16_t bios_boot_wait; /* BIOS boot time delay */ 668 u_int16_t serial1; /* EEPROM serial number word 1 */ 669 u_int16_t serial2; /* EEPROM serial number word 2 */ 670 u_int16_t serial3; /* EEPROM serial number word 3 */ 671 } ADW_DVC_CFG; 672 673 /* 674 * Adapter operation variable structure. 675 * 676 * One structure is required per host adapter. 677 * 678 * Field naming convention: 679 * 680 * *_able indicates both whether a feature should be enabled or disabled 681 * and whether a device is capable of the feature. At initialization 682 * this field may be set, but later if a device is found to be incapable 683 * of the feature, the field is cleared. 684 */ 685 typedef struct adw_softc { 686 687 struct device sc_dev; 688 689 bus_space_tag_t sc_iot; 690 bus_space_handle_t sc_ioh; 691 bus_dma_tag_t sc_dmat; 692 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 693 void *sc_ih; 694 695 struct adw_control *sc_control; /* control structures */ 696 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; 697 struct scsipi_link sc_link; /* prototype for devs */ 698 struct scsipi_adapter sc_adapter; 699 700 TAILQ_HEAD(, scsipi_xfer) sc_queue; 701 702 u_int32_t sc_flags; /* see below sc_flags values */ 703 704 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ 705 ulong isr_callback; /* pointer to function, called in AdvISR() */ 706 ulong sbreset_callback; /* pointer to function, called in AdvISR() */ 707 u_int16_t wdtr_able; /* try WDTR for a device */ 708 u_int16_t sdtr_able; /* try SDTR for a device */ 709 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */ 710 u_int16_t tagqng_able; /* try tagged queuing with a device */ 711 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ 712 u_int16_t start_motor; /* start motor command allowed */ 713 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ 714 u_int8_t chip_no; /* should be assigned by caller */ 715 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */ 716 u_int8_t cur_host_qng; /* total number of queue command */ 717 u_int8_t irq_no; /* IRQ number */ 718 u_int16_t no_scam; /* scam_tolerant of EEPROM */ 719 u_int16_t idle_cmd_done; /* microcode idle command done set by AdvISR() */ 720 ulong drv_ptr; /* driver pointer to private structure */ 721 u_int8_t chip_scsi_id; /* chip SCSI target ID */ 722 /* 723 * Note: The following fields will not be used after initialization. The 724 * driver may discard the buffer after initialization is done. 725 */ 726 ADW_DVC_CFG cfg; /* temporary configuration structure */ 727 } ADW_SOFTC; 728 729 /* sc_flags values */ 730 #define ADW_WIDE_BOARD 0x04 731 732 733 #define ADW_IS_NARROW_BOARD(sc) (((sc)->sc_flags & ADW_WIDE_BOARD) == 0) 734 #define ADW_IS_WIDE_BOARD(sc) ((sc)->sc_flags & ADW_WIDE_BOARD) 735 736 737 #define NO_OF_SG_PER_BLOCK 15 738 739 typedef struct adw_sg_block { 740 u_int8_t reserved1; 741 u_int8_t reserved2; 742 u_int8_t first_entry_no; /* starting entry number */ 743 u_int8_t last_entry_no; /* last entry number */ 744 struct adw_sg_block *sg_ptr; /* links to the next sg block */ 745 struct { 746 u_int32_t sg_addr; /* SG element address */ 747 u_int32_t sg_count; /* SG element count */ 748 } sg_list[NO_OF_SG_PER_BLOCK]; 749 } ADW_SG_BLOCK; 750 751 /* 752 * ADW_SCSI_REQ_Q - microcode request structure 753 * 754 * All fields in this structure up to byte 60 are used by the microcode. 755 * The microcode makes assumptions about the size and ordering of fields 756 * in this structure. Do not change the structure definition here without 757 * coordinating the change with the microcode. 758 */ 759 typedef struct adw_scsi_req_q { 760 u_int8_t cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 761 u_int8_t sg_entry_cnt; /* SG element count. Zero for no SG. */ 762 u_int8_t target_id; /* Device target identifier. */ 763 u_int8_t target_lun; /* Device target logical unit number. */ 764 ulong data_addr; /* Data buffer physical address. */ 765 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 766 ulong sense_addr; /* Sense buffer physical address. */ 767 ulong ccb_ptr; /* Driver request pointer. */ 768 u_int8_t a_flag; /* Adv Library flag field. */ 769 u_int8_t sense_len; /* Auto-sense length. Ucode sets to residual. */ 770 u_int8_t cdb_len; /* SCSI CDB length. */ 771 u_int8_t tag_code; /* SCSI-2 Tag Queue Code: 00, 20-22. */ 772 u_int8_t done_status; /* Completion status. */ 773 u_int8_t scsi_status; /* SCSI status byte. (see below) */ 774 u_int8_t host_status; /* Ucode host status. */ 775 u_int8_t ux_sg_ix; /* Ucode working SG variable. */ 776 u_int8_t cdb[12]; /* SCSI command block. */ 777 ulong sg_real_addr; /* SG list physical address. */ 778 struct adw_scsi_req_q *free_scsiq_link; 779 ulong ux_wk_data_cnt; /* Saved data count at disconnection. */ 780 struct adw_scsi_req_q *scsiq_ptr; 781 ADW_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */ 782 /* 783 * End of microcode structure - 60 bytes. The rest of the structure 784 * is used by the Adv Library and ignored by the microcode. 785 */ 786 ulong vsense_addr; /* Sense buffer virtual address. */ 787 ulong vdata_addr; /* Data buffer virtual address. */ 788 u_int8_t orig_sense_len; /* Original length of sense buffer. */ 789 u_int8_t pads[3]; /* padding bytes (align to long) */ 790 } ADW_SCSI_REQ_Q; 791 792 /* 793 * scsi_status conditions 794 */ 795 #define SS_GOOD 0x00 796 #define SS_CHK_CONDITION 0x02 797 #define SS_CONDITION_MET 0x04 798 #define SS_TARGET_BUSY 0x08 799 #define SS_INTERMID 0x10 800 #define SS_INTERMID_COND_MET 0x14 801 #define SS_RSERV_CONFLICT 0x18 802 #define SS_CMD_TERMINATED 0x22 803 #define SS_QUEUE_FULL 0x28 804 805 /* 806 * Microcode idle loop commands 807 */ 808 #define IDLE_CMD_COMPLETED 0 809 #define IDLE_CMD_STOP_CHIP 0x0001 810 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 811 #define IDLE_CMD_SEND_INT 0x0004 812 #define IDLE_CMD_ABORT 0x0008 813 #define IDLE_CMD_DEVICE_RESET 0x0010 814 #define IDLE_CMD_SCSI_RESET 0x0020 815 816 /* 817 * AdvSendIdleCmd() flag definitions. 818 */ 819 #define ADW_NOWAIT 0x01 820 821 /* 822 * Wait loop time out values. 823 */ 824 #define SCSI_WAIT_10_SEC 10 /* 10 seconds */ 825 #define SCSI_MS_PER_SEC 1000 /* milliseconds per second */ 826 827 828 /* Read byte from a register. */ 829 #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \ 830 bus_space_read_1((iot), (ioh), (reg_off)) 831 832 /* Write byte to a register. */ 833 #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \ 834 bus_space_write_1((iot), (ioh), (reg_off), (byte)) 835 836 /* Read word (2 bytes) from a register. */ 837 #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \ 838 bus_space_read_2((iot), (ioh), (reg_off)) 839 840 /* Write word (2 bytes) to a register. */ 841 #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ 842 bus_space_write_2((iot), (ioh), (reg_off), (word)) 843 844 /* Read byte from LRAM. */ 845 #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ 846 do { \ 847 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 848 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \ 849 } while (0) 850 851 /* Write byte to LRAM. */ 852 #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \ 853 do { \ 854 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 855 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \ 856 } while (0) 857 858 /* Read word (2 bytes) from LRAM. */ 859 #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \ 860 do { \ 861 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 862 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \ 863 } while (0) 864 865 /* Write word (2 bytes) to LRAM. */ 866 #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \ 867 do { \ 868 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 869 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \ 870 } while (0) 871 872 /* Write double word (4 bytes) to LRAM */ 873 /* Because of unspecified C language ordering don't use auto-increment. */ 874 #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \ 875 do { \ 876 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 877 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 878 (ushort) ((dword) & 0xFFFF)); \ 879 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \ 880 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 881 (ushort) ((dword >> 16) & 0xFFFF)); \ 882 } while (0) 883 884 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 885 #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \ 886 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \ 887 888 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 889 #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \ 890 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)) 891 892 /* 893 * Define macro to check for Condor signature. 894 * 895 * Evaluate to ADW_TRUE if a Condor chip is found the specified port 896 * address 'iop_base'. Otherwise evalue to ADW_FALSE. 897 */ 898 #define ADW_FIND_SIGNATURE(iot, ioh) \ 899 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \ 900 ADW_CHIP_ID_BYTE) && \ 901 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \ 902 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE) 903 904 /* 905 * Define macro to Return the version number of the chip at 'iop_base'. 906 * 907 * The second parameter 'bus_type' is currently unused. 908 */ 909 #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \ 910 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV) 911 912 /* 913 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must 914 * match the ASC_SCSI_REQ_Q 'srb_ptr' field. 915 * 916 * If the request has not yet been sent to the device it will simply be 917 * aborted from RISC memory. If the request is disconnected it will be 918 * aborted on reselection by sending an Abort Message to the target ID. 919 * 920 * Return value: 921 * ADW_TRUE(1) - Queue was successfully aborted. 922 * ADW_FALSE(0) - Queue was not found on the active queue list. 923 */ 924 #define ADW_ABORT_CCB(sc, ccb_ptr) \ 925 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, \ 926 (ulong) (ccb_ptr), 0) 927 928 /* 929 * Send a Bus Device Reset Message to the specified target ID. 930 * 931 * All outstanding commands will be purged if sending the 932 * Bus Device Reset Message is successful. 933 * 934 * Return Value: 935 * ADW_TRUE(1) - All requests on the target are purged. 936 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 937 * are not purged. 938 */ 939 #define ADW_RESET_DEVICE(sc, target_id) \ 940 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, \ 941 (ulong) (target_id), 0) 942 943 /* 944 * SCSI Wide Type definition. 945 */ 946 #define ADW_SCSI_BIT_ID_TYPE ushort 947 948 /* 949 * AdvInitScsiTarget() 'cntl_flag' options. 950 */ 951 #define ADW_SCAN_LUN 0x01 952 #define ADW_CAPINFO_NOLUN 0x02 953 954 /* 955 * Convert target id to target id bit mask. 956 */ 957 #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) 958 959 /* 960 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values. 961 */ 962 963 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 964 #define QD_NO_ERROR 0x01 965 #define QD_ABORTED_BY_HOST 0x02 966 #define QD_WITH_ERROR 0x04 967 968 #define QHSTA_NO_ERROR 0x00 969 #define QHSTA_M_SEL_TIMEOUT 0x11 970 #define QHSTA_M_DATA_OVER_RUN 0x12 971 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 972 #define QHSTA_M_QUEUE_ABORTED 0x15 973 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 974 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 975 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 976 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 977 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 978 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 979 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 980 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 981 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 982 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 983 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 984 #define QHSTA_M_WTM_TIMEOUT 0x41 985 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 986 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 987 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 988 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 989 990 /* 991 * SCSI Iquiry structure 992 */ 993 994 typedef struct 995 { 996 u_int8_t peri_dvc_type:5; 997 u_int8_t peri_qualifier:3; 998 } ASC_SCSI_INQ0; 999 1000 typedef struct 1001 { 1002 u_int8_t dvc_type_modifier:7; 1003 u_int8_t rmb:1; 1004 } ASC_SCSI_INQ1; 1005 1006 typedef struct 1007 { 1008 u_int8_t ansi_apr_ver:3; 1009 u_int8_t ecma_ver:3; 1010 u_int8_t iso_ver:2; 1011 } ASC_SCSI_INQ2; 1012 1013 typedef struct 1014 { 1015 u_int8_t rsp_data_fmt:4; 1016 u_int8_t res:2; 1017 u_int8_t TemIOP:1; 1018 u_int8_t aenc:1; 1019 } ASC_SCSI_INQ3; 1020 1021 typedef struct 1022 { 1023 u_int8_t StfRe:1; 1024 u_int8_t CmdQue:1; 1025 u_int8_t Reserved:1; 1026 u_int8_t Linked:1; 1027 u_int8_t Sync:1; 1028 u_int8_t WBus16:1; 1029 u_int8_t WBus32:1; 1030 u_int8_t RelAdr:1; 1031 } ASC_SCSI_INQ7; 1032 1033 typedef struct 1034 { 1035 ASC_SCSI_INQ0 byte0; 1036 ASC_SCSI_INQ1 byte1; 1037 ASC_SCSI_INQ2 byte2; 1038 ASC_SCSI_INQ3 byte3; 1039 u_int8_t add_len; 1040 u_int8_t res1; 1041 u_int8_t res2; 1042 ASC_SCSI_INQ7 byte7; 1043 u_int8_t vendor_id[8]; 1044 u_int8_t product_id[16]; 1045 u_int8_t product_rev_level[4]; 1046 } ASC_SCSI_INQUIRY; 1047 1048 1049 #define ASC_MAX_SENSE_LEN 32 1050 #define ASC_MIN_SENSE_LEN 14 1051 1052 typedef struct asc_req_sense { 1053 u_int8_t err_code:7; 1054 u_int8_t info_valid:1; 1055 u_int8_t segment_no; 1056 u_int8_t sense_key:4; 1057 u_int8_t reserved_bit:1; 1058 u_int8_t sense_ILI:1; 1059 u_int8_t sense_EOM:1; 1060 u_int8_t file_mark:1; 1061 u_int8_t info1[4]; 1062 u_int8_t add_sense_len; 1063 u_int8_t cmd_sp_info[4]; 1064 u_int8_t asc; 1065 u_int8_t ascq; 1066 u_int8_t fruc; 1067 u_int8_t sks_byte0:7; 1068 u_int8_t sks_valid:1; 1069 u_int8_t sks_bytes[2]; 1070 u_int8_t notused[2]; 1071 u_int8_t ex_sense_code; 1072 u_int8_t info2[4]; 1073 } ASC_REQ_SENSE; 1074 1075 1076 /* 1077 * Adv Library functions available to drivers. 1078 */ 1079 1080 int AdvInitFromEEP __P((ADW_SOFTC *)); 1081 int AdvExeScsiQueue __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 1082 int AdvISR __P((ADW_SOFTC *)); 1083 int AdvSendIdleCmd __P((ADW_SOFTC *, u_int16_t, u_int32_t, int)); 1084 int AdvInitGetConfig __P((ADW_SOFTC *)); 1085 int AdvInitAsc3550Driver __P((ADW_SOFTC *)); 1086 void AdvResetChip __P((bus_space_tag_t, bus_space_handle_t)); 1087 void AdvResetSCSIBus __P((ADW_SOFTC *)); 1088 int AdvResetCCB __P((ADW_SOFTC *)); 1089 1090 #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */ 1091
Indexes created Mon Sep 22 13:09:51 GMT 2025