adwlib.h revision 1.7
1 /* $NetBSD: adwlib.h,v 1.7 2000/02/03 20:29:16 dante Exp $ */ 2 3 /* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-1996 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55 #ifndef _ADVANSYS_WIDE_LIBRARY_H_ 56 #define _ADVANSYS_WIDE_LIBRARY_H_ 57 58 59 /* 60 * --- Adv Library Constants and Macros 61 */ 62 63 #define ADW_LIB_VERSION_MAJOR 5 64 #define ADW_LIB_VERSION_MINOR 2 65 66 /* 67 * Define Adv Reset Hold Time grater than 25 uSec. 68 * See AdvResetSCSIBus() for more info. 69 */ 70 #define ASC_SCSI_RESET_HOLD_TIME_US 60 71 72 /* 73 * Define Adv EEPROM constants. 74 */ 75 76 #define ASC_EEP_DVC_CFG_BEGIN (0x00) 77 #define ASC_EEP_DVC_CFG_END (0x15) 78 #define ASC_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 79 #define ASC_EEP_MAX_WORD_ADDR (0x1E) 80 81 #define ASC_EEP_DELAY_MS 100 82 83 /* 84 * EEPROM bits reference by the RISC after initialization. 85 */ 86 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 87 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 88 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 89 90 /* 91 * EEPROM configuration format 92 * 93 * Field naming convention: 94 * 95 * *_enable indicates the field enables or disables the feature. The 96 * value is never reset. 97 * 98 * *_able indicates both whether a feature should be enabled or disabled 99 * and whether a device isi capable of the feature. At initialization 100 * this field may be set, but later if a device is found to be incapable 101 * of the feature, the field is cleared. 102 * 103 * Default values are maintained in a_init.c in the structure 104 * Default_EEPROM_Config. 105 */ 106 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 107 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 108 /* 109 * For the ASC3550 Bit 13 is Termination Polarity control bit. 110 * For later ICs Bit 13 controls whether the CIS (Card Information 111 * Service Section) is loaded from EEPROM. 112 */ 113 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 114 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 115 116 typedef struct adw_eep_3550_config 117 { 118 /* Word Offset, Description */ 119 120 u_int16_t cfg_lsw; /* 00 power up initialization */ 121 /* bit 13 set - Term Polarity Control */ 122 /* bit 14 set - BIOS Enable */ 123 /* bit 15 set - Big Endian Mode */ 124 u_int16_t cfg_msw; /* 01 unused */ 125 u_int16_t disc_enable; /* 02 disconnect enable */ 126 u_int16_t wdtr_able; /* 03 Wide DTR able */ 127 u_int16_t sdtr_able; /* 04 Synchronous DTR able */ 128 u_int16_t start_motor; /* 05 send start up motor */ 129 u_int16_t tagqng_able; /* 06 tag queuing able */ 130 u_int16_t bios_scan; /* 07 BIOS device control */ 131 u_int16_t scam_tolerant; /* 08 no scam */ 132 133 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 134 u_int8_t bios_boot_delay; /* power up wait */ 135 136 u_int8_t scsi_reset_delay; /* 10 reset delay */ 137 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 138 /* high nibble is lun */ 139 /* low nibble is scsi id */ 140 141 u_int8_t termination; /* 11 0 - automatic */ 142 /* 1 - low off / high off */ 143 /* 2 - low off / high on */ 144 /* 3 - low on / high on */ 145 /* There is no low on / high off */ 146 147 u_int8_t reserved1; /* reserved byte (not used) */ 148 149 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 150 /* bit 0 set: BIOS don't act as initiator. */ 151 /* bit 1 set: BIOS > 1 GB support */ 152 /* bit 2 set: BIOS > 2 Disk Support */ 153 /* bit 3 set: BIOS don't support removables */ 154 /* bit 4 set: BIOS support bootable CD */ 155 /* bit 5 set: */ 156 /* bit 6 set: BIOS support multiple LUNs */ 157 /* bit 7 set: BIOS display of message */ 158 /* bit 8 set: */ 159 /* bit 9 set: Reset SCSI bus during init. */ 160 /* bit 10 set: */ 161 /* bit 11 set: No verbose initialization. */ 162 /* bit 12 set: SCSI parity enabled */ 163 /* bit 13 set: */ 164 /* bit 14 set: */ 165 /* bit 15 set: */ 166 u_int16_t ultra_able; /* 13 ULTRA speed able */ 167 u_int16_t reserved2; /* 14 reserved */ 168 u_int8_t max_host_qng; /* 15 maximum host queuing */ 169 u_int8_t max_dvc_qng; /* maximum per device queuing */ 170 u_int16_t dvc_cntl; /* 16 control bit for driver */ 171 u_int16_t bug_fix; /* 17 control bit for bug fix */ 172 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 173 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 174 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 175 u_int16_t check_sum; /* 21 EEP check sum */ 176 u_int8_t oem_name[16]; /* 22 OEM name */ 177 u_int16_t dvc_err_code; /* 30 last device driver error code */ 178 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 179 u_int16_t adv_err_addr; /* 32 last uc error address */ 180 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 181 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 182 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 183 u_int16_t num_of_err; /* 36 number of error */ 184 } ADW_EEP_3550_CONFIG; 185 186 typedef struct adw_eep_38C0800_config 187 { 188 /* Word Offset, Description */ 189 190 u_int16_t cfg_lsw; /* 00 power up initialization */ 191 /* bit 13 set - Load CIS */ 192 /* bit 14 set - BIOS Enable */ 193 /* bit 15 set - Big Endian Mode */ 194 u_int16_t cfg_msw; /* 01 unused */ 195 u_int16_t disc_enable; /* 02 disconnect enable */ 196 u_int16_t wdtr_able; /* 03 Wide DTR able */ 197 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 198 u_int16_t start_motor; /* 05 send start up motor */ 199 u_int16_t tagqng_able; /* 06 tag queuing able */ 200 u_int16_t bios_scan; /* 07 BIOS device control */ 201 u_int16_t scam_tolerant; /* 08 no scam */ 202 203 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 204 u_int8_t bios_boot_delay; /* power up wait */ 205 206 u_int8_t scsi_reset_delay; /* 10 reset delay */ 207 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 208 /* high nibble is lun */ 209 /* low nibble is scsi id */ 210 211 u_int8_t termination_se; /* 11 0 - automatic */ 212 /* 1 - low off / high off */ 213 /* 2 - low off / high on */ 214 /* 3 - low on / high on */ 215 /* There is no low on / high off */ 216 217 u_int8_t termination_lvd; /* 11 0 - automatic */ 218 /* 1 - low off / high off */ 219 /* 2 - low off / high on */ 220 /* 3 - low on / high on */ 221 /* There is no low on / high off */ 222 223 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 224 /* bit 0 set: BIOS don't act as initiator. */ 225 /* bit 1 set: BIOS > 1 GB support */ 226 /* bit 2 set: BIOS > 2 Disk Support */ 227 /* bit 3 set: BIOS don't support removables */ 228 /* bit 4 set: BIOS support bootable CD */ 229 /* bit 5 set: BIOS scan enabled */ 230 /* bit 6 set: BIOS support multiple LUNs */ 231 /* bit 7 set: BIOS display of message */ 232 /* bit 8 set: */ 233 /* bit 9 set: Reset SCSI bus during init. */ 234 /* bit 10 set: */ 235 /* bit 11 set: No verbose initialization. */ 236 /* bit 12 set: SCSI parity enabled */ 237 /* bit 13 set: */ 238 /* bit 14 set: */ 239 /* bit 15 set: */ 240 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 241 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 242 u_int8_t max_host_qng; /* 15 maximum host queueing */ 243 u_int8_t max_dvc_qng; /* maximum per device queuing */ 244 u_int16_t dvc_cntl; /* 16 control bit for driver */ 245 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 246 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 247 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 248 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 249 u_int16_t check_sum; /* 21 EEP check sum */ 250 u_int8_t oem_name[16]; /* 22 OEM name */ 251 u_int16_t dvc_err_code; /* 30 last device driver error code */ 252 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 253 u_int16_t adv_err_addr; /* 32 last uc error address */ 254 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 255 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 256 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 257 u_int16_t reserved36; /* 36 reserved */ 258 u_int16_t reserved37; /* 37 reserved */ 259 u_int16_t reserved38; /* 38 reserved */ 260 u_int16_t reserved39; /* 39 reserved */ 261 u_int16_t reserved40; /* 40 reserved */ 262 u_int16_t reserved41; /* 41 reserved */ 263 u_int16_t reserved42; /* 42 reserved */ 264 u_int16_t reserved43; /* 43 reserved */ 265 u_int16_t reserved44; /* 44 reserved */ 266 u_int16_t reserved45; /* 45 reserved */ 267 u_int16_t reserved46; /* 46 reserved */ 268 u_int16_t reserved47; /* 47 reserved */ 269 u_int16_t reserved48; /* 48 reserved */ 270 u_int16_t reserved49; /* 49 reserved */ 271 u_int16_t reserved50; /* 50 reserved */ 272 u_int16_t reserved51; /* 51 reserved */ 273 u_int16_t reserved52; /* 52 reserved */ 274 u_int16_t reserved53; /* 53 reserved */ 275 u_int16_t reserved54; /* 54 reserved */ 276 u_int16_t reserved55; /* 55 reserved */ 277 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 278 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 279 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 280 u_int16_t subsysid; /* 59 SubSystem ID */ 281 u_int16_t reserved60; /* 60 reserved */ 282 u_int16_t reserved61; /* 61 reserved */ 283 u_int16_t reserved62; /* 62 reserved */ 284 u_int16_t reserved63; /* 63 reserved */ 285 } ADW_EEP_38C0800_CONFIG; 286 287 /* 288 * EEPROM Commands 289 */ 290 #define ASC_EEP_CMD_READ 0x80 291 #define ASC_EEP_CMD_WRITE 0x40 292 #define ASC_EEP_CMD_WRITE_ABLE 0x30 293 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 294 295 #define ASC_EEP_CMD_DONE 0x0200 296 #define ASC_EEP_CMD_DONE_ERR 0x0001 297 298 /* cfg_word */ 299 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000 300 301 /* bios_ctrl */ 302 #define BIOS_CTRL_BIOS 0x0001 303 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 304 #define BIOS_CTRL_GT_2_DISK 0x0004 305 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 306 #define BIOS_CTRL_BOOTABLE_CD 0x0010 307 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 308 #define BIOS_CTRL_DISPLAY_MSG 0x0080 309 #define BIOS_CTRL_NO_SCAM 0x0100 310 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 311 #define BIOS_CTRL_INIT_VERBOSE 0x0800 312 #define BIOS_CTRL_SCSI_PARITY 0x1000 313 314 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 315 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */ 316 317 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 318 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ 319 320 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 321 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ 322 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ 323 324 /* 325 * Byte I/O register address from base of 'iop_base'. 326 */ 327 #define IOPB_INTR_STATUS_REG 0x00 328 #define IOPB_CHIP_ID_1 0x01 329 #define IOPB_INTR_ENABLES 0x02 330 #define IOPB_CHIP_TYPE_REV 0x03 331 #define IOPB_RES_ADDR_4 0x04 332 #define IOPB_RES_ADDR_5 0x05 333 #define IOPB_RAM_DATA 0x06 334 #define IOPB_RES_ADDR_7 0x07 335 #define IOPB_FLAG_REG 0x08 336 #define IOPB_RES_ADDR_9 0x09 337 #define IOPB_RISC_CSR 0x0A 338 #define IOPB_RES_ADDR_B 0x0B 339 #define IOPB_RES_ADDR_C 0x0C 340 #define IOPB_RES_ADDR_D 0x0D 341 #define IOPB_SOFT_OVER_WR 0x0E 342 #define IOPB_RES_ADDR_F 0x0F 343 #define IOPB_MEM_CFG 0x10 344 #define IOPB_RES_ADDR_11 0x11 345 #define IOPB_GPIO_DATA 0x12 346 #define IOPB_RES_ADDR_13 0x13 347 #define IOPB_FLASH_PAGE 0x14 348 #define IOPB_RES_ADDR_15 0x15 349 #define IOPB_GPIO_CNTL 0x16 350 #define IOPB_RES_ADDR_17 0x17 351 #define IOPB_FLASH_DATA 0x18 352 #define IOPB_RES_ADDR_19 0x19 353 #define IOPB_RES_ADDR_1A 0x1A 354 #define IOPB_RES_ADDR_1B 0x1B 355 #define IOPB_RES_ADDR_1C 0x1C 356 #define IOPB_RES_ADDR_1D 0x1D 357 #define IOPB_RES_ADDR_1E 0x1E 358 #define IOPB_RES_ADDR_1F 0x1F 359 #define IOPB_DMA_CFG0 0x20 360 #define IOPB_DMA_CFG1 0x21 361 #define IOPB_TICKLE 0x22 362 #define IOPB_DMA_REG_WR 0x23 363 #define IOPB_SDMA_STATUS 0x24 364 #define IOPB_SCSI_BYTE_CNT 0x25 365 #define IOPB_HOST_BYTE_CNT 0x26 366 #define IOPB_BYTE_LEFT_TO_XFER 0x27 367 #define IOPB_BYTE_TO_XFER_0 0x28 368 #define IOPB_BYTE_TO_XFER_1 0x29 369 #define IOPB_BYTE_TO_XFER_2 0x2A 370 #define IOPB_BYTE_TO_XFER_3 0x2B 371 #define IOPB_ACC_GRP 0x2C 372 #define IOPB_RES_ADDR_2D 0x2D 373 #define IOPB_DEV_ID 0x2E 374 #define IOPB_RES_ADDR_2F 0x2F 375 #define IOPB_SCSI_DATA 0x30 376 #define IOPB_RES_ADDR_31 0x31 377 #define IOPB_RES_ADDR_32 0x32 378 #define IOPB_SCSI_DATA_HSHK 0x33 379 #define IOPB_SCSI_CTRL 0x34 380 #define IOPB_RES_ADDR_35 0x35 381 #define IOPB_RES_ADDR_36 0x36 382 #define IOPB_RES_ADDR_37 0x37 383 #define IOPB_RAM_BIST 0x38 384 #define IOPB_PLL_TEST 0x39 385 #define IOPB_PCI_INT_CFG 0x3A 386 #define IOPB_RES_ADDR_3B 0x3B 387 #define IOPB_RFIFO_CNT 0x3C 388 #define IOPB_RES_ADDR_3D 0x3D 389 #define IOPB_RES_ADDR_3E 0x3E 390 #define IOPB_RES_ADDR_3F 0x3F 391 392 /* 393 * Word I/O register address from base of 'iop_base'. 394 */ 395 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 396 #define IOPW_CTRL_REG 0x02 /* CC */ 397 #define IOPW_RAM_ADDR 0x04 /* LA */ 398 #define IOPW_RAM_DATA 0x06 /* LD */ 399 #define IOPW_RES_ADDR_08 0x08 400 #define IOPW_RISC_CSR 0x0A /* CSR */ 401 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 402 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 403 #define IOPW_RES_ADDR_10 0x10 404 #define IOPW_SEL_MASK 0x12 /* SM */ 405 #define IOPW_RES_ADDR_14 0x14 406 #define IOPW_FLASH_ADDR 0x16 /* FA */ 407 #define IOPW_RES_ADDR_18 0x18 408 #define IOPW_EE_CMD 0x1A /* EC */ 409 #define IOPW_EE_DATA 0x1C /* ED */ 410 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 411 #define IOPW_RES_ADDR_20 0x20 412 #define IOPW_Q_BASE 0x22 /* QB */ 413 #define IOPW_QP 0x24 /* QP */ 414 #define IOPW_IX 0x26 /* IX */ 415 #define IOPW_SP 0x28 /* SP */ 416 #define IOPW_PC 0x2A /* PC */ 417 #define IOPW_RES_ADDR_2C 0x2C 418 #define IOPW_RES_ADDR_2E 0x2E 419 #define IOPW_SCSI_DATA 0x30 /* SD */ 420 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 421 #define IOPW_SCSI_CTRL 0x34 /* SC */ 422 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 423 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 424 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 425 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 426 #define IOPW_RES_ADDR_3C 0x3C 427 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 428 429 /* 430 * Doubleword I/O register address from base of 'iop_base'. 431 */ 432 #define IOPDW_RES_ADDR_0 0x00 433 #define IOPDW_RAM_DATA 0x04 434 #define IOPDW_RES_ADDR_8 0x08 435 #define IOPDW_RES_ADDR_C 0x0C 436 #define IOPDW_RES_ADDR_10 0x10 437 #define IOPDW_COMMA 0x14 438 #define IOPDW_COMMB 0x18 439 #define IOPDW_RES_ADDR_1C 0x1C 440 #define IOPDW_SDMA_ADDR0 0x20 441 #define IOPDW_SDMA_ADDR1 0x24 442 #define IOPDW_SDMA_COUNT 0x28 443 #define IOPDW_SDMA_ERROR 0x2C 444 #define IOPDW_RDMA_ADDR0 0x30 445 #define IOPDW_RDMA_ADDR1 0x34 446 #define IOPDW_RDMA_COUNT 0x38 447 #define IOPDW_RDMA_ERROR 0x3C 448 449 #define ADW_CHIP_ID_BYTE 0x25 450 #define ADW_CHIP_ID_WORD 0x04C1 451 452 #define ADW_SC_SCSI_BUS_RESET 0x2000 453 454 #define ADW_INTR_ENABLE_HOST_INTR 0x01 455 #define ADW_INTR_ENABLE_SEL_INTR 0x02 456 #define ADW_INTR_ENABLE_DPR_INTR 0x04 457 #define ADW_INTR_ENABLE_RTA_INTR 0x08 458 #define ADW_INTR_ENABLE_RMA_INTR 0x10 459 #define ADW_INTR_ENABLE_RST_INTR 0x20 460 #define ADW_INTR_ENABLE_DPE_INTR 0x40 461 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 462 463 #define ADW_INTR_STATUS_INTRA 0x01 464 #define ADW_INTR_STATUS_INTRB 0x02 465 #define ADW_INTR_STATUS_INTRC 0x04 466 467 #define ADW_RISC_CSR_STOP (0x0000) 468 #define ADW_RISC_TEST_COND (0x2000) 469 #define ADW_RISC_CSR_RUN (0x4000) 470 #define ADW_RISC_CSR_SINGLE_STEP (0x8000) 471 472 #define ADW_CTRL_REG_HOST_INTR 0x0100 473 #define ADW_CTRL_REG_SEL_INTR 0x0200 474 #define ADW_CTRL_REG_DPR_INTR 0x0400 475 #define ADW_CTRL_REG_RTA_INTR 0x0800 476 #define ADW_CTRL_REG_RMA_INTR 0x1000 477 #define ADW_CTRL_REG_RES_BIT14 0x2000 478 #define ADW_CTRL_REG_DPE_INTR 0x4000 479 #define ADW_CTRL_REG_POWER_DONE 0x8000 480 #define ADW_CTRL_REG_ANY_INTR 0xFF00 481 482 #define ADW_CTRL_REG_CMD_RESET 0x00C6 483 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 484 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 485 #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 486 #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 487 488 #define ADV_TICKLE_NOP 0x00 489 #define ADV_TICKLE_A 0x01 490 #define ADV_TICKLE_B 0x02 491 #define ADV_TICKLE_C 0x03 492 493 #define ADW_SCSI_CTRL_RSTOUT 0x2000 494 495 #define ADW_IS_INT_PENDING(iot, ioh) \ 496 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) 497 498 /* 499 * SCSI_CFG0 Register bit definitions 500 */ 501 #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 502 #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 503 #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */ 504 #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 505 #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 506 #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */ 507 #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */ 508 #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 509 #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 510 #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 511 #define ADW_OUR_ID 0x000F /* SCSI ID */ 512 513 /* 514 * SCSI_CFG1 Register bit definitions 515 */ 516 #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 517 #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 518 #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 519 #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */ 520 #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 521 #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 522 #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 523 #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */ 524 #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 525 #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 526 #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 527 #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */ 528 #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 529 #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 530 #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 531 532 /* 533 * Addendum for ASC-38C0800 Chip 534 */ 535 #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 536 #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 537 #define ADW_HVD 0x1000 /* HVD Device Detect */ 538 #define ADW_LVD 0x0800 /* LVD Device Detect */ 539 #define ADW_SE 0x0400 /* SE Device Detect */ 540 #define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */ 541 #define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 542 #define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 543 #define ADW_TERM_SE 0x0030 /* SE Termination Bits */ 544 #define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 545 #define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 546 #define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 547 #define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 548 #define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 549 #define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */ 550 #define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 551 #define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 552 553 554 #define CABLE_ILLEGAL_A 0x7 555 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 556 557 #define CABLE_ILLEGAL_B 0xB 558 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 559 560 /* 561 The following table details the SCSI_CFG1 Termination Polarity, 562 Termination Control and Cable Detect bits. 563 564 Cable Detect | Termination 565 Bit 3 2 1 0 | 5 4 | Notes 566 _____________|________|____________________ 567 1 1 1 0 | on on | Internal wide only 568 1 1 0 1 | on on | Internal narrow only 569 1 0 1 1 | on on | External narrow only 570 0 x 1 1 | on on | External wide only 571 1 1 0 0 | on off| Internal wide and internal narrow 572 1 0 1 0 | on off| Internal wide and external narrow 573 0 x 1 0 | off off| Internal wide and external wide 574 1 0 0 1 | on off| Internal narrow and external narrow 575 0 x 0 1 | on off| Internal narrow and external wide 576 1 1 1 1 | on on | No devices are attached 577 x 0 0 0 | on on | Illegal (all 3 connectors are used) 578 0 x 0 0 | on on | Illegal (all 3 connectors are used) 579 580 x means don't-care (either '0' or '1') 581 582 If term_pol (bit 13) is '0' (active-low terminator enable), then: 583 'on' is '0' and 'off' is '1'. 584 585 If term_pol bit is '1' (meaning active-hi terminator enable), then: 586 'on' is '1' and 'off' is '0'. 587 */ 588 589 /* 590 * MEM_CFG Register bit definitions 591 */ 592 #define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 593 #define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */ 594 #define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */ 595 #define ADW_RAM_SZ_2KB 0x00 /* 2 KB */ 596 #define ADW_RAM_SZ_4KB 0x04 /* 4 KB */ 597 #define ADW_RAM_SZ_8KB 0x08 /* 8 KB */ 598 #define ADW_RAM_SZ_16KB 0x0C /* 16 KB */ 599 #define ADW_RAM_SZ_32KB 0x10 /* 32 KB */ 600 #define ADW_RAM_SZ_64KB 0x14 /* 64 KB */ 601 602 /* 603 * DMA_CFG0 Register bit definitions 604 * 605 * This register is only accessible to the host. 606 */ 607 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 608 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 609 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 610 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 611 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 612 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 613 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 614 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 615 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 616 #define START_CTL 0x0C /* DMA start conditions */ 617 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 618 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 619 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 620 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 621 #define READ_CMD 0x03 /* Memory Read Method */ 622 #define READ_CMD_MR 0x00 /* Memory Read */ 623 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 624 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 625 626 /* 627 * ASC-38C0800 RAM BIST Register bit definitions 628 */ 629 #define RAM_TEST_MODE 0x80 630 #define PRE_TEST_MODE 0x40 631 #define NORMAL_MODE 0x00 632 #define RAM_TEST_DONE 0x10 633 #define RAM_TEST_STATUS 0x0F 634 #define RAM_TEST_HOST_ERROR 0x08 635 #define RAM_TEST_INTRAM_ERROR 0x04 636 #define RAM_TEST_RISC_ERROR 0x02 637 #define RAM_TEST_SCSI_ERROR 0x01 638 #define RAM_TEST_SUCCESS 0x00 639 #define PRE_TEST_VALUE 0x05 640 #define NORMAL_VALUE 0x00 641 642 643 /* 644 * Adv Library Status Definitions 645 */ 646 #define ADW_TRUE 1 647 #define ADW_FALSE 0 648 #define ADW_NOERROR 1 649 #define ADW_SUCCESS 1 650 #define ADW_BUSY 0 651 #define ADW_ERROR (-1) 652 653 654 /* 655 * ASC_DVC_VAR 'warn_code' values 656 */ 657 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 658 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 659 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 660 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ 661 #define ASC_WARN_ERROR 0xFFFF /* ADW_ERROR return */ 662 663 #define ADW_MAX_TID 15 /* max. target identifier */ 664 #define ADW_MAX_LUN 7 /* max. logical unit number */ 665 666 667 /* 668 * AscInitGetConfig() and AscInitAsc1000Driver() Definitions 669 * 670 * Error code values are set in ASC_DVC_VAR 'err_code'. 671 */ 672 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ 673 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 674 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ 675 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 676 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ 677 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 678 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ 679 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 680 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ 681 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ 682 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ 683 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ 684 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ 685 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ 686 687 /* 688 * Fixed locations of microcode operating variables. 689 */ 690 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 691 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 692 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 693 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 694 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 695 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 696 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 697 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 698 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 699 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 700 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 701 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 702 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 703 #define ASC_MC_CHIP_TYPE 0x009A 704 #define ASC_MC_INTRB_CODE 0x009B 705 #define ASC_MC_WDTR_ABLE 0x009C 706 #define ASC_MC_SDTR_ABLE 0x009E 707 #define ASC_MC_TAGQNG_ABLE 0x00A0 708 #define ASC_MC_DISC_ENABLE 0x00A2 709 #define ASC_MC_IDLE_CMD_STATUS 0x00A4 710 #define ASC_MC_IDLE_CMD 0x00A6 711 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 712 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 713 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 714 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 715 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 716 #define ASC_MC_SDTR_DONE 0x00B6 717 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 718 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 719 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 720 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 721 #define ASC_MC_WDTR_DONE 0x0124 722 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 723 #define ASC_MC_ICQ 0x0160 724 #define ASC_MC_IRQ 0x0164 725 726 /* 727 * BIOS LRAM variable absolute offsets. 728 */ 729 #define BIOS_CODESEG 0x54 730 #define BIOS_CODELEN 0x56 731 #define BIOS_SIGNATURE 0x58 732 #define BIOS_VERSION 0x5A 733 734 /* 735 * Microcode Control Flags 736 * 737 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 738 * and handled by the microcode. 739 */ 740 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 741 742 /* 743 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 744 */ 745 #define HSHK_CFG_WIDE_XFR 0x8000 746 #define HSHK_CFG_RATE 0x0F00 747 #define HSHK_CFG_OFFSET 0x001F 748 749 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 750 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 751 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 752 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 753 754 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 755 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 756 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 757 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 758 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ 759 760 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 761 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 762 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 763 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 764 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 765 /* 766 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 767 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 768 */ 769 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 770 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 771 772 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 773 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 774 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 775 776 /* 777 * Adapter temporary configuration structure 778 * 779 * This structure can be discarded after initialization. Don't add 780 * fields here needed after initialization. 781 * 782 * Field naming convention: 783 * 784 * *_enable indicates the field enables or disables a feature. The 785 * value of the field is never reset. 786 */ 787 typedef struct adw_dvc_cfg { 788 u_int16_t disc_enable; /* enable disconnection */ 789 u_int8_t chip_version; /* chip version */ 790 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 791 u_int16_t pci_device_id; /* PCI device code number */ 792 u_int16_t lib_version; /* Adv Library version number */ 793 u_int16_t control_flag; /* Microcode Control Flag */ 794 u_int16_t mcode_date; /* Microcode date */ 795 u_int16_t mcode_version; /* Microcode version */ 796 u_int16_t pci_slot_info; /* high byte device/function number */ 797 /* bits 7-3 device num., bits 2-0 function num. */ 798 /* low byte bus num. */ 799 u_int16_t serial1; /* EEPROM serial number word 1 */ 800 u_int16_t serial2; /* EEPROM serial number word 2 */ 801 u_int16_t serial3; /* EEPROM serial number word 3 */ 802 } ADW_DVC_CFG; 803 804 805 #define NO_OF_SG_PER_BLOCK 15 806 807 typedef struct adw_sg_block { 808 u_int8_t reserved1; 809 u_int8_t reserved2; 810 u_int8_t reserved3; 811 u_int8_t sg_cnt; /* Valid entries in block. */ 812 u_int32_t sg_ptr; /* links to next sg block */ 813 struct { 814 u_int32_t sg_addr; /* SG element address */ 815 u_int32_t sg_count; /* SG element count */ 816 } sg_list[NO_OF_SG_PER_BLOCK]; 817 } ADW_SG_BLOCK; 818 819 820 /* 821 * Adapter operation variable structure. 822 * 823 * One structure is required per host adapter. 824 * 825 * Field naming convention: 826 * 827 * *_able indicates both whether a feature should be enabled or disabled 828 * and whether a device is capable of the feature. At initialization 829 * this field may be set, but later if a device is found to be incapable 830 * of the feature, the field is cleared. 831 */ 832 #define CCB_HASH_SIZE 32 /* hash table size for phystokv */ 833 #define CCB_HASH_SHIFT 9 834 #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) 835 836 #define CARRIER_HASH_SIZE 32 /* hash table size for phystokv */ 837 #define CARRIER_HASH_SHIFT 9 838 #define CARRIER_HASH(x) ((((x)) >> CARRIER_HASH_SHIFT) & (CARRIER_HASH_SIZE - 1)) 839 840 typedef int (* ADW_CALLBACK) (int); 841 842 typedef struct adw_softc { 843 844 struct device sc_dev; 845 846 bus_space_tag_t sc_iot; 847 bus_space_handle_t sc_ioh; 848 bus_dma_tag_t sc_dmat; 849 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 850 bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */ 851 void *sc_ih; 852 853 struct adw_control *sc_control; /* control structures */ 854 855 struct adw_carrier *sc_carrhash[CARRIER_HASH_SIZE]; 856 struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE]; 857 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; 858 struct scsipi_link sc_link; /* prototype for devs */ 859 struct scsipi_adapter sc_adapter; 860 861 TAILQ_HEAD(, scsipi_xfer) sc_queue; 862 863 ADW_CALLBACK isr_callback; /* pointer to function, called in AdvISR() */ 864 ADW_CALLBACK async_callback; /* pointer to function, called in AdvISR() */ 865 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ 866 u_int16_t wdtr_able; /* try WDTR for a device */ 867 u_int16_t sdtr_able; /* try SDTR for a device */ 868 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */ 869 u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 870 u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 871 u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 872 u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 873 u_int16_t tagqng_able; /* try tagged queuing with a device */ 874 u_int16_t start_motor; /* start motor command allowed */ 875 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ 876 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ 877 u_int8_t chip_no; /* should be assigned by caller */ 878 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */ 879 u_int8_t irq_no; /* IRQ number */ 880 u_int8_t chip_type; /* chip SCSI target ID */ 881 u_int16_t no_scam; /* scam_tolerant of EEPROM */ 882 u_int32_t drv_ptr; /* driver pointer to private structure */ 883 u_int8_t chip_scsi_id; /* chip SCSI target ID */ 884 u_int8_t bist_err_code; 885 u_int16_t carr_pending_cnt; /* Count of pending carriers. */ 886 struct adw_carrier *carr_freelist; /* Carrier free list. */ 887 struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */ 888 struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */ 889 /* 890 * Note: The following fields will not be used after initialization. The 891 * driver may discard the buffer after initialization is done. 892 */ 893 ADW_DVC_CFG cfg; /* temporary configuration structure */ 894 } ADW_SOFTC; 895 896 897 /* 898 * ADW_SCSI_REQ_Q - microcode request structure 899 * 900 * All fields in this structure up to byte 60 are used by the microcode. 901 * The microcode makes assumptions about the size and ordering of fields 902 * in this structure. Do not change the structure definition here without 903 * coordinating the change with the microcode. 904 */ 905 typedef struct adw_scsi_req_q { 906 u_int8_t cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 907 u_int8_t target_cmd; 908 u_int8_t target_id; /* Device target identifier. */ 909 u_int8_t target_lun; /* Device target logical unit number. */ 910 u_int32_t data_addr; /* Data buffer physical address. */ 911 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 912 u_int32_t sense_addr; /* Sense buffer physical address. */ 913 u_int32_t carr_pa; /* Carrier p-address */ 914 u_int8_t mflag; /* Adv Library flag field. */ 915 u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */ 916 u_int8_t cdb_len; /* SCSI CDB length. */ 917 u_int8_t scsi_cntl; 918 u_int8_t done_status; /* Completion status. */ 919 u_int8_t scsi_status; /* SCSI status byte. (see below) */ 920 u_int8_t host_status; /* Ucode host status. */ 921 u_int8_t sg_working_ix; /* Ucode working SG variable. */ 922 u_int8_t cdb[12]; /* SCSI command block. */ 923 u_int32_t sg_real_addr; /* SG list physical address. */ 924 u_int32_t scsiq_rptr; /* Iternal pointer to ADW_SCSI_REQ_Q */ 925 u_int32_t sg_working_data_cnt; 926 u_int32_t ccb_ptr; /* CCB Physical Address */ 927 u_int32_t carr_va; /* Carrier v-address (unused) */ 928 /* 929 * End of microcode structure - 60 bytes. The rest of the structure 930 * is used by the Adv Library and ignored by the microcode. 931 */ 932 struct scsipi_sense_data *vsense_addr; /* Sense buffer virtual address. */ 933 u_char *vdata_addr; /* Data buffer virtual address. */ 934 u_int8_t orig_sense_len; /* Original length of sense buffer. */ 935 u_int8_t pads[3]; /* padding bytes (align to long) */ 936 } ADW_SCSI_REQ_Q; 937 938 /* 939 * Microcode idle loop commands 940 */ 941 #define IDLE_CMD_COMPLETED 0 942 #define IDLE_CMD_STOP_CHIP 0x0001 943 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 944 #define IDLE_CMD_SEND_INT 0x0004 945 #define IDLE_CMD_ABORT 0x0008 946 #define IDLE_CMD_DEVICE_RESET 0x0010 947 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 948 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 949 #define IDLE_CMD_SCSIREQ 0x0080 950 951 #define IDLE_CMD_STATUS_SUCCESS 0x0001 952 #define IDLE_CMD_STATUS_FAILURE 0x0002 953 954 /* 955 * AdvSendIdleCmd() flag definitions. 956 */ 957 #define ADW_NOWAIT 0x01 958 959 /* 960 * Wait loop time out values. 961 */ 962 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */ 963 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 964 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 965 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */ 966 #define SCSI_MAX_RETRY 10 /* retry count */ 967 968 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 969 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 970 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 971 972 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 973 974 975 /* Read byte from a register. */ 976 #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \ 977 bus_space_read_1((iot), (ioh), (reg_off)) 978 979 /* Write byte to a register. */ 980 #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \ 981 bus_space_write_1((iot), (ioh), (reg_off), (byte)) 982 983 /* Read word (2 bytes) from a register. */ 984 #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \ 985 bus_space_read_2((iot), (ioh), (reg_off)) 986 987 /* Write word (2 bytes) to a register. */ 988 #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ 989 bus_space_write_2((iot), (ioh), (reg_off), (word)) 990 991 /* Read byte from LRAM. */ 992 #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ 993 do { \ 994 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 995 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \ 996 } while (0) 997 998 /* Write byte to LRAM. */ 999 #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \ 1000 do { \ 1001 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1002 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \ 1003 } while (0) 1004 1005 /* Read word (2 bytes) from LRAM. */ 1006 #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \ 1007 do { \ 1008 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1009 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \ 1010 } while (0) 1011 1012 /* Write word (2 bytes) to LRAM. */ 1013 #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \ 1014 do { \ 1015 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1016 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \ 1017 } while (0) 1018 1019 /* Write double word (4 bytes) to LRAM */ 1020 /* Because of unspecified C language ordering don't use auto-increment. */ 1021 #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \ 1022 do { \ 1023 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1024 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 1025 (ushort) ((dword) & 0xFFFF)); \ 1026 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \ 1027 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 1028 (ushort) ((dword >> 16) & 0xFFFF)); \ 1029 } while (0) 1030 1031 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 1032 #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \ 1033 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \ 1034 1035 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 1036 #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \ 1037 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)) 1038 1039 /* 1040 * Define macro to check for Condor signature. 1041 * 1042 * Evaluate to ADW_TRUE if a Condor chip is found the specified port 1043 * address 'iop_base'. Otherwise evalue to ADW_FALSE. 1044 */ 1045 #define ADW_FIND_SIGNATURE(iot, ioh) \ 1046 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \ 1047 ADW_CHIP_ID_BYTE) && \ 1048 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \ 1049 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE) 1050 1051 /* 1052 * Define macro to Return the version number of the chip at 'iop_base'. 1053 * 1054 * The second parameter 'bus_type' is currently unused. 1055 */ 1056 #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \ 1057 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV) 1058 1059 /* 1060 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must 1061 * match the ASC_SCSI_REQ_Q 'srb_ptr' field. 1062 * 1063 * If the request has not yet been sent to the device it will simply be 1064 * aborted from RISC memory. If the request is disconnected it will be 1065 * aborted on reselection by sending an Abort Message to the target ID. 1066 * 1067 * Return value: 1068 * ADW_TRUE(1) - Queue was successfully aborted. 1069 * ADW_FALSE(0) - Queue was not found on the active queue list. 1070 */ 1071 #define ADW_ABORT_CCB(sc, ccb_ptr) \ 1072 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) 1073 1074 /* 1075 * Send a Bus Device Reset Message to the specified target ID. 1076 * 1077 * All outstanding commands will be purged if sending the 1078 * Bus Device Reset Message is successful. 1079 * 1080 * Return Value: 1081 * ADW_TRUE(1) - All requests on the target are purged. 1082 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1083 * are not purged. 1084 */ 1085 #define ADW_RESET_DEVICE(sc, target_id) \ 1086 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) 1087 1088 /* 1089 * SCSI Wide Type definition. 1090 */ 1091 #define ADW_SCSI_BIT_ID_TYPE u_int16_t 1092 1093 /* 1094 * AdvInitScsiTarget() 'cntl_flag' options. 1095 */ 1096 #define ADW_SCAN_LUN 0x01 1097 #define ADW_CAPINFO_NOLUN 0x02 1098 1099 /* 1100 * Convert target id to target id bit mask. 1101 */ 1102 #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) 1103 1104 /* 1105 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values. 1106 */ 1107 1108 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 1109 #define QD_NO_ERROR 0x01 1110 #define QD_ABORTED_BY_HOST 0x02 1111 #define QD_WITH_ERROR 0x04 1112 1113 #define QHSTA_NO_ERROR 0x00 1114 #define QHSTA_M_SEL_TIMEOUT 0x11 1115 #define QHSTA_M_DATA_OVER_RUN 0x12 1116 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 1117 #define QHSTA_M_QUEUE_ABORTED 0x15 1118 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 1119 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 1120 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 1121 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 1122 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 1123 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 1124 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 1125 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 1126 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 1127 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 1128 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 1129 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 1130 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 1131 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 1132 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 1133 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 1134 #define QHSTA_M_WTM_TIMEOUT 0x41 1135 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 1136 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 1137 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 1138 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 1139 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 1140 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 1141 1142 /* 1143 * SCSI Iquiry structure 1144 */ 1145 1146 typedef struct { 1147 u_int8_t peri_dvc_type : 5; /* peripheral device type */ 1148 u_int8_t peri_qualifier : 3; /* peripheral qualifier */ 1149 u_int8_t dvc_type_modifier : 7; /* device type modifier (for SCSI I) */ 1150 u_int8_t rmb : 1; /* RMB - removable medium bit */ 1151 u_int8_t ansi_apr_ver : 3; /* ANSI approved version */ 1152 u_int8_t ecma_ver : 3; /* ECMA version */ 1153 u_int8_t iso_ver : 2; /* ISO version */ 1154 u_int8_t rsp_data_fmt : 4; /* response data format */ 1155 /* 0 SCSI 1 */ 1156 /* 1 CCS */ 1157 /* 2 SCSI-2 */ 1158 /* 3-F reserved */ 1159 u_int8_t res1 : 2; /* reserved */ 1160 u_int8_t TemIOP : 1; /* terminate I/O process bit (see 5.6.22) */ 1161 u_int8_t aenc : 1; /* asynch. event notification (processor) */ 1162 u_int8_t add_len; /* additional length */ 1163 u_int8_t res2; /* reserved */ 1164 u_int8_t res3; /* reserved */ 1165 u_int8_t StfRe : 1; /* soft reset implemented */ 1166 u_int8_t CmdQue : 1; /* command queuing */ 1167 u_int8_t res4 : 1; /* reserved */ 1168 u_int8_t Linked : 1; /* linked command for this logical unit */ 1169 u_int8_t Sync : 1; /* synchronous data transfer */ 1170 u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */ 1171 u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */ 1172 u_int8_t RelAdr : 1; /* relative addressing mode */ 1173 u_int8_t vendor_id[8]; /* vendor identification */ 1174 u_int8_t product_id[16]; /* product identification */ 1175 u_int8_t product_rev_level[4]; /* product revision level */ 1176 u_int8_t vendor_specific[20]; /* vendor specific */ 1177 u_int8_t IUS : 1; /* information unit supported */ 1178 u_int8_t QAS : 1; /* quick arbitrate supported */ 1179 u_int8_t Clocking : 2; /* clocking field */ 1180 u_int8_t res5 : 4; /* reserved */ 1181 u_int8_t res6; /* reserved */ 1182 } ADW_SCSI_INQUIRY; /* 58 bytes */ 1183 1184 #define SS_GOOD 0x00 1185 #define SS_CHK_CONDITION 0x02 1186 #define SS_CONDITION_MET 0x04 1187 #define SS_TARGET_BUSY 0x08 1188 #define SS_INTERMID 0x10 1189 #define SS_INTERMID_COND_MET 0x14 1190 #define SS_RSERV_CONFLICT 0x18 1191 #define SS_CMD_TERMINATED 0x22 1192 #define SS_QUEUE_FULL 0x28 1193 #define MS_CMD_DONE 0x00 1194 #define MS_EXTEND 0x01 1195 #define MS_SDTR_LEN 0x03 1196 #define MS_SDTR_CODE 0x01 1197 #define MS_WDTR_LEN 0x02 1198 #define MS_WDTR_CODE 0x03 1199 #define MS_MDP_LEN 0x05 1200 #define MS_MDP_CODE 0x00 1201 #define M1_SAVE_DATA_PTR 0x02 1202 #define M1_RESTORE_PTRS 0x03 1203 #define M1_DISCONNECT 0x04 1204 #define M1_INIT_DETECTED_ERR 0x05 1205 #define M1_ABORT 0x06 1206 #define M1_MSG_REJECT 0x07 1207 #define M1_NO_OP 0x08 1208 #define M1_MSG_PARITY_ERR 0x09 1209 #define M1_LINK_CMD_DONE 0x0A 1210 #define M1_LINK_CMD_DONE_WFLAG 0x0B 1211 #define M1_BUS_DVC_RESET 0x0C 1212 #define M1_ABORT_TAG 0x0D 1213 #define M1_CLR_QUEUE 0x0E 1214 #define M1_INIT_RECOVERY 0x0F 1215 #define M1_RELEASE_RECOVERY 0x10 1216 #define M1_KILL_IO_PROC 0x11 1217 #define M2_QTAG_MSG_SIMPLE 0x20 1218 #define M2_QTAG_MSG_HEAD 0x21 1219 #define M2_QTAG_MSG_ORDERED 0x22 1220 #define M2_IGNORE_WIDE_RESIDUE 0x23 1221 1222 1223 #define ASC_MAX_SENSE_LEN 32 1224 #define ASC_MIN_SENSE_LEN 14 1225 1226 typedef struct asc_req_sense { 1227 u_int8_t err_code:7; 1228 u_int8_t info_valid:1; 1229 u_int8_t segment_no; 1230 u_int8_t sense_key:4; 1231 u_int8_t reserved_bit:1; 1232 u_int8_t sense_ILI:1; 1233 u_int8_t sense_EOM:1; 1234 u_int8_t file_mark:1; 1235 u_int8_t info1[4]; 1236 u_int8_t add_sense_len; 1237 u_int8_t cmd_sp_info[4]; 1238 u_int8_t asc; 1239 u_int8_t ascq; 1240 u_int8_t fruc; 1241 u_int8_t sks_byte0:7; 1242 u_int8_t sks_valid:1; 1243 u_int8_t sks_bytes[2]; 1244 u_int8_t notused[2]; 1245 u_int8_t ex_sense_code; 1246 u_int8_t info2[4]; 1247 } ASC_REQ_SENSE; 1248 1249 1250 /* 1251 * Adv Library functions available to drivers. 1252 */ 1253 1254 int AdvInitAsc3550Driver __P((ADW_SOFTC *)); 1255 int AdvInitAsc38C0800Driver __P((ADW_SOFTC *)); 1256 int AdvInitFrom3550EEP __P((ADW_SOFTC *)); 1257 int AdvInitFrom38C0800EEP __P((ADW_SOFTC *)); 1258 int AdvExeScsiQueue __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 1259 int AdvISR __P((ADW_SOFTC *)); 1260 void AdvResetChip __P((bus_space_tag_t, bus_space_handle_t)); 1261 int AdvSendIdleCmd __P((ADW_SOFTC *, u_int16_t, u_int32_t)); 1262 int AdvResetSCSIBus __P((ADW_SOFTC *)); 1263 int AdvResetCCB __P((ADW_SOFTC *)); 1264 1265 #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */ 1266
Indexes created Mon Sep 22 05:09:51 GMT 2025